Layout correction method, storage medium and terminal

Abstract

A layout correction method, a storage medium and a terminal, wherein the layout correction method comprises: acquiring a correction layout; performing optical proximity correction verification processing on the correction layout to obtain error points in the correction layout; acquiring a first local area based on the error points, the first local area having a plurality of to-be-corrected patterns; and performing correction processing on the to-be-corrected patterns in the first local area. Based on the error points, a first local area is acquired, and the first local area has a plurality of to-be-corrected patterns. By performing correction processing only on the to-be-corrected patterns in the first local area, the correction of the whole chip area is avoided, thereby effectively improving the correction efficiency, and avoiding the reoccurrence of correction errors in the originally corrected area, and improving the correction accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a layout correction method, a storage medium and a terminal. BACKGROUND

[0002] Photolithography is a very important technology in semiconductor manufacturing, which can transfer a pattern from a mask to a wafer to form a semiconductor product according to the design requirements. The photolithography process includes an exposure step, a developing step after the exposure step, and an etching step after the developing step. In the exposure step, light passes through the transparent region of the mask and irradiates the wafer coated with photoresist, and the photoresist undergoes a chemical reaction under the irradiation of light. In the developing step, the light-sensitive and non-light-sensitive photoresist are dissolved to different degrees in the developing agent, forming a photoresist pattern and transferring the mask pattern to the photoresist. In the etching step, the wafer is etched based on the photoresist pattern formed by the photoresist layer, and the pattern of the mask is further transferred to the wafer.

[0003] In semiconductor manufacturing, as the design size continues to shrink, the design size is closer and closer to the limit of the photolithography imaging system, and the diffraction effect of light becomes more and more obvious, resulting in optical image degradation of the design pattern, and the actual photoresist pattern formed is severely distorted relative to the pattern on the mask. The actual pattern formed on the wafer after photolithography is different from the design pattern, which is called optical proximity effect (OPE).

[0004] In order to correct the optical proximity effect, optical proximity correction (OPC) is generated. The core idea of optical proximity correction is to establish an optical proximity correction model based on the consideration of offsetting the optical proximity effect, and to design a photomask pattern according to the optical proximity correction model. Although the photoresist pattern after photolithography has an optical proximity effect relative to the photomask pattern, since the photomask pattern has been designed according to the optical proximity correction model, the photoresist pattern after photolithography is close to the target pattern that the user actually wants to obtain.

[0005] However, there are still many problems in the layout correction process in the prior art. SUMMARY

[0006] The technical problem solved by the present application is to provide a layout correction method, a storage medium and a terminal to improve the correction efficiency and the correction accuracy.

[0007] To solve the above problems, the technical scheme of the present application provides a layout correction method, comprising: obtaining a correction layout; performing optical proximity correction verification processing on the correction layout to obtain error points in the correction layout; obtaining a first local area in the correction layout based on the error points, the first local area having a plurality of to-be-corrected patterns; and performing correction processing on the to-be-corrected patterns in the first local area.

[0008] Optionally, the method for obtaining a correction layout comprises: providing an initial layout; and performing first optical proximity correction on the initial layout to obtain the correction layout.

[0009] Optionally, the method for performing correction processing on the to-be-corrected patterns in the first local area comprises: providing an optical proximity correction verification database; searching for a historical correction area that matches the first local area in the optical proximity correction verification database; when the historical correction area is searched for in the optical proximity correction verification database, applying correction data of a plurality of patterns in the historical correction area to the first local area to perform correction processing on the plurality of to-be-corrected patterns.

[0010] Optionally, when the historical correction area is not searched for in the optical proximity correction verification database, performing second optical proximity correction processing on the to-be-corrected patterns in the first local area.

[0011] Optionally, after performing second optical proximity correction processing on the to-be-corrected patterns in the first local area, the method further comprises: updating second optical proximity correction data for the to-be-corrected patterns in the first local area to the optical proximity correction verification database.

[0012] Optionally, the method for obtaining a first local area based on error points comprises: constructing a frame selection area with the error points as a center coordinate point to obtain the first local area.

[0013] Optionally, the first local area comprises a square with a side length ranging from 1.5 microns to 2.5 microns.

[0014] Optionally, the correction layout has a corresponding initial layout and a target layout, and obtaining a first local area in the correction layout based on the error points further comprises: simultaneously obtaining a corresponding second local area in the initial layout and the target layout, the second local area in the initial layout and the second local area in the target layout having a plurality of reference patterns corresponding to the to-be-corrected patterns.

[0015] Optionally, the method for searching the historical correction region matching the first local region in the optical proximity correction verification database comprises: formulating index information of the initial layout and the target layout; obtaining first search range data in the optical proximity correction verification database according to the index information; formulating feature information of the reference patterns in the second local region; searching the historical correction region by comparing the feature information in the first search range data.

[0016] Optionally, the index information comprises: a manufacturer, a product, and a process level.

[0017] Optionally, the feature information of the reference patterns in the second local region comprises: self feature information of each reference pattern, and associated feature information between two adjacent reference patterns.

[0018] Optionally, the associated feature information between two adjacent reference patterns is represented by vertex information of two adjacent edges between the two adjacent reference patterns.

[0019] Optionally, the method for representing the associated feature information between two adjacent reference patterns by vertex information of two adjacent edges between the two adjacent reference patterns comprises: constructing a virtual quadrilateral based on two adjacent edges between the two adjacent reference patterns; and obtaining self feature information of the virtual quadrilateral, taking the self feature information of the virtual quadrilateral as the associated feature information between the two adjacent reference patterns.

[0020] Optionally, the self feature information comprises: vertex information of a pattern, and information of each edge of the pattern.

[0021] Optionally, the information of each edge of the pattern is represented by two vertex information of the edge.

[0022] Optionally, the method for searching the historical correction region by comparing the feature information in the first search range data comprises: dividing the second local region into a first region and a plurality of second regions, the first region being a square constructed with the error point as a center coordinate point, and the plurality of second regions being successively surrounded with the first region as a reference, and the second region located at the innermost side surrounding the first region; the feature information of the reference patterns in the first region being the same as feature information of patterns in a corresponding region in the historical correction region; and the feature information of the reference patterns in the plurality of second regions and the feature information of patterns in a corresponding region in the historical correction region having an error rate not more than a preset error rate, and the error rate being positively correlated with a distance between the second region and the error point.

[0023] Optionally, the area ratio of the first region to the second local region is 65% to 75%.

[0024] Optionally, the preset error rate ranges from 5%.

[0025] Correspondingly, the present application also provides a storage medium having computer instructions stored thereon, wherein the computer instructions perform the steps of any of the above methods when executed.

[0026] Correspondingly, the present application also provides a terminal comprising a memory and a processor, wherein the memory has computer instructions stored thereon and capable of being executed on the processor, and wherein the processor performs the steps of any of the above methods when executing the computer instructions.

[0027] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0028] In the layout correction method of the present application, a first local region is obtained based on the error points, and the first local region has a plurality of to-be-corrected patterns, and by only correcting the to-be-corrected patterns in the first local region, the correction of the whole chip region is avoided, thereby effectively improving the correction efficiency, and avoiding the reoccurrence of correction errors in the originally correctly corrected region, and improving the correction accuracy.

[0029] Further, the method for correcting the to-be-corrected patterns in the first local region comprises: providing an optical proximity correction verification database; searching for a historical correction region that is suitable for the first local region in the optical proximity correction verification database; when the historical correction region is searched in the optical proximity correction verification database, applying the correction data of the patterns in the historical correction region to the first local region for correction of the to-be-corrected patterns. By directly calling the historical correction data in the optical proximity correction verification database, repeated work is avoided, and the correction efficiency is further improved.

[0030] Further, after the second optical proximity correction of the to-be-corrected patterns in the first local region is performed, the method further comprises: updating the second optical proximity correction data of the to-be-corrected patterns in the first local region to the optical proximity correction verification database, so as to improve the coverage of the optical proximity correction verification database.

[0031] Further, the method for searching the historical correction region according to the feature information in the first search range data comprises: dividing the second local region into a first region and a plurality of second regions, the first region is a square constructed with the error point as a center coordinate point, and a plurality of second regions are sequentially surrounded with the first region as a reference, and the second region located at the innermost side surrounds the first region; the feature information of a plurality of reference patterns in the first region is the same as the feature information of patterns in the corresponding region in the historical correction region; the feature information of a plurality of reference patterns in a plurality of second regions is not more than a preset error rate from the feature information of patterns in the corresponding region in the historical correction region, and the error rate is positively correlated with the distance between the second region and the error point. By reducing the search comparison requirements, it is ensured that the historical correction data is directly called in the optical proximity correction verification database as much as possible on the basis of applicability, so as to improve the correction efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 is a flowchart of a layout correction method according to an embodiment of the present application;

[0033] Figures 2 to 10 is a structural schematic diagram of each step of the layout correction method according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] As described in the background, there are still many problems in the layout correction process in the prior art. The following will be specifically explained.

[0035] At present, the optical proximity correction used in the layout correction process is often repeatedly corrected in the full-chip region when debugging a single correction error pattern (error point), which is time-consuming and labor-intensive. Moreover, in the process of correcting the full-chip region, factors such as insufficient optical proximity correction license (OPC license) may be encountered, and queuing for the license may also affect the progress of debugging. In addition, for the regions in the full-chip that do not appear correction errors, the combination of newly introduced correction codes and original codes often has a counteractive effect in the process of repeatedly correcting the full-chip region, causing the regions that were originally corrected accurately to reappear correction errors, thereby affecting the accuracy of the optical proximity correction.

[0036] On this basis, the present application provides a layout correction method, a storage medium and a terminal, a first local region is obtained based on the error point, the first local region has a plurality of to-be-corrected patterns, by only correcting the to-be-corrected patterns in the first local region, the correction of the full-chip region is avoided, thereby effectively improving the correction efficiency, and avoiding the reappearance of correction errors in the regions that were originally corrected accurately, thereby improving the correction accuracy.

[0037] In order to make the above objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] Figure 1 is a flowchart of a layout modification method according to an embodiment of the present application, comprising:

[0039] Step S101, obtaining a modified layout;

[0040] Step S102, performing optical proximity correction verification processing on the modified layout to obtain error points in the modified layout;

[0041] Step S103, obtaining a first local region based on the error points, the first local region having a plurality of to-be-modified patterns;

[0042] Step S104, performing modification processing on the to-be-modified patterns of the first local region.

[0043] The various steps of the layout modification method are described in detail below with reference to the accompanying drawings.

[0044] Figures 2 to 10 is a schematic diagram of the steps of the layout modification method according to an embodiment of the present application.

[0045] Obtaining a modified layout. The specific process of obtaining the modified layout is described in detail with reference to Figures 2 to 3 .

[0046] The initial layout 100 is provided as described in Figure 2 .

[0047] It should be noted that in this embodiment, the initial layout 100 is an initial input and has not been modified. In an ideal state without optical proximity effect, the device pattern formed on the wafer from the initial layout 100 through steps such as exposure, development and etching should be in a proportional scaling with the pattern on the initial layout 100. Then, due to the existence of optical proximity effect, the device pattern formed on the wafer from the initial layout 100 will often have a large deviation, so the initial layout 100 needs to be subjected to optical proximity correction processing in subsequent processes.

[0048] The initial layout 100 is subjected to first optical proximity correction as described in Figure 3 , to obtain the modified layout 200.

[0049] It should be noted that in the present embodiment, in the integrated circuit manufacturing, the modified layout 200 obtained after the first optical proximity correction needs to be subjected to an optical proximity correction verification process (OPC Verify) before being sent to a mask factory to manufacture a mask, that is, simulation calculation is performed on the modified layout 200 to determine whether it meets the requirements of the process window.

[0050] It should be noted that in the present embodiment, in the integrated circuit manufacturing, the modified layout 200 obtained after the first optical proximity correction needs to be subjected to an optical proximity correction verification process (OPC Verify) before being sent to a mask factory to manufacture a mask, that is, simulation calculation is performed on the modified layout 200 to determine whether it meets the requirements of the process window. Figure 4 The optical proximity correction verification process is performed on the modified layout 200 to obtain an error point A in the modified layout 200.

[0051] It should be noted that in the present embodiment, the optical proximity correction verification process performed on the modified layout 200 is mainly to verify whether there is a bridge check between patterns and a pinch check of the placement edge of the pattern itself in the modified layout 200. When a problem is found in the verification, the error point A is reported near the corresponding pattern, and the error point A must be processed separately to meet the requirements of the process window.

[0052] It should be noted that in the present embodiment, the optical proximity correction verification process performed on the modified layout 200 is mainly to verify whether there is a bridge check between patterns and a pinch check of the placement edge of the pattern itself in the modified layout 200. When a problem is found in the verification, the error point A is reported near the corresponding pattern, and the error point A must be processed separately to meet the requirements of the process window. Figure 5 A first local area S1 is obtained based on the error point A, and the first local area S1 has a plurality of to-be-corrected patterns 201.

[0053] In the present embodiment, the method for obtaining the first local area S1 based on the error point A includes: constructing a frame selection area with the error point A as a center coordinate point to obtain the first local area S1.

[0054] In the present embodiment, the first local area S1 includes a square with a side length ranging from 1.5 microns to 2.5 microns.

[0055] In the present embodiment, the modified layout 200 has a corresponding initial layout 100 and a target layout 300, and based on the error point A, the first local area S1 is obtained in the modified layout 200, and at the same time, a corresponding second local area S2 is obtained in the initial layout 100 and the target layout 300. The second local area S2 in the initial layout 100 has a plurality of reference patterns 101 corresponding to the to-be-corrected patterns 201, and the second local area S2 in the target layout 300 has a plurality of reference patterns 301 corresponding to the to-be-corrected patterns 201.

[0056] It should be noted that in the embodiment, the target layout 300 is the device pattern formed on the wafer by the initial layout 100 after exposure, development and etching, and the pattern on the target layout 300 should be completely consistent with the pattern on the target layout 300. The pattern in the initial layout 100 and the pattern in the target layout 300 are regular, and the patterns of the two are similar, and the difference is that the sizes of the patterns are different. The modified layout 200, the initial layout 100 and the target layout 300 are stacked, and when the first local area S1 is intercepted in the modified layout 200, the corresponding second local area S2 is simultaneously intercepted in the initial layout 100 and the target layout 300.

[0057] In the embodiment, after the first local area S1 is obtained, the method further comprises: performing a correction process on the to-be-corrected pattern 201 in the first local area S1. For details, please refer to Figures 6 to 10 .

[0058] In the embodiment, the first local area S1 is obtained based on the error point A1, and the first local area S1 has a plurality of to-be-corrected patterns 201. By performing a correction process only on the to-be-corrected pattern 201 in the first local area S1, the correction of the full-chip region is avoided, thereby effectively improving the correction efficiency, and avoiding the reoccurrence of correction errors in the originally corrected region, and improving the correction accuracy.

[0059] In the embodiment, the method for performing a correction process on the to-be-corrected pattern 201 in the first local area S1 comprises: providing an optical proximity correction verification database (OPC Verify Database); searching for a historical correction area suitable for the first local area S1 in the optical proximity correction verification database; when the historical correction area is searched in the optical proximity correction verification database, applying the correction data of the pattern in the historical correction area to the first local area S1 for correction processing of a plurality of to-be-corrected patterns 201. By directly calling historical correction data in the optical proximity correction verification database, the correction efficiency is further improved.

[0060] In the embodiment, the process of searching for a historical correction area suitable for the first local area S1 in the optical proximity correction verification database will be described in detail with reference to Figures 6 to 8 .

[0061] Please refer to Figure 6 , the index information of the initial layout 100 and the target layout 300 is established; and first search range data is obtained in the optical proximity correction verification database according to the index information.

[0062] In the embodiment, the index information comprises a manufacturer 401, a product 402, and a process level 403.

[0063] In the embodiment, after the first search range is obtained, feature information of a plurality of reference patterns in the second local area is formulated; and the historical correction area is searched by comparing the feature information in the first search range data. For details, please refer to Figure 7 and Figure 8 .

[0064] In the embodiment, the feature information of the plurality of reference patterns in the second local area comprises self feature information of each reference pattern and associated feature information between two adjacent reference patterns.

[0065] In the embodiment, the associated feature information between two adjacent reference patterns is represented by vertex information of two adjacent edges between the two adjacent reference patterns.

[0066] In the embodiment, the self feature information comprises vertex information of a pattern and information of each edge of the pattern.

[0067] In the embodiment, the information of each edge of the pattern is represented by two vertex information of the edge.

[0068] Please refer to Figure 7 For an undirected graph 501, in the expression of an adjacency matrix, each vertex information of the undirected graph 501 is represented by a number in a set {0, 1, …, n-1}, and the information of each edge is represented by two vertex information of the edge. Figure 7 The information of each edge is stored in a cell of a two-dimensional array A. For example, a cell A[i, j] stores the information of an edge e, where the vertex information of one vertex u of the edge e is i, and the vertex information of another vertex v of the edge e is j. If there is no such edge, A[i, j] = None. For the undirected graph 501, the two-dimensional array A is symmetrical, i.e., A[i, j] = A[j, i].

[0069] In the embodiment, the method for representing the associated feature information between two adjacent reference patterns by vertex information of two adjacent edges between the two adjacent reference patterns comprises: constructing a virtual quadrilateral based on the two adjacent edges between the two adjacent reference patterns; and obtaining self feature information of the virtual quadrilateral, and taking the self feature information of the virtual quadrilateral as the associated feature information between the two adjacent reference patterns.

[0070] Please refer to Figure 8For the complete graph abcd and the graph efgh, Lab corresponds to the edge between a and b, Lbc corresponds to the edge between b and c, Lcd corresponds to the edge between c and d, and Lda corresponds to the edge between d and a; Lef corresponds to the edge between e and f, Lfg corresponds to the edge between f and g, Lgh corresponds to the edge between g and h, and Lhe corresponds to the edge between h and e, and the complete information of the two graphs is represented by graph matrix A[a, d] and A[e, h], i.e.:

[0071]

[0072] The graph abcd and the graph efgh are adjacent, and the corresponding edges Lbc and Leh are adjacent, so when the associated information between the graph abcd and the graph efgh is obtained, the vertex b and the vertex e are connected, and the vertex c and the vertex h are connected to construct a virtual quadrilateral behc, and the virtual quadrilateral behc has two constructed edges Lbe and Lch. Since the edge Lbc and the edge Leh have been respectively stored in the graph abcd and the graph efgh in the virtual quadrilateral behc, it is not necessary to store them repeatedly, and the complete information of the virtual quadrilateral behc is represented by graph matrix A[b, c], i.e.:

[0073]

[0074] It should be noted that in the embodiment, the graph in the second local region in the initial layout and the target layout is stored according to the above format, and the BFS (Breadth-First Search) algorithm is used to traverse the generated graph matrix when the problem occurs in the optical proximity correction verification process, and the same graph matrix is matched in the optical proximity correction verification database to search the historical correction region.

[0075] In the embodiment, the feature information is compared in the first search range data to search the historical correction region, and the process is specifically referred to Figure 9 ,

[0076] Please refer to Figure 9The second local area S2 is divided into a first area S21 and a plurality of second areas S22, the first area S21 is a square constructed with the error point A as a central coordinate point, with the first area S21 as a reference, the plurality of second areas S22 are sequentially surrounded, and the second area S22 located at the innermost side surrounds the first area S21; the feature information of the plurality of reference patterns 101 (only taking the initial layout as an example in the figure, the processing process of the target layout is consistent with this) in the first area S21 is the same as the feature information of the patterns in the corresponding area in the historical correction area; the feature information of the plurality of reference patterns 101 in the plurality of second areas S22 has an error rate that does not exceed a preset error rate with the feature information of the patterns in the corresponding area in the historical correction area, and the error rate is positively correlated with the distance between the second area S22 and the error point A.

[0077] In the embodiment, by reducing the requirement of search contrast, it is ensured that the historical correction data is directly called in the optical proximity correction verification database as much as possible on the basis of applicability, so that the correction efficiency is improved.

[0078] In the embodiment, the area ratio of the first area S21 to the second local area S2 is 65% to 75%.

[0079] In the embodiment, the preset error rate ranges from 5%.

[0080] Please refer to Figure 10 When the historical correction area is not searched in the optical proximity correction verification database, the second optical proximity correction processing is performed on the to-be-corrected pattern 201 in the first local area S1.

[0081] In the embodiment, after the second optical proximity correction processing is performed on the to-be-corrected pattern in the first local area, the second optical proximity correction data of the to-be-corrected pattern 201 in the first local area S1 is updated to the optical proximity correction verification database, so as to improve the coverage of the optical proximity correction verification database.

[0082] Correspondingly, the embodiment of the application further provides a storage medium having computer instructions stored thereon, and the computer instructions are characterized in that the computer instructions perform the steps of the above-mentioned method when running.

[0083] Correspondingly, the embodiment of the application further provides a terminal including a memory and a processor, and the memory has computer instructions capable of running on the processor stored thereon, and the processor is characterized in that the processor performs the steps of the above-mentioned method when running the computer instructions.

[0084] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A layout correction method, characterized by, The method comprises the following steps: obtaining a modified layout; performing optical proximity correction verification on the modified layout to obtain error points in the modified layout; based on the error points, obtaining a first local area in the modified layout, and the first local area has a plurality of to-be-corrected patterns; performing correction processing on the to-be-corrected patterns in the first local area; wherein the method for performing correction processing on the to-be-corrected patterns in the first local area comprises: providing an optical proximity correction verification database; searching the optical proximity correction verification database for a historical correction area that matches the first local area; when the historical correction area is searched in the optical proximity correction verification database, applying correction data of patterns in the historical correction area to the first local area to perform correction processing on the plurality of to-be-corrected patterns; the modified layout has a corresponding initial layout and a target layout, and based on the error points, the first local area is obtained in the modified layout, and at the same time, a corresponding second local area is obtained in the initial layout and the target layout, and the second local area in the initial layout and the second local area in the target layout have a plurality of reference patterns corresponding to the to-be-corrected patterns.

2. The layout modification method of claim 1, wherein, The method for obtaining a modified layout comprises the following steps:

3. The layout modification method of claim 1, wherein, providing an initial layout; 4. The layout modification method of claim 3, wherein, performing first optical proximity correction on the initial layout to obtain the modified layout.

5. The layout modification method of claim 1, wherein, When the historical correction area is not searched in the optical proximity correction verification database, second optical proximity correction processing is performed on the to-be-corrected patterns in the first local area.

6. The layout modification method of claim 1, wherein, After the second optical proximity correction processing is performed on the to-be-corrected patterns in the first local area, the second optical proximity correction data of the to-be-corrected patterns in the first local area is updated in the optical proximity correction verification database.

7. The layout modification method of claim 1, wherein, The method for obtaining a first local area based on error points comprises the following steps:

8. The layout modification method of claim 7, wherein, constructing a bounding area with the error points as the center coordinate point to obtain the first local area.

9. The layout modification method of claim 7, wherein, The first local area comprises a square with a side length ranging from 1.5 microns to 2.5 microns.

10. The layout modification method of claim 9, wherein, The method for searching a historical correction area that matches the first local area in the optical proximity correction verification database comprises the following steps: establishing index information of the initial layout and the target layout; obtaining first search range data in the optical proximity correction verification database according to the index information; establishing feature information of a plurality of reference patterns in the second local area; performing comparison in the first search range data according to the feature information to search the historical correction area. The index information comprises a manufacturer, a product, and a process level. The feature information of a plurality of reference patterns in the second local area comprises self-feature information of each reference pattern and associated feature information between two adjacent reference patterns. The associated feature information between two adjacent reference patterns is represented by vertex information of two adjacent edges between the two adjacent reference patterns.

11. The layout modification method of claim 10, wherein, The method for representing the associated feature information between the two adjacent reference patterns by the vertex information of the two adjacent edges between the two adjacent reference patterns comprises: constructing a virtual quadrilateral based on the two adjacent edges between the two adjacent reference patterns; and obtaining the self-feature information of the virtual quadrilateral, and taking the self-feature information of the virtual quadrilateral as the associated feature information between the two adjacent reference patterns.

12. The layout modification method according to claim 9 or 11, wherein The self-feature information comprises vertex information of a pattern and information of each edge of the pattern.

13. The layout modification method of claim 12, wherein, The information of each edge of the pattern is represented by the two relative vertex information of each edge.

14. The layout modification method of claim 7, wherein, The method for searching the historical correction region according to the comparison of the feature information in the first search range data comprises: dividing the second local region into a first region and a plurality of second regions, the first region is a square constructed with the error point as the center coordinate point, and a plurality of second regions are sequentially surrounded with the first region as the reference, and the second region located at the innermost side surrounds the first region; the feature information of a plurality of reference patterns in the first region is the same as the feature information of the patterns in the corresponding region in the historical correction region; the feature information of a plurality of reference patterns in a plurality of second regions is not more than a preset error rate from the feature information of the patterns in the corresponding region in the historical correction region, and the error rate is positively correlated with the distance between the second region and the error point.

15. The layout modification method of claim 14, wherein, The area ratio of the first region to the second local region is 65% to 75%.

16. The layout modification method of claim 14, wherein, The range of the preset error rate is 5%.

17. A storage medium having stored thereon computer instructions, characterized in that, The computer instructions perform the steps of the method of any one of claims 1 to 16 when running.

18. A terminal comprising a memory and a processor, said memory having stored thereon computer instructions capable of running on said processor, characterized in that, The processor performs the steps of the method of any one of claims 1 to 16 when running the computer instructions.

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