Csd coding multiplier optimization structure for fft processor

Abstract

The application discloses a CSD coding multiplier optimization structure for an FFT processor and belongs to the technical field of coding multiplier optimization, in particular to a CSD coding multiplier optimization structure for an FFT processor.The application provides a CSD coding multiplier optimization structure for an FFT processor.The application comprises a first control logic line and a second control logic line, characterized in that the first control logic line controls selection of multiplication by 1 or multiplication calculation of input data, and the second control logic line controls selection of multiplication by 1 or multiplication by '-j'; the control logic is solved by using a Karnaugh map; and the CSD coding multiplier is controlled by the first control logic line and the second control logic line, so that complex multiplication operation is completed at a correct clock.

Description

Technical Field

[0001] This invention belongs to the field of code multiplier optimization technology, and particularly relates to a CSD code multiplier optimization structure for FFT processors. Background Technology

[0002] FFT processors are widely used in fields such as spectrum analysis, image processing, speech recognition, biomedicine, radar, filtering, and wireless and wired communications. The multiplier is the unit module in an FFT processor that consumes a significant amount of hardware resources; therefore, controlling its hardware cost has become a research focus for many scholars. Because CSD-encoded multipliers consume few hardware resources and are easy to implement, they are often used in FFT processor design.

[0003] Currently, the control logic of the CSD-encoded multiplier implemented in the FFT processor is to directly control it according to the system clock, and to complete the complex multiplication operation of the input data and the rotation factor according to the rhythm of the system clock.

[0004] Complex multiplication in the FFT processor is controlled by the system clock 'CLK'. It processes the complex multiplication of input data and the rotation factor according to the 'CLK' clock cycle. The table below shows the radix-2 multiplication under system clock 'CLK' control. 2 The calculation process of the 8-point FFT algorithm.

[0005]

[0006]

[0007] As shown in the table above, the 3-bit system clock 'CLK' controls the butterfly unit and complex multiplication calculations. 'R' represents the data buffer unit. In the first 4 clock cycles, data x(0-3) sequentially enters a 4-unit buffer unit, waiting for the next clock cycle and x(4-7) to complete the BFI butterfly operation. After the butterfly operation, the data enters the next stage for the BFI and BFII butterfly operations. The last stage completes the BFI, BFII, and twiddle factor W8. 1 Complex number multiplication operations.

[0008] When using a CSD-encoded multiplier in an FFT processor operating scenario, previous research on control logic directly utilized the system clock 'CLK' to control the complex multiplication of the rotation factor based on the value of the corresponding clock cycle, as shown in the following code (using Verilog HDL for hardware description of the 8-point SDFFFT complex multiplication stage):

[0009] case(clk)

[0010] 3'b001:

[0011] begin

[0012] out_re = in_im;

[0013] out_im = -in_re;

[0014] end

[0015] / / When CLK=001, perform rotation factor W8 2 Complex number multiplication, where out_re, out_im, in_re, and in_im correspond to the real and imaginary parts of the input and output data, respectively.

[0016] 3'b011:

[0017] begin

[0018] out_re = w8_out_re;

[0019] out_im = w8_out_im;

[0020] end

[0021] / / When CLK=011, perform rotation factor W8 1 Complex multiplication operations, where w8_out_re and w8_out_im correspond to the input data and W8... 1 The real and imaginary parts after multiplication / /

[0022] 3'b101:

[0023] begin

[0024] out_re = w8_out_im;

[0025] out_im = -w8_out_re;

[0026] end

[0027] / / When CLK=101, perform rotation factor W8 3 Complex number multiplication operations / / . Summary of the Invention

[0028] This invention addresses the aforementioned problems by providing an optimized CSD-encoded multiplier structure for FFT processors.

[0029] To achieve the above objectives, the present invention adopts the following technical solution: the present invention includes a first control logic line and a second control logic line, characterized in that the first control logic line controls whether the input data is multiplied by 1 or by W8. 1The calculation involves two control logic lines: the second line controls whether to perform multiplication by 1 or multiplication by '-j' (the -j operation is a simple operation, which only requires swapping the positions of the real and imaginary parts of the complex number sequence and then inverting the imaginary part); the control logic is solved using a Karnaugh map; the CSD encoder multiplier is controlled by the first and second control logic lines to complete the complex multiplication operation at the correct clock.

[0030] As a preferred embodiment, the Karnaugh map described in this invention is as follows:

[0031]

[0032] C2, C1, and C0 represent the individual bits of the 3-bit 'CLK' clock. The logic output of the first control logic line is the value on the left side of the table, and the logic output of the second control logic line is the value on the right side of the table. By analyzing the relationship between the input and output of the Karnaugh map, the relationship between the output control logic and the system clock 'CLK' can be derived.

[0033] The control logic for the first control logic line is: in The second control logic line represents the XOR logic; the control logic of the second control logic line is... in Invert 'C1'; after obtaining the control logic, fill the logic expression into the two control logic positions of the CSD-encoded complex multiplier in the TOP file.

[0034] As another preferred embodiment, the code for filling the logical expression into the two control logic points of the CSD-encoded complex multiplier in the TOP file, as described in this invention, is as follows:

[0035] bf2i_1i2(bf1_re,bf1_im,

[0036] xn_re,xn_im,clk,clr,qqq[2]);

[0037] / / Complete the first stage of butterfly operation / /

[0038] bf2ii_1i3(bf2_re,bf2_im,bf1_re,

[0039] bf1_im,clk,clr,t1[2],t1[1]);

[0040] / / Complete the second stage of butterfly operation / /

[0041] w8csd i4(tw_re,tw_im,bf2_re,bf2_im,

[0042] (t2[2]^t2[1])&t2[0],~t2[1]&t2[0]);

[0043] / / Use the CSD complex multiplier to perform rotation factor operations / /

[0044] bf2i_2i5(Xk_re,Xk_im,tw_re,

[0045] tw_im,clk,clr,t2[0]);

[0046] / / Complete the final output / / .

[0047] The beneficial effects of this invention.

[0048] Based on the CSD representation relationship between the clock and the rotation factor constant, this invention optimizes the control logic and calculates the 'CLK' clock control logic ahead of time. By adding simple logic circuits, it can significantly reduce the hardware resources occupied by the CSD-encoded multiplier in the FFT processor hardware implementation. Furthermore, since the design and implementation of a long-point FFT processor includes multiple CSD-encoded multipliers, the optimized structure of this invention can amplify these effects, further reducing the hardware resource consumption of the FFT processor and making it more suitable for applications with low hardware cost requirements. Attached Figure Description

[0049] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0050] Figure 1 It is the base 2 in RTLViewer that adopts the optimized structure of this invention. 2 Algorithm 8-point SDFFFT architecture diagram. Detailed Implementation

[0051] This invention includes a first control logic line and a second control logic line. The first control logic line controls whether the input data is multiplied by 1 or by W8. 1 The calculation, the second control logic line controls whether to perform the multiplication by 1 or multiplication by '-j' (because... Karnaugh maps are used to solve the control logic.

[0052] The Karnaugh map is as follows: The Karnaugh map below is the control logic solution for a CSD-encoded multiplier adapted to an 8-point FFT.

[0053]

[0054] C2, C1, and C0 represent the individual bits of the 3-bit 'CLK' clock. The logic output of the first control logic line is the value on the left side of the table, and the logic output of the second control logic line is the value on the right side of the table. By analyzing the relationship between the input and output of the Karnaugh map, the relationship between the output control logic and the system clock 'CLK' can be derived.

[0055] The control logic for the first control logic line is: in The second control logic line represents the XOR logic; the control logic of the second control logic line is... in Invert 'C1'; after obtaining the control logic, fill the logic expression into the two control logic positions of the CSD-encoded complex multiplier in the TOP file.

[0056] The code for filling the logical expression into the two control logic sections of the CSD-encoded complex multiplier in the TOP file is as follows:

[0057] bf2i_1i2(bf1_re,bf1_im,

[0058] xn_re,xn_im,clk,clr,qqq[2]);

[0059] / / Complete the first stage of butterfly operation / /

[0060] bf2ii_1i3(bf2_re,bf2_im,bf1_re,

[0061] bf1_im,clk,clr,t1[2],t1[1]);

[0062] / / Complete the second stage of butterfly operation / /

[0063] w8csd i4(tw_re,tw_im,bf2_re,bf2_im,

[0064] (t2[2]^t2[1])&t2[0],~t2[1]&t2[0]); This is the optimized control logic expression for the CSD-encoded complex multiplier;

[0065] / / Use the CSD complex multiplier to perform rotation factor operations / /

[0066] bf2i_2i5(Xk_re,Xk_im,tw_re,

[0067] tw_im,clk,clr,t2[0]);

[0068] / / Complete the final output / / .

[0069] Figure 1 The part enclosed in the middle frame is the simple logic circuit that needs to be added for the pre-calculated control logic proposed in this invention (the "logic circuit" is added after the second stage butterfly operation is completed and before the CSD-encoded multiplier is used to complete the rotation factor operation) (i.e. the first control logic line and the second control logic line). The CSD-encoded complex multiplier is controlled by the two control logic lines to complete the complex multiplication operation at the correct clock.

[0070] Furthermore, regardless of how the FFT point count increases, if a CSD-encoded multiplier is used for the rotation factor... This optimization logic is universal. For example, when calculating a 16-point FFT, if a rotation factor is used... The complex number multiplication operation has two control logic lines, and their control logic is as follows: And so on.

[0071] The optimization scheme proposed in this invention is not limited to calculating the rotation factor. CSD-encoded complex multipliers, also applicable to twitch factors CSD-encoded complex multipliers, specific optimization schemes and rotation factors The same applies, so I won't go into details.

[0072] In tests using the proposed solution (based on the QUARTUSPRIME platform): when implementing 8-point, 16-point, 32-point, and 64-point FFT processors, the hardware resources consumed can be reduced by 3%, 9%, 17%, and 26% respectively compared to traditional control logic, as shown in the table below:

[0073] Hardware cost comparison before and after optimization

[0074]

[0075] It is understood that the above specific description of the present invention is only for illustrating the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effect; as long as the use needs are met, they are all within the protection scope of the present invention.

Claims

1. An optimized structure for a CSD-encoded multiplier in an FFT processor, comprising a first control logic line and a second control logic line, characterized in that... The first control logic line controls whether the input data is multiplied by 1 or multiplied by 2. The calculation, the second control logic line controls whether to perform multiplication by 1 or multiplication by... The calculation is performed; the control logic is solved using Karnaugh maps; the CSD encoder multiplier is controlled by the first and second control logic lines to perform complex multiplication operations at the correct clock. The Karnaugh map is as follows: ； , and This represents each bit of the 3-bit 'CLK' clock. The logic output of the first control logic line is the value on the left side of the table, and the logic output of the second control logic line is the value on the right side of the table. By using the Karnaugh map to determine the relationship between the output control logic and the system clock 'CLK', we can derive the relationship between the output control logic and the system clock 'CLK'. The control logic for the first control logic line is: ,in The second control logic line represents XOR logic; the control logic of the second control logic line is... ,in represent Invert the expression; after obtaining the control logic, fill the logical expression into the two control logic fields of the CSD-encoded complex multiplier in the TOP file. The two control logics of the CSD-encoded complex multiplier function as follows: first, complete the first stage butterfly operation of bf2i and bf1, and then complete the second stage butterfly operation of bf2ii and bf2. Next, the CSD complex multiplier is used to perform the rotation factor W8 operation, and the final output is completed. The simple logic circuit required for the control logic is pre-calculated. This logic circuit is added after the second-stage butterfly operation is completed and before the CSD-encoded multiplier performs the rotation factor operation. The CSD-encoded complex multiplier is controlled by two control logic lines to complete the complex multiplication operation at the correct clock.

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