Shift register, display panel, and display device

Abstract

Embodiments of the present invention provide a shift register, a display panel, and a display device. The shift register includes a first output tube, a control terminal of the first output tube coupled to a first node, a first terminal of the first output tube coupled to a first clock signal terminal, and a second terminal of the first output tube coupled to an output terminal of the shift register. During an operating cycle of the shift register, the second terminal of the first output tube provides a first-level signal to the output terminal of the shift register, which serves as an enable signal for the shift register. The shift register also includes a capacitance reduction module connected between the first node and the control terminal of the first output tube, and configured to reduce the capacitance of a capacitor coupled to the first terminal of the first output tube after the shift register outputs the enable signal. The present invention can reduce the power consumption of the shift register.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a display panel and a display device. Background Art

[0002] With the development of communication technology, the functions of electronic devices such as mobile phones and tablets are becoming more and more abundant, and users are using electronic devices for longer and longer periods of time. The power consumption of electronic devices has also become an important indicator to measure their working performance. Summary of the Invention

[0003] Embodiments of the present invention provide a shift register, a display panel, and a display device to solve the technical problem of high power consumption of a shift driving circuit in the prior art.

[0004] In a first aspect, an embodiment of the present invention provides a shift register, comprising a first output tube, wherein a control terminal of the first output tube is coupled to a first node, a first terminal of the first output tube is coupled to a first clock signal terminal, and a second terminal of the first output tube is coupled to an output terminal of the shift register; during a working cycle of the shift register, a first level signal provided by the second terminal of the first output tube to the output terminal of the shift register is an enable signal output by the shift register;

[0005] The shift register also includes a capacitance reduction module, which is connected between the first node and the control end of the first output tube. The capacitance reduction module is used to reduce the capacitance value of the capacitor coupled to the first end of the first output tube after the shift register outputs an enable signal.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display panel, the display panel includes a shift drive circuit, and the shift drive circuit includes the shift register provided by any embodiment of the present invention.

[0007] In a third aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0008] The shift register, display panel, and display device provided by the embodiments of the present invention have the following beneficial effects: a capacitance reduction module is provided in the shift register, and the capacitance reduction module is connected between the first node and the control end of the first output tube. The capacitance reduction module can reduce the capacitance value of the capacitor coupled to the first end of the first output tube after the output end of the shift register outputs an enable signal. When the first end of the first output tube receives a first clock signal, the capacitance reduction module can reduce the capacitance value of the capacitor receiving the first clock signal. After the capacitance value of the capacitor is reduced, the power consumption generated by charging and discharging under the influence of the first clock signal is also reduced, thereby achieving the effect of reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 It is a simplified schematic diagram of a shift register in the prior art;

[0011] Figure 2 for Figure 1 Timing diagram of the shift register in the figure;

[0012] Figure 3 A simplified schematic diagram of a shift register provided by an embodiment of the present invention;

[0013] Figure 4 A timing diagram of a shift register provided by an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of another shift register provided by an embodiment of the present invention;

[0015] Figure 6 for Figure 5 A timing diagram of a shift register provided in an embodiment;

[0016] Figure 7 A schematic diagram of another shift register provided by an embodiment of the present invention;

[0017] Figure 8 A schematic diagram of another shift register provided by an embodiment of the present invention;

[0018] Figure 9 for Figure 8 A timing diagram of a shift register provided in an embodiment;

[0019] Figure 10 A schematic diagram of another shift register provided by an embodiment of the present invention;

[0020] Figure 11 for Figure 10 A timing diagram of a shift register provided in an embodiment;

[0021] Figure 12 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0022] Figure 13 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0025] The display panel is equipped with a shift drive circuit, which includes multiple cascaded shift registers. The shift registers provide enable signals to scan lines to drive the pixel rows connected to the scan lines for display. The shift drive circuit is used to drive the multiple pixel rows in the panel row by row to display a single frame of image. Figure 1 FIG. 1 is a simplified schematic diagram of a shift register in the prior art. Figure 2 for Figure 1 The timing diagram of the shift register in FIG. Figure 1 As shown, the shift register 01 includes a first output tube 011 and a second output terminal 012. The control terminal of the first output tube 011 is connected to the first node N1' and the first terminal receives the clock signal CK'. The control terminal of the second output terminal 012 is connected to the second node N2' and the first terminal receives the high level signal VGH'. The first output tube 011 and the second output terminal 012 are both connected to the output terminal OUT of the shift register 01. 01 The first voltage stabilizing capacitor C1′ is connected to the first node N1′ and the output terminal OUT 01 The second voltage stabilizing capacitor C2′ is connected between the second node N2′ and the output high level signal VGH′. The first output tube 011 and the second output terminal 012 are both p-type transistors, and the output terminal OUT 01 For example, the output low-level signal is the enable signal for driving the scan line. Figure 2 As shown, during the operation of the shift register 01, the input terminal IN of the shift register 01 01 After inputting a low-level signal, at time t', the first node N1' is at a low potential and the second node N2' is at a high potential. The first output tube 011 is turned on and the second output terminal 012 is turned off. The first output tube 011 provides the low-level signal provided by the clock signal CK' to the output terminal OUT. 01 , output terminal OUT 01Output low level enable signal; after time t', the output terminal OUT 01 Continuously output high level signal until the input terminal IN 01 Input a low-level signal again.

[0026] In the shift register 01, the size of the first output transistor 011 is larger than that of other switch transistors ( Figure 1 (not shown), resulting in a large parasitic capacitance between the control terminal and the first terminal of the first output transistor 011. The first terminal of the first output transistor 011 receives the clock signal CK', which is a pulse signal with frequent high and low level jumps. During the operating cycle of the shift register 01, after it outputs an enable signal once, the parasitic capacitance of the first output transistor 011 is frequently charged and discharged under the influence of the clock signal CK', affecting the power consumption of the shift register 01.

[0027] High-frequency display can achieve excellent visual effects when displaying dynamic images. This is especially true in gaming scenarios, where smooth dynamic images can be displayed to provide users with a high-quality visual experience. Therefore, high-frequency display is one of the more important functions in display-type electronic products. However, high-frequency display requires that the frequency of the output enable signal of the shift register 01 be increased, and the frequency of the high and low level changes of the clock signal CK′ also be increased. As a result, the frequency of the charge and discharge of the parasitic capacitance of the first output tube 011 under the influence of the clock signal CK′ increases, further increasing power consumption.

[0028] In order to solve the problems existing in the prior art, a capacitance reduction module is provided in the shift register provided in an embodiment of the present invention. The capacitance reduction module is connected between the first node and the control end of the first output end. After the shift register outputs an enable signal, the capacitance reduction module is used to reduce the capacitance value of the capacitor receiving the clock signal. The capacitor with a smaller capacitance value is charged and discharged under the influence of the clock signal, thereby achieving the effect of reducing power consumption.

[0029] Figure 3 A simplified schematic diagram of a shift register provided by an embodiment of the present invention is provided. Figure 4 A timing diagram of a shift register provided by an embodiment of the present invention. Figure 3 As shown, the shift register includes a first output tube 10, a control terminal of the first output tube 10 is coupled to a first node N1, a first terminal of the first output tube 10 is coupled to a first clock signal terminal CK, and a second terminal of the first output tube 10 is coupled to an output terminal OUT of the shift register. During a working cycle of the shift register, the second terminal of the first output tube 10 provides a first level signal to the output terminal OUT of the shift register, which is an enable signal output by the shift register. The first level signal is a low level signal or a high level signal. The enable signal is used to control the operation of devices connected to the shift register.

[0030] The shift register also includes a capacitance reduction module 20, which is connected between the first node N1 and the control end of the first output tube 10. The capacitance reduction module 20 is used to reduce the capacitance value of the capacitor coupled to the first end of the first output tube 10 after the shift register outputs an enable signal. The first end of the first output tube 10 receives the first clock signal CK, and the capacitance reduction module 20 can reduce the capacitance value of the capacitor receiving the first clock signal CK after the shift register outputs the enable signal.

[0031] like Figure 3 As shown, the shift register further includes a second output transistor 30, a control terminal of the second output transistor 30 coupled to the second node N2, a first terminal of the second output transistor 30 coupled to the first constant voltage V1, and a second terminal of the second output transistor 30 coupled to the output terminal OUT of the shift register. The shift register further includes a first stabilizing capacitor C1 and a second stabilizing capacitor C2. The first stabilizing capacitor C1 is connected between the first node N1 and the output terminal OUT, and the first stabilizing capacitor C1 is used to stabilize the potential of the first node N1. The second stabilizing capacitor C2 is connected between the second node N2 and the first terminal of the second output transistor 30, and the second stabilizing capacitor C2 is used to stabilize the potential of the second node N2. The shift register further includes an input control unit 40. The first node N1 and the second node N2 are respectively connected to the input control unit 40. The output terminal IN of the shift register is connected to the input control unit 40. The input control unit 40 is used to control the potentials of the first node N1 and the second node N2, respectively.

[0032] Figure 3 In the example, the first output tube 10 and the second output tube 30 are both p-type transistors. Figure 4 In the example, the first level signal is a low level signal, that is, the low level signal output by the shift register is an enable signal. Figure 4 As shown, at the first moment t1, a low-level signal is input to the input terminal IN, and the output terminal OUT outputs a high-level signal. Optionally, at this moment, both the first node N1 and the second node N2 are at a low potential. The first node N1 provides the low-level signal to the control terminal of the first output transistor 10 via the capacitance reduction module 20 to control the first output transistor 10 to turn on. After the first output transistor 10 turns on, it provides a high-level signal to the output terminal OUT. The second node N2 is at a low potential, controlling the second output transistor 30 to turn on. After the second output transistor 30 turns on, it provides the high-level signal of the first constant voltage V1 to the output terminal OUT. Optionally, the first constant voltage V1 is a positive power supply voltage. This causes the output terminal OUT to output a high-level signal. At the second moment t2, the first node N1 remains at a low potential, and the second node N2 is written to a high potential. The second output transistor 30 is turned off. After the first output transistor 10 turns on, it provides the low-level signal provided by the clock signal CK to the output terminal OUT. At this time, the output terminal OUT outputs the low-level first-level signal as an enable signal.

[0033] The shift register provided by an embodiment of the present invention includes a capacitance reduction module 20, which is connected between a first node N1 and a control end of a first output tube 10. The capacitance reduction module 20 can reduce the capacitance value of a capacitor coupled to a first end of the first output tube 10 after an enable signal is output from an output end OUT of the shift register. When the first end of the first output tube 10 receives a first clock signal CK, the capacitance reduction module 20 can reduce the capacitance value of the capacitor receiving the first clock signal CK. After the capacitance value of the capacitor is reduced, the power consumption generated by charging and discharging under the influence of the first clock signal CK is also reduced, thereby achieving the effect of reducing power consumption.

[0034] In some embodiments, Figure 5 Another shift register schematic diagram provided by an embodiment of the present invention is as follows: Figure 5 As shown, the capacitance reduction module 20 includes a switch submodule 21 and a capacitor submodule 22; the switch submodule 21 is used to disconnect the path between the first output tube 10 and the first node N1 after the shift register outputs the enable signal; the capacitor submodule 22 is used to form a series circuit with the first parasitic capacitor Cgs of the first output tube 10 after the shift register outputs the enable signal, and the first parasitic capacitor Cgs is a parasitic capacitance between the control end and the first end of the first output tube 10. Figure 5 The first parasitic capacitor Cgs is shown in FIG. 1 , which is connected by a dotted line. In the embodiment of the present invention, the switch submodule 21 and the capacitor submodule 22 cooperate to disconnect the path between the first node N1 and the control terminal of the first output tube 10 by using the switch submodule 21. Only then can the capacitor submodule 22 form a series circuit with the first parasitic capacitor Cgs, thereby allowing the series circuit to receive the first clock signal CK and utilizing the series circuit to reduce the capacitance of the capacitor receiving the first clock signal CK. In a solution where the capacitance reduction module 20 is not provided, the first parasitic capacitor Cgs receives the first clock signal CK. After the shift register outputs the enable signal, the first clock signal CK controls the charging and discharging of the first parasitic capacitor Cgs. Due to the large capacitance of the first parasitic capacitor Cgs, the charging and discharging power consumption is relatively large. In an embodiment of the present invention, a capacitance reduction module 20 is provided. After the shift register outputs an enable signal, the capacitor submodule 22 forms a series circuit with the first parasitic capacitor Cgs. The principle that the total capacitance value is reduced after the capacitors are connected in series is utilized to reduce the capacitance value of the capacitor receiving the first clock signal CK. After the capacitance value of the capacitor is reduced, the power consumption generated by charging and discharging under the influence of the first clock signal CK is also reduced, thereby achieving the effect of reducing power consumption.

[0035] In some embodiments, as Figure 5As shown, the switch submodule 21 includes a first switch transistor T1, and the capacitor submodule 22 includes a first capacitor C3. The first terminal of the first switch transistor T1 is coupled to the first node N1, and the second terminal of the first switch transistor T1 is coupled to the control terminal of the first output transistor 10. The control terminal of the first switch transistor T1 is coupled to the first control terminal K1. The first plate of the first capacitor C3 is coupled to the control terminal of the first output transistor 10, and the second plate of the first capacitor C3 is coupled to the first signal terminal D1. The first signal terminal D1 provides a constant voltage signal. In the working cycle of the shift register, the first control terminal K1 provides a signal to control the first switch transistor T1 to turn on at least when the first output transistor 10 needs to output a first level signal (low level signal), and provides a signal to control the first switch transistor T1 to turn off during the period after the first output transistor 10 outputs the first level signal.

[0036] Figure 6 for Figure 5 A timing diagram of a shift register provided in the embodiment, combined with Figure 6 To understand the working mode of the first switch tube T1. Figure 6 As shown, at the second moment t2, the first output transistor 10 turns on and provides the first level signal provided by the first clock signal CK to the output terminal OUT of the shift register. The second moment t2 is the moment when the output terminal OUT of the shift register outputs the enable signal. At the second moment t2, the first control terminal K1 provides a low level signal to control the first switch transistor T1 to turn on, thereby ensuring that the first node N1 is electrically connected to the control terminal of the first output transistor 10. The first output transistor 10 is then turned on under the control of the potential of the first node N1, ensuring that the shift register can normally output the enable signal. After the shift register outputs the enable signal, that is, after the second moment t2, the first control terminal K1 provides a high level signal to control the first switch transistor T1 to turn off. After the first switch transistor T1 is turned off, the path between the control terminal of the first output transistor 10 and the first node N1 is disconnected. At this time, the first parasitic capacitor Cgs of the first output transistor 10 forms a series circuit with the first capacitor C3. The total capacitance value of the first parasitic capacitor Cgs and the first capacitor C3 connected in series is less than the capacitance value of the first parasitic capacitor Cgs, thereby reducing the capacitance value of the capacitor receiving the first clock signal CK. After the capacitance value of the capacitor is reduced, the power consumption generated by charging and discharging under the influence of the first clock signal CK is also reduced, thereby achieving the effect of reducing power consumption.

[0037] In some embodiments, Figure 7 Another shift register schematic diagram provided by an embodiment of the present invention is as follows: Figure 7 As shown, the control terminal of the first switch tube T1 is coupled to the first node N1, which is multiplexed as the first control terminal K1. In this embodiment, the working state of the first switch tube T1 is controlled by the potential of the first node N1. The type of the first switch tube T1 is the same as that of the first output tube 10. Figure 7 In the figure, the first switch transistor T1 and the first output transistor 10 are both p-type transistors. When the first node N1 is at a low voltage, the first switch transistor T1 is turned on, and the first node N1 is electrically connected to the control terminal of the first output transistor 10. When the shift register needs to output an enable signal, the first output transistor 10 can be controlled by the voltage of the first node N1 to turn on and provide a first-level signal to the output terminal OUT. When the first node N1 is at a high voltage, the first node N1 controls the first switch transistor T1 to turn off. After the first switch transistor T1 is turned off, the path between the control terminal of the first output transistor 10 and the first node N1 is disconnected. At this time, the first parasitic capacitance Cgs of the first output transistor 10 forms a series circuit with the first capacitor C3, thereby reducing the capacitance value of the capacitor receiving the first clock signal CK. In this embodiment, the control terminal of the first switch transistor T1 is coupled to the first node N1. The first switch transistor T1 can cooperate with the operation of the first output transistor 10 to ensure that the shift register outputs the enable signal. The first switch transistor T1 can also cooperate with the operation of the first capacitor C3 to form a series circuit with the first parasitic capacitor Cgs, thereby reducing the capacitance of the capacitor receiving the first clock signal CK, thereby reducing power consumption. In addition, this embodiment can reduce the number of signals required for the shift register to operate, which can reduce the amount of wiring in electronic products and reduce wiring complexity.

[0038] In some other embodiments, the control terminal of the first switch tube T1 is coupled to the first node N1 , and the first switch tube T1 and the first output tube 10 are both n-type transistors, which are not illustrated in the drawings here.

[0039] In some embodiments, Figure 8 A schematic diagram of another shift register provided by an embodiment of the present invention is shown. Figure 9 for Figure 8 A timing diagram of a shift register provided in the embodiment, such as Figure 8As shown, the control terminal of the first switch transistor T1 is coupled to the first node N1, which is multiplexed as the first control terminal K1. The input control unit 40 in the shift register also includes an input transistor T2, a second switch transistor T3, and a third switch transistor T4. The control terminal of input transistor T2 is coupled to the second clock signal terminal XCK, which provides the second clock signal XCK. For ease of illustration and description, the second clock signal terminal XCK and the second clock signal XCK are labeled the same. The duty cycle of the low-level signal in the second clock signal XCK and the first clock signal CK is the same. The first terminal of input transistor T2 is coupled to the input terminal IN of the shift register, and the second terminal of the input terminal is coupled to the first node N1. The control terminal of the second switch transistor T3 is connected to the first node N1, the first terminal is connected to the second clock signal terminal XCK, and the second terminal is connected to the second node N2. The control terminal of the third switch transistor T4 is connected to the second clock signal terminal XCK, the first terminal receives the second constant voltage V2, and the second terminal is connected to the second node N2. The second constant voltage V2 and the first constant voltage V1 are respectively a positive power supply voltage and a negative power supply voltage.

[0040] Figure 8 In the embodiment, each transistor in the shift register is a p-type transistor. Figure 9 The timing diagram in the figure can help us understand the working process of the shift register. Figure 9 As shown, at first moment t1: input transistor T2 turns on under the control of the second clock signal XCK and writes the low-level signal input from input terminal IN to the first node N1. The low-level signal at first node N1 controls the first switch transistor T1 to turn on, creating a path between first node N1 and the control terminal of first output transistor 10. First output transistor 10 turns on under the control of the potential of first node N1 and provides the high-level signal of the first clock signal CK to output terminal OUT. After input transistor T2 turns on, it writes the low-level signal to the control terminal of second switch transistor T3. Second switch transistor T3 turns on and writes the low-level signal input from its first terminal to second node N2. The second clock signal XCK also controls the third switch transistor T4 to write the second constant voltage V2 to second node N2. The second constant voltage V2 is a low-level voltage, while the first constant voltage V1 is a high-level voltage. During this period, second node N2 is at a low level, and second output transistor 20 turns on, providing the high-level signal of the first constant voltage V1 to output terminal OUT. During this period, output terminal OUT outputs a high-level signal.

[0041] At the second time t2, the second clock signal XCK controls the input transistor T2 to turn off, maintaining the low level of the first node N1 at the first time t1. Simultaneously, the high level of the second clock signal XCK controls the first switch transistor T1 to turn on, electrically connecting the first node N1 to the control terminal of the first output transistor 10. The first output transistor 10 is then turned on under the control of the potential of the first node N1. After turning on, the first output transistor 10 provides the low level of the first clock signal CK to the output terminal OUT. Furthermore, the low level of the first node N1 controls the second switch transistor T3 to turn on, writing the high level of the second clock signal XCK to the second node N2. At this time, the third switch transistor T4 is off, the second node N2 is at a high level, and the second output transistor 30 is turned off. During this period, the output terminal OUT outputs a low level signal, which serves as an enable signal.

[0042] After the second time t2 and before the input terminal IN inputs a low-level signal again, when the second clock signal XCK provides a low-level signal to control the input tube T2 to turn on, the high-level signal provided by the input terminal IN is written to the first node N1. The high potential of the first node N1 controls the first switch tube T1 to turn off, thereby disconnecting the path between the first node N1 and the control terminal of the first output tube 10. At this time, the first capacitor C3 and the first parasitic capacitor Cgs form a series circuit. By utilizing the principle that the total capacitance value of capacitors connected in series is reduced, the capacitance value of the capacitor receiving the first clock signal CK is reduced. After the capacitance value of the capacitor is reduced, the power consumption generated by the charging and discharging of the capacitor under the influence of the first clock signal CK is also reduced, thereby achieving the effect of reducing power consumption.

[0043] In other embodiments, Figure 10 A schematic diagram of another shift register provided by an embodiment of the present invention is shown. Figure 11 for Figure 10 A timing diagram of a shift register provided in the embodiment, such as Figure 10 As shown, the control terminal of the first switch transistor T1 is coupled to the second clock signal terminal XCK, and the second clock signal terminal XCK is multiplexed into the first control terminal K1. The input control unit 40 in the shift register includes an input transistor T2, a second switch transistor T3, and a third switch transistor T4. The control terminal of the input transistor T2 is coupled to the second clock signal terminal XCK, the first terminal of the input transistor T2 is coupled to the input terminal IN of the shift register, and the second terminal of the input terminal is coupled to the first node N1.

[0044] Figure 10 The first switch tube T1 is an n-type transistor, and the first output tube 10 is a p-type transistor. Figure 11 To understand the working process of the shift register.

[0045] At the first moment t1, input transistor T2 turns on under the control of the low-level signal of the second clock signal XCK, writing the low-level signal input from input terminal IN to the first node N1. The low-level signal of the second clock signal XCK controls the first switch transistor T1 to turn off, disconnecting the path between the first node N1 and the control terminal of the first output transistor 10. After turning on, input transistor T2 writes the low-level signal to the control terminal of the second switch transistor T3. The second switch transistor T3 turns on and writes the low-level signal input from its first terminal to the second node N2. The second clock signal XCK also controls the third switch transistor T4 to write the second constant voltage V2 to the second node N2. The second constant voltage V2 is a low-level voltage, and the first constant voltage V1 is a high-level voltage. During this period, the second node N2 is at a low level, and the second output transistor 20 turns on, providing the high-level signal of the first constant voltage V1 to the output terminal OUT, which then outputs a high-level signal.

[0046] At the second time t2, the second clock signal XCK controls the input transistor T2 to turn off, maintaining the low level of the first node N1 at the first time t1. Simultaneously, the high level of the second clock signal XCK controls the first switch transistor T1 to turn on, electrically connecting the first node N1 to the control terminal of the first output transistor 10. The first output transistor 10 is then turned on under the control of the potential of the first node N1. After turning on, the first output transistor 10 provides the low level of the first clock signal CK to the output terminal OUT. Furthermore, the low level of the first node N1 controls the second switch transistor T3 to turn on, writing the high level of the second clock signal XCK to the second node N2. At this time, the third switch transistor T4 is off, the second node N2 is at a high level, and the second output transistor 30 is turned off. During this period, the output terminal OUT outputs a low level signal, which serves as an enable signal.

[0047] After the second time t2 and before the input terminal IN inputs a low-level signal again, during the period when the second clock signal XCK provides a low-level signal to control the first switch tube T1 to be turned off, the path between the first node N1 and the control terminal of the first output tube 10 is disconnected. At this time, the first capacitor C3 and the first parasitic capacitor Cgs form a series circuit. By utilizing the principle that the total capacitance value of capacitors connected in series is reduced, the capacitance value of the capacitor receiving the first clock signal CK is reduced. After the capacitance value of the capacitor is reduced, the power consumption generated by the charging and discharging of the capacitor under the influence of the first clock signal CK is also reduced, thereby achieving the effect of reducing power consumption.

[0048] In other embodiments, the first switch tube T1 is a p-type transistor, the first output tube 10 is an n-type transistor, and the control terminal of the first switch tube T1 is coupled to the second clock signal terminal XCK. The figure is not shown here. The working process can also be combined with Figure 11 The embodiments are for comprehension only and will not be described in detail here.

[0049] In some embodiments, the first signal terminal D1 provides a constant voltage signal. Such a setting can ensure the stability of the potential of the control terminal of the first output tube 10 when the first switch tube T1 is in the on state and the first output tube 10 needs to output the first level signal under the control of the potential of the first node N1, thereby ensuring that the first output tube 10 stably outputs the first level signal to the output terminal OUT, thereby ensuring the stable working performance of the shift register output enable signal.

[0050] In some embodiments, the first signal terminal D1 provides a low-level constant voltage signal. The signals received during operation of the shift register include a positive power supply signal and a negative power supply signal. Optionally, the first signal terminal D1 provides the negative power supply signal. Since the first capacitor C3 is connected to the control terminal of the first output transistor 10, the first output transistor 10 is turned on when the control terminal of the first output transistor 10 is at a low potential. Therefore, providing the first signal terminal D1 with a negative power supply signal is more conducive to ensuring the stability of the potential at the control terminal of the first output transistor 10 when it is turned on.

[0051] In some embodiments, as Figure 5 As shown, the shift register includes a first voltage-stabilizing capacitor C1, a first plate of the first voltage-stabilizing capacitor C1 is coupled to the first node N1, and a second plate of the first voltage-stabilizing capacitor C1 is coupled to the output terminal OUT of the shift register; the vertical distance between the first plate and the second plate of the first voltage-stabilizing capacitor C1 is d1, and the vertical distance between the first plate and the second plate of the first capacitor C3 is d2, d2≥d1. The shift register provided in the embodiment of the present invention is provided with a first capacitor C3 in the capacitance reduction module 20. After the enable signal is output during the working cycle of the shift register, the first capacitor C3 and the first parasitic capacitor Cgs of the first output tube 10 are connected in series to form a series circuit. The principle of reducing the total capacitance value after the capacitors are connected in series is used to reduce the capacitance value of the capacitor receiving the first clock signal CK, thereby reducing power consumption. In some applications, d2=d1, and the two plates of the first capacitor C3 can be respectively set on the same layer as the two plates of the first voltage-stabilizing capacitor C1, thereby simplifying the process. In other applications, d2>d1 can also be set, that is, two film layers with a larger spacing are used to make the first capacitor C3, and the vertical distance between the two plates in the first capacitor C3 is increased, thereby reducing the capacitance value of the first capacitor C3. The total capacitance value of the first voltage-stabilizing capacitor C1 and the first capacitor C3 after being connected in series is smaller, thereby further reducing the capacitance value of the capacitor receiving the first clock signal CK, thereby more significantly reducing the power consumption.

[0052] Take the application of a shift register in a display panel as an example for illustration. In some embodiments, the display panel includes a substrate, and a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer located on the substrate, wherein the first metal layer, the second metal layer, and the third metal layer are sequentially arranged away from the semiconductor layer. The active layer of the transistor is located in the semiconductor layer, one plate of the storage capacitor in the pixel circuit is located in the first metal layer, and the other plate is located in the second metal layer. The power line and data line in the display panel are arranged in the third metal layer. The two plates of the first stabilizing capacitor C1 in the shift register are located in the same layer as the two plates of the storage capacitor, that is, the first plate of the first stabilizing capacitor C1 is located in the first metal layer, and the second plate is located in the second metal layer. For the first capacitor C3, one plate of the first capacitor C3 can be located in the first metal layer and the other plate is located in the second metal layer; or one plate of the first capacitor C3 can be located in the first metal layer and the other plate is located in the third metal layer. In this way, d2>d1 is achieved, which can make the capacitance value of the first capacitor C3 smaller. Alternatively, one plate of the first capacitor C3 may be located in the second metal layer and the other plate may be located in the third metal layer, and the thickness of the insulating layer between the second metal layer and the third metal layer may be greater than the thickness of the insulating layer between the first metal layer and the second metal layer. In this way, d2>d1 can also be achieved.

[0053] In addition, it should be noted that Figure 8 and Figure 10 The input control unit 40 is illustrated as including only three transistors, and the present invention does not limit the structure of the input control unit 40. The solution of adding the capacitance reduction module 20 between the first node N1 and the first output terminal 10 in the embodiment of the present invention can be applied to any shift register in the prior art.

[0054] Based on the same inventive concept, an embodiment of the present invention provides a display panel, Figure 12 A schematic diagram of a display panel provided by an embodiment of the present invention, such as Figure 12 As shown, the display panel includes a shift drive circuit 50, which includes multiple cascaded shift registers 51. The shift registers are one of the types provided in any of the above embodiments. The display panel includes a display area AA and a non-display area NA. The shift drive circuit 50 is located in the non-display area NA, and the shift registers 51 are electrically connected to the gate lines 60 in the display area AA. Figure 12 In the figure, each end of a gate line 60 is connected to a shift register 51. In this embodiment, two sets of shift drive circuits 50 are provided for one type of gate line 60, that is, the gate line 60 is driven in a bilateral driving manner. In other embodiments, only one end of the gate line 60 is connected to the shift register 51, and the gate line 60 is driven in a unilateral driving manner. This is not illustrated in the figure here.

[0055] In addition, the display panel is provided with a scan driver circuit and a light driver circuit. The scan driver circuit is used to drive the scan lines, and the light driver circuit is used to drive the light control lines. Both the scan lines and the light control lines are connected to the pixel circuits. The scan driver circuit and / or the light driver circuit include the shift register provided by an embodiment of the present invention.

[0056] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Figure 13 A schematic diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 13 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, a mobile phone, a tablet, a laptop computer, a smart wearable product, or other display device.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shift register, characterized in that: The shift register includes a first output tube, a control terminal of the first output tube is coupled to the first node, a first terminal of the first output tube is coupled to the first clock signal terminal, and a second terminal of the first output tube is coupled to the output terminal of the shift register; During a working cycle of the shift register, the first level signal provided by the second end of the first output tube to the output end of the shift register is an enable signal output by the shift register; The shift register further includes a capacitance reduction module, the capacitance reduction module being connected between the first node and the control terminal of the first output transistor, the capacitance reduction module being configured to reduce the capacitance of the capacitor coupled to the first terminal of the first output transistor after the shift register outputs an enable signal; The capacitance reduction module includes a switch submodule and a capacitance submodule; The switch submodule is used to disconnect the path between the first output tube and the first node after the shift register outputs the enable signal; The capacitor submodule is used to form a series circuit with the first parasitic capacitor of the first output tube after the shift register outputs the enable signal. The first parasitic capacitor is a parasitic capacitor between the control end and the first end of the first output tube.

2. The shift register according to claim 1, wherein: The switch submodule includes a first switch tube, and the capacitor submodule includes a first capacitor; A first terminal of the first switching transistor is coupled to the first node, a second terminal of the first switching transistor is coupled to the control terminal of the first output transistor, and the control terminal of the first switching transistor is coupled to the first control terminal. During a working cycle of the shift register, the first control terminal provides a signal to control the first switching transistor to be turned on at least during a period when the first output transistor needs to output the first level signal, and the first control terminal provides a signal to control the first switching transistor to be turned off during a period after the first output transistor outputs the first level signal. The first plate of the first capacitor is coupled to the control terminal of the first output tube, and the second plate of the first capacitor is coupled to the first signal terminal.

3. The shift register according to claim 2, wherein: The control end of the first switch tube is coupled to the first node, and the first node is multiplexed as the first control end.

4. The shift register according to claim 3, wherein: The type of the first switching tube is the same as the type of the first output tube.

5. The shift register according to claim 2, wherein: The control terminal of the first switch tube is coupled to the second clock signal terminal, and the second clock signal line is multiplexed as the first control terminal; The shift register includes an input tube, a control end of the input tube is coupled to the second clock signal end, a first end of the input tube is coupled to the input end of the shift register, and a second end of the input end is coupled to the first node.

6. The shift register according to claim 5, wherein: One of the first switch tube and the first output tube is an n-type transistor, and the other is a p-type transistor.

7. The shift register according to claim 2, wherein: The first signal terminal provides a constant voltage signal.

8. The shift register according to claim 2, wherein: The shift register includes a first voltage-stabilizing capacitor, a first plate of the first voltage-stabilizing capacitor is coupled to the first node, and a second plate of the first voltage-stabilizing capacitor is coupled to an output terminal of the shift register; A vertical distance between the first plate and the second plate of the first voltage-stabilizing capacitor is d1, and a vertical distance between the first plate and the second plate of the first capacitor is d2, where d2≥d1.

9. A display panel, characterized in that: The invention comprises a shift drive circuit, wherein the shift drive circuit comprises the shift register according to any one of claims 1 to 8.

10. A display device, characterized in that: The display panel comprises the display panel according to claim 9.

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