Equalizer test method, circuit, apparatus, device, and storage medium

Abstract

The present disclosure provides an equalizer test method, circuit, device, equipment and storage medium, relating to the technical field of semiconductors. The method comprises: after turning off the current word line power supply of a chip, applying a sense amplifier control voltage to a sense amplifier to keep the sense amplifier open, the current word line being connected to the gate of a storage transistor of the chip, the drain of the storage transistor being connected to a bit line of the chip, the sense amplifier being located between the bit line and a corresponding complementary bit line, so that after an operation of applying an equalization control voltage to an equalizer in response to a pre-charge signal, the power consumption of the chip under the sense amplifier control voltage is measured, a chip power consumption measurement result is obtained, the equalizer is located between the bit line and the complementary bit line, and the state of the equalizer is obtained according to the chip power consumption measurement result to test the equalizer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to an equalizer testing method, circuit, apparatus, electronic device, and readable storage medium. Background Technology

[0002] In Dynamic Random Access Memory (DRAM) circuits, a large number of memory cells are typically arranged in an array. Multiple bit lines and word lines are used to write to and read from each memory cell in both row and column directions. A column in the memory cell array is usually connected to a pair of bit lines (BLs). During DRAM operation, the bit lines need to be precharged to a predetermined voltage; this is called precharge. An equalizer is typically used to precharge a pair of bit lines. Therefore, determining whether the equalizer is functioning correctly is a crucial problem to solve.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide an equalizer testing method, circuit, apparatus, electronic device, and readable storage medium.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, an equalizer testing method is provided, comprising: after shutting down the current word line power supply of a chip, applying a sensitive amplifier control voltage to a sensitive amplifier to keep the sensitive amplifier on, wherein the current word line is connected to the gate of a memory transistor of the chip, the drain of the memory transistor is connected to a bit line of the chip, and the sensitive amplifier is located between the bit line and a corresponding complementary bit line, so that after applying an equalizer control voltage to the equalizer, the power consumption of the chip under the sensitive amplifier control voltage is measured to obtain a chip power consumption measurement result, wherein the equalizer is located between the bit line and the complementary bit line, and the state of the equalizer is obtained based on the chip power consumption measurement result, for testing the equalizer.

[0007] According to one embodiment of this disclosure, after shutting down the current word line power supply of the chip, applying a sensitive amplifier control voltage to a sensitive amplifier to keep the sensitive amplifier on includes: in response to an entry test mode control information, after shutting down the current word line power supply in response to a precharge signal, applying the sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on, wherein the precharge signal is used to precharge the bit line and the complementary bit line; after applying an equalization control voltage to an equalizer, measuring the power consumption of the chip under the sensitive amplifier control voltage includes: after applying the equalization control voltage to the equalizer in response to the precharge signal, measuring the power consumption of the chip under the sensitive amplifier control voltage.

[0008] According to one embodiment of this disclosure, in response to an enter test mode control information, after a current word line power supply shutdown operation performed in response to a precharge signal, applying the sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on includes: receiving bit line group selection information sent in response to the enter test mode control information, the bit line group selection information including information on selecting the bit line and the complementary bit line; and applying the sensitive amplifier control voltage to the sensitive amplifier according to the bit line group selection information to keep the sensitive amplifier on after the current word line power supply shutdown operation performed in response to the precharge signal.

[0009] According to one embodiment of this disclosure, the state of the equalizer is obtained based on the chip power consumption measurement result for testing the equalizer, including: determining whether the power consumption of the chip under the sensitive amplifier control voltage is less than a preset power consumption threshold; if the power consumption of the chip under the sensitive amplifier control voltage is less than the preset power consumption threshold, the state of the equalizer is determined to be faulty.

[0010] According to one embodiment of this disclosure, if the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold, the state of the equalizer is determined to be faulty, including: if the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold, the state of the equalizer is determined to be faulty, and bit line group failure information is output, wherein the bit line group failure information is used to indicate that the bit line and / or the complementary bit line is faulty.

[0011] According to one embodiment of this disclosure, the equalizer's state is obtained based on the chip power consumption measurement result for testing the equalizer. The method further includes: if the chip's power consumption under the sensitive amplifier control voltage is not less than a preset power consumption threshold, then the equalizer's state is determined to be valid, and bit line group valid information is output. This bit line group valid information indicates that the bit line and / or the complementary bit line are valid. The bit line group failure information includes a low level, and the bit line group valid information includes a high level.

[0012] According to another aspect of this disclosure, an equalizer test circuit is provided, including a sensitivity controller and a load resistor, wherein: the sensitivity controller is connected to the PMOS source power supply and / or the NMOS drain power supply of the sensitivity amplifier; the sensitivity controller is used to measure the chip's sensitivity after applying a sensitivity amplifier control voltage to the sensitivity amplifier to keep the sensitivity amplifier on, and after applying an equalization control voltage to the equalizer, by measuring the current through the load resistor or measuring the voltage across the load resistor. The amplifier controls the power consumption under the control voltage to obtain the chip power consumption measurement result. The current word line is connected to the gate of the memory transistor of the chip, and the drain of the memory transistor is connected to the bit line of the chip. The sensitive amplifier is located between the bit line and the corresponding complementary bit line, and the equalizer is located between the bit line and the complementary bit line. The sensitive controller is also used to obtain the state of the equalizer according to the chip power consumption measurement result in order to test the equalizer. The load resistor is connected to the PMOS source power supply and / or the NMOS drain power supply of the sensitive amplifier.

[0013] According to one embodiment of this disclosure, the load resistor is located between the PMOS source power supply of the sensitive amplifier and the equalizer, and / or the load resistor is located between the NMOS drain power supply of the sensitive amplifier and the equalizer.

[0014] According to one embodiment of this disclosure, the circuit further includes an address generator, wherein the address generator is connected to the chip and is configured to send bit line group selection information to the sensitive controller in response to test mode control information, the bit line group selection information including information for selecting the bit line and the complementary bit line.

[0015] According to one embodiment of this disclosure, the sensitive controller is further configured to determine whether the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold; the sensitive controller is further configured to determine that the equalizer is in a state of failure if the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold.

[0016] According to one embodiment of this disclosure, the circuit further includes a failure storage and counter, which is connected to the address generator and the sensitivity controller, respectively. The address generator is further configured to send the bit line group selection information to the failure storage and counter. The sensitivity controller is further configured to determine that the equalizer is in a failed state if the power consumption of the chip under the control voltage of the sensitivity amplifier is less than a preset power consumption threshold, and output bit line group failure information to the failure storage and counter. The bit line group failure information is used to indicate that the bit line and / or the complementary bit line is failed. The failure storage and counter is further configured to record the failure of the bit line and / or the complementary bit line according to the bit line group selection information and the bit line group failure information.

[0017] According to one embodiment of this disclosure, the sensitive controller is further configured to determine that the equalizer is valid if the power consumption of the chip under the control voltage of the sensitive amplifier is not less than a preset power consumption threshold, and output bit line group valid information to the failure storage and counter. The bit line group valid information is used to indicate that the bit line and / or the complementary bit line is valid; wherein, the bit line group failure information includes a low level, and the bit line group valid information includes a high level.

[0018] According to another aspect of this disclosure, an equalizer testing apparatus is provided, comprising: a main control module and a sensitivity control module disposed inside a chip, wherein: the main control module is configured to apply a sensitivity amplifier control voltage to the sensitivity amplifier to keep the sensitivity amplifier on after the current word line power supply of the chip is turned off, the current word line is connected to the gate of a memory transistor of the chip, the drain of the memory transistor is connected to a bit line of the chip, and the sensitivity amplifier is located between the bit line and a corresponding complementary bit line; the sensitivity control module is configured to measure the power consumption of the chip under the sensitivity amplifier control voltage after applying the equalizer control voltage to the equalizer, and obtain a chip power consumption measurement result, the equalizer being located between the bit line and the complementary bit line; and obtain the state of the equalizer based on the chip power consumption measurement result to test the equalizer.

[0019] According to one embodiment of this disclosure, the sensitive control module is connected to the peripheral output path of the chip.

[0020] According to another aspect of this disclosure, an electronic device is provided, comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, wherein the processor, when executing the executable instructions, implements any of the methods described above.

[0021] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, which, when executed by a processor, implement any of the methods described above.

[0022] The equalizer testing method provided in the embodiments of this disclosure involves applying a sensitive amplifier control voltage to a sensitive amplifier located between a bit line and a complementary bit line after the current word line power supply of the chip is turned off to keep the sensitive amplifier on. This allows the chip power consumption under the sensitive amplifier control voltage to be measured after the equalizer control voltage is applied to the equalizer located between the bit line and the complementary bit line, thereby obtaining the chip power consumption measurement result. The state of the equalizer is then obtained based on the chip power consumption measurement result, thus enabling the equalizer to be tested.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0024] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0025] Figure 1 An exemplary schematic diagram of a DRAM core operation sequence is shown.

[0026] Figure 2 according to Figure 1 An example of an equalization circuit schematic is shown.

[0027] Figure 3A This is an equalizer test circuit illustrated according to an exemplary embodiment.

[0028] Figure 3B This is another equalizer test circuit illustrated according to an exemplary embodiment.

[0029] Figure 3C This is another equalizer test circuit illustrated according to an exemplary embodiment.

[0030] Figure 4A It is based on Figures 3A to 3C The diagram shows a schematic of an equalizer test circuit implementation.

[0031] Figure 4B It is based on Figures 3A to 3C A schematic diagram of another equalizer test circuit implementation is shown.

[0032] Figure 5 It is based on Figure 3C Another equalizer test circuit is shown.

[0033] Figure 6 It is based on Figure 5The flowchart illustrates an equalizer testing method.

[0034] Figure 7 This is a schematic diagram illustrating an equalizer testing device disposed inside a chip according to an exemplary embodiment.

[0035] Figure 8 It is based on Figure 7 The flowchart illustrates an equalizer testing method.

[0036] Figure 9 according to Figure 6 and Figure 8 A schematic diagram of the operation sequence under DRAM test mode is shown.

[0037] Figure 10 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0038] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0039] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0040] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0041] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0042] As mentioned above, determining whether the equalizer is working properly is a pressing issue. Related technologies limit the row pre-charge time (tRP), pre-charge within a finite time, and then read the data, comparing the read and written data to determine if the equalizer is functioning correctly. However, this method has several problems. First, it easily introduces noise, such as sensing margin, and differences in cell retention performance can affect the accuracy of the result. Second, because this method involves read and write operations, it consumes machine input / output (I / O), thus limiting the test count for Probabilistic Adjacent Row Activation (PARA).

[0043] Figure 1 An exemplary schematic diagram of a DRAM core operation sequence is shown. Figure 1 As shown, the control logic of the main controller for the DRAM precharge process, the core operation sequence in the related technology is as follows: precharge control signal (S102) → word line (WL) off (S104) → sensing amplifier (SA) off (S106) → BLEQ on (S108) → enable equalizer (EQ), and then after tRP time after the precharge control signal, the activation operation is performed (S110).

[0044] Figure 2 according to Figure 1 An example diagram of an equalization circuit is shown. Figure 2 As shown, according to Figure 1 In the control logic, after SA 202 is turned off in step S106, since the high voltage control signal (Positive Collect Select, PCS) and low voltage control signal (Negative Collect Select, NCS) of SA 202 are no longer generated, after BLEQ2008 is turned on in step S108, regardless of whether the equalizer 204 is successfully enabled, the short circuit between BL 2002 and / BL 2004 (the complementary bit line of BL 2002) will not cause the external power supply to continue to supply power. Therefore, the memory cell 206 of the chip (whose gate is connected to WL 2006) generates no power consumption.

[0045] In view of this, this disclosure provides an equalizer testing method. After turning off the current word line power supply of the chip, a sensitive amplifier control voltage is applied to the sensitive amplifier located between the bit line and the complementary bit line to keep the sensitive amplifier on. After applying the equalization control voltage to the equalizer located between the bit line and the complementary bit line, the power consumption of the chip under the sensitive amplifier control voltage is measured to obtain the chip power consumption measurement result. Then, the state of the equalizer is obtained based on the chip power consumption measurement result. This allows for equalizer testing while avoiding the technical problems of introducing noise and occupying the input and output of the equipment, which are present in the method of judging the equalizer state by limiting tRP.

[0046] Figure 3A This is an equalizer test circuit illustrated according to an exemplary embodiment. For example... Figure 3A As shown, the equalizer test circuit may include a sensitivity controller 302 and a load resistor 304. The sensitivity controller 302 and the load resistor 304 form a loop with the chip 3002 of the equalizer under test (i.e., the equalizer) corresponding to the sensitivity amplifier, the PMOS source power supply (e.g., the PCS voltage can be VDD or Vary) 3004 of the sensitivity amplifier, and the NMOS drain power supply (e.g., the NCS voltage can be VSS) 3006 of the sensitivity amplifier.

[0047] Reference Figure 4A The gate of storage transistor 406 is connected to the current word line (WL) 4006, and the drain of storage transistor 406 is connected to the bit line (BL) 4002. A sensitive amplifier 402 and an equalizer 404 are provided between bit line 4002 and complementary bit line ( / BL) 4004. The gate of column select transistor 408 is connected to the column select signal line (YSelect, YS) 4010, the source of column select transistor 408 is connected to the local input / output (LIO) line 4012, and the drain of column select transistor 408 is connected to the bit line (BL) 4002. The sensitive controller 302 and the load resistor 304 can be correspondingly set... Figure 4A At point B, the sensitivity controller 302 can be connected to the PMOS source power supply 3004 of the sensitivity amplifier 402. After the main controller (not shown) shuts down the current word line 4006 power supply of the chip 3002 in response to the precharge signal, it applies a sensitivity amplifier control voltage to the sensitivity amplifier 402 to keep the sensitivity amplifier 402 on. Specifically, the main controller can provide the voltage Vary corresponding to PCS 3004 to create a voltage difference between Vary and the voltage VSS corresponding to NCS 3006; this voltage difference is the sensitivity amplifier control voltage.

[0048] In some embodiments, the main controller may also be used to apply a sensitive amplifier control voltage to the sensitive amplifier 402 to keep the sensitive amplifier 402 on, in response to (e.g., a control message sent by the main controller) entering a test mode, after (e.g., the main controller) performs a power-off operation on the current word line 4006 of the chip 3002 in response to a pre-charge signal. This test mode is used to test the state of the equalizer 404.

[0049] The precharge signal can be used to precharge bit line 4002 and complementary bit line 4004 of the chip. Sensitive amplifier 402 is located between bit line 4002 and complementary bit line 4004, and equalizer is also located between bit line 4002 and complementary bit line 4004.

[0050] The sensitive controller 302 can integrate an ammeter and / or a voltmeter. It can also be used to measure the power consumption of chip 3002 under the sensitive amplifier control voltage by measuring the current through the load resistor 304 or the voltage across the load resistor after the main controller performs the operation of applying the equalization control voltage BLEQ 4008 to the equalizer 404 in response to the pre-charge signal, and obtain the chip power consumption measurement result.

[0051] In some embodiments, the resistance value of the load resistor 304 is fixed at a certain temperature, so the power consumption of the load resistor 304 is proportional to the current in the circuit.

[0052] The sensitive controller 302 can also be used to obtain the state of the equalizer 404 based on the chip power consumption measurement results, so as to test the equalizer.

[0053] Figure 3B This is another equalizer test circuit illustrated according to an exemplary embodiment. Figure 3B and Figure 3A The difference lies in that, in the circuit, the load resistor 304 is positioned between the PMOS source power supply 3004 of the sensitive amplifier and the equalizer (of chip 3002), while the sensitive controller 302 is located between the NMOS drain power supply 3006 of the sensitive amplifier and the equalizer (of chip 3002). (Refer to...) Figure 4A The sensitivity controller 302 can be set at point A in the figure, and the load resistor 304 can be set at point B in the figure. The main controller (not shown in the figure) can provide the voltage VSS corresponding to NCS 3006 to create a voltage difference between it and the voltage Vary corresponding to PCS3004. This voltage difference is the control voltage of the sensitivity amplifier.

[0054] Figure 3C This is another equalizer test circuit illustrated according to an exemplary embodiment. Figure 3C and Figure 3AThe difference lies in the inclusion of two load resistors 304 in the circuit. These are positioned between the PMOS source power supply 3004 of the sensitive amplifier and the equalizer (of chip 3002), respectively, and between the NMOS drain power supply 3006 of the sensitive amplifier and the equalizer (of chip 3002). (Refer to...) Figure 4A The sensitive controller 302 and one load resistor 304 can be set at point B in the figure, and the other load resistor 304 can be set at point A in the figure. When the state of the equalizer 404 is obtained based on the chip power consumption measurement result, the sensitive controller 302 can combine the voltage and / or current measurement results of the two load resistors 304 to obtain the chip power consumption measurement result.

[0055] Figure 4A It is based on Figures 3A to 3C The diagram shows a schematic of an equalizer test circuit implementation. Figure 4A The diagram shows the normal state of equalizer 404, where the three MOSFETs of equalizer 404 are turned on, thus making the loop formed between PCS 3004 and NCS 3006, the sensitive controller 302 set at point A and / or B, and the applied load resistor 304 conduct. Therefore, when the power consumption of the load resistor 304 is measured (i.e., the power consumption of chip 3003 under the control voltage of the sensitive amplifier is greater than the preset power consumption threshold), it indicates that equalizer 404 is in a normal state.

[0056] Figure 4B It is based on Figures 3A to 3C A schematic diagram of another equalizer test circuit implementation is shown. Figure 4A The diagram illustrates an abnormal state of equalizer 404, where the three MOSFETs of equalizer 404 are not turned on. This prevents a conduction loop from being formed between PCS 3004 and NCS 3006, the sensitive controller 302 located at point A and / or B, and the applied load resistor 304. Therefore, when the power consumption of the load resistor 304 cannot be measured (i.e., the power consumption of chip 3003 under the control voltage of the sensitive amplifier is less than the preset power consumption threshold), it indicates that equalizer 404 is in a faulty state.

[0057] Figure 5 It is based on Figure 3C Another equalizer test circuit is shown. Figure 5 (as well as Figures 3A to 3C The equalizer test circuit shown can be set at the test terminal (Tester). Figure 3C compared to, Figure 5 The circuit also includes an address generator 506 and a failure memory and counter 508. The sensitivity controller 502 can perform the same function as the sensitivity controller 302, and the load resistor 504 can perform the same function as the load resistor 302.

[0058] Reference Figure 5 Address generator 506 is connected to chip 5003 and can be used to send bit line group selection information to sensitive controller 502 in response to (e.g., sent by the main controller) a test mode entry control message. The bit line group selection information includes information about the selected bit line and complementary bit line (e.g., the Y address, see reference). Figure 4A and / or Figure 4B The bit line group formed by bit line 4002 and complementary bit line 4004 can be selected by applying a YS signal to column select signal line 4010. Address generator 506 is also used to send the bit line group selection information to fail-safe memory and counter 508.

[0059] The main controller in chip 5002 can be used to apply a sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on, based on bit line group selection information (e.g., a Y address), after a power-off operation of the current word line power supply is performed in response to a precharge signal.

[0060] The failure memory and counter 508 can be connected to the address generator 506 and the sensitivity controller 502, respectively.

[0061] The sensitive controller 502 can also be used to determine whether the load resistor consumes power (i.e. whether the chip consumes power under the control voltage of the sensitive amplifier) ​​based on the values ​​in the ammeter A and / or voltmeter V integrated in the sensitive controller 502. If the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold (i.e. no power consumption), the equalizer is deemed to be in a state of failure, and bit line failure group information is output to the failure storage and counter 508. The bit line failure group information is used to indicate the failure of the bit line and / or complementary bit line.

[0062] In some embodiments, bit line group failure information may include a low level, that is, when the sensitivity controller 502 determines that the equalizer is in a state of failure, it outputs a low level to the failure storage and counter 508.

[0063] The sensitivity controller 502 can also be used to determine the state of the equalizer as valid if the power consumption of the chip under the control voltage of the sensitivity amplifier is not less than a preset power consumption threshold, and output the bit line group valid information. The bit line group valid information is used to indicate that the bit line and / or complementary bit line are valid.

[0064] In some embodiments, the bit line group valid information may include a high level, that is, when the sensitivity controller 502 determines that the state of the equalizer is valid, it outputs a high level to the failure storage and counter 508.

[0065] The failure storage and counter 508 can be used to record bit line and / or complementary bit line failures based on bit line group selection information and bit line group failure information.

[0066] The failure memory and counter 508 can also be used to record the validity of bit lines and / or complementary bit lines based on bit line group selection information and bit line group validity information.

[0067] Figure 6 It is based on Figure 5 A flowchart illustrating an equalizer testing method is shown. (Reference) Figure 6 The method 60 provided in this embodiment may include the following steps.

[0068] In step S602, bit line group selection information is received in response to the sending of test mode control information. The bit line group selection information includes information on selected bit lines and complementary bit lines.

[0069] In step S604, after the current word line power supply is turned off in response to the precharge signal, a sensitive amplifier control voltage is applied to the sensitive amplifier according to the bit line group selection information to keep the sensitive amplifier on.

[0070] In some embodiments, refer to Figure 4A and / or Figure 4B The bit line group formed by bit line 4002 and complementary bit line 4004 can be selected by applying a signal to column select signal line 4010.

[0071] The precharge signal is used to precharge the chip's bit lines and complementary bit lines, with the sensitive amplifier located between the bit lines and complementary bit lines.

[0072] In step S606, it is determined whether the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold.

[0073] In step S608, if the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold, the equalizer is determined to be in a state of failure, and bit line failure information is output. The bit line group failure information is used to indicate the failure of bit lines and / or complementary bit lines.

[0074] Figure 6 The specific implementation of each step in the provided method can be found above. Figures 3A to 5 The contents of the circuit will not be described in detail here.

[0075] Figure 7 This is a schematic diagram illustrating an equalizer testing device disposed inside a chip according to an exemplary embodiment. (Reference) Figure 7 , Figure 7This paper illustrates an internal chip architecture diagram of DDR (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM, abbreviated as DDR), which can be divided into three parts: array 702, peripheral control logic circuit 704, and peripheral input / output path 706. The device provided in this embodiment may include a sensitive control module 7002, which can be connected to the peripheral output path in the peripheral input / output path 706 of the chip, and the sensitive control module 7002 is only enabled (normal operation) after entering test mode.

[0076] The peripheral control logic circuit 704 may include a main controller 7042, an address register 7044, a row address data selector (MUX), a column address latch & decoder 7048, a refresh counter 70410, a bank control logic unit 70412, and a row address latch & decoder 70414, etc., to implement functions such as controlling which rows and columns to write / read.

[0077] The memory arrays Bank0 to Bank15 7022 and their corresponding SA and column decoder 7026 are located in the array 702 section. The data I / O mask (DQM) module 7024 is used to control which data input or output to the memory array 7022 is canceled by the I / O port.

[0078] The external input / output path 706 may include a First-In-First-Out (FIFO) data selector (MUX) 7062, a data interface 7064, a read driver 7066, a write driver & input logic 7068, and a circuit 70610 that implements the data strobe pulse. The external output path is... Figure 7 The data mask module 7024 is connected to the FIFO MUX 7062, which is then connected to the read driver 7066. The sensitivity control module 7002 can be connected to the read driver 7066, for example.

[0079] The main controller 7042 can be used to apply a sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on after a current word line power supply operation that shuts down the chip in response to a precharge signal. The precharge signal is used to precharge the bit lines and complementary bit lines of the chip, and the sensitive amplifier is located between the bit lines and complementary bit lines.

[0080] The sensitive control module 7002 can also be used to measure the chip's power consumption under the sensitive amplifier control voltage after the main controller 7042 performs the operation of applying the equalization control voltage to the equalizer in response to the pre-charge signal, and obtain the chip power consumption measurement result. The equalizer is located between the bit line and the complementary bit line.

[0081] The sensitive control module 7002 can also be used to obtain the equalizer's state based on chip power consumption measurements for equalizer testing. The output of the sensitive control module 7002 can be output from an IO pin. By designing the operational logic of the sensitive control module 7002, the failure level of the bit line and complementary bit line can be determined based on the chip power consumption measurement results, thereby obtaining the equalizer's state.

[0082] Figure 8 It is based on Figure 7 A flowchart illustrating an equalizer testing method is shown. (Reference) Figure 8 The method 80 provided in this embodiment may include the following steps.

[0083] In step S802, after turning off the current word line power supply of the chip, a sensitive amplifier control voltage is applied to the sensitive amplifier to keep the sensitive amplifier on.

[0084] The current word line is connected to the gate of the chip's storage transistor, the drain of the storage transistor is connected to the chip's bit line, and the sensitive amplifier is located between the bit line and the corresponding complementary bit line.

[0085] In some embodiments, in response to the test mode control information, after the current word line power supply operation of the chip is turned off in response to the precharge signal, a sensitive amplifier control voltage is applied to the sensitive amplifier to keep the sensitive amplifier on, wherein the precharge signal is used to precharge the bit lines and complementary bit lines of the chip.

[0086] In step S804, after applying the equalization control voltage to the equalizer, the power consumption of the chip under the control voltage of the sensitive amplifier is measured to obtain the chip power consumption measurement result.

[0087] The equalizer is located between the bit line and the complementary bit line.

[0088] In some embodiments, after applying an equalization control voltage to the equalizer in response to a precharge signal, the chip power consumption under the sensitive amplifier control voltage is measured to obtain the chip power consumption measurement result.

[0089] In step S806, the state of the equalizer is obtained based on the chip power consumption measurement results in order to test the equalizer.

[0090] In some embodiments, it is determined whether the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold.

[0091] If the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold, the equalizer is considered to be in a state of failure.

[0092] Figure 8 For specific implementation methods corresponding to each step, please refer to 3A to 3B. Figure 5 The contents of the circuit will not be described in detail here.

[0093] Figure 9 according to Figure 6 and Figure 8 A schematic diagram illustrating the operation sequence under DRAM test mode is shown. (Refer to...) Figure 1 The core operation sequence can be changed by entering test mode: precharge control signal (S902) → WL off (S904) → SA kept on (S906) → BLEQ on (S908), enabling EQ, and then performing activation operation (S910) after tRP time following the precharge control signal. The normal operation of the equalizer can be directly evaluated through power consumption monitoring. This avoids noise interference from sensing tolerance, memory cell data retention capabilities, etc.

[0094] Figure 10 A schematic diagram of the structure of an electronic device according to an embodiment of this disclosure is shown. It should be noted that... Figure 10 The devices shown are merely examples of computer systems and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0095] like Figure 10 As shown, device 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage section 1008 into random access memory (RAM) 1003. The RAM 1003 also stores various programs and data required for the operation of device 1000. CPU 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0096] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 1010 as needed so that computer programs read from it can be installed into storage section 1008 as needed.

[0097] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1009, and / or installed from removable medium 1011. When the computer program is executed by central processing unit (CPU) 1001, it performs the functions defined above in the system of this disclosure.

[0098] It should be noted that the computer-readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0099] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0100] The modules described in the embodiments of this disclosure can be implemented in software or hardware. The described modules can also be housed in a processor; for example, a processor may be described as including a sensitivity control module. The name of the module does not necessarily limit the module itself; for example, a sensitivity control module may also be described as "a module that sends control signals to a connected sensitivity amplifier."

[0101] In another aspect, this disclosure also provides a computer-readable medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable medium carries one or more programs, which, when executed by the device, cause the device to include:

[0102] After shutting down the current word line power supply of the chip, a sensitive amplifier control voltage is applied to the sensitive amplifier to keep it on. The current word line is connected to the gate of the chip's storage transistor, and the drain of the storage transistor is connected to the chip's bit line. The sensitive amplifier is located between the bit line and the corresponding complementary bit line. After applying an equalization control voltage to the equalizer in response to the precharge signal, the chip's power consumption under the sensitive amplifier control voltage is measured to obtain the chip power consumption measurement result. The equalizer is located between the bit line and the complementary bit line. The state of the equalizer is obtained based on the chip power consumption measurement result to test the equalizer.

[0103] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. An equalizer testing method, characterized in that, include: After the current word line power supply of the chip is turned off, a sensitive amplifier control voltage is applied to the sensitive amplifier to keep the sensitive amplifier on. The current word line is connected to the gate of the chip's memory transistor, and the drain of the memory transistor is connected to the chip's bit line. The sensitive amplifier is located between the bit line and the corresponding complementary bit line so that after applying an equalization control voltage to the equalizer, the power consumption of the chip under the sensitive amplifier control voltage is measured to obtain the chip power consumption measurement result. The equalizer is located between the bit line and the complementary bit line, and the state of the equalizer is obtained based on the chip power consumption measurement result to test the equalizer.

2. The method according to claim 1, characterized in that, After shutting down the current word line power supply of the chip, applying a sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on includes: In response to the test mode control information, after the current word line power supply is turned off in response to the precharge signal, the sensitive amplifier control voltage is applied to the sensitive amplifier to keep the sensitive amplifier on, and the precharge signal is used to precharge the bit line and the complementary bit line; After applying the equalization control voltage to the equalizer, the power consumption of the chip under the control voltage of the sensitive amplifier is measured, including: After applying the equalization control voltage to the equalizer in response to the precharge signal, the power consumption of the chip under the sensitive amplifier control voltage is measured.

3. The method according to claim 2, characterized in that, In response to the test mode control information, after the current word line power supply operation of the chip is shut down in response to the precharge signal, the sensitive amplifier control voltage is applied to the sensitive amplifier to keep the sensitive amplifier on, including: Receive bit line group selection information in response to the control information for entering test mode, wherein the bit line group selection information includes information for selecting the bit line and the complementary bit line; After the current word line power supply is turned off in response to the precharge signal, the sensitive amplifier control voltage is applied to the sensitive amplifier according to the bit line group selection information to keep the sensitive amplifier on.

4. The method according to claim 1, characterized in that, The equalizer's state is obtained based on the chip power consumption measurement results, and the equalizer is tested, including: Determine whether the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold. If the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold, then the equalizer is considered to be in a state of failure.

5. The method according to claim 4, characterized in that, If the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold, the equalizer is deemed to be in a faulty state, including: If the power consumption of the chip under the control voltage of the sensitive amplifier is less than the preset power consumption threshold, the equalizer is deemed to be in a state of failure, and bit line group failure information is output. The bit line group failure information is used to indicate that the bit line and / or the complementary bit line has failed.

6. The method according to claim 5, characterized in that, The equalizer's state is obtained based on the chip power consumption measurement results for testing the equalizer, and the testing process further includes: If the power consumption of the chip under the control voltage of the sensitive amplifier is not less than the preset power consumption threshold, then the state of the equalizer is obtained as valid, and bit line group valid information is output. The bit line group valid information is used to indicate that the bit line and / or the complementary bit line is valid. The bit line group failure information includes a low level, and the bit line group validity information includes a high level.

7. An equalizer test circuit, characterized in that, Includes a sensitive controller and a load resistor, wherein: The sensitive controller is connected to the PMOS source power supply and / or the NMOS drain power supply of the sensitive amplifier. The sensitive controller is used to apply a sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on after the current word line power supply of the chip is turned off, and after applying an equalization control voltage to the equalizer, measure the power consumption of the chip under the sensitive amplifier control voltage by measuring the current through the load resistor or measuring the voltage across the load resistor, and obtain the chip power consumption measurement result. The current word line is connected to the gate of the chip's memory transistor, the drain of the memory transistor is connected to the chip's bit line, the sensitive amplifier is located between the bit line and the corresponding complementary bit line, and the equalizer is located between the bit line and the complementary bit line. The sensitive controller is also used to obtain the state of the equalizer based on the chip power consumption measurement results, so as to test the equalizer; The load resistor is connected to the PMOS source power supply and / or the NMOS drain power supply of the sensitive amplifier.

8. The circuit according to claim 7, characterized in that, The load resistor is located between the PMOS source power supply of the sensitive amplifier and the equalizer, and / or the load resistor is located between the NMOS drain power supply of the sensitive amplifier and the equalizer.

9. The circuit according to claim 7, characterized in that, It also includes an address generator, where: The address generator is connected to the chip and is used to send bit line group selection information to the sensitive controller in response to the test mode control information. The bit line group selection information includes information on selecting the bit line and the complementary bit line.

10. The circuit according to claim 9, characterized in that, The sensitive controller is also used to determine whether the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold. The sensitivity controller is further configured to determine that the equalizer is in a state of failure if the power consumption of the chip under the control voltage of the sensitivity amplifier is less than a preset power consumption threshold.

11. The circuit according to claim 10, characterized in that, The circuit also includes a failure memory and a counter, which are connected to the address generator and the sensitive controller, respectively. The address generator is also used to send the bit line group selection information to the failed memory and counter; The sensitive controller is further configured to determine that the equalizer is in a state of failure if the power consumption of the chip under the control voltage of the sensitive amplifier is less than a preset power consumption threshold, and output bit line group failure information to the failure storage and counter. The bit line group failure information is used to indicate that the bit line and / or the complementary bit line is in failure. The failure storage and counter is also used to record the failure of the bit line and / or the complementary bit line based on the bit line group selection information and the bit line group failure information.

12. The circuit according to claim 11, characterized in that, The sensitive controller is further configured to determine that the equalizer is valid if the power consumption of the chip under the control voltage of the sensitive amplifier is not less than a preset power consumption threshold, and output bit line group valid information to the failure storage and counter. The bit line group valid information is used to indicate that the bit line and / or the complementary bit line is valid. The bit line group failure information includes a low level, and the bit line group validity information includes a high level.

13. An equalizer testing device, characterized in that, Located inside the chip, the device includes a main control module and a sensitive control module, wherein: The main control module is used to apply a sensitive amplifier control voltage to the sensitive amplifier to keep the sensitive amplifier on after the current word line power supply of the chip is turned off. The current word line is connected to the gate of the storage transistor of the chip, the drain of the storage transistor is connected to the bit line of the chip, and the sensitive amplifier is located between the bit line and the corresponding complementary bit line. The sensitive control module is used to measure the power consumption of the chip under the control voltage of the sensitive amplifier after applying the equalization control voltage to the equalizer, and obtain the chip power consumption measurement result. The equalizer is located between the bit line and the complementary bit line. The sensitive control module is also used to obtain the state of the equalizer based on the chip power consumption measurement results, so as to test the equalizer.

14. The apparatus according to claim 13, characterized in that, The sensitive control module is connected to the peripheral output path of the chip.

15. An electronic device comprising: A memory, a processor, and executable instructions stored in the memory and executable in the processor, characterized in that the processor, when executing the executable instructions, implements the method as described in any one of claims 1-6.

16. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that, When the executable instructions are executed by the processor, they implement the method as described in any one of claims 1-6.

Images