Semiconductor structure and method of manufacturing the same

By designing a bent or tilted structure in the semiconductor structure where the channel layer intersects with the substrate surface, the contact area between the gate and the channel layer is increased, solving the problem of insufficient transistor control capability in 2T0C memory cells and improving the integration and performance of DRAM.

CN116525539BActive Publication Date: 2026-07-24CHANGXIN MEMORY TECH INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHANGXIN MEMORY TECH INC
Filing Date
2023-05-24
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

The traditional 1T1C memory structure of DRAM is limited in its development due to problems with capacitor manufacturing and data refresh, while the dual-gate transistor design of 2T0C memory cells makes it difficult to balance integration and performance.

Method used

Design a semiconductor structure in which a portion of the channel layer located between the first and second gates intersects with the substrate surface, forming a bend or tilt, thereby increasing the contact area between the gate and the channel layer and improving the transistor's control over the channel.

Benefits of technology

It improves the transistor's turn-off capability and threshold voltage, alleviates the IR drop problem, and promotes the integration and performance improvement of DRAM.

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Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof, the semiconductor structure comprises: a transistor, the transistor comprises: a source and a drain which are located on a substrate surface and arranged side by side along a first direction, the first direction is parallel to the substrate surface; a channel layer, one end of the channel layer is in contact with the source, and the other end opposite to the one end is in contact with the drain; a plane where at least a partial region of the channel layer is located intersects with the substrate surface; the partial region has two surfaces which are oppositely arranged along the first direction; a first gate is arranged on one surface of the partial region, and a first gate dielectric layer is arranged between the first gate and the channel layer; a second gate is arranged on the other surface of the partial region, and a second gate dielectric layer is arranged between the second gate and the channel layer.
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