FPGA-based sha256 high-efficiency digital encryption method and system

Abstract

The application discloses a kind of based on FPGA's SHA256 high-efficiency digital encryption method and system, including, through PC module, generates the data to be encrypted, it is used as data source and is sent to FPGA module using PCIE protocol;Using PCIE interface control module receives the data source, and the data source is sent to receiving data control module;The receiving data control module sends the data source received to SHA256 algorithm kernel implementation module and is calculated, obtains the hash value after encryption;The hash value is sent back to receiving data control module, and it is sent to PCIE interface control module and through PCIE protocol, the hash value is returned to PC module;The hash value is compared with the original correct hash value after encryption of PC module, and high-efficiency digital encryption method is obtained;The application is analyzed FPGA chip resource characteristics by the SHA256 algorithm designed, and algorithm hard implementation IP with high bandwidth, good portability is designed, the number of algorithm kernel can be flexibly configured, and it is convenient to extend.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of encryption technology, and in particular to a high-efficiency digital encryption method and system based on FPGA. BACKGROUND

[0002] With the development of information technology, the security and reliability of information are becoming more and more important. We often need some measures to protect our data from being destroyed by some people with ulterior motives. The direct way to protect information security is to use encryption technology, and currently encryption technology is mainly realized through microprocessors.

[0003] Hash algorithm is the most common algorithm applied in the above-mentioned information security field, and the hash algorithm that can be practically applied must meet the one-wayness, collision resistance, mapping uniformity and differential uniformity. SHA256, as an international standard hash algorithm, is widely used in international standard protocols (such as DSA) and cryptographic applications (such as financial security field).

[0004] The encryption algorithm can be completed through software, but when facing massive data, the encryption system has problems such as high CPU occupancy and large memory usage. At the same time, software encryption algorithm will face extreme ways such as brute force cracking software, product formatting, and disassembling of storage data flash chip, and all of these can be easily cracked. In contrast, all encrypted information in hardware encryption is built into the hardware chip, so that hackers' usual method of stealing data by hacking encryption information will be completely ineffective. SUMMARY

[0005] The purpose of this section is to summarize some aspects of the embodiments of the present application and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of the specification to avoid obscuring the purpose of this section, the abstract and the title, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0006] In view of the above-mentioned existing problems, the present application is proposed. Therefore, the present application provides a high-efficiency digital encryption method based on FPGA SHA256 to solve the problem that the encryption system is easy to be hacked and has problems such as high CPU occupancy and large memory usage in practical problems.

[0007] To solve the above technical problems, the present application provides the following technical solutions:

[0008] In a first aspect, the present application provides a high-efficiency digital encryption method based on FPGA SHA256, comprising:

[0009] The PC module generates data to be encrypted, and sends the data to the FPGA module as a data source through a PCIE protocol;

[0010] The PCIE interface control module receives the data source and sends the data source to the data receiving control module;

[0011] The data receiving control module sends the received data source to the SHA256 algorithm kernel implementation module for calculation to obtain an encrypted hash value;

[0012] The hash value is sent back to the data receiving control module, and then sent to the PCIE interface control module and returned to the PC module through the PCIE protocol.

[0013] The original correct encrypted hash value of the PC module is compared with the hash value to obtain an efficient digital encryption method.

[0014] As a preferred scheme of the SHA256 efficient digital encryption method based on FPGA, the PC module generates data to be encrypted, including:

[0015] The data to be encrypted is a 256-bit data source after preprocessing.

[0016] As a preferred scheme of the SHA256 efficient digital encryption method based on FPGA, the PCIE interface control module receives the data source and sends the data source to the data receiving control module, including:

[0017] The PCIE interface control module is divided into two parts: reading and writing, the first part is data reading and writing, and the second part is configuration data reading and writing.

[0018] As a preferred scheme of the SHA256 efficient digital encryption method based on FPGA, the data receiving control module sends the received data source to the SHA256 algorithm kernel implementation module, including:

[0019] After the data receiving control module accepts data through a standard protocol, the data is stored in a FIFO for one level of buffering and isolation from the next module, and is spliced and stored in the FIFO.

[0020] As a preferred scheme of the SHA256 efficient digital encryption method based on FPGA, the calculation of the encrypted hash value includes:

[0021] Firstly, the data stored in the FIFO is read, and the output data is spliced by the state machine, when the frame data symbol is valid, the spliced data is the data to be encrypted, that is, the data source;

[0022] Secondly, 8 splicing operations are performed, and the frame delimiter is limited in height at the 8th splicing operation, at this time a spliced data valid signal is generated, which is used to judge that the data splicing signal has been spliced for 8 times to become the data to be encrypted, after the splicing is completed, the spliced data valid signal is pulled high according to the actual needs of the system, the spliced data is obtained, and an initial hash value is initialized, and the initial hash value is stored in a 256-bit initial hash register;

[0023] Finally, the spliced data, the spliced data valid signal and the initial hash value are sent to the SHA256 algorithm core implementation module as the data input of the module; and the 256-bit output hash register and the hash output valid signal are used as the output.

[0024] As a preferred scheme of the SHA256 high-efficiency digital encryption method based on FPGA, the encrypted hash value obtained by calculation further comprises:

[0025] 64 encryption cycles are performed, when the spliced data valid signal is 1, the bit width of the 8 encryption data ports is 32 bits, the initial value of the 8 encryption data ports is equal to the initial hash register, the 8 encryption data ports are iterated each time, and the final calculation result output hash register equal to the 8 encryption data ports is 256 bits.

[0026] The iteration loop is realized by the state machine, and the state machine has 66 states, the initial state does not operate until the spliced data and the spliced data valid signal are pulled high according to the actual needs of the system, the state machine jumps to the next state to perform the iteration loop, the iteration loop consumes 64 states, each state performs corresponding calculation operation, and the iteration loop ends to enter the 66th state, in which the encrypted hash value and the hash register value are output, and the hash output valid signal is output.

[0027] As a preferred scheme of the SHA256 high-efficiency digital encryption method based on FPGA, the hash value is sent to the receiving data control module, and then sent to the PCIE interface control module and returned to the PC module through the PCIE protocol, and the method comprises the following steps:

[0028] The receiving data control module receives a hash output valid signal as an input, a 256-bit output hash register, and an AXI4 bus interface output, which accepts a hash value calculated by an SHA256 algorithm core implementation module and converts the hash value into an AXI4 standard bus interface output to a PCIE interface control module;

[0029] The internal logic of the module is as follows: a FIFO is created, the FIFO has a 256-bit input bit width and a 64-bit output bit width; when the hash output valid signal is at a high level, the value of the output hash register is written into the FIFO; when the FIFO is not empty, the FIFO read enable is always valid, and all the data stored in the FIFO are output, and a counter is set; when the FIFO read enable is at a high level, the counter is incremented by one, and when the counter value is 3, the counter is cleared to 0.

[0030] In a second aspect, the present application provides an FPGA-based SHA256 high-efficiency digital encryption system, which comprises:

[0031] A PC module for sending a message to be encrypted and accepting encrypted information;

[0032] An FPGA module for accepting the message to be encrypted, performing encryption processing on the message to be encrypted, and then sending the encrypted information back to the PC module;

[0033] A PCIE interface control module for realizing data exchange between the PC module and the FPGA module, accepting the message to be encrypted sent by the PC module, and transmitting the encrypted information back to the PC module;

[0034] A PCIE space register access module for accessing the space register of the PCIE interface control module, realizing interrupt enable, interrupt clearing and related register configuration, detecting PCIE interface key signals, and generating an interrupt request signal;

[0035] A receiving data control module for accepting data of the PC module received by the PCIE interface control module and outputting the data to the SHA256 algorithm core implementation module, and also accepting encrypted information returned by the SHA256 algorithm core implementation module and sending the encrypted information to the PCIE interface control module;

[0036] An SHA256 algorithm core implementation module for calculating a hash value after encryption and sending the calculated hash value to the receiving data control module.

[0037] In a third aspect, the present application provides a computer device comprising a memory and a processor, and the memory stores a computer program, wherein the processor realizes any step of the above method when executing the computer program.

[0038] In a fourth aspect, the present application provides a computer readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements any of the steps of the method described above.

[0039] Compared with the prior art, the present application has the following advantages: the FPGA module is faster than the software implementation, the delay time is mainly caused by the delay of the gate circuit, and the CPU and memory usage are less, so the processor has enough time to process other tasks to improve the efficiency of the entire system; through the hardware encryption method, all encryption information in the hardware encryption is built-in in the hardware chip, so that the method of hacking by hacking encryption information to steal data will be completely ineffective; according to the principle of SHA-256 algorithm, the FPGA chip resource characteristics are analyzed, and an algorithm hard implementation IP with high bandwidth and good portability is designed, and the number of algorithm cores can be flexibly configured for easy expansion. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor. Among them:

[0041] Figure 1 The principle diagram of the FPGA-based SHA256 high-efficiency digital encryption method according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of protection of the present application.

[0043] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0044] Second, the "one embodiment" or "an embodiment" referred to herein means a specific feature, structure, characteristic, or combination of features and characteristics described herein that can be included in at least one implementation of the present application. The various appearances of "in one embodiment" or "an embodiment" in the specification do not all refer to the same embodiment, although they can.

[0045] The present application is described in detail in conjunction with the schematic drawings, and in the detailed description of the embodiments of the present application, the sectional view of the device structure is partially enlarged without the general proportion for the convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of protection of the present application. In addition, three-dimensional spatial dimensions including length, width and depth should be included in actual production.

[0046] Meanwhile, in the description of the present application, it should be noted that the terms "upper, lower, inner and outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first, second or third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0047] Unless otherwise expressly specified and limited, the terms "mounting, connecting, connection" in the present application should be understood broadly, for example: it can be fixed connection, detachable connection or integral connection; it can also be mechanical connection, electrical connection or direct connection, it can also be indirectly connected through intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] Embodiment 1

[0049] Reference Figure 1 For the first embodiment of the present application, the embodiment provides a high-efficiency digital encryption method based on FPGA SHA256, which comprises:

[0050] S1, the PC module generates a data to be encrypted (data source) and sends it to the FPGA module through the PCIE protocol;

[0051] S2, the PCIE interface control module (xdma) accepts the data to be encrypted (data source) and sends the data to the PCIE interface control module (rev_data_ctrl);

[0052] S3, the received data control module (rev_data_ctrl) sends the received data to the SHA256 algorithm core implementation module (SHA256_CORE) for operation;

[0053] S4, the SHA256 algorithm core implementation module (SHA256_CORE) calculates the encrypted hash value, and sends the calculated hash value to the received data control module (rev_data_ctrl);

[0054] S5, the received data control module (rev_data_ctrl) receives the hash value calculated by the SHA256 algorithm core implementation module (SHA256_CORE), and sends it to the PCIE interface control module (xdma);

[0055] S6, the PCIE interface control module (xdma) sends the encrypted hash value to the PC module through the PCIE protocol;

[0056] It should be noted that the PC and FPGA data transmission is through PCIE 2.0x2, and the theoretical bandwidth is 10Gb / s; The FPGA module uses xilinx xc7a100tffg484-2 chip; The xdma module calls the IP core of the internal PCIE of the FPGA chip; The ram2reg module is mainly the PC module accessing the rev_data_ctrl module control management SHA256_CORE algorithm and PCIE end XDMA communication;

[0057] Compare the original correct encrypted hash value of the PC module with the hash value to obtain an efficient digital encryption method;

[0058] Further, in S1, the sent data to be encrypted (encryption source) is a 256-bit data source after preprocessing; The PC module includes two parts: PCIe card driver and PCIe host test program; The PCIe card driver is responsible for data exchange between the host test program and the PCIe card; The PCIe host test program is responsible for completing the functional operation, which can be manifested as visual encrypted data, secret data and correct data comparison, and speed measurement of the digital encryption system in the present application; Here, it is assumed that the data to be encrypted is 80bit (bit) wide, and the hexadecimal representation is 426c6f636b436861696e; Before sending the data to the FPGA through the PCIE interface, the data is preprocessed, and the preprocessed data pre_data[511:0] is {80'h426c6f636b436861696e,1'b1,367'd0,64'd80};

[0059] Wherein, "{}" is a bit splicing symbol, and the port name is connected after the [] to represent the port bit width, and [0:0] represents 1bit bit width, and the default port is not connected after the [] and is 1bit bit width;

[0060] Further, in S2, XDMA is a Xilinx packaged PCIE DMA transmission IP, which can conveniently map the data transmission transaction on the PCIE bus to the AXI bus, realize the direct reading and writing of the upper computer to the AXI bus, and be insensitive to the packet assembling and unpacking of the PCIE itself TLP, the xdma module is responsible for the communication between the PC module and the FPGA, and mainly performs data transmission; the XDMA reading and writing part is divided into two kinds, one is the reading and writing of data, and the other is the reading and writing of configuration data;

[0061] Here, the XDMA module controls the PCIE interface to accept the pre_data data sent by the PC, the module output adopts the AXI4_STREAM standard protocol, and then outputs the received pre_data[511:0] data to the rev_data_ctrl module in 8 64bit data, and the output port is represented as:

[0062] M_AXIS_H2C_0_0_tdata[63:0],

[0063] M_AXIS_H2C_0_0_tkeep[7:0],

[0064] M_AXIS_H2C_0_0_tlast,

[0065] M_AXIS_H2C_0_0_tready,

[0066] M_AXIS_H2C_0_0_tvalid;

[0067] And the data is output in turn as follows:

[0068] 64'h426c6f636b436861,

[0069] {16'696e,1'b1,47'd0},

[0070] 64'd0,64'd0,64'd0,

[0071] 64'd0,64'd0,64'd80;

[0072] It should be noted that in the data reading and writing part, the DMA directly reads and writes data through the AXI4_STREAM standard protocol interface; the configuration data reading and writing is completed through the connection of BRAM and AXI-lite bus, which reduces the difficulty of direct operation of axi lite interface and improves the reliability of register access;

[0073] Further, in S3, the rev_data_ctrl module receives the data to be encrypted (data source), and the receiving interface is an AXI4_stream standard interface. The specific receiving data port is represented as:

[0074] M_AXIS_H2C_0_0_tdata[63:0],

[0075] M_AXIS_H2C_0_0_tkeep[7:0],

[0076] M_AXIS_H2C_0_0_tlast,

[0077] M_AXIS_H2C_0_0_tready,

[0078] M_AXIS_H2C_0_0_tvalid;

[0079] The output data of the module after processing is represented as:

[0080] dout[64:0], rd_en, empty;

[0081] After the rev_data_ctrl module receives the data through the standard protocol, the data is stored in a FIFO for one-stage buffering, so as to be fully isolated from the next module. The receiving data M_AXIS_H2C_0_0_tdata is 64 bits, and the data stored in the FIFO is 65 bits. The M_AXIS_H2C_0_0_tlast and M_AXIS_H2C_0_0_tdata are spliced and stored in the FIFO together.

[0082] It should be noted that the splicing is to enable the next module to correctly determine the frame data boundary.

[0083] A FIFO is created in the rev_data_ctrl module, which is used for module isolation. The logic of the module is as follows: the states (0 or 1) of M_AXIS_H2C_0_0_tlast, M_AXIS_H2C_0_0_tready and M_AXIS_H2C_0_0_tvalid control the writing of the FIFO, and the reading of the FIFO is controlled by the SHA256_CORE module. Under the control of the SHA256_CORE module, the data is output in sequence, which is represented as:

[0084] {1'b0,64'h426c6f636b436861},{1'b0,16'696e,1'b1,47'd0},......{1'b1,64'd80};

[0085] It can be seen that in the last 64 bits of the data frame, the header extension is 1 bit value 1, and at other times the header extension is 1 bit value 0;

[0086] It should be noted that the AXI4_stream interface has the advantages of good flexibility, simple interconnection mode, reliable and easy-to-control data interaction, and the output port adopts a normal interface.

[0087] Further, in S4, the SHA256 algorithm is implemented, which is the core module of the entire system algorithm implementation. In this module, the data stored in the FIFO by the previous stage is first read, and a state machine is adopted to splice the output data. When the frame data symbol is valid, the spliced data is the data to be encrypted (data source) at this time. It has been stated in S1 that the data to be encrypted (data source) is 256 bits, and the valid data stored in the FIFO is 64 bits (1 bit is a frame delimiter). Therefore, the data needs to be spliced for 8 times. At the same time, the frame delimiter is high at the 8th splicing operation, which will generate an in_wr valid signal. The signal is 1 bit wide, which is used to judge that the data splicing signal has become the data to be encrypted (data source) after 8 times of splicing. The in_wr signal is pulled high after splicing. Here, when in_wr is 1, the spliced data msg is {80'h426c6f636b436861696e, 1'b1, 367'd0, 64'd80}.

[0088] Through the spliced data msg obtained by the above method and the spliced data valid signal in_wr, an initial hash value iv is initialized. In the FPGA, the initial hash value is directly stored in a 256-bit register iv[255:0]. These data are sent to the SHA256_Compress module, msg, in_wr and iv are used as the data input hvalue[255:0] and h_wr as the output of the module, and the module is the core processing module of the SHA256 algorithm.

[0089] SHA256_Compress module, the SHA256 algorithm is to be encrypted 64 times, in_wr is 1, a~h each port bit width is 32bit, {a, b, c, d, e, f, g, h} is assigned an initial value equal to iv[255:0], each loop iteration {a, b, c, d, e, f, g, h}, the last calculation result output hash value hvalue[255:0] = {a, b, c, d, e, f, g, h}; This iterative loop can be realized by the way of state machine in FPGA, set the state machine has 66 states, the initial state does not operate, wait for the splicing data msg and the valid signal in_wr pull high, the state machine jumps to the next state to carry out the iterative loop, the iterative loop consumes 64 states, each state executes the corresponding calculation operation, the iterative loop ends and enters the 66th state, in which the encrypted hash value hvalue[255:0] is output, the output valid signal h_wr is pulled high, which is effective for indicating that the output hash value is valid; The iteration update of {a, b, c, d, e, f, g, h} is realized by the instantiation module SHA256_Round (round function) in the SHA256_Compress module; After the calculation of the SHA256_Compress module, h_wr is output as 1 in the 66th state of the state machine, and the calculation result is:

[0090] hvalue[255:0] = 16'h3a6fed5fc11392b3ee9f81caf017b48640d7458766a8eb0382899a605b41f2b9;

[0091] The SHA256_Round module completes the iteration update of {a, b, c, d, e, f, g, h}, and the module output signal is {a_o, b_o, c_o, d_o, e_o, f_o, g_o, h_o}, the iteration logic is as follows:

[0092] {b_o, c_o, d_o, f_o, g_o, h_o} = {b, c, d, g, f, h}

[0093] a_o = T1 + T2

[0094] e_o = d + T1

[0095] T1, T2 are related to the calculation of σ0(x), σ1(x), ∑0(x), ∑1(x), M aj (x, y, z), CH(x, y, z) and addition operation; σ0(x), σ1(x), ∑0(x), ∑1(x), Maj (x, y, z), CH(x, y, z) involves some simple logic operations: bitwise XOR, bitwise AND, bitwise NOT, right shift and cyclic right shift, which can be obtained directly by logic operators in FPGA, consuming very few resources and very low delay; The maximum delay in the SHA256_Compress module comes from the addition module, especially the addition operation involved in the calculation of a (32-bit width) up to 6 times, e needs five addition operations, which requires a large number of DSP resources to support addition operations;

[0096] It should be noted that in order to improve the parallel speed of multi-algorithm kernel and reduce the dependence of single algorithm on DSP, the bit shift carry reduction addition method is used instead of DSP, which reduces resource consumption without reducing operation speed;

[0097] Further, assuming that the input 6 data is x0, x1, x2, x3, x4, x5, the data bit width is 32 bits, and the output y is 32 bits, the bit shift carry reduction addition running process is as follows: x0, x1, x2, x3, x4, x5 are spliced to get 32 6-bit data {x0[0],..., x5[0]},..., {x0

[31] ,..., x5

[31] } Input into the lookup table to get {sum[0],..., sum

[31] }, sum[i] is the number of 1s in each group {x0[i],..., x5[i]} in binary form, y = {sum

[31] ,..., sum[0]} + {sum

[30] ,..., sum[0], 1'b0} + {sum

[29] ,..., sum[0], 2'b0};

[0098] It can be seen that the above process changes the 6-input addition circuit into a lookup table and a 3-input addition circuit; The circuit delay of the lookup table is very low, and a 6-input addition operation method with very fast operation speed is obtained;

[0099] Further, in S5, the rev_data_ctrl module inputs h_wr, hvalue[255:0] and outputs AXI4 bus interface, port s_axis_tdata[63:0], s_axis_tvalid, s_axis_tlast; this part accepts the hash value calculated by the SHA256_CORE module and converts it into an AXI4 standard bus interface output to the XDMA module; the internal logic of this module is as follows: a FIFO is created, the input bit width of the FIFO is 256 bits, the output bit width is 64 bits, when h_wr is 1, hvalue[255:0] is written into the FIFO, when the FIFO is not empty, the FIFO read enable rd_en is always valid, and all the data stored in the FIFO is output; at the same time, a counter cnt[1:0] is set, when rd_en, the counter is incremented by one, when the counter cnt value is 3, cnt is cleared to 0; rd_en is valid, s_axis_tvalid is assigned 1, when cnt is equal to 3, s_axis_tlast is assigned 1; in S5, the SHA256_CORE module calculates the encrypted hash value, and s_axis_tdata will continuously output 4 64-bit data, and the output data is as follows:

[0100] 64'h3a6fed5fc11392b3,

[0101] 64'hee9f81caf017b486,

[0102] 64'h40d7458766a8eb03,

[0103] 64'h82899a605b41f2b9;

[0104] s_axis_tvalid is 1 during output data, and s_axis_tlast is also high at the fourth data;

[0105] Further, in S6, the xdma module accepts the calculated hash value through the AXI4 standard bus protocol, and controls the PCIE interface to send the encrypted hash value to the PC host;

[0106] Further, in S7, a source data is obtained in advance, and a hash value is calculated by a computer, then the source data is sent to the FPGA end for processing, the FPGA calculates a hash encryption value, and the hash value calculated by the computer is compared with the hash value calculated by the FPGA to verify the correctness of the FPGA calculation.

[0107] Further, the embodiment also provides a SHA256 high-efficiency digital encryption system based on FPGA, which comprises:

[0108] a PC module for sending a message to be encrypted and accepting the encrypted information;

[0109] an FPGA module for accepting the message to be encrypted, encrypting the message to be encrypted, and sending the encrypted information back to the PC module;

[0110] a PCIE interface control module for realizing data exchange between the PC module and the FPGA module, accepting the message to be encrypted sent by the PC module, and sending the encrypted information back to the PC module;

[0111] a PCIE space register access module for accessing the space register of the PCIE interface control module, realizing interrupt enable, interrupt clearing, and related register configuration, detecting PCIE interface key signals, and generating an interrupt request signal;

[0112] an accepting data control module for accepting the data of the PC module received by the PCIE interface control module, and outputting the data to the SHA256 algorithm core implementation module; and accepting the encrypted information returned by the SHA256 algorithm core implementation module, and sending the encrypted information to the PCIE interface control module;

[0113] a SHA256 algorithm core implementation module for calculating the encrypted hash value, and sending the calculated hash value to the accepting data control module.

[0114] The embodiment also provides a computer device suitable for the case of the FPGA-based SHA256 high-efficiency digital encryption method.

[0115] a memory and a processor; the memory is used for storing computer executable instructions, and the processor is used for executing the computer executable instructions to realize the FPGA-based SHA256 high-efficiency digital encryption method proposed in the above embodiment.

[0116] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is configured to perform wired or wireless communication with an external terminal. The wireless communication can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0117] The embodiment also provides a storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the FPGA-based SHA256 high-efficiency digital encryption method according to the above embodiment.

[0118] The storage medium according to the embodiment and the data storage method according to the above embodiment belong to the same inventive concept, and the technical details not described in the embodiment can be referred to the above embodiment, and the embodiment has the same beneficial effects as the above embodiment.

[0119] Embodiment 2

[0120] Referring to Table 1, the second embodiment of the present application provides a FPGA-based SHA256 high-efficiency digital encryption method, which includes the following steps:

[0121] Through simulation experiment data, the FPGA system, the ASIC system and the CPLD system according to the method of the present application are compared, as shown in Table 1:

[0122] Table 1: Comparison of SHA256 algorithms of three systems

[0123]

[0124] It can be seen that in the three programmable circuit products of ASIC, CPLD and FPGA, when using SHA256 algorithm for hashing, the system running time, data transmission bandwidth and accuracy under different input data lengths will increase with the increase of input data length, and the system running time and data transmission bandwidth will increase, while the accuracy will gradually decrease; compared with ASIC and CPLD, the FPGA used in the application has higher flexibility and programmability, and can realize different computing tasks by reprogramming; it can be seen from the table that when processing SHA256 hashing algorithm, FPGA shows excellent performance under all input data lengths; when the input data length is 10 bytes, the system running time and data transmission bandwidth of FPGA are about 20% and 10% faster than ASIC and CPLD respectively; when the input data length is 1000 bytes and 10000 bytes, the system running time and data transmission bandwidth of FPGA are about 20% and 30% faster than ASIC and CPLD respectively; when the input data length is 100000 bytes, the system running time and data transmission bandwidth of FPGA are about 30% and 80% faster than ASIC and CPLD respectively.

[0125] In addition to the advantages in performance, FPGA also has higher programmability and scalability, which can quickly adapt to different computing needs and algorithm changes; FPGA can realize highly customized computing tasks, and can continuously optimize and upgrade system performance through reprogramming, with longer service life and lower maintenance cost; in summary, FPGA shows obvious advantages in processing hashing algorithm, with higher performance, higher flexibility and programmability.

[0126] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit it, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalent, without departing from the spirit and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

1. A high-efficiency digital encryption method based on FPGA using SHA256, characterized in that, include: The PC module generates the data to be encrypted and sends it to the FPGA module as a data source using the PCIE protocol. The PCIe interface control module receives the data source and sends the data source to the receiving data control module. The receiving data control module sends the received data source to the SHA256 algorithm core implementation module for calculation to obtain the encrypted hash value; The hash value is sent back to the receiving data control module, then sent to the PCIE interface control module, and returned to the PC module via the PCIE protocol; By comparing the original correctly encrypted hash value of the PC module with the hash value mentioned above, an efficient digital encryption method is obtained. The data to be encrypted is a pre-processed 256-bit data source. The PCIE interface control module is divided into two parts: reading and writing. The first part is reading and writing data, and the second part is reading and writing configuration data. After the data receiving control module receives data through the standard protocol, it stores the data in a FIFO as a first-level buffer and isolates it from the next module, while also splicing the data into the FIFO. The encrypted hash value is calculated, including: First, the data stored in the FIFO is read, and the output data is concatenated using a state machine. When the frame data symbol is valid, the concatenated data is the data to be encrypted, i.e., the data source. Secondly, eight splicing operations are performed. During the eighth splicing operation, the frame qualifier is height-limited. At this time, a splicing data valid signal is generated to determine that the data splicing signal has been spliced ​​eight times and has become the data to be encrypted. After the splicing is completed, the splicing data valid signal is pulled high according to the actual needs of the system to obtain the spliced ​​data. At the same time, an initial hash value is initialized and stored in a 256-bit initial hash register. Finally, the concatenated data, the valid signal of the concatenated data, and the initial hash value are sent to the SHA256 algorithm core implementation module as the data input of the module; the 256-bit output hash register and the valid signal of the hash output are used as the output.

2. The FPGA-based high-efficiency digital encryption method for SHA256 as described in claim 1, characterized in that, The calculated encrypted hash value also includes: The encryption loop is performed 64 times. When the valid signal of the concatenated data is 1, the bit width of each of the 8 encryption data ports is 32 bits. The initial value of each of the 8 encryption data ports is equal to the initial hash register. Each loop iterates through the 8 encryption data ports. The final calculation result outputs a hash value of 256 bits. The output hash register is equal to the 8 encryption data ports. The iterative loop is implemented using a state machine with 66 states. The initial state is inactive until the concatenated data and the concatenated data validity signal are pulled high according to the actual needs of the system. The state machine then jumps to the next state to start the iterative loop. The iterative loop consumes 64 states. Each state performs the corresponding calculation operation. When the iterative loop ends, it enters the 66th state, where it outputs the encrypted hash value, the hash register value, and the hash output validity signal.

3. The FPGA-based high-efficiency digital encryption method for SHA256 as described in claim 1 or 2, characterized in that, The hash value is sent back to the receiving data control module, then sent to the PCIe interface control module, and returned to the PC module via the PCIe protocol, including: The input to the data control module is a hash output valid signal. The output hash register is 256 bits, and the output is an AXI4 bus interface. It accepts the hash value calculated by the SHA256 algorithm core implementation module and converts it into an AXI4 standard bus interface output to the PCIE interface control module. The internal logic of this module is as follows: A FIFO is created with an input width of 256 bits and an output width of 64 bits; when the hash output valid signal is high, the value of the output hash register is written into the FIFO; when the FIFO is not empty, the FIFO read enable is always valid, all the data stored in the FIFO is output, and a counter is set; when the FIFO read enable is high, the counter is incremented by one, and when the counter value is 3, the counter is cleared to 0.

4. A high-efficiency SHA256 digital encryption system based on FPGA, based on the high-efficiency SHA256 digital encryption method based on FPGA as described in any one of claims 1 to 3, characterized in that, include: The PC module is used to send messages to be encrypted and to receive encrypted information. The FPGA module is used to receive messages to be encrypted, encrypt the messages, and then send the encrypted information back to the PC module. The PCIe interface control module is used to realize data exchange between the PC module and the FPGA module. The PCIe interface control module receives the message to be encrypted sent by the PC module and transmits the encrypted information back to the PC module. The PCIE space register access module is used to access the space registers of the PCIE interface control module, enable interrupts, clear interrupts and related register configurations, detect key PCIE interface signals, and generate interrupt request signals. The data receiving control module is used to receive data from the PC module received by the PCIe interface control module and output the data to the SHA256 algorithm core implementation module; at the same time, it also receives encrypted information returned by the SHA256 algorithm core implementation module and sends it to the PCIe interface control module. The SHA256 algorithm core implementation module is used to calculate the encrypted hash value and send the calculated hash value to the receiving data control module.

5. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 3.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.

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