A test circuit, an array substrate, and a display device

Abstract

This application provides a test circuit, an array substrate, and a display device. The test circuit includes a first TFT switch and first and second pads arranged adjacent to each other along a first direction. The first pad is configured to input the first test signal into the GOA circuit for testing when a first test signal is received and the first TFT switch is turned on. The second pad is configured to turn on the first TFT switch using a control signal when a control signal is received. The control signal has the opposite logic level to the first test signal. This application utilizes the second pad to control the first TFT switch to determine whether to perform GOA testing. Since the signal levels input by the adjacent first and second pads are opposite, the first TFT switch can be disconnected in case of accidental contact due to external test probe misalignment, preventing abnormal charge from flowing into the GOA circuit and improving the reliability of the electrical function of the GOA circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display devices, and in particular to a test circuit, an array substrate, and a display device. BACKGROUND

[0002] The related art provides a Gate Driven on Array (GOA) circuit by integrating a Gate row scanning driving signal circuit on an array substrate, thereby enabling a row-by-row scanning driving function of a liquid crystal panel, which can save scanning driving related integrated circuits, reduce manufacturing process procedures, lower product process costs, and save panel structure design space.

[0003] In the manufacturing process of the existing GOA circuit, the adjacent lines on the panel are relatively close, which can easily cause an electrostatic discharge or other unexpected situations, and can destructively affect the function of the circuit. Therefore, in the manufacturing process of the GOA product or after the manufacturing is completed, an electrical test of the GOA circuit is an indispensable process. However, the electrical function test of the GOA circuit is affected by many factors such as structure design and operator error, which often has a negative impact on the electrical function of the GOA circuit. Therefore, the technical problem to be solved by the technical personnel at present is how to reduce the possibility of negative impact of the electrical test on the GOA circuit.

[0004] It should be noted that the information in the above background art distinguishes the invention, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] Embodiments of the present application provide a test circuit, an array substrate, and a display device, which are designed to control a first TFT switch to determine whether to perform a GOA test by using a second pad, and the signal level of the adjacent first pad and the second pad is opposite, so that in the case of position offset and accidental touch of the external test probe, the first test signal with the opposite level of the control signal is provided to the second pad, the first TFT switch is turned off, abnormal charges are prevented from flowing into the GOA circuit through the test circuit, and the reliability of the electrical function of the GOA circuit is improved.

[0006] In one aspect, embodiments of the present application provide a test circuit, comprising:

[0007] a first TFT switch, and a first pad and a second pad arranged adjacent to each other in a first direction;

[0008] the first pad is configured to, in a case where a first test signal is obtained and the first TFT switch is turned on, introduce the first test signal into a GOA circuit, and test the GOA circuit.

[0009] The second pad is configured to, in a case where a control signal is obtained, use the control signal to turn on the first TFT switch.

[0010] The control signal is opposite in logic level to the first test signal.

[0011] Optionally, the test circuit further comprises:

[0012] The third pad is configured to, in a case where a second test signal is obtained and the first TFT switch is turned on, introduce the second test signal into the GOA circuit for testing.

[0013] The fourth pad is configured to, in a case where the first test signal is obtained and the first TFT switch is turned on, introduce the first test signal into the GOA circuit for testing.

[0014] The first pad, the third pad, and the fourth pad are arranged side by side along the first direction, and the first pad and the fourth pad are respectively located on two adjacent sides of the second pad.

[0015] Optionally, the test circuit further comprises:

[0016] The third pad is configured to, in a case where a second test signal is obtained and the first TFT switch is turned on, introduce the second test signal into the GOA circuit for testing.

[0017] The first pad and the third pad are arranged side by side along the first direction, and the third pad is located on a side of the first pad away from the second pad.

[0018] Optionally, the second pad comprises one of: a drain power voltage pad, a switch pad.

[0019] The drain power voltage pad is further configured to, in a case where the control signal is obtained and the first TFT switch is turned on, introduce the control signal as a third test signal into the GOA circuit for testing.

[0020] Optionally, the test circuit further comprises: a semiconductor switch.

[0021] An input end of the semiconductor switch is electrically connected to an output end of the second pad, and an output end of the semiconductor switch is electrically connected to a gate of the first TFT switch.

[0022] Optionally, the semiconductor switch comprises: a diode or a second TFT switch.

[0023] The gate of the second TFT switch is electrically connected with the output end of the second pad, the gate of the second TFT switch is electrically connected with the source, and the drain of the second TFT switch is electrically connected with the gate of the first TFT switch.

[0024] Through the above embodiment, the test circuit provided by the application has the following advantages:

[0025] (1) The application controls the first TFT switch through the second pad to determine whether the first test signal is introduced into the GOA circuit for testing. Whether the test on the GOA circuit is performed can be determined by whether the second pad is connected to the control signal. On the basis of receiving the stylus signal through the pad for GOA circuit testing, double control is realized.

[0026] (2) The first pad and the second pad in the embodiment of the application are arranged adjacent to each other, and the logic levels of the signals introduced by the two pads are opposite. In the case of position offset and accidental touch of the external test stylus, the first test signal with an opposite level to the control signal is given to the second pad, and then the first TFT switch is turned off, so as to avoid abnormal charges from flowing into the GOA circuit through the test circuit, thereby improving the reliability of the electrical function of the GOA circuit.

[0027] In summary, the embodiment of the application can reduce the possibility of negatively affecting the electrical function of the GOA circuit from multiple aspects.

[0028] In another aspect, the embodiment of the application also provides an array substrate, comprising:

[0029] a display area;

[0030] a circuit area located on at least one side of the display area;

[0031] The circuit area comprises a GOA circuit and a test circuit according to any one of claims 1 to 6.

[0032] Optionally, the circuit area is located on opposite sides of the display area arranged side by side along the first direction.

[0033] The second pad is located on at least one side of the opposite sides arranged side by side along the first direction.

[0034] Optionally, the first TFT switch and the first pad are located on opposite sides arranged side by side along the first direction.

[0035] The first pad is configured to test the GOA circuit on the same side of the opposite sides arranged side by side along the first direction.

[0036] The second pad is configured to turn on the first TFT switch on at least one side of the two opposite sides arranged side by side along the first direction.

[0037] Optionally, the circuit region extends along the second direction, and the test circuit is arranged at one end of the circuit region.

[0038] The first TFT switch is arranged side by side along the first direction at a position where the test circuit intersects with the GOA circuit.

[0039] Optionally, the first test signal is a low-level gate voltage signal, and the control signal is a high-level signal.

[0040] The array substrate provided by the embodiments of the present application includes the test circuit in the above embodiments and has all the advantages of the test circuit.

[0041] In another aspect, the embodiments of the present application further provide a display device including the array substrate in the above embodiments.

[0042] The display device provided by the embodiments of the present application includes the array substrate in the above embodiments and has all the advantages of the array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings are only used for reference and illustration, and are not used to limit the protection scope of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present application.

[0044] Figure 1 A structural block diagram of a test circuit in one embodiment provided by the present application is shown;

[0045] Figure 2 A structural block diagram of another test circuit in one embodiment provided by the present application is shown;

[0046] Figure 3 A structural block diagram of another test circuit in one embodiment provided by the present application is shown;

[0047] Figure 4A structural diagram of an array substrate in one embodiment provided by the present application is shown;

[0048] Figure 5 A structural diagram of an array substrate in one embodiment provided by the present application is shown;

[0049] Figure 6 A structural diagram of an array substrate in one embodiment provided by the present application is shown;

[0050] Figure 7 A structural diagram of an array substrate in one embodiment provided by the present application is shown;

[0051] Figure 8 A structural diagram of an array substrate in one embodiment provided by the present application is shown;

[0052] Figure 9 A structural diagram of an array substrate in one embodiment provided by the present application is shown;

[0053] Figure 10 A structural diagram of a first TFT switch in one embodiment provided by the present application is shown;

[0054] Figure 11 A structural diagram of a first TFT switch in one embodiment provided by the present application is shown;

[0055] Figure 12 A structural diagram of a first TFT switch in one embodiment provided by the present application is shown;

[0056] Figure 13 A structural diagram of a semiconductor switch in one embodiment provided by the present application is shown;

[0057] Figure 14 A structural diagram of a display data pad in one embodiment provided by the present application is shown.

[0058] Explanation of reference numerals:

[0059] 101 - first pad; 102 - second pad; 103 - third pad; 104 - fourth pad; 108 - display data pad; 201 - first TFT switch; 301 - control signal line; 302 - test signal line; 401 - second TFT switch; test circuit - 700; 800 - GOA circuit; 900 - display area; 501 - first gate; 502 - first source; 503 - first drain; 504 - first active layer; 505 - first channel; 601 - second gate; 602 - second source; 603 - second drain; 604 - second active layer; 605 - second channel; 801 - third TFT switch. DETAILED DESCRIPTION

[0060] In order to make the purposes, technical solutions and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0061] Currently, GOA products generally adopt the mode of electrically connecting test probes and product sample pads to import test signals and complete electrical testing. However, the current test of the electrical function of the GOA circuit is affected by many factors such as structural design and personnel operation errors, which often has a negative impact on the electrical function of the GOA circuit. Taking the Cell test of the display substrate with the GOA circuit as an example, in the case of the product sample and the test probe position offset, the test probe is misaligned with the test pad configured to input the test signal, the test pad will import abnormal charge into the GOA circuit, thereby causing the display substrate to light abnormally, and after the correct electrical connection between the test probe and the product sample is restored, the display substrate will continue to have display picture flicker due to the residual charge in the product pixels, which seriously affects the electrical function of the display product.

[0062] In the display substrate, when static electricity is induced to the storage capacitor on the product, the static electricity of the capacitor can release the charge on the pixel through the leakage current of the TFT. The inventors found that after the first electrical test, the product is generally in a charge storage state. Since the leakage current of the oxide GOA product is about 1e-12A and the leakage current of the a-Si TFT product is 1e-9A, the oxide GOA product is about 1000 times slower than the a-Si TFT product in extreme cases. Obviously, the charge release capacity of the oxide GOA product pixel is much weaker than that of the A-Si TFT product. Because the leakage current is smaller, the abnormal residual charge on the oxide GOA product is more difficult to release, and display picture flicker and other defects will occur in the subsequent lighting process.

[0063] In order to improve the above problems, the embodiment of the present application provides a test circuit, an array substrate and a display device. The second pad is used to control the first TFT switch, and determine whether the first test signal is introduced into the GOA circuit for testing. The first pad and the second pad are arranged adjacently, the logic levels of the signals introduced by the two pads are opposite, the test of the GOA circuit can be controlled, the error conduction caused by the deviation of the external test probe can be avoided, the first TFT switch can be controlled to be turned off when the second pad does not input the control signal, the abnormal charge on the first pad can be prevented from flowing into the GOA circuit, the possibility of the negative influence on the electrical function of the GOA circuit is reduced from multiple aspects, the accuracy and the test efficiency of the test circuit are improved, and the production yield and the production efficiency of the GOA product are improved.

[0064] The embodiment of the present application will be described below with reference to the drawings.

[0065] Referring to Figure 1 , Figure 1 The structure block diagram of a test circuit 700 in one embodiment provided by the present application is shown. As shown in Figure 1 The embodiment of the present application provides a test circuit 700, which includes a first TFT switch 201 and a first pad 101 and a second pad 102 arranged adjacently along a first direction.

[0066] The first TFT switch 201 can include a gate, a source and a drain.

[0067] In an optional example, the first pad 101 can be electrically connected with a first test signal line 302 extending along a second direction, the second pad 102 can be electrically connected with a control signal line 301 extending along the first direction, and the first TFT switch 201 can be arranged at an insulating overlapping position of the first test signal line 302 and the control signal line 301. Thus, the control signal line 301 can be electrically connected with the gate of the first TFT switch 201, the first TFT switch 201 can be controlled to be turned on or off, and the first TFT switch 201 can control the signal of the test signal line 302 including the first test signal line 302 to be turned on or off through the turning on or off of the source and the drain.

[0068] The first pad 101, the second pad 102, the third pad 103 and the like in the embodiment of the present application can be metal pads capable of conducting electricity, which can also be called metal contacts, and are configured to be electrically connected with external conductive probes, so as to realize various electrical tests including CT lighting test.

[0069] In an optional example, the test circuit 700 can be arranged on one side of the GOA circuit 800 to be tested, and the test circuit 700 and the GOA circuit 800 can be arranged on an array substrate. Further, the array substrate can be provided with a display area 900, and the first direction can be a direction along a side edge of the display area 900 on the array substrate. Alternatively, the first direction can be a direction in which a gate line extends in the array substrate. Correspondingly, the second direction can be a direction in which a data line extends in the array substrate.

[0070] The first pad 101 is configured to, in a case where the first test signal is obtained and the first TFT switch 201 is turned on, introduce the first test signal into the GOA circuit 800 to test the GOA circuit 800.

[0071] Specifically, the first pad 101 can be electrically connected to the GOA circuit 800 through a first test signal line 302, and the source and the drain of the first TFT switch 201 can be arranged on the first test signal line 302. Thus, by turning on and off the first TFT switch 201, the turning on and off of the first test signal transmitted on the first test signal line 302 can be controlled, and then whether the first test signal can be introduced into the GOA circuit 800 to be tested can be controlled.

[0072] The first pad 101 can be electrically connected to an external first test probe to obtain the first test signal.

[0073] Taking a light test as an example, the first pad 101 can be used to load the first test signal when the TFT LCD Single cell is subjected to a light test. In the embodiment of the present application, the test pads can include the first pad 101, a third pad 103, and a fourth pad 104, which are configured to input test signals to the GOA circuit 800.

[0074] The second pad 102 is configured to, in a case where a control signal is obtained, turn on the first TFT switch 201 by using the control signal.

[0075] In the embodiment of the present application, the second pad 102 is configured to control the turning on and off of the first TFT switch 201, and can be referred to as a control pad.

[0076] Specifically, the second pad 102 can be electrically connected to the gate of the first TFT switch 201 through a control signal line 301, and a specific level signal can be used to control the turning on and off of the first TFT switch 201.

[0077] The second pad 102 can be electrically connected to an external control probe to obtain the control signal.

[0078] The control signal is opposite in logic level to the first test signal.

[0079] Specifically, when the second pad 102 is not connected to the control signal, the first TFT switch 201 is turned off, and no test signal is input to the GOA circuit 800, the display is L0, no abnormal charge is filled into the pixel, and no charge residue and display flicker are caused subsequently.

[0080] The first TFT switch 201 can be turned on under a high-level signal. In order to not increase additional inverter and other components, reduce component cost and save structure design space, in an optional embodiment, the first test signal is a low-level signal, and the control signal is a high-level signal.

[0081] In the embodiments of the present application, the test circuit 700 can be used not only for GOA circuit testing of oxide GOA products, but also for GOA circuit testing of A-si TFT products.

[0082] In the related art, taking CT lighting test as an example, due to personnel operation or abnormal device needle contact, the sample and the external test needle position may be offset, the test alignment accuracy, i.e. the position offset distance, the offset causes the input GOA test signal to be abnormal, the output of the GOA circuit 800 is also abnormal, and then abnormal lighting occurs, abnormal charge is filled into the pixel, and it is not easy to release, charge residue or gray scale flicker occurs, especially for oxide GOA products, the leakage current is extremely small, the abnormal charge is not easy to release, and charge residue and display flicker and other defects exist in the subsequent lighting process, and it is not easy to dissipate, which seriously affects the product yield.

[0083] By the above embodiments, the present application controls the first TFT switch 201 through the second pad 102 to determine whether the first test signal is input to the GOA circuit 800 for testing, and whether the test on the GOA circuit 800 is performed by whether the second pad 102 is connected to the control signal. On the basis of using the pad to receive the test needle signal for GOA circuit 800 testing, double control is realized. The first pad 101 and the second pad 102 in the embodiments of the present application are arranged adjacent to each other, and the logic levels of the signals input by the two pads are opposite, so that the error conduction caused by the external test needle offset and miscontact can be avoided, and the first TFT switch 201 can be controlled to be turned off when the second pad 102 is not connected to the control signal, so that the residual charge on the first pad 101 does not flow into the GOA circuit 800. Therefore, the embodiments of the present application can reduce the possibility of negatively affecting the electrical function of the GOA circuit 800 from multiple aspects.

[0084] Reference Figure 3 , Figure 3 A structure schematic block diagram of another test circuit 700 in an embodiment provided by the present application is shown. As Figure 3As shown, considering that the second pad 102 can be connected to a high-level signal, the first TFT switch 201 can be directly turned on. In general, more than one test pad can be connected to a low-level signal. Therefore, two test pads connected to a low-level signal can be provided, and the two test pads are arranged on the two sides of the second pad 102. For this purpose, in an alternative embodiment, the application further provides a test circuit 700, which further comprises:

[0085] The third pad 103 is configured to introduce a second test signal into the GOA circuit 800 for testing when the second test signal is obtained and the first TFT switch 201 is turned on.

[0086] The fourth pad 104 is configured to introduce a first test signal into the GOA circuit 800 for testing when the first test signal is obtained and the first TFT switch 201 is turned on.

[0087] Considering that the test pads are generally connected to a low-level signal, for this purpose, in an alternative embodiment, the first test signal is a low-level signal, and the control signal is a high-level signal.

[0088] Considering that the test pads are generally not connected to a low-level signal in normal testing, that is, if all the test pads are connected to a high-level signal, the first pad 101 can only be connected to a high-level signal for testing, in order to make the signal level introduced by the first pad 101 opposite to the signal level introduced by the second pad 102, the second pad 102 can only be connected to a low-level signal. In another alternative embodiment, the first test signal is a high-level signal, and the control signal is a low-level signal.

[0089] In order to make the first TFT switch 201 turned on after the control probe inputs the control signal to the second pad 102, a signal inverter is arranged between the second pad 102 and the first TFT switch 201.

[0090] In the related art, due to the precision of the equipment and the operation of the personnel, the position offset distance of the sample and the external test probe is generally close to the width of a test pad. In the case of accidental position offset of the sample and the external test probe, in order to make the first test signal with a level opposite to that of the control signal input to the second pad 102, so that the second pad 102 is at a potential that makes the first TFT switch 201 closed, thereby avoiding abnormal charge from flowing into the GOA circuit 800. In an alternative embodiment, the application further provides a test circuit 700, wherein the widths of the first pad 101, the second pad 102, and the fourth pad 104 are the same in the first direction.

[0091] The ratio of the distance between the second pad 102 and the first pad 101 or the fourth pad 104 to the width of the first pad 101 in the first direction is greater than 50% and less than 150%.

[0092] Preferably, the ratio of the distance between the second pad 102 and the first pad 101 or the fourth pad 104 to the width of the first pad 101 in the first direction can be 100%.

[0093] In the above embodiment, in the case that the sample and the external test probe are misaligned, it is expected that the external test probe for contacting the first pad 101 will contact the second pad 102. In the case that the sample and the external test probe are misaligned, the first test signal opposite to the level of the control signal is input to the second pad 102, so that the second pad 102 is at a potential that makes the first TFT switch 201 closed, thereby avoiding abnormal charge flowing into the GOA circuit 800, and further avoiding abnormal charge remaining, gray scale flickering and other defects of the panel.

[0094] Reference Figure 2 , Figure 2 A structure schematic block diagram of another test circuit 700 in an embodiment provided by the present application is shown. As shown in Figure 2 To this end, in an alternative embodiment, the present application further provides a test circuit 700, which further comprises:

[0095] The third pad 103 is configured to input the second test signal to the GOA circuit 800 for testing in the case that the second test signal is obtained and the first TFT switch 201 is turned on.

[0096] The first pad 101 and the third pad 103 are arranged side by side in the first direction, and the third pad 103 is located on the side of the first pad 101 away from the second pad 102.

[0097] Since the external probe is often integrated, if the test probe position is misaligned relative to the sample, the control probe will also be misaligned. If the distance between the second pad 102 and all test pads including the first pad and the fourth pad is greater than a preset distance threshold, even if the test probe position is misaligned relative to the sample, the test probe will not contact the second pad 102, and the second pad 102 will not input the test signal, so the voltage on the second pad 102 is 0V, and the first TFT switch 201 can remain open, and the abnormal charge generated on the test pad by the misaligned contact of the test probe and the test pad will not flow into the GOA circuit 800. To this end, in an alternative embodiment, the present application further provides a test circuit 700, wherein the width of the first pad 101 in the first direction is the same as the width of the second pad 102.

[0098] The ratio of the distance between the first pad 101 and the second pad 102 to the width of the first pad 101 in the first direction is greater than 200% and less than 400%.

[0099] Preferably, the ratio of the distance between the first pad 101 and the second pad 102 to the width of the first pad 101 in the first direction can be 250%.

[0100] Referring to Figure 7 , Figure 7 A structure of another array substrate in an embodiment provided by the present application is shown. As shown in FIG. 7, when the test circuit 700 is arranged in the array substrate, the second pad 102 in the test circuit 700 on both sides of the display area 900 can be arranged away from the test pads on the side, i.e., the first pad 101, the third pad 103 and the fourth pad 104. Figure 7

[0101] Through the above embodiments, the first pad 101 is arranged at the edge of all the test pads, and the second pad 102 is arranged at a position far away from all the test pads. In this way, the design space of the GOA circuit 800 is not wasted, and when the position of the test probe is offset relative to the sample, the control signal cannot be input to the second pad 102, the first TFT switch 201 is turned off, and abnormal charges cannot flow into the GOA circuit 800, thereby ensuring that the electrical function of the GOA circuit 800 is not negatively affected.

[0102] In an alternative embodiment, the present application further provides a test circuit 700, wherein the second pad 102 includes one of the following: a drain power voltage pad, a switch pad (Switch TFT, SW).

[0103] The drain power voltage pad is further configured to, when the control signal is obtained and the first TFT switch 201 is turned on, input the control signal as a third test signal to the GOA circuit 800 for testing.

[0104] Since the drain power voltage pad can input a drain power voltage signal to the GOA circuit using a high-level signal to test the GOA circuit, the drain power voltage signal is a high-level signal. When the control signal is also a high-level signal, the drain power voltage pad can simultaneously serve as a pad for inputting the test signal and the control signal. Through the design of the circuit, no additional control pad needs to be added, which can further reduce the design cost and manufacturing cost of the improvement.

[0105] ​Through the above embodiment, in the test circuit 700 of the related art, a switch pad can be newly arranged side by side with the test pad, configured to control the on-off of the first TFT switch 201, and the circuit of the drain power voltage pad originally used to import the high-level signal can be redesigned to make the drain power voltage pad complete the input of the VDD signal at the same time, realize the GOA test, and also be used to control the on-off of the first TFT switch 201 at the same time.

[0106] Referring to Figure 8 , Figure 8 A structure diagram of another array substrate in an embodiment provided by the present application is shown. As Figure 8 shown, in order to further guarantee the reliability of the test circuit 700, in an alternative embodiment, the present application further provides a test circuit 700, wherein the test circuit 700 further comprises: a semiconductor switch.

[0107] The input end of the semiconductor switch is electrically connected with the output end of the second pad 102, and the output end of the semiconductor switch is electrically connected with the gate of the first TFT switch 201.

[0108] Referring to Figure 13 , Figure 13 A structure connection diagram of a semiconductor switch in an embodiment provided by the present application is shown. As Figure 13 shown, in order to facilitate the manufacturing of the entire array substrate, in an alternative example, the semiconductor switch can adopt a TFT, wherein the gate and the source of the TFT can be short-circuited, that is, the control signal line 301 is connected with the gate of the TFT, so that the signal is unidirectionally conducted.

[0109] Therefore, further, in an alternative embodiment, the semiconductor switch can specifically comprise: a diode or a second TFT switch 401.

[0110] As Figure 13 shown, specifically, the second TFT switch 401 can comprise: a second gate 601, a second source 602, a second drain 603, a second active layer 604, and a second channel 605.

[0111] The output end of the second pad 102 can be electrically connected with the second gate 601, and the second gate 601 is further electrically connected with the second source 602, thereby realizing the short-circuiting between the gate and the source, and further realizing the similar function of the diode, including: unidirectional conduction and voltage limiting.

[0112] The first drain can be electrically connected with the second gate 601.

[0113] Through the above embodiment, the semiconductor switch adopts the TFT, and since the TFT can be manufactured synchronously with other TFTs on the substrate, the manufacturing of the array substrate in the embodiment of the present application can be further facilitated, the manufacturing process is reduced, and the manufacturing efficiency is improved.

[0114] Referring to Figure 9 , Figure 9 A structure diagram of another array substrate in an embodiment provided by the present application is shown. As shown in Figure 8 or Figure 9 , the TFT can include an M1 TFT and an M2 TFT, wherein the structure connection and the stacked switching mode of the TFT can be consistent with the first TFT switch 201, and the structures of the cross sections "C-C'" and "D-D'" can refer to the cross sections "A-A'" and "B-B'". The M1 TFT can be applied in the case where the second pad 102 only serves as a control pad, that is, the input end is electrically connected with the output end of the second pad 102, and the output end is electrically connected with the gate line. The M2 TFT can be applied in the case where the second pad 102 simultaneously serves as a control pad and a test pad, such as a VDD pad, that is, the input end is electrically connected with the output end of the second pad 102, the output end is electrically connected with the gate line, and the output end of the second pad 102 is also electrically connected with the source electrode of the first TFT switch 201.

[0115] Through the above embodiment, the unidirectional conductivity and voltage limiting function of the semiconductor switch are utilized to further avoid the conduction of the first TFT switch 201 in the case where the control signal is not input to the second pad 102, and double protection of the circuit is realized.

[0116] Referring to Figure 4 , Figure 4 A structure diagram of an array substrate in an embodiment provided by the present application is shown. As shown in Figure 4 , based on the same inventive concept, the embodiment of the present application further provides an array substrate, which includes:

[0117] A display area 900.

[0118] A circuit area located at least one side of the display area 900.

[0119] The circuit area includes a GOA circuit 800 and a test circuit 700.

[0120] Specifically, the GOA circuit 800 can extend along a second direction, and the test circuit 700 can be arranged at one end of the GOA circuit 800, specifically, one end located at a side of a data pad (DP), that is, the test pad can be designed on the same side as the remaining data pads.

[0121] Exemplarily, in the case that the GOA circuit 800 is located at opposite sides of the display area 900 along the first direction, the test circuit 700 can be located at one side of the intersection of the side edge of the display area 900 along the first direction and the side edge along the second direction.

[0122] The two sides of the edge of the display area 900 along the first direction can be provided with gate lines extending along the first direction, and the second pad 102 can be electrically connected with the gate lines, and the first TFT switch 201 can be controlled by the gate lines and the test signal line 302 extending along the second direction.

[0123] Through the above embodiments, the test circuit 700 in the array substrate is provided in the above embodiments, the test circuit 700 controls the first TFT switch 201 through the second pad 102, and determines whether the first test signal is introduced into the GOA circuit 800 for testing. Whether the test of the GOA circuit 800 is performed can be determined by whether the second pad 102 is connected with the control signal. On the basis of the GOA circuit 800 test by receiving the probe signal through the pad, double control is realized. Moreover, the first pad 101 and the second pad 102 are arranged adjacent to each other in the test circuit 700, and the logic levels of the signals introduced by the two pads are opposite, so that the error conduction caused by the offset of the external test probe when the test probe is misaligned can be avoided. Moreover, the first TFT switch 201 can be controlled to be turned off when the second pad 102 is not given the control signal, so that the residual charge on the first pad 101 does not flow into the GOA circuit 800. The test circuit 700 in the above embodiments can reduce the negative influence of the test circuit 700 on the electrical function of the GOA circuit 800 from multiple aspects, the electrical function of the GOA circuit 800 of the array substrate in the embodiments of the present application is further guaranteed, and the array substrate can avoid the residual of abnormal charge filled in the pixels due to the CT test, reduce the flicker of the display picture, improve the production yield of the array substrate and the display effect of the display product applied.

[0124] Reference Figure 14 , Figure 14 A structure connection diagram of a display data pad in one embodiment of the present application is shown. As shown in FIG. 6, the display data pad 100 is connected with the GOA circuit 800 through the first TFT switch 201 and the second TFT switch 202. Figure 14As shown, in the embodiment of the present application, the array substrate can further include display data pads 108 arranged in parallel with the test pads, wherein, different from the embodiment above in which the test pads are configured to control the GOA circuit and the GOA circuit is used to implement the CT point light test, the display data pads 108 can be electrically connected to the circuit input end of the display area through the circuit extending along the Gate Pad (GP) side or the Gate Pad Opposition (GPO) side of the array substrate, and control the on-off of the third TFT switch 801 through the data pad opposition of the display area, control whether to write the display area test signal obtained by the display data pad 108, and complete various display area tests including pixel tests.

[0125] The third TFT switch 801 is arranged on the GPO side of the display area, opposite to the position of the first TFT switch 201 arranged on the GP side of the display area, which can facilitate the wiring of the array substrate and make the space application of the array substrate more efficient.

[0126] In order to narrow the frame of the display product to which the array substrate is applied, the GOA circuit 800 is often designed in a symmetrical form on both sides of the array substrate. Therefore, in an alternative embodiment, the present application further provides an array substrate, wherein the circuit area is located on opposite sides of the display area 900 arranged in parallel along the first direction.

[0127] The second pad 102 is located on at least one of the opposite sides arranged in parallel along the first direction.

[0128] In the embodiment of the present application, the opposite sides arranged in parallel along the first direction can include the Gate Pad (GP) side and the Gate Pad Opposition (GPO) side arranged opposite to the two sides of the display area.

[0129] Correspondingly, the opposite sides arranged in parallel along the second direction can include the Data Pad (DP) side and the Data Pad Opposition (DPO) side arranged opposite to the two sides of the display area.

[0130] Specifically, the test circuit 700 can be arranged at one end of the circuit area on the Gate Pad (GP) side and the Gate Pad Opposition (GPO) side of the display area 900 of the array substrate close to the Data Pad side, and the second pad 102 can be designed to control whether the test circuit 700 on either side tests the GOA circuit. Therefore, in an alternative embodiment, the present application further provides an array substrate, wherein the first TFT switch 201 and the first pad 101102 are located on opposite sides arranged in parallel along the first direction.

[0131] The first pad is configured to test the GOA circuit on the same side of the opposite sides arranged in parallel along the first direction.

[0132] The second pad is configured to turn on the first TFT switch on at least one side of the two opposite sides arranged side by side along the first direction.

[0133] The test circuit 700 can be arranged on the side of the GOA circuit 800 close to the data pad, and the test circuit 700 can test the GOA circuit 800 on the same side of the display area 900 respectively.

[0134] The gate line can be used as the control signal line 301, and the first TFT switch 201 on the two sides of the display area 900 can be turned off, so that the second pad 102 on the two sides controls the on-off of the first TFT switch 201 on the two sides respectively.

[0135] Through the above-mentioned embodiments, the second pad 102 can control whether the first TFT switch 201 on the same side is turned on, and the test circuit 700 on the two sides can independently control whether the side has completed the lighting test without interfering with each other.

[0136] Referring to Figure 5 , Figure 5 A structure diagram of another array substrate in an embodiment provided by the present application is shown. As Figure 5 shown, the first TFT switch 201 on the two sides of the display area 900 can also control the conduction of the control signal, so that the second pad 102 on one side is designed to control the test circuit 700 on any side. For this purpose, in an alternative embodiment, the present application also provides an array substrate, wherein the first TFT switch 201 on the two opposite sides is electrically connected to each other.

[0137] The second pad 102 is also configured to turn on the first TFT switch 201 on the opposite side.

[0138] The gate line can be used as the control signal line 301, and the first TFT switch 201 on the two sides of the display area 900 can be turned on through the gate line to realize the conduction of the control signal, so that the second pad 102 on the two sides controls the on-off of the first TFT switch 201 on any side respectively.

[0139] Through the above-mentioned embodiments, when the test pad on one side is offset from the position of the test probe, the second pad 102 on the side does not import the control signal, and only the import of the test signal on one side is insufficient to turn on the first TFT switch 201. Then the first TFT switch 201 on the two sides of the display area 900 can be turned off, and the charge imported by the test pad cannot be imported into the GOA circuit 800, thereby avoiding the negative impact on the GOA electrical function.

[0140] Referring toFigure 6 , Figure 6 A structure diagram of another array substrate in an embodiment provided by the present application is shown. As shown in Figure 6 , in order to further save the design space of the array substrate, one second pad 102 can be arranged in the test circuit 700 on both sides of the display area 900 to control the on-off of the first TFT switch 201 on both sides. For this purpose, in an alternative embodiment, the present application further provides an array substrate, wherein the first TFT switch 201 and the first pad 101 are located on opposite sides; the second pad 102 is located on one side of the opposite sides. The first TFT switches 201 on the opposite sides are electrically connected to each other.

[0141] The first pad 101 is configured to test the GOA circuit 800 on the same side.

[0142] The second pad 102 is configured to turn on the first TFT switch 201 on the opposite side.

[0143] The gate line can be used as the control signal line 301, and the first TFT switch 201 on both sides of the display area 900 can be turned on through the gate line to realize the on-off control of the control signal, so that the second pad 102 on both sides controls the on-off of the first TFT switch 201 on any side, respectively.

[0144] As shown in Figure 5 or Figure 6 , the present application considers improving the current signal line to further reduce the design and manufacturing costs. For this purpose, in an alternative embodiment, the present application further provides an array substrate, further comprising: a gate line extending in a first direction and a data line arranged in the first direction and extending in a second direction. The first direction intersects the second direction.

[0145] The first pad is configured to introduce the first test signal into the GOA circuit through the data line for testing.

[0146] The second pad is configured to control the on-off of the TFT switch first TFT switch through the gate line. The source and drain of the first TFT switch are electrically connected to the first pad 101 and the GOA circuit 800 through the data line, respectively.

[0147] Further, in some alternative embodiments, the circuit area extends in the second direction, and the test circuit is arranged at one end of the circuit area.

[0148] The first TFT switch is arranged in parallel in the first direction at the position where the test circuit and the GOA circuit intersect.

[0149] Through the above embodiment, the GOA circuit in the circuit area can extend along the GP side and the GPO side of the array substrate, and the test circuit is arranged at one end of the data pad side of the GOA circuit, and can be arranged on the same side with the remaining data pads in the array substrate, so as to reduce the design cost and manufacturing cost of the improved design. The first TFT switch is arranged at the position where the test circuit intersects with the GOA circuit, so as to further save the structural design space of the array substrate.

[0150] With reference to Figure 10 , Figure 10 A structure connection diagram of a first TFT switch 201 in an embodiment provided by the present application is shown. As shown in the figure, Figure 10 in an alternative embodiment, the shape of the first TFT switch 201 can be any one of a linear type, a U type or an L type.

[0151] Specifically, the first TFT switch 201 can include a first gate 501, a first source 502, a first drain 503, a first active layer 504 and a first channel 505.

[0152] The first gate 501 can be electrically connected with the second pad 102, and controls the on-off between the first source 502 and the first drain 503 forming a TFT channel through the first active layer 504, so as to control the on-off of the signal transmission on the test signal line.

[0153] With reference to Figure 11 , Figure 11 A cross-sectional structure diagram of a first TFT switch 201 in an embodiment provided by the present application is shown. As shown in the figure, Figure 11 in which the linear TFT structure is a commonly used TFT structure of an oxide GOA product, and the control signal line 301 can be disconnected in the middle of the gate of the first TFT switch 201, so as to control the on-off of the source and drain of the first TFT switch 201.

[0154] With reference to Figure 12 , Figure 12 A cross-sectional structure diagram of a TFT switching in an embodiment provided by the present application is shown. As shown in the figure, Figure 12 in an alternative embodiment, the array substrate can further include a gate insulating layer mask (GIMASK), and a via is arranged in the gate insulating layer mask. In the embodiment of the present application, the switching of the control signal line 301 and the source and drain of the first TFT switch 201 can be completed by using the via in the gate insulating layer mask.

[0155] In yet another alternative embodiment, the array substrate can further include an Indium Tin Oxide (ITO) layer. The switching of the source-drain lines of the first TFT switch 201 and the control signal line 301 can also be accomplished by the ITO layer in the embodiments of the present application.

[0156] For GOA products, the test pads for the light-on test can include the drain power voltage pad (Voltage Drain Drain, VDD) related to the gate signal, the first gate voltage low pad (Voltage Gate Low, VGL), the second gate voltage low pad (lowest Voltage Gate Low, LVGL), the clock frequency pad (Clock, CLK), and other pads related to the GATE signal. The pins of the CT light-on equipment are in contact with the test pads to achieve electrical connection, load test signals to the panel, achieve panel light-on display of different pictures, and check whether the panel has various types of defects.

[0157] To this end, in some alternative embodiments, the first test signal is a low-level gate voltage signal, and the control signal is a high-level signal.

[0158] Further, in an alternative example, in the array substrate provided with the test circuit 700, the first test signal can be a VGL signal or an LVGL signal related to the gate signal. Accordingly, the first pad 101 can be a first pad 101 VGL pad or an LVGL pad. The VGL signal or the LVGL signal can be a low-level signal.

[0159] In an alternative example, in the array substrate provided with the test circuit 700, the fourth test signal can include a voltage drain-drain (VDD) VDD signal or a CLK signal related to the gate signal. Accordingly, the fourth pad 104 can include a VDD pad or a CLK pad.

[0160] The first pad 101, the third pad 103, and the fourth pad 104 are arranged side by side along the first direction, and the first pad 101 and the fourth pad 104 are respectively located on the adjacent two sides of the second pad 102.

[0161] The first pad 101 and the fourth pad 104 can be one of a VGL pad or an LVGL pad, respectively.

[0162] Specifically, the third pad 103 can be multiple, and can be respectively arranged on any side of the first pad 101 or the fourth pad 104 away from the second pad 102, and can be arranged on the same side or different sides away from the second pad 102, and no limitation is made to this.

[0163] Through the above embodiments, the present application can only improve the pad design, circuit design and TFT design of the side edge of the display area 900 of the array substrate, the related art process, mask and material can be used, the electrical test of the array substrate can be efficiently and reliably realized, the electrical function of the GOA circuit 800 is ensured, and then the electrical function of the array substrate is ensured, and the charge residue, picture flicker and other defects of the display product applied by the array substrate are reduced or avoided.

[0164] Based on the same inventive concept, the embodiments of the present application also provide a display device comprising the array substrate in the above embodiments.

[0165] Specifically, considering that the array substrate in the above embodiments can be used to improve the display effect of various display products, the display device can include a display panel, and can also include a display screen of a smart watch, a mobile phone, a tablet computer, a VR device or a computer display and the like.

[0166] The display device can include a frame structure, and the frame structure can encapsulate the array substrate and other components such as a color film by a frame seal. The first TFT switch can be arranged on the DP side edge of the display area, connected with the starting end of the GOA circuit, and the first TFT switch is located below the frame seal.

[0167] Based on the same inventive concept, the embodiments of the present application also provide a display device, which comprises the display device in the above embodiments.

[0168] Specifically, considering that the array substrate in the above embodiments can be used to improve the display effect of various display products, the display device can include a smart watch, a mobile phone, a tablet computer, a VR device, a computer and the like.

[0169] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0170] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0171] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0172] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0173] In this application, the terms "comprise", "contain", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or terminal device. Without more limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0174] Finally, it should be noted that specific examples are used in the description of the principles and implementation of the application. The above description of the examples is only intended to help understand the technical solutions of the application and its core ideas. Although the preferred embodiments of the examples of the application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the examples of the application.

Claims

1. A test circuit, characterized by, The test circuit comprises: a first TFT switch and a first pad and a second pad arranged adjacent to each other in a first direction; the first pad is configured to, in a case where a first test signal is obtained and the first TFT switch is turned on, introduce the first test signal into a GOA circuit to test the GOA circuit; the second pad is configured to, in a case where a control signal is obtained, turn on the first TFT switch by using the control signal, and in a case where no control signal is obtained, turn off the first TFT switch; wherein the control signal is opposite in logic level to the first test signal; the first pad and the second pad have the same width in the first direction, so that, in a case where a sample and an external test stylus position in contact with the first pad are offset, the first test signal opposite in logic level to the control signal is fed into the second pad, so that the second pad is at a potential that turns off the first TFT switch, thereby avoiding abnormal charge from flowing into the GOA circuit.

2. The test circuit of claim 1, wherein, Further comprising: a third pad configured to, in a case where a second test signal is obtained and the first TFT switch is turned on, introduce the second test signal into the GOA circuit to test the GOA circuit; a fourth pad configured to, in a case where the first test signal is obtained and the first TFT switch is turned on, introduce the first test signal into the GOA circuit to test the GOA circuit; the first pad, the third pad and the fourth pad are arranged side by side in the first direction, and the first pad and the fourth pad are respectively located on two adjacent sides of the second pad.

3. The test circuit of claim 1, wherein, Further comprising: a third pad configured to, in a case where a second test signal is obtained and the first TFT switch is turned on, introduce the second test signal into the GOA circuit to test the GOA circuit; the first pad and the third pad are arranged side by side in the first direction, and the third pad is located on a side of the first pad away from the second pad.

4. The test circuit of claim 1, wherein, The second pad comprises one of: a drain power voltage pad, a switch pad; wherein the drain power voltage pad is further configured to, in a case where the control signal is obtained and the first TFT switch is turned on, introduce the control signal as a third test signal into the GOA circuit to test the GOA circuit.

5. The test circuit according to any one of claims 1 to 4, characterized in that, The test circuit further comprises a semiconductor switch; an input end of the semiconductor switch is electrically connected to an output end of the second pad, and an output end of the semiconductor switch is electrically connected to a gate of the first TFT switch.

6. The test circuit of claim 5, wherein, The semiconductor switch comprises a diode or a second TFT switch; wherein a gate of the second TFT switch is electrically connected to the output end of the second pad, a source of the second TFT switch is electrically connected to the gate of the second TFT switch, and a drain of the second TFT switch is electrically connected to the gate of the first TFT switch.

7. An array substrate, characterized by, The display device comprises: a display area; a circuit area located on at least one side of the display area; the circuit area comprises a GOA circuit and the test circuit according to any one of claims 1 to 6.

8. The array substrate of claim 7, wherein, The circuit area is located on opposite sides of the display area arranged side by side in the first direction; The second pad is located on at least one side of the opposite sides arranged side by side along the first direction.

9. The array substrate of claim 8, wherein, The first TFT switch and the first pad are located on opposite sides arranged side by side along the first direction. The first pad is configured to test the GOA circuit on the same side of the opposite sides arranged side by side along the first direction. The second pad is configured to turn on the first TFT switch on at least one side of the opposite sides arranged side by side along the first direction.

10. The array substrate of claim 9, wherein, Further comprising: a gate line extending along a first direction and a data line arranged along the first direction and extending along a second direction; the first direction intersects the second direction; The first pad is configured to introduce a first test signal into the GOA circuit for testing through the data line; The second pad is configured to control the on-off of the first TFT switch through the gate line; The source and drain of the first TFT switch are respectively electrically connected to the data line, the first pad and the GOA circuit through the data line.

11. The array substrate of claim 10, wherein, The circuit area extends along the second direction, and the test circuit is arranged at one end of the circuit area; The first TFT switch is arranged at a position where the test circuit intersects the GOA circuit along the first direction.

12. The array substrate of claim 7, wherein, The first test signal is a low-level gate voltage signal, and the control signal is a high-level signal.

13. A display device comprising: Comprise: The array substrate according to any one of claims 7 to 12.

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