Shift register, gate driving circuit and display device

Abstract

The embodiment of the present disclosure provides a shift register, which comprises a voltage regulating circuit, a light-emitting cascade output circuit, a first light-emitting driving output circuit and a second light-emitting driving output circuit; wherein the voltage regulating circuit is configured to adjust the voltage at the first node and the second node, the light-emitting cascade output circuit is configured to write corresponding signals to the light-emitting cascade signal output end according to the voltage at the first node and the second node, the first light-emitting driving output circuit is configured to write corresponding signals to the light-emitting control driving signal output end according to the voltage at the first node and the second node, and the second light-emitting driving output circuit is configured to write the first working voltage provided by the first power supply end to the light-emitting control driving signal output end in response to the control of the signal provided by the forced output control end, so that the light-emitting control driving signal output end outputs an effective level signal. The embodiment of the present disclosure also provides a gate driving circuit and a display device.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming increasingly widespread. The pixel display device of AMOLED is Organic Light-Emitting Diode (OLED). AMOLED emits light by driving thin-film transistors to generate a driving current in a saturated state, which drives the light-emitting device to emit light. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a shift register, including:

[0004] A voltage regulating circuit is connected to a light-emitting signal input terminal, a first clock signal terminal, a second clock signal terminal, a first node, and a second node, and is configured to adjust the voltage at the first node and the second node in response to the control of signals provided by the light-emitting signal input terminal, the first clock signal terminal, and the second clock signal terminal;

[0005] A light-emitting cascaded output circuit is connected to a first power supply terminal, a second power supply terminal, a light-emitting cascaded signal output terminal, a first node, and a second node. It is configured to write a second operating voltage provided by the second power supply terminal to the light-emitting cascaded signal output terminal in response to the control of the voltage at the first node, and to write a first operating voltage provided by the first power supply terminal to the light-emitting cascaded signal output terminal in response to the control of the voltage at the second node.

[0006] A first light-emitting drive output circuit is connected to a first power supply terminal, a second power supply, a light-emitting control drive signal output terminal, a second node, and a sixth node. It is configured to write a second operating voltage provided by the second power supply terminal to the light-emitting control drive signal output terminal in response to voltage control at the sixth node, and to write a first operating voltage provided by the first power supply terminal to the light-emitting control drive signal output terminal in response to voltage control at the second node; the sixth node is connected to the first node.

[0007] The second light-emitting drive output circuit is connected to the first power supply terminal, the light-emitting control drive signal output terminal, and the forced output control terminal. It is configured to write the first operating voltage provided by the first power supply terminal to the light-emitting control drive signal output terminal in response to the control of the signal provided by the forced output control terminal.

[0008] In some embodiments, the shift register further includes a node control circuit, the node control circuit being located between the sixth node and the first node, the sixth node being connected to the first node through the node control circuit;

[0009] The node control circuit is also connected to the second power supply terminal and the forced output control terminal. The node control circuit is configured to respond to the control of the signal provided by the forced output control terminal, thereby disconnecting the sixth node from the first node and writing the second operating voltage provided by the second power supply terminal to the sixth node.

[0010] In some embodiments, the node control circuit includes a first write sub-circuit, a second write sub-circuit, a twenty-fourth transistor, and a twenty-fifth transistor;

[0011] The first writing sub-circuit is connected to the second power supply terminal, the forced output control terminal, and the control electrode of the 24th transistor, and is configured to write the second operating voltage provided by the second power supply terminal to the control electrode of the 24th transistor in response to the control of the signal provided by the forced output control terminal.

[0012] The second write sub-circuit is connected to the second power supply, the forced output control terminal, and the sixth node, and is configured to write the second operating voltage provided by the second power supply terminal to the sixth node in response to the control of the signal provided by the forced output control terminal.

[0013] The first terminal of the 24th transistor is connected to the first node, and the second terminal of the 24th transistor is connected to the sixth node;

[0014] The control electrode of the 25th transistor is connected to the first power supply terminal or the second clock signal terminal, the first electrode of the 25th transistor is connected to the control electrode of the 25th transistor, and the second electrode of the 25th transistor is connected to the second electrode of the 26th transistor.

[0015] In some embodiments, the first write sub-circuit includes a twenty-sixth transistor, and the second write sub-circuit includes a twenty-seventh transistor;

[0016] The control electrode of the 26th transistor is connected to the forced output control terminal, the first electrode of the 26th transistor is connected to the second power supply terminal, and the second electrode of the 26th transistor is connected to the control electrode of the 24th transistor.

[0017] The control electrode of the 27th transistor is connected to the forced output control terminal, the first electrode of the 27th transistor is connected to the second power supply terminal, and the second electrode of the 27th transistor is connected to the sixth node.

[0018] In some embodiments, the forced output control terminal includes a first control terminal and a second control terminal;

[0019] The first write sub-circuit includes two twenty-sixth transistors connected in series between the second power supply terminal and the control electrode of the twenty-fourth transistor; the second write sub-circuit includes two twenty-seventh transistors connected in series between the second power supply terminal and the sixth node.

[0020] The control electrode of one of the two twenty-sixth transistors is connected to the first control terminal, and the control electrode of the other twenty-sixth transistor is connected to the second control terminal;

[0021] The control electrode of one of the two twenty-seventh transistors is connected to the first control terminal, and the control electrode of the other twenty-seventh transistor is connected to the second control terminal.

[0022] In some embodiments, a twenty-eighth transistor is also included;

[0023] The control electrode of the 28th transistor is connected to the second node, the first electrode of the 28th transistor is connected to the second power supply terminal, and the second electrode of the 28th transistor is connected to the sixth node.

[0024] In some embodiments, the second light-emitting drive output circuit includes a twenty-third transistor;

[0025] The control electrode of the 23rd transistor is connected to the forced output control terminal, the first electrode of the 23rd transistor is connected to the first power supply terminal, and the second electrode of the 23rd transistor is connected to the light emission control drive signal output terminal.

[0026] In some embodiments, the forced output control terminal includes a first control terminal and a second control terminal;

[0027] The second light-emitting drive output circuit includes two twenty-third transistors connected in series between the first power supply terminal and the light-emitting control drive signal output terminal.

[0028] The control electrode of one of the two 23rd transistors is connected to the first control terminal, and the control electrode of the other 23rd transistor is connected to the second control terminal.

[0029] In some embodiments, the voltage regulating circuit includes:

[0030] A first input circuit is connected to a light-emitting signal input terminal, a first clock signal terminal, and a second node, and is configured to write the signal provided by the light-emitting signal input terminal to the second node in response to the control of the signal provided by the first clock signal terminal.

[0031] The second input circuit is connected to the first clock signal terminal, the first power supply terminal, and the second node, and is configured to write the first operating voltage provided by the first power supply terminal to the third node in response to the control of the signal provided by the first clock signal terminal, and to write the signal provided by the first clock signal terminal to the third node in response to the control of the voltage at the second node.

[0032] A first voltage control circuit is connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node. It is configured to write the signal provided by the second clock signal terminal to the first node in response to the control of the voltage at the third node and the signal provided by the second clock signal terminal, and to write the second operating voltage provided by the second power supply terminal to the first node in response to the control of the voltage at the second node.

[0033] The second voltage control circuit is connected to the second clock signal terminal, the second power supply terminal, and the third node, and is configured to write the second operating voltage provided by the second power supply terminal to the second node in response to the voltage at the third node and the signal provided by the second clock signal terminal.

[0034] In some embodiments, the first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor, the second voltage control circuit includes a seventh transistor and an eighth transistor, the light-emitting cascaded output circuit includes a ninth transistor and a tenth transistor, and the first light-emitting drive output circuit includes a twenty-first transistor and a twenty-second transistor.

[0035] The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the light emission signal input terminal, and the second electrode of the first transistor is connected to the second node.

[0036] The control electrode of the second transistor is connected to the first clock signal terminal, the first electrode of the second transistor is connected to the second power supply terminal, and the second electrode of the second transistor is connected to the third node;

[0037] The control electrode of the third transistor is electrically connected to the second node, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the first clock signal terminal.

[0038] The control electrode of the fourth transistor is connected to the third node, the first electrode of the fourth transistor is connected to the second clock signal terminal, and the second electrode of the fourth transistor is connected to the fourth node.

[0039] The control electrode of the fifth transistor is connected to the second clock signal terminal, the first electrode of the fifth transistor is connected to the fourth node, and the second electrode of the fifth transistor is connected to the first node.

[0040] The control electrode of the sixth transistor is connected to the second node, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the second power supply terminal.

[0041] The first terminal of the third capacitor is connected to the third node, and the second terminal of the third capacitor is connected to the fourth node;

[0042] The control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the second power supply terminal, and the second electrode of the seventh transistor is connected to the first terminal of the eighth transistor.

[0043] The control electrode of the eighth transistor is connected to the second clock signal terminal, and the second electrode of the eighth transistor is connected to the second node;

[0044] The control electrode of the ninth transistor is connected to the first node, the first electrode of the ninth transistor is connected to the second power supply terminal, and the second electrode of the ninth transistor is connected to the output terminal of the light-emitting cascade signal.

[0045] The control electrode of the tenth transistor is connected to the second node, the first electrode of the tenth transistor is connected to the output terminal of the light-emitting cascade signal, and the second electrode of the tenth transistor is connected to the first power supply terminal.

[0046] The control electrode of the 21st transistor is connected to the sixth node, the first electrode of the 21st transistor is connected to the second power supply terminal, and the second electrode of the 21st transistor is connected to the light emission control drive signal output terminal.

[0047] The control electrode of the 22nd transistor is connected to the second node, the first electrode of the 22nd transistor is connected to the output terminal of the light emission control drive signal, and the second electrode of the 22nd transistor is connected to the first power supply terminal.

[0048] In some embodiments, the voltage regulating circuit further includes a first leakage protection circuit, wherein the first input circuit, the second input circuit, and the second node control voltage are connected to the fifth node, the first leakage protection circuit is located between the fifth node and the second node, and the first input circuit, the second input circuit, and the second voltage control circuit are all connected to the second node through the first leakage protection circuit;

[0049] The first leakage protection circuit is also connected to the first power supply terminal and the third power supply terminal. The first leakage protection circuit is configured to write the third working voltage provided by the third power supply terminal to the first leakage protection node under the control of the voltage at the second node. The first leakage protection node is located between the second node and the fifth node.

[0050] And / or, the voltage regulating circuit further includes a second leakage protection circuit, the output circuit is connected to the second power supply terminal through the second leakage protection circuit, and the output circuit and the second leakage protection circuit are connected to the second leakage protection node;

[0051] The second leakage protection circuit is also connected to the first node, the first power supply terminal, and the second power supply terminal. The second leakage protection circuit is also connected to the light-emitting cascade signal output terminal or the light-emitting control drive signal output terminal. The second leakage protection circuit is configured to write the first operating voltage provided by the first power supply terminal to the second leakage protection node in response to the voltage control at the light-emitting cascade signal output terminal or the light-emitting control drive signal output terminal.

[0052] And / or, the voltage regulation circuit further includes: a global light emission reset circuit, which is connected to a global light emission reset signal terminal, a first power supply terminal, and a second node, and is configured to write a first operating voltage provided by the first power supply terminal to the second node in response to the control of a signal provided by the global light emission reset signal terminal.

[0053] In some embodiments, the first leakage protection circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0054] The control electrode of the eleventh transistor is connected to the first power supply terminal, the first electrode of the eleventh transistor is connected to the fifth node, and the second electrode of the eleventh transistor is connected to the first leakage protection node.

[0055] The control electrode of the twelfth transistor is connected to the first power supply terminal, the first electrode of the twelfth transistor is connected to the first leakage protection node, and the second electrode of the twelfth transistor is connected to the second node;

[0056] The control electrode of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the third power supply terminal, and the second electrode of the thirteenth transistor is connected to the first leakage protection node.

[0057] The second leakage protection circuit includes a fourteenth transistor and a fifteenth transistor;

[0058] The control electrode of the fourteenth transistor is connected to the first node, the first electrode of the fourteenth transistor is connected to the second power supply terminal, and the second electrode of the fourteenth transistor is connected to the second leakage protection node.

[0059] The control electrode of the fifteenth transistor is connected to the light-emitting cascade signal output terminal or the light-emitting control drive signal output terminal, the first electrode of the fifteenth transistor is connected to the first power supply terminal, and the second electrode of the fifteenth transistor is connected to the second leakage protection node.

[0060] The light-emitting global reset circuit includes a sixteenth transistor;

[0061] The control electrode of the sixteenth transistor is connected to the global reset signal terminal, the first electrode of the sixteenth transistor is connected to the second node, and the second electrode of the sixteenth transistor is connected to the first power supply terminal.

[0062] In a second aspect, embodiments of this disclosure also provide a gate driving circuit, including: a plurality of cascaded first shift registers, wherein the first shift registers employ the shift registers provided in the first aspect above;

[0063] The signal input terminal of the first shift register located in the first stage is connected to the light emission start signal line, and the first shift registers in other stages besides the first stage are connected to the light emission cascade signal output terminal of the first shift register of their respective preceding stage.

[0064] The output terminal of the light emission control drive signal of each of the first shift registers is connected to the corresponding light emission control signal line.

[0065] Thirdly, this disclosure also provides a display device, including: a display area and a peripheral area located around the display area, the display area including a plurality of pixel units arranged in an array, each row of pixel units being configured with a corresponding light emission control signal line, the light emission control signal line being connected to the control electrode of the light emission control transistor in the corresponding pixel unit;

[0066] The peripheral region includes a first gate driving circuit, which employs the gate driving circuit provided in the second aspect described above.

[0067] In some embodiments, each row of pixel units is further configured with a corresponding second gate line, the second gate line being connected to the control electrode of the sensing transistor in the corresponding pixel unit;

[0068] The peripheral region further includes a second gate driving circuit, which includes a plurality of cascaded second shift registers, each of which is configured with a second gate driving signal output terminal, and the second gate driving signal output terminal is connected to the corresponding second gate line.

[0069] The second shift register includes a first display precharge reset circuit, a sensing cascade circuit, a first sensing precharge reset circuit, a first pull-down control circuit, a gate cascade output circuit, and a second gate drive output circuit;

[0070] The sensing cascade circuit and the first sensing precharge reset circuit are connected to the sensing cascade node. The first display precharge reset circuit, the first sensing precharge reset circuit, the first pull-down control circuit, the gate cascade output circuit and the second gate drive output circuit are connected to the first pull-up node. The first pull-down control circuit, the gate cascade output circuit and the second gate drive output circuit are connected to the first pull-down node.

[0071] The first display precharge reset circuit is connected to the display signal input terminal, the display reset signal terminal and the fifth power supply terminal, and is configured to write the signal provided by the display signal input terminal into the first pull-up node in response to the control of the signal provided by the display signal input terminal, and to write the fifth operating voltage provided by the fifth power supply terminal into the first pull-down node in response to the control of the signal provided by the display reset signal terminal.

[0072] The sensing cascade circuit is connected to the sensing signal input terminal and the random signal terminal, and is configured to write the signal provided by the sensing signal input terminal into the sensing cascade node in response to the control of the signal provided by the random signal terminal.

[0073] The first sensing precharge reset circuit is connected to a third clock signal terminal, a sensing reset signal terminal, and a fifth power supply terminal. It is configured to write the signal provided by the third clock signal terminal to the sensing precharge node in response to the control of the voltage at the sensing cascade node, and to write the voltage at the sensing precharge node to the first pull-up node in response to the control of the signal provided by the third clock signal terminal, and to write the fifth operating voltage provided by the fifth power supply terminal to the first pull-up node in response to the control of the signal provided by the sensing reset signal terminal.

[0074] The first pull-down control circuit is connected to the fourth power supply terminal and the fifth power supply terminal, and is configured to write a voltage that is opposite to the voltage at the first pull-up node to the first pull-down node;

[0075] The gate cascaded output circuit is connected to the cascaded clock signal terminal, the fifth power supply terminal, and the gate cascaded signal output terminal. It is configured to write the signal provided by the cascaded clock signal terminal to the gate cascaded signal output terminal in response to the control of the voltage at the first pull-up node, and to write the fifth operating voltage provided by the fifth power supply terminal to the gate cascaded signal output terminal in response to the control of the voltage at the first pull-down node.

[0076] The second gate drive output circuit is connected to the second drive clock signal terminal and the sixth power supply terminal, and is configured to write the signal provided by the second drive clock signal terminal to the second gate drive signal output terminal in response to the control of the voltage at the first pull-up node, and to write the sixth operating voltage provided by the sixth power supply terminal to the second gate drive signal output terminal in response to the control of the voltage at the first pull-down node.

[0077] In some embodiments, within the first gate driving circuit, any one of the first shift registers connected to the forced output control terminal includes: a second gate driving signal output terminal or a gate cascade signal output terminal configured in the second shift register corresponding to the same row of pixel units as the first shift register;

[0078] Alternatively, within the first gate driving circuit, the first control terminal and the second control terminal connected to any one of the first shift registers are respectively the sensing cascade node inside the second shift register corresponding to the same row of pixel units as the first shift register and the pre-configured fourth clock signal terminal.

[0079] In some embodiments, the second shift register is configured with a fourth gate drive signal output terminal, which is connected to the corresponding second gate line;

[0080] The second shift register further includes a second display precharge reset circuit, a second sensing precharge reset circuit, a second pull-down control circuit, and a fourth gate drive output circuit; the second display precharge reset circuit, the second sensing precharge reset circuit, the second pull-down control circuit, and the fourth gate drive output circuit are connected to the second pull-up node, and the second pull-down control circuit and the fourth gate drive output circuit are connected to the second pull-down node;

[0081] The second display precharge reset circuit is connected to the display signal input terminal, the display reset signal terminal and the fifth power supply terminal, and is configured to write the signal provided by the display signal input terminal into the second pull-up node in response to the control of the signal provided by the display signal input terminal, and to write the fifth operating voltage provided by the fifth power supply terminal into the second pull-down node in response to the control of the signal provided by the display reset signal terminal.

[0082] The second sensing precharge reset circuit is connected to the sensing precharge signal terminal, the third clock signal terminal, the sensing reset signal terminal and the fifth power supply terminal, and is configured to write the voltage at the sensing precharge node to the second pull-up node in response to the control of the signal provided by the third clock signal terminal, and to write the fifth operating voltage provided by the fifth power supply terminal to the second pull-up node in response to the control of the signal provided by the sensing reset signal terminal.

[0083] The second pull-down control circuit is connected to the seventh power supply terminal and the fifth power supply terminal, and is configured to write a voltage that is opposite to the voltage at the second pull-up node to the second pull-down node;

[0084] The fourth gate drive output circuit is connected to the fourth drive clock signal terminal and the sixth power supply terminal, and is configured to write the signal provided by the fourth drive clock signal terminal to the fourth gate drive signal output terminal in response to the control of the voltage at the second pull-up node, and to write the sixth operating voltage provided by the sixth power supply terminal to the fourth gate drive signal output terminal in response to the control of the voltage at the second pull-down node.

[0085] In some embodiments, the second shift register further includes: a blank valid output circuit;

[0086] The blank valid output circuit is connected to the first pull-up node, the first pull-down node, the blank valid clock signal terminal, the blank valid signal output terminal, and the sixth power supply terminal. It is configured to write the signal provided by the blank valid clock signal terminal to the blank valid signal output terminal in response to the control of the voltage at the first pull-up node, and to write the sixth operating voltage provided by the sixth power supply terminal to the blank valid signal output terminal in response to the control of the voltage at the first pull-down node.

[0087] Alternatively, the blank valid output circuit is connected to the second pull-up node, the second pull-down node, the blank valid clock signal terminal, the blank valid signal output terminal, and the sixth power supply terminal, and is configured to write the signal provided by the blank valid clock signal terminal to the blank valid signal output terminal in response to the control of the voltage at the second pull-up node, and to write the sixth operating voltage provided by the sixth power supply terminal to the blank valid signal output terminal in response to the control of the voltage at the second pull-down node.

[0088] Within the first gate driving circuit, any one of the first shift registers connected to the forced output control terminal includes: a blank valid signal output terminal configured in the second shift register corresponding to the same row of pixel units as the first shift register.

[0089] In some embodiments, each row of pixel units is further configured with a corresponding first gate line, the first gate line being connected to the control electrode of the data write transistor in the corresponding pixel unit;

[0090] The second shift register also includes a first gate drive output circuit and a third gate drive output circuit;

[0091] The first gate drive output circuit is connected to the first pull-up node, the first pull-down node, the first gate drive signal output terminal, the first drive clock signal terminal, and the sixth power supply terminal. It is configured to write the signal provided by the first drive clock signal terminal to the first gate drive signal output terminal in response to the control of the voltage at the first pull-up node, and to write the sixth operating voltage provided by the sixth power supply terminal to the first gate drive signal output terminal in response to the control of the voltage at the first pull-down node.

[0092] The third gate drive output circuit is connected to the second pull-up node, the second pull-down node, the third gate drive signal output terminal, the third drive clock signal terminal, and the sixth power supply terminal. It is configured to write the signal provided by the third drive clock signal terminal to the third gate drive signal output terminal in response to the control of the voltage at the second pull-up node, and to write the sixth operating voltage provided by the sixth power supply terminal to the third gate drive signal output terminal in response to the control of the voltage at the second pull-down node.

[0093] The first gate drive signal output terminal and the third gate drive signal output terminal are respectively connected to the corresponding first gate line. Attached Figure Description

[0094] Figure 1 This is a schematic diagram of a circuit structure for a pixel unit within a display substrate, as described in the relevant technology.

[0095] Figure 2 for Figure 1 A timing diagram of one type of pixel unit shown;

[0096] Figure 3 This is a schematic diagram of another circuit structure for a pixel unit within a display substrate, as described in the related technology.

[0097] Figure 4A for Figure 3 A timing diagram of one type of pixel unit shown;

[0098] Figure 4B for Figure 3 The shown pixel unit performs external compensation sensing during the blank period, which is a working timing diagram;

[0099] Figure 5 A schematic diagram of a circuit structure of a first shift register provided in an embodiment of this disclosure;

[0100] Figure 6 This is a driving timing diagram for a light-emitting control gate driving circuit involved in related technologies;

[0101] Figure 7 This is a driving timing diagram of the light-emitting control gate driving circuit involved in this disclosure;

[0102] Figure 8 This is a schematic diagram of another circuit structure of the first shift register in an embodiment of this disclosure;

[0103] Figure 9 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0104] Figure 10 for Figure 9 The diagram shows one possible timing diagram of the first shift register.

[0105] Figure 11 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0106] Figure 12 for Figure 11 The diagram shows one possible timing diagram of the first shift register.

[0107] Figure 13 for Figure 11 Another timing diagram of the first shift register is shown;

[0108] Figure 14 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0109] Figure 15 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0110] Figure 16 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0111] Figure 17 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0112] Figure 18 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0113] Figure 19 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure;

[0114] Figure 20This is a schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of the present disclosure;

[0115] Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0116] Figure 22 This is a schematic diagram of a circuit structure of the second shift register in an embodiment of this disclosure;

[0117] Figure 23 This is a schematic diagram of another circuit structure of the second shift register in an embodiment of this disclosure;

[0118] Figure 24 for Figure 23 The figure shows one timing diagram of the second shift register.

[0119] Figure 25A This is a timing diagram of the cascaded clock signal terminal, the second drive clock signal terminal, the gate cascaded signal output terminal, and the second gate drive signal output terminal in an embodiment of this disclosure.

[0120] Figure 25B This is another timing diagram of the cascaded clock signal terminal, the second drive clock signal terminal, the gate cascaded signal output terminal, and the second gate drive signal output terminal in an embodiment of this disclosure;

[0121] Figure 25C This is a timing diagram of the sensing cascade node, the fourth clock signal terminal, and the second gate drive signal output terminal in an embodiment of this disclosure;

[0122] Figure 26 A schematic diagram of yet another circuit structure of the second shift register provided in an embodiment of this disclosure;

[0123] Figure 27 This is a timing diagram of the first driving clock signal terminal, the second driving clock signal terminal, the first gate driving signal output terminal, and the second gate driving signal output terminal in an embodiment of this disclosure.

[0124] Figure 28 A schematic diagram of another circuit structure of the second shift register provided in the embodiments of this disclosure;

[0125] Figure 29 A schematic diagram of another circuit structure of the second shift register provided in the embodiments of this disclosure;

[0126] Figure 30 This is a schematic diagram of a circuit structure in an embodiment of the present disclosure where two pixel units located in adjacent rows share the same light-emitting control transistor. Detailed Implementation

[0127] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register, gate driving circuit and display device provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0128] The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "coupled" or "connected" are not limited to physical or mechanical coupling, but can include electrical connections, whether direct or indirect.

[0129] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchanged; therefore, the drain and source of each transistor in this disclosure embodiment are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example.

[0130] In this disclosure, "effective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to conduct, and "ineffective level signal" refers to a signal that, when input to the gate electrode of a transistor, can control the transistor to cut off. For N-type transistors, a high-level signal is an effective level signal, and a low-level signal is an ineffective level signal; for P-type transistors, a low-level signal is an effective level signal, and a high-level signal is an ineffective level signal.

[0131] In the following description, an N-type transistor will be used as an example. In this case, the active level signal refers to a high-level signal, and the inactive level signal refers to a low-level signal. It is conceivable that when using a P-type transistor, the timing of the control signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of this disclosure.

[0132] Figure 1 This is a schematic diagram of a circuit structure for a pixel unit within a display substrate, as described in the relevant technology. Figure 2 for Figure 1 A timing diagram of the pixel unit shown, such as Figure 1 and Figure 2As shown, the pixel circuit has a 3T1C structure, which includes three transistors (data write transistor QTFT, driving transistor DTFT, and sensing transistor STFT) and one capacitor (storage capacitor Cst). The control electrode of the data write transistor QTFT is connected to the first gate line G1, and the first electrode of the data write transistor QTFT is connected to the data line DATA. The control electrode of the sensing transistor STFT is connected to the second gate line G2, and the first electrode of the sensing transistor STFT is connected to the sensing line SENCE.

[0133] For a single pixel unit, it needs to go through a data writing stage and a light emission stage in one frame. During the data writing stage, the first gate line G1 controls the data writing transistor QTFT to turn on, and the data line Data writes the data voltage Vdata to the control electrode of the driving transistor DTFT. During the light emission stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at its control electrode to drive the light-emitting element OLED to emit light.

[0134] In addition, a blank period (also known as a blank period) is usually configured between two adjacent frames. At this time, a frame includes a display-driven period and a blank period. The blank period can generally be used to randomly perform external compensation sensing on a certain pixel unit row.

[0135] exist Figure 1 In the pixel unit shown, the display brightness of the OLED element in one frame can only be controlled by the data voltage Vdata. However, the data voltage Vdata is output by the IC. If the IC's precision is insufficient, it will cause the problem of low grayscale not being unfolded. For example, if the IC precision is 0.1V, and the grayscale corresponding to 0.1V data voltage is L20, then the IC cannot accurately output the grayscales corresponding to L1 to L19.

[0136] To address the aforementioned technical issues, related technologies have improved the circuit structure of pixel units. Figure 3 This is a schematic diagram of another circuit structure for a pixel unit within a display substrate, as described in the related technology. Figure 4A for Figure 3 The image shows a timing diagram of one type of pixel unit. Figure 4B for Figure 3 The diagram shows a working timing diagram of the pixel unit performing external compensation sensing during the blank period, as follows: Figures 3 to 4B As shown, the new pixel unit provided by the related technology is a 4T1C structure, which not only includes Figure 1 The data writing transistor (QTFT), driving transistor (DTFT), sensing transistor (STFT), and light-emitting control transistor (ETFT) are included. See, as an example, [link to example]. Figure 3As shown, the light-emitting control transistor ETFT is disposed between the driving transistor DTFT and the power supply terminal ELVDD, and the control electrode of the light-emitting control transistor ETFT is connected to the light-emitting control signal line. As another example, the light-emitting control transistor can be disposed between the driving transistor DTFT and the light-emitting device OLED (no corresponding figure is given).

[0137] See Figure 4A As shown, for a single pixel unit, during the light-emitting phase, the light-emitting control signal line controls the conduction or cutoff of the light-emitting control transistor ETFT, thereby controlling the illumination time of the OLED element during the light-emitting phase, and consequently controlling the equivalent brightness of the OLED element in one frame (i.e., the brightness perceived by the human eye, also known as sensory brightness). Specifically, the light-emitting phase includes a lighting phase and a black-insertion phase. The light-emitting control signal includes a light-emitting drive signal and a black-insertion drive signal. During the lighting phase, the light-emitting control signal line provides a light-emitting drive signal (i.e., an effective level signal) to control the conduction of the light-emitting control transistor ETFT. At this time, the drive transistor can output drive current normally, and the OLED element emits light. During the black-insertion phase, the light-emitting control signal line provides a black-insertion drive signal (i.e., an ineffective level signal) to control the cutoff of the light-emitting control transistor ETFT. At this time, the drive transistor DTFT has no drive current output, and the OLED element does not emit light. Generally, the longer the total duration of the black-insertion phase, the lower the equivalent brightness of the OLED element.

[0138] Figure 4A The example shown illustrates a scenario where the light-emitting stage includes two black insertion stages. Of course, in practical applications, the light-emitting stage can also include one, three, or more black insertion stages.

[0139] As seen above, by setting the ETFT (Emitting Power Transistor), the light-emitting element can display the brightness corresponding to lower grayscale levels, thus effectively solving the problem that insufficient IC precision prevents pixel units from displaying low grayscale brightness. However, in practical applications, it has been found that because all the shift registers inside the existing gate drive circuit (generally called the light-emitting control gate drive circuit) used to provide the black insertion drive signal are cascaded sequentially, the existing gate drive circuit used to provide the black insertion drive signal will continuously and sequentially output the black insertion drive signal to each light-emitting control signal line. Inevitably, the light-emitting control signal line corresponding to some row pixel units will receive the black insertion drive signal during a blank period. And through... Figure 4BAs shown in the timing diagram, when performing external compensation sensing on a row of pixel units, the signal provided by the light emission control signal line connected to that row of pixel units must always be a light emission driving signal (i.e., an effective level signal). Therefore, external compensation sensing cannot be performed on pixel unit rows that receive a black insertion driving signal during blank periods. In other words, the related technology cannot support random external compensation sensing during blank periods.

[0140] To effectively address the problem that related technologies cannot support random external compensation sensing during blank periods, this disclosure provides a shift register. The inventive principle of this disclosure will be described in detail below with reference to specific embodiments. It should be noted that, to distinguish it from shift registers in other gate driving circuits on a display device, the shift register located in the light-emitting control gate driving circuit is referred to as the first shift register in this disclosure. This first shift register can be used to provide light-emitting control signals (including light-emitting drive signals and black-insertion drive signals) to the corresponding light-emitting control signal lines.

[0141] Figure 5 A schematic diagram of a circuit structure of a first shift register provided in an embodiment of this disclosure is shown below. Figure 5 As shown, the first shift register includes: a voltage regulation circuit 20, a light-emitting cascaded output circuit 25, a first light-emitting drive output circuit 29, and a second light-emitting drive output circuit 30.

[0142] The voltage regulating circuit 20 is connected to the light-emitting signal input terminal INPUT, the first clock signal terminal CKA, the second clock signal terminal CKB, the first node N1, and the second node N2. The voltage regulating circuit 20 is configured to adjust the voltage at the first node N1 and the second node N2 in response to the control of the signals provided by the light-emitting signal input terminal INPUT, the first clock signal terminal CKA, and the second clock signal terminal CKB.

[0143] The cascaded output circuit 25 is connected to a first power supply terminal, a second power supply terminal, a cascaded output signal terminal CR, a first node N1, and a second node N2. The cascaded output circuit 25 is configured to write a second operating voltage provided by the second power supply terminal to the cascaded output signal terminal CR in response to the control of the voltage at the first node N1, and to write a first operating voltage provided by the first power supply terminal to the cascaded output signal terminal CR in response to the control of the voltage at the second node N2.

[0144] The first light-emitting drive output circuit 29 is connected to the first power supply terminal, the second power supply terminal, the light-emitting control drive signal output terminal OUT, the second node N2, and the sixth node N6. The first light-emitting drive output circuit 29 is configured to write the second operating voltage provided by the second power supply terminal to the light-emitting control drive signal output terminal OUT in response to the control of the voltage at the sixth node N6, and to write the first operating voltage provided by the first power supply terminal to the light-emitting control drive signal output terminal OUT in response to the control of the voltage at the second node N2. The sixth node N6 is connected to the first node N1.

[0145] The second light-emitting drive output circuit 30 is connected to the first power supply terminal, the light-emitting control drive signal output terminal OUT, and the forced output control terminal CSD. The second light-emitting drive output circuit 30 is configured to write the first operating voltage provided by the first power supply terminal to the light-emitting control drive signal output terminal OUT in response to the control of the signal provided by the forced output control terminal CSD.

[0146] In this embodiment, the first operating voltage provided by the first power supply terminal is a valid level signal. When the second light-emitting driving circuit is in the working state and writes the first operating voltage to the light-emitting control driving signal output terminal OUT, regardless of what voltage the first light-emitting driving circuit outputs to the light-emitting control driving signal output terminal OUT, the light-emitting control driving signal output terminal OUT always outputs a light-emitting driving signal (i.e., a valid level signal). When the second light-emitting driving circuit is in the non-working state, the signal output by the light-emitting control driving signal output terminal OUT is affected by the first light-emitting driving circuit.

[0147] In this embodiment, the light emission cascade signal output terminal CR and the light emission control drive signal output terminal OUT of the first shift register are respectively configured. The light emission cascade output circuit 25 is used to control the output of the light emission cascade signal output terminal CR, and the first light emission drive output circuit 29 and the second light emission drive output circuit 30 jointly control the output of the light emission control drive signal output terminal OUT. That is, the light emission cascade signal and the light emission control signal output by the first shift register can be controlled separately. Based on this, in this disclosure, while ensuring the normal cascading of the first shift registers in the light emission control gate drive circuit, the light emission control signals output by each first shift register can be independently controlled.

[0148] When a row of pixel units requires external compensation sensing and, if driven by a conventional light-emitting control gate driving circuit, receives a black-insertion drive signal (i.e., an inactive level signal) during a blank period, this disclosure can control the output terminal OUT of the first shift register corresponding to the row of pixel units requiring external compensation sensing to forcibly output a light-emitting drive signal (i.e., an active level signal) through the forced output control terminal CSD connected to the first shift register corresponding to the row of pixel units requiring external compensation sensing. This ensures that the light-emitting control signal received by the row of pixel units requiring external compensation sensing during the blank period is a light-emitting drive signal. In other words, the row of pixel units that would normally receive a black-insertion drive signal and require external compensation sensing during the blank period will actually receive a light-emitting drive signal during the blank period, thus ensuring the smooth progress of the external compensation sensing process for that row of pixel units.

[0149] The technical solution disclosed herein will be described in detail below with reference to a specific example. Figure 6 This is a driving timing diagram for a light-emitting control gate driving circuit involved in related technologies. Figure 7 This is a driving timing diagram of the light-emitting control gate driving circuit involved in this disclosure, such as... Figure 6 and Figure 7 As shown in the figure, EM Let represent the i-th light emission control signal line, i.e., the light emission control signal line configured in the i-th row of pixel units, where i is an integer and 1≤i≤n, and n is the total number of rows of pixel units. The m-th row of pixel units is the row of pixel units that requires external compensation sensing.

[0150] See Figure 6 As shown, assuming that the gate driving circuit provided by the related technology is used to drive the light emission control signal line, the light emission control signal line EM corresponding to the m-th row pixel unit... <m>It will receive the black insertion drive signal during the blank period ( Figure 6 and Figure 7 The example illustrates a case where each row of pixels in a frame is configured with two black insertion stages, and each light emission control signal line theoretically receives two black insertion drive signals. In this case, due to the configuration of the light emission control signal line EM in the m-th row of pixels... <m>During the blank period, a black insertion drive signal will be received. As can be seen from the previous content, the m-th row pixel unit cannot perform external compensation sensing normally.

[0151] See Figure 7 As shown in this embodiment, the CR output terminal and OUT output terminal of the cascaded luminescence signal of each first shift register in the luminescence control gate driving circuit are respectively configured. Under normal cascading of the first shift registers in the luminescence control gate driving circuit, the luminescence control signals output by each first shift register can be independently controlled. Therefore, the second luminescence control driving circuit in the first shift register connected to the m-th row pixel unit can be controlled to operate during the blank period, so that the OUT output terminal of the luminescence control driving signal of the first shift register connected to the m-th row pixel unit always outputs a luminescence driving signal (i.e., an effective level signal) during the blank period, thereby ensuring that the m-th row pixel unit can perform external compensation sensing normally. Furthermore, since the first shift registers in the luminescence control gate driving circuit remain normally cascaded, the first shift register corresponding to the (m+1)-th row pixel unit can normally output a black insertion driving signal during the blank period.

[0152] Figure 8 This is a schematic diagram of another circuit structure of the first shift register in an embodiment of this disclosure, as shown below. Figure 8 As shown, in some embodiments, the voltage regulation circuit 20 in the first shift register includes a first input circuit 21, a second input circuit 22, a first voltage control circuit 23, and a second voltage control circuit 24.

[0153] The first input circuit 21 is connected to the light-emitting signal input terminal INPUT, the first clock signal terminal CKA, and the second node N2. The first input circuit 21 is configured to write the signal provided by the light-emitting signal input terminal INPUT to the second node N2 in response to the control of the signal provided by the first clock signal terminal CKA.

[0154] The second input circuit 22 is connected to the first clock signal terminal CKA, the first power supply terminal, and the second node N2. The second input circuit 22 is configured to write the first operating voltage provided by the first power supply terminal to the third node N3 in response to the control of the signal provided by the first clock signal terminal CKA, and to write the signal provided by the first clock signal terminal CKA to the third node in response to the control of the voltage at the second node N2.

[0155] The first voltage control circuit 23 is connected to the second clock signal terminal CKB, the second power supply terminal, the first node N1, the second node N2, and the third node N3. The first voltage control circuit is configured to write the signal provided by the second clock signal terminal CKB to the first node N1 in response to the control of the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB, and to write the second operating voltage provided by the second power supply terminal to the first node N1 in response to the control of the voltage at the second node N2.

[0156] The second voltage control circuit 24 is connected to the second clock signal terminal CKB, the second power supply terminal, and the third node. The second voltage control circuit 24 is configured to write the second operating voltage provided by the second power supply terminal to the second node N2 in response to the voltage at the third node N3 and the signal provided by the second clock signal terminal CKB.

[0157] Of course, the voltage regulating circuit 20 in this embodiment is not limited to... Figure 8 The situation shown is as follows: Figure 8 The circuit structure of the voltage regulating circuit 20 shown is for illustrative purposes only and does not limit the technical solutions of this disclosure.

[0158] In some embodiments, the first shift register further includes a first leakage protection circuit 26; wherein the first input circuit 21, the second input circuit 22, and the control voltage of the second node N2 are connected to the fifth node N5, the first leakage protection circuit 26 is located between the fifth node N5 and the second node N2, and the first input circuit 21, the second input circuit, and the second voltage control circuit 24 are all connected to the second node N2 through the first leakage protection circuit 26. The first leakage protection circuit 26 is also connected to a first power supply terminal and a third power supply terminal, and the first leakage protection circuit 26 is configured to write the third operating voltage provided by the third power supply terminal to the first leakage protection node OFF1 under the control of the voltage at the second node N2, and the first leakage protection node OFF1 is located between the second node N2 and the fifth node N5.

[0159] In some embodiments, the first shift register further includes a second leakage protection circuit 27; the output circuit is connected to the second power supply terminal through the second leakage protection circuit 27, and the light-emitting cascade output circuit 25 is connected to the second leakage protection circuit 27 at the second leakage protection node OFF2; the second leakage protection circuit 27 is also connected to the first node N1, the first power supply terminal, and the second power supply terminal, and the second leakage protection circuit 27 is also connected to the light-emitting cascade signal output terminal CR or the light-emitting control drive signal output terminal OUT. The second leakage protection circuit 27 is configured to write the first operating voltage provided by the first power supply terminal to the second leakage protection node OFF2 in response to the voltage control at the light-emitting cascade signal output terminal CR or the light-emitting control drive signal output terminal OUT.

[0160] Figure 9 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, such as... Figure 9 As shown, in some embodiments, the first input circuit 21 includes a first transistor T1, the second input circuit 22 includes a second transistor T2 and a third transistor T3, the first voltage control circuit 23 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a third capacitor C3, the second voltage control circuit 24 includes a seventh transistor T7 and an eighth transistor T8, the light-emitting cascaded output circuit 25 includes a ninth transistor T9 and a tenth transistor T10, and the first light-emitting drive output circuit 29 includes a twenty-first transistor T21 and a twenty-second transistor T22.

[0161] In this configuration, the control electrode of the first transistor T1 is connected to the first clock signal terminal CKA, the first electrode of the first transistor T1 is connected to the light emission signal input terminal INPUT, and the second electrode of the first transistor T1 is connected to the second node N2.

[0162] The control electrode of the second transistor T2 is connected to the first clock signal terminal CKA, the first electrode of the second transistor T2 is connected to the second power supply terminal, and the second electrode of the second transistor T2 is connected to the third node N3.

[0163] The control electrode of the third transistor T3 is electrically connected to the second node N2, the first electrode of the third transistor T3 is connected to the third node N3, and the second electrode of the third transistor T3 is connected to the first clock signal terminal CKA.

[0164] The control electrode of the fourth transistor T4 is connected to the third node N3, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CKB, and the second electrode of the fourth transistor T4 is connected to the fourth node N4.

[0165] The control terminal of the fifth transistor T5 is connected to the second clock signal terminal CKB, the first terminal of the fifth transistor T5 is connected to the fourth node N4, and the second terminal of the fifth transistor T5 is connected to the first node N1.

[0166] The control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the second power supply terminal.

[0167] The first terminal of the third capacitor C3 is connected to the third node N3, and the second terminal of the third capacitor C3 is connected to the fourth node N4.

[0168] The control electrode of the seventh transistor T7 is connected to the third node N3, the first electrode of the seventh transistor T7 is connected to the second power supply terminal, and the second electrode of the seventh transistor T7 is connected to the first terminal of the eighth transistor T8.

[0169] The control terminal of the eighth transistor T8 is connected to the second clock signal terminal CKB, and the second terminal of the eighth transistor T8 is connected to the second node N2.

[0170] The control electrode of the ninth transistor T9 is connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the second power supply terminal, and the second electrode of the ninth transistor T9 is connected to the output terminal of the cascaded light emission signal.

[0171] The control electrode of the tenth transistor T10 is connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the output terminal of the cascaded light-emitting signal, and the second electrode of the tenth transistor T10 is connected to the first power supply terminal.

[0172] The control electrode of the 21st transistor T21 is connected to the sixth node N6, the first electrode of the 21st transistor T21 is connected to the second power supply terminal, and the second electrode of the 21st transistor T21 is connected to the light emission control drive signal output terminal OUT.

[0173] The control electrode of the 22nd transistor T22 is connected to the second node, the first electrode of the 22nd transistor T22 is connected to the output terminal OUT of the light emission control drive signal, and the second electrode of the 22nd transistor T22 is connected to the first power supply terminal.

[0174] In some embodiments, the cascaded output circuit 25 further includes a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second power supply terminal. The first terminal of the second capacitor C2 is connected to the cascaded output signal terminal, and the second terminal of the second capacitor C2 is connected to the second node N2. The first capacitor C1 and the second capacitor C2 are configured to improve voltage stability at the first and second nodes.

[0175] In some embodiments, the first light-emitting drive output circuit 29 further includes a fourth capacitor C4 and a fifth capacitor C5. The first terminal of the fourth capacitor C4 is connected to the sixth node N6, and the second terminal of the fourth capacitor C4 is connected to the second power supply terminal. The first terminal of the fifth capacitor C5 is connected to the light-emitting control drive signal output terminal, and the second terminal of the fifth capacitor C5 is connected to the second node N2.

[0176] In some embodiments, the first leakage protection circuit 26 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

[0177] Among them, the control electrode of the eleventh transistor T11 is connected to the first power supply terminal, the first electrode of the eleventh transistor T11 is connected to the fifth node N5, and the second electrode of the eleventh transistor T11 is connected to the first leakage protection node OFF1.

[0178] The control electrode of the twelfth transistor T12 is connected to the first power supply terminal, the first electrode of the twelfth transistor T12 is connected to the first leakage protection node OFF1, and the second electrode of the twelfth transistor T12 is connected to the second node N2.

[0179] The control electrode of the thirteenth transistor T13 is connected to the second node N2, the first electrode of the thirteenth transistor T13 is connected to the third power supply terminal, and the second electrode of the thirteenth transistor T13 is connected to the first leakage protection node OFF1.

[0180] In some embodiments, the second leakage protection circuit 27 includes a fourteenth transistor T14 and a fifteenth transistor T15.

[0181] The control electrode of the fourteenth transistor T14 is connected to the first node N1, the first electrode of the fourteenth transistor T14 is connected to the second power supply terminal, and the second electrode of the fourteenth transistor T14 is connected to the second leakage protection node OFF2.

[0182] The control electrode of the fifteenth transistor T15 is connected to the CR output terminal of the light-emitting cascade signal or the OUT output terminal of the light-emitting control drive signal. The first electrode of the fifteenth transistor T15 is connected to the first power supply terminal, and the second electrode of the fifteenth transistor T15 is connected to the second leakage protection node OFF2. It should be noted that... Figure 9 The example shown is only the case where the control electrode of the fifteenth transistor T15 is connected to the output terminal CR of the light-emitting cascade signal.

[0183] Figure 10 for Figure 9 The following is a timing diagram of one type of operation of the first shift register, as shown: Figure 10 As shown, the first operating voltage provided by the first power supply terminal is a high-level operating voltage VGH1, the second operating voltage provided by the second power supply terminal is a low-level operating voltage VGL, and the third operating voltage provided by the third power supply terminal is a high-level operating voltage VGH2, where VGH2 is slightly greater than VGH1. The process of the first shift register outputting an cascaded light-emitting signal through the cascaded light-emitting signal output terminal will be described in detail below. Figure 9 The process of the first shift register outputting the cascaded light signal includes the following working stages:

[0184] In the first stage t1, the LED signal input terminal INPUT provides a low-level signal, the first clock signal terminal CKA provides a high-level signal, and the second clock signal terminal CKB provides a low-level signal. Transistors T1, T2, T4, T7, T11, T12, and T15 are all turned on; transistors T3, T5, T6, T8, T9, T10, T13, and T14 are all turned off.

[0185] Specifically, when the first clock signal terminal CKA provides a high-level signal, both the first transistor T1 and the second transistor T2 are turned on. The low-level signal provided by the light-emitting signal input terminal INPUT is written to the fifth node N5. At this time, both the eleventh transistor T11 and the twelfth transistor T12 are turned on, so the low-level signal is written to the second node N2 through the eleventh transistor T11 and the twelfth transistor T12. The voltage at the second node N2 is in a low-level state, so the sixth transistor T6, the thirteenth transistor T13, and the tenth transistor T10 are all turned off. At the same time, the first operating voltage VGH1 is written to the third node N3 through the second transistor T2. The voltage at the third node N3 is in a high-level state, and the fourth transistor T4 is turned on. The low-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, so the voltage at the fourth node N4 is in a low-level state.

[0186] Since the second clock signal is at a low level, the fifth transistor T5 is turned off. At this time, the first node N1 is in a floating state, and the voltage at the first node N1 maintains the low level state of the previous stage. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the output terminal of the cascaded light-emitting signal is in a floating state, and the output terminal of the cascaded light-emitting signal maintains the high level state of the previous stage, that is, the output terminal CR of the cascaded light-emitting signal outputs a high level signal. At this time, the fifteenth transistor T15 is turned on, and the first operating voltage VGH1 is written to the second leakage protection node OFF2 through the fifteenth transistor T15. This effectively prevents the voltage at the output terminal CR of the cascaded light-emitting signal from leaking through the ninth transistor T9, which helps to maintain the stability of the voltage at the output terminal of the cascaded light-emitting signal.

[0187] The second phase t2 consists of two alternating sub-phases s1 and s2.

[0188] In sub-stage s1, the LED signal input terminal INPUT provides a low-level signal, the first clock signal terminal CKA provides a low-level signal, and the second clock signal terminal CKB provides a high-level signal. Transistors T4, T5, T7, T8, T9, T11, and T12 are all turned on; transistors T1, T2, T3, T6, T10, T13, T14, and T15 are all turned off.

[0189] Specifically, when the first clock signal terminal CKA is at a low level, both the first transistor T1 and the second transistor T2 are turned off, and the third node N3 remains in a floating state at a high level. The high-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, causing the voltage at the fourth node N4 to change from a low level to a high level. Under the bootstrap effect of the third capacitor C3, the voltage at the third node N3 is further pulled up to a higher level. At the same time, since the second clock signal terminal CKB provides a high-level signal, the fifth transistor T5 and the eighth transistor T8 are turned on. Since both the seventh transistor T7 and the eighth transistor T8 are turned on, the second operating voltage VGL1 is written to the fifth node N5 through the seventh transistor T7 and the eighth transistor T8, and the fifth node N5 remains at a low level. Correspondingly, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the second node N2 also remains at a low level. The sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 remain turned off.

[0190] Because the fifth transistor T5 is turned on, the high-level signal at the fourth node N4 can be written to the first node N1 through the fifth transistor T5. The voltage at the first node N1 is at a high level. At this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned on. The second operating voltage VGL is written to the cascaded light-emitting signal output terminal CR through the fourteenth transistor T14 and the ninth transistor T9. The cascaded light-emitting signal output terminal CR outputs a low-level signal. Correspondingly, the fifteenth transistor T15 is turned off.

[0191] In sub-stage s2, the light emission signal input terminal INPUT provides a low-level signal, the first clock signal terminal CKA provides a high-level signal, and the second clock signal terminal CKB provides a low-level signal.

[0192] Transistors T1, T2, T4, T7, T9, T11, and T12 are all on; transistors T3, T5, T6, T8, T10, T13, T14, and T15 are all off.

[0193] Specifically, when the first clock signal terminal CKA provides a high-level signal, both the first transistor T1 and the second transistor T2 are turned on. The low-level signal provided by the LED signal input terminal INPUT is written to the fifth node N5, keeping node N5 at a low level. Correspondingly, the second node N2 also remains at a low level. The sixth transistor T6, the tenth transistor T10, and the thirteenth transistor T13 remain off. Simultaneously, the first operating voltage is written to the third node N3 through the second transistor T2, causing the voltage at node N3 to drop to VGH1, placing it at a high level, and the fourth transistor T4 is turned on. The low-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, keeping the voltage at node N4 at a low level.

[0194] Since the second clock signal terminal CKB is at a low level, both the fifth transistor T5 and the eighth transistor T8 are turned off. At this time, the first node N1 is in a floating state and maintains the high level of the previous node. The ninth transistor T9 and the fourteenth transistor T14 remain on, and the cascaded light output terminal CR maintains a low-level signal output. Correspondingly, the fifteenth transistor T15 remains off.

[0195] In the third stage (t3), the LED signal input terminal INPUT provides a high-level signal, the first clock signal terminal CKA provides a low-level signal, and the second clock signal terminal CKB provides a high-level signal. Transistors T4, T5, T7, T8, T9, T11, and T12 are all turned on; transistors T1, T2, T3, T6, T10, T13, T14, and T15 are all turned off.

[0196] The specific working process of the first shift register in the third stage t3 is the same as that in the sub-stage s1, and will not be repeated here.

[0197] The fourth stage, t4, consists of two alternating sub-stages, s3 and s4.

[0198] In sub-stage s3, the LED signal input terminal INPUT provides a high-level signal, the first clock signal terminal CKA provides a high-level signal, and the second clock signal terminal CKB provides a low-level signal. Transistors T1, T2, T3, T6, T10, T13, and T15 are all turned on; transistors T4, T5, T7, T8, T9, and T14 are all turned off; and transistors T11 and T12 are first turned on and then switched to the off state.

[0199] Specifically, when the first clock signal terminal CKA is in a high-level state, both the first transistor T1 and the second transistor T2 are turned on. The high-level signal provided by the light-emitting signal input terminal INPUT is written to the fifth node N5 through the first transistor T1. At this time, both the eleventh transistor T11 and the twelfth transistor T12 are turned on. Therefore, the high-level signal is written to the second node N2 through the eleventh transistor T11 and the twelfth transistor T12. The voltage at the second node N2 is in a low-level state, so the sixth transistor T6, the thirteenth transistor T13, and the tenth transistor T10 are all turned on. Because the thirteenth transistor T13 is turned on, the third operating voltage VGH2 is written to the first leakage protection node OFF1 through the thirteenth transistor T13. Correspondingly, the voltages at the fifth node N5 and the second node N2 are pulled up through the eleventh transistor T11 and the twelfth transistor T12. At this time, the gate-source voltages of the eleventh transistor T11 and the twelfth transistor T12 decrease until the gate-source voltage of the eleventh transistor T11 equals the threshold voltage of the eleventh transistor T11 and the gate-source voltage of the twelfth transistor T12 equals the threshold voltage of the twelfth transistor T12. Then, the eleventh transistor T11 and the twelfth transistor T12 are both turned off, and the first leakage protection node OFF1 is in a floating state. Through this design, leakage current can be effectively prevented from occurring at the second node N2 through other transistors, so as to maintain the voltage at the second node N2 at a high level. It should be noted that during the process of charging the fifth node N5 and the second node N2 through the eleventh transistor T11 and the twelfth transistor T12 respectively at the first leakage protection node OFF1, the voltage at the fifth node N5 and the second node N2 increases only slightly before the eleventh transistor T11 and the twelfth transistor T12 are turned off.

[0200] At the same time, the first operating voltage VGH1 is written to the third node N3 through the second transistor T2, and the voltage at the third node N3 is in a high-level state. The fourth transistor T4 is turned on, and the low-level signal provided by the second clock signal terminal CKB is written to the fourth node N4 through the fourth transistor T4, and the voltage at the fourth node N4 is in a low-level state.

[0201] Since the second clock signal is at a low level, the fifth transistor T5 is turned off. At this time, because the sixth transistor T6 is turned on, the second operating voltage VGL is written to the first node N1 through the sixth transistor T6, and the voltage at the first node N1 is at a low level. At this time, both the ninth transistor T9 and the fourteenth transistor T14 are turned off.

[0202] With the ninth transistor T9 off and the tenth transistor T10 on, the cascaded LED signal output terminal CR outputs a high-level signal. Correspondingly, the fifteenth transistor T15 turns on.

[0203] In sub-stage s4, the LED signal input terminal INPUT provides a high-level signal, the first clock signal terminal CKA provides a low-level signal, and the second clock signal terminal CKB provides a high-level signal. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, and the fifteenth transistor T15 are all turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the fourteenth transistor T14 are all turned off. The eleventh transistor T11 and the twelfth transistor T12 are first turned on and then switched to the off state.

[0204] Specifically, when the first clock signal terminal CKA is in a low-level state, both the first transistor T1 and the second transistor T2 are turned off, the fifth node N5 maintains the high-level state of the previous stage, the third transistor T3 is turned on, and the low-level signal provided by the first clock signal terminal CKA is written to the third node N3 through the third transistor T3. The voltage at the third node N3 is in a low-level state, and the fourth transistor T4 and the seventh transistor T7 are turned off.

[0205] Since both the eleventh transistor T11 and the twelfth transistor T12 are off, the second node N2 is floating to maintain the high level state of the previous stage. At this time, the sixth transistor T6, the tenth transistor T10 and the thirteenth transistor T13 are all turned on, the voltage at the first node N1 is maintained at a low level, and the ninth transistor T9 and the fourteenth transistor T14 are both kept off.

[0206] With the ninth transistor T9 off and the tenth transistor T10 on, the output terminal CR of the cascaded LED signal maintains a high-level signal. Correspondingly, the fifteenth transistor T15 is turned on.

[0207] Subsequently, when the first clock signal terminal CKA provides a high-level signal and the light-emitting signal input terminal INPUT provides a low-level signal, the first stage t1 of the next cycle begins.

[0208] It should be noted that the preferred embodiment of this disclosure is the inclusion of a first leakage protection circuit 26 and a second leakage protection circuit 27 within the first shift register. The first leakage protection circuit 26 can maintain voltage stability at the second node N2 during the fourth stage t4, and the second leakage protection circuit 27 can maintain voltage stability at the output terminal CR of the cascaded light emission signal during the first stage t1. Those skilled in the art should understand that in some embodiments, the first shift register may optionally exclude the first leakage protection circuit 26 and / or the second leakage protection circuit 27.

[0209] See you again Figure 9 As shown, in some embodiments, the first shift register further includes: a global light-emitting reset circuit 28, which is connected to the global light-emitting reset signal terminal TRST, the first power supply terminal, and the second node N2, and is configured to write the first operating voltage provided by the first power supply terminal to the second node N2 in response to the control of the signal provided by the global light-emitting reset signal terminal TRST.

[0210] See Figure 9 As shown, in some embodiments, the light-emitting global reset circuit 28 includes a sixteenth transistor T16; the control electrode of the sixteenth transistor T16 is connected to the light-emitting global reset signal terminal, the first electrode of the sixteenth transistor T16 is connected to the second node N2, and the second electrode of the sixteenth transistor T16 is connected to the first power supply terminal.

[0211] When a global reset is required, the global reset signal terminal provides a high-level signal (i.e., an effective level signal) to turn on the sixteenth transistor T16 in the first shift register. At this time, the first operating voltage VGH1 is written to the fifth node N5 through the sixteenth transistor T16, thereby keeping the second node N2 in a high-level state to achieve the purpose of global reset. It should be understood by those skilled in the art that in some embodiments, the first shift register may optionally exclude the light-emitting global reset circuit.

[0212] The following section will describe in detail the process of the first shift register outputting the light-emitting control signal through the light-emitting control drive signal output terminal, using several specific examples.

[0213] Figure 11 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 11 As shown, in some embodiments, the first node N1 is directly connected to the sixth node N6, and the second light-emitting drive output circuit 30 includes a twenty-third transistor T23. The control electrode of the twenty-third transistor T23 is connected to the forced output control terminal CSD, the first electrode of the twenty-third transistor T23 is connected to the first power supply terminal, and the second electrode of the twenty-third transistor T23 is connected to the light-emitting control drive signal output terminal OUT.

[0214] Figure 12 for Figure 11 The following is a timing diagram of one type of operation of the first shift register, as shown: Figure 12 As shown, in one scenario, when the first shift register is not required to force an effective output signal, a low-level signal (i.e., an ineffective signal) can be continuously provided to the forced output control terminal CSD. During the process of the first shift register outputting the cascaded light-emitting signal through the cascaded light-emitting signal output terminal CR, the twenty-third transistor T23 remains off (the second light-emitting drive output circuit is in a non-operating state). At this time, the signal output by the light-emitting control drive signal output terminal OUT is only affected by the first light-emitting drive output circuit 29. Since the operating state of the twenty-first transistor T21 is consistent with the operating state of the ninth transistor T9, and the operating state of the twenty-second transistor T22 is consistent with the operating state of the tenth transistor T10, the output signal of the light-emitting control drive signal output terminal OUT is consistent with the output signal of the cascaded light-emitting signal output terminal CR.

[0215] Figure 13 for Figure 11 Another timing diagram of the first shift register shown is as follows: Figure 13 As shown, in another scenario, when the first shift register needs to force the output of a valid level signal during a preset period (e.g., a blank period), a high-level signal (i.e., a valid level signal) can be continuously provided to the forced output control terminal CSD during the required period, and a low-level signal (i.e., an invalid level signal) can be provided to the forced output control terminal CSD at other times. Therefore, during the preset period, the clock of the twenty-third transistor T23 is in the on state (the second light-emitting drive output circuit 30 is in the working state), and during other times, the clock of the twenty-third transistor T23 is in the off state (the second light-emitting drive output circuit is in the non-working state). At this time, regardless of the state of the twenty-first transistor T21 and the twenty-second transistor T22 in the first light-emitting drive output circuit during the preset period, the light-emitting control drive signal output terminal OUT always outputs a high-level signal (i.e., a valid level signal); at other times, the signal output by the light-emitting control drive signal output terminal OUT is consistent with the signal output by the light-emitting cascade signal output terminal CR.

[0216] It should be noted that, in Figure 13 In the scenario shown, since the first node N1 and the sixth node N6 are directly connected, that is, the voltage of the first node N1 and the sixth node N6 is always consistent, there will be a situation where the twenty-first transistor T21 and the twenty-third transistor T23 are turned on at the same time. In order to ensure that the output terminal OUT of the light emission control drive signal can output a high-level signal, the channel width-to-length ratio of the twenty-third transistor T23 can be made greater than the channel width-to-length ratio of the twenty-first transistor T21.

[0217] Figure 14 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 14 As shown, in some embodiments, the forced output control terminal includes a first control terminal and a second control terminal; the second light-emitting drive output circuit includes two 23rd transistors T23' and T23" connected in series between the first power supply terminal and the light-emitting control drive signal output terminal; the control electrode of one of the two 23rd transistors T23' and T23" is connected to the first control terminal CP1, and the control electrode of the other 23rd transistor T23" is connected to the second control terminal CP2.

[0218] In other words, when the first control terminal CP1 and the second control terminal CP2 simultaneously provide a high-level signal (effective level signal), the two twenty-third transistors T23' and T23" are simultaneously turned on, and the second light-emitting drive output circuit 30 is in working state. That is, the period when the first control terminal CP1 and the second control terminal CP2 simultaneously provide effective level signals is the period when the first shift register needs to force the output of an effective level signal.

[0219] In some embodiments, the first control terminal and the second control terminal connected to the first shift register are respectively: the sensing cascade node inside the second shift register corresponding to the same row of pixel units in the display sensing gate driving circuit and the pre-configured fourth clock signal terminal; for a detailed description of the display sensing gate driving circuit and the second shift register, please refer to the following content.

[0220] Figure 15 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 15 As shown, unlike the previous embodiments, Figure 15 The first shift register in the illustrated embodiment further includes a node control circuit 31; wherein, the node control circuit 31 is located between the sixth node N6 and the first node N1, the sixth node N6 is connected to the first node N1 through the node control circuit 31, the node control circuit 31 is also connected to the second power supply terminal and the forced output control terminal CSD, and the node control circuit 31 is configured to respond to the control of the signal provided by the forced output control terminal CSD, thereby disconnecting the sixth node N6 from the first node N1 and writing the second operating voltage provided by the second power supply terminal to the sixth node N6.

[0221] In this embodiment of the disclosure, when the forced output control terminal CSD provides a valid level signal, the sixth node N6 and the first node N1 can be disconnected, and an invalid level signal can be written to the sixth node N6. Through this design, the situation where the second light-emitting drive output circuit 30 writes the first working voltage to the light-emitting control drive signal output terminal OUT while the first light-emitting drive output circuit 29 writes the second working voltage to the light-emitting control drive signal output terminal OUT can be effectively avoided.

[0222] Figure 16 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 16 As shown, in some embodiments, the node control circuit 31 includes a first write sub-circuit 311, a second write sub-circuit 312, a twenty-fourth transistor T24, and a twenty-fifth transistor T25.

[0223] The first write sub-circuit 311 is connected to the second power supply terminal, the forced output control terminal CSD, and the control electrode of the twenty-fourth transistor T24. The first write sub-circuit 311 is configured to write the second operating voltage provided by the second power supply terminal to the control electrode of the twenty-fourth transistor T24 in response to the control of the signal provided by the forced output control terminal CSD.

[0224] The second write sub-circuit 312 is connected to the second power supply, the forced output control terminal CSD, and the sixth node N6. The second write sub-circuit 312 is configured to write the second operating voltage provided by the second power supply terminal to the sixth node N6 in response to the control of the signal provided by the forced output control terminal CSD.

[0225] The first terminal of the twenty-fourth transistor T24 is connected to the first node N1, and the second terminal of the twenty-fourth transistor T24 is connected to the sixth node N6.

[0226] The control electrode of the 25th transistor T25 is connected to the first power supply terminal or the second clock signal terminal. The first terminal of the 25th transistor T25 is connected to the control electrode of the 25th transistor T25. The second terminal of the 25th transistor T25 is connected to the second terminal of the 26th transistor T26.

[0227] Figure 17 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 17 As shown, in some embodiments, the first write sub-circuit 311 includes a twenty-sixth transistor T26, and the second write sub-circuit 312 includes a twenty-seventh transistor T27.

[0228] Among them, the control electrode of the twenty-sixth transistor T26 is connected to the forced output control terminal CSD, the first electrode of the twenty-sixth transistor T26 is connected to the second power supply terminal, and the second electrode of the twenty-sixth transistor T26 is connected to the control electrode of the twenty-fourth transistor T24.

[0229] The control electrode of the 27th transistor T27 is connected to the forced output control terminal CSD, the first electrode of the 27th transistor T27 is connected to the second power supply terminal, and the second electrode of the 27th transistor T27 is connected to the sixth node N6.

[0230] When the forced output control terminal CSD provides a high-level signal (valid level signal), the 26th and 27th transistors are turned on, and both the first write sub-circuit 311 and the second write sub-circuit 312 are in operation. The second operating voltage can be written to the control electrode of the 24th transistor and the sixth node N6, respectively. At this time, the 24th transistor is turned off, so that the circuit between the first node N1 and the sixth node N6 is broken. When the forced output control terminal CSD provides a low-level signal (invalid level signal), the 25th transistor can write the valid level signal to the control electrode of the 24th transistor, and the 24th transistor is turned on, so that the circuit between the first node N1 and the sixth node N6 is connected. At this time, the voltages of the first node N1 and the sixth node N6 are consistent.

[0231] Figure 18 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 18 As shown, in some embodiments, the forced output control terminal CSD includes a first control terminal CP1 and a second control terminal CP2.

[0232] The first write sub-circuit 311 includes two 26th transistors T26' and T26" connected in series between the second power supply terminal and the control electrode of the 24th transistor T24; the control electrode of one of the two 26th transistors T26' and T26" is connected to the first control terminal CP1, and the control electrode of the other 26th transistor T26" is connected to the second control terminal CP2.

[0233] The second write sub-circuit 312 includes two 27th transistors T27' and T27" connected in series between the second power supply terminal and the sixth node N6; the control electrode of one of the two 27th transistors T27' and T27" is connected to the first control terminal CP1, and the control electrode of the other 27th transistor T27" is connected to the second control terminal CP2.

[0234] Figure 19 This is a schematic diagram of another circuit structure of the first shift register in the embodiments of this disclosure, as shown below. Figure 19 As shown, in some embodiments, the first shift register further includes a twenty-eighth transistor T28; the control electrode of the twenty-eighth transistor T28 is connected to the second node N2, the first electrode of the twenty-eighth transistor T28 is connected to the second power supply terminal, and the second electrode of the twenty-eighth transistor T28 is connected to the sixth node N6.

[0235] When the voltage at the second node N2 is at an effective level, the twenty-eighth transistor T28 is turned on, and the low-level voltage VGL is written to the sixth node N6 through the twenty-eighth transistor T28, so that when the second node N2 is at an effective level, the voltage at the sixth node N6 is stably maintained at an ineffective level.

[0236] Based on the same inventive concept, this disclosure also provides a gate driving circuit, which is a light-emitting control gate driving circuit, and for ease of description, it is referred to as the first gate driving circuit. Figure 20 This is a schematic diagram of a circuit structure for a gate driving circuit provided in an embodiment of the present disclosure, as shown below. Figure 20 As shown, the first gate drive circuit 200 includes: a plurality of cascaded first shift registers SR_1, SR_2, SR_3, and SR_4; wherein, the first shift registers SR_1, SR_2, SR_3, and SR_4 are the first shift registers provided in the above embodiment; the light emission signal input terminal INPUT of the first shift register SR_1 located in the first stage is connected to the light emission start signal line STV, and the first shift registers SR_2, SR_3, and SR_4 in other stages are connected to the light emission cascade signal output terminal CR of the first shift register of their respective preceding stage; the light emission control drive signal output terminal OUT of each first shift register SR_1, SR_2, SR_3, and SR_4 is connected to the corresponding light emission control signal line EM.

[0237] In some embodiments, the first gate driving circuit is configured with a first clock signal line CK1 and a second clock signal line CK2; wherein, the first clock signal terminal CKA of the first shift register located at the odd level in the first gate driving circuit is connected to the first clock signal line CK1, the second clock signal terminal CKB of the first shift register located at the odd level is connected to the second clock signal line CK2, the first clock signal terminal CKA of the first shift register located at the even level is connected to the second clock signal line CK2, and the second clock signal terminal CKB of the first shift register located at the even level is connected to the first clock signal line CK1.

[0238] When a global light-emitting reset circuit is configured in the first shift register within the first gate driving circuit, the first gate driving circuit is also configured with a global light-emitting reset signal line Reset, and the global light-emitting reset signal terminals TRST configured in each stage of the first shift register are connected to the same global light-emitting reset signal line Reset.

[0239] Based on the same inventive concept, this disclosure also provides a display device. Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure, such as... Figure 21 As shown, the display device 100 includes a display area 101 and a peripheral area 102 located around the display area 101. The display area 101 includes a plurality of pixel units 300 arranged in an array. Each row of pixel units is configured with a corresponding light emission control signal line EM. The light emission control signal line EM is connected to the control electrode of the light emission control transistor in the corresponding pixel unit 300. The peripheral area 102 includes a first gate driving circuit 200 for providing a light emission control signal to the light emission control signal line EM. The first gate driving circuit 200 adopts the first gate driving circuit provided in the above embodiment.

[0240] In some embodiments of this disclosure, the pixel unit 300 may be adopted Figure 3 The 4T1C structure shown herein, for the second gate line within the display area 100, allows for the configuration of a corresponding second gate drive circuit 400 within the peripheral area. The second gate drive circuit 400 includes multiple cascaded second shift registers. Figure 21 (not shown in the diagram), the second shift register can provide the corresponding drive signal to at least the corresponding second gate line.

[0241] Figure 22 This is a schematic diagram of a circuit structure of the second shift register in an embodiment of this disclosure, such as... Figure 22 As shown, in some embodiments, the second shift register is configured with a second gate drive signal output terminal OUT2, which is connected to the corresponding second gate line.

[0242] The second shift register includes a first display precharge reset circuit 41, a sensing cascade circuit 42, a first sensing precharge reset circuit 43, a first pull-down control circuit 44, a gate cascade output circuit 45, and a second gate drive output circuit 46.

[0243] The sensing cascade circuit 42 and the first sensing precharge reset circuit 43 are connected to the sensing cascade node H. The first display precharge reset circuit 41, the first sensing precharge reset circuit 43, the first pull-down control circuit 44, the gate cascade output circuit 45, and the second gate drive output circuit 46 are connected to the first pull-up node PU1. The first pull-down control circuit 44, the gate cascade output circuit 45, and the second gate drive output circuit 46 are connected to the first pull-down node PD1.

[0244] The first display precharge reset circuit 41 is connected to the display signal input terminal STU1, the display reset signal terminal STD, and the fifth power supply terminal. The first display precharge reset circuit 41 is configured to write the signal provided by the display signal input terminal STU1 to the first pull-up node PU1 in response to the control of the signal provided by the display signal input terminal STU1, and to write the fifth operating voltage provided by the fifth power supply terminal to the first pull-down node PD1 in response to the control of the signal provided by the display reset signal terminal STD.

[0245] The sensing cascade circuit 42 is connected to the sensing signal input terminal STU2 and the random signal terminal OE. The sensing cascade circuit 42 is configured to write the signal provided by the sensing signal input terminal STU2 into the sensing cascade node H in response to the control of the signal provided by the random signal terminal OE.

[0246] The first sensing precharge reset circuit 43 is connected to the third clock signal terminal CKC, the sensing reset signal terminal SRST, and the fifth power supply terminal. The first sensing precharge reset circuit 43 is configured to write the signal provided by the third clock signal terminal CKC to the sensing precharge node N in response to the control of the voltage at the sensing cascade node H, and to write the voltage at the sensing precharge node N to the first pull-up node PU1 in response to the control of the signal provided by the third clock signal terminal CKC, and to write the fifth operating voltage provided by the fifth power supply terminal to the first pull-up node PU1 in response to the control of the signal provided by the sensing reset signal terminal SRST.

[0247] The first pull-down control circuit 44 is connected to the fourth power supply terminal and the fifth power supply terminal. The first pull-down control circuit 44 is configured to write a voltage that is opposite to the voltage at the first pull-up node PU1 to the first pull-down node PD1.

[0248] The gate cascade output circuit 45 is connected to the cascade clock signal terminal CLKX, the fifth power supply terminal, and the gate cascade signal output terminal CR1. The gate cascade output circuit 45 is configured to write the signal provided by the cascade clock signal terminal CLKX to the gate cascade signal output terminal CR1 in response to the control of the voltage at the first pull-up node PU1, and to write the fifth operating voltage provided by the fifth power supply terminal to the gate cascade signal output terminal CR1 in response to the control of the voltage at the first pull-down node PD1.

[0249] The second gate drive output circuit 46 is connected to the second drive clock signal terminal CLK2 and the sixth power supply terminal. The second gate drive output circuit 46 is configured to write the signal provided by the second drive clock signal terminal CLK2 to the second gate drive signal output terminal OUT2 in response to the control of the voltage at the first pull-up node PU1, and to write the sixth operating voltage provided by the sixth power supply terminal to the second gate drive signal output terminal OUT2 in response to the control of the voltage at the first pull-down node PD1.

[0250] In some embodiments, when the forced output control terminal is a single control terminal, within the first gate drive circuit 200, any forced output control terminal CSD connected to a first shift register includes: a second gate drive signal output terminal OUT2 or a gate cascade signal output terminal CR1 configured by a second shift register corresponding to the same row of pixel units as the first shift register.

[0251] In some embodiments, when the forced output control terminal CSD includes a first control terminal CP1 and a second control terminal CP2, within the first gate drive circuit 200, the first control terminal CP1 and the second control terminal CP2 connected to any one of the first shift registers are respectively: the sensing cascade node H inside the second shift register corresponding to the same row of pixel units as the first shift register and the pre-configured fourth clock signal terminal.

[0252] Figure 23 This is a schematic diagram of another circuit structure of the second shift register in an embodiment of this disclosure, as shown below. Figure 23 As shown, the first display precharge reset circuit 41 includes a thirty-first transistor T31 and a thirty-second transistor T32.

[0253] Among them, the control electrode of the thirty-first transistor T31 is connected to the display signal input terminal STU1, the first electrode of the thirty-first transistor T31 is connected to the control electrode of the thirty-first transistor T31, and the second electrode of the thirty-first transistor T31 is connected to the first pull-up node PU1.

[0254] The control terminal of the 32nd transistor T32 is connected to the display reset signal terminal STD, the first terminal of the 32nd transistor T32 is connected to the first pull-up node PU1, and the second terminal of the 32nd transistor T32 is connected to the fifth power supply terminal.

[0255] In some embodiments, the sensing cascade circuit 42 includes a thirty-third transistor T33; the control terminal of the third transistor is connected to the random signal terminal OE, the first terminal of the thirty-third transistor T33 is connected to the sensing signal input terminal STU2, and the second terminal of the thirty-third transistor T33 is connected to the sensing cascade node H.

[0256] In some embodiments, the first sensing precharge reset circuit 43 includes a thirty-fourth transistor T34, a thirty-fifth transistor T35, and a thirty-sixth transistor T36.

[0257] Among them, the control electrode of the thirty-fourth transistor T34 is connected to the sensing cascade node H, the first electrode of the thirty-fourth transistor T34 is connected to the third clock signal terminal CKC, and the second electrode of the thirty-fourth transistor T34 is connected to the sensing precharge node N.

[0258] The control terminal of the 35th transistor T35 is connected to the third clock signal terminal CKC, the first terminal of the 35th transistor T35 is connected to the sensing precharge node N, and the second terminal of the 35th transistor T35 is connected to the first pull-up node PU1.

[0259] The control terminal of the thirty-sixth transistor T36 is connected to the sensing reset signal terminal SRST, the first terminal of the thirty-sixth transistor T36 is connected to the first pull-up node PU1, and the second terminal of the thirty-sixth transistor T36 is connected to the fifth power supply terminal.

[0260] In some embodiments, the first pull-down control circuit 44 includes a thirty-seventh transistor T37, a thirty-eighth transistor T38, a thirty-ninth transistor T39, and a fortieth transistor T40.

[0261] The control electrode of the thirty-seventh transistor T37 is connected to the fourth power supply terminal, the first electrode of the thirty-seventh transistor T37 is connected to the control electrode of the thirty-seventh transistor T37, and the second electrode of the thirty-seventh transistor T37 is connected to the control electrode of the thirty-eighth transistor T38.

[0262] The control terminal of the thirty-eighth transistor T38 is connected to the first terminal of the fortieth transistor T40. The first terminal of the thirty-eighth transistor T38 is connected to the fourth power supply terminal. The second terminal of the thirty-eighth transistor T38 is connected to the first pull-down node PD1.

[0263] The control electrode of the thirty-ninth transistor T39 is connected to the first pull-up node PU1, the first electrode of the thirty-ninth transistor T39 is connected to the first pull-down node PD1, and the second electrode of the thirty-ninth transistor T39 is connected to the fifth power supply terminal.

[0264] The control electrode of the 40th transistor T40 is connected to the first pull-up node PU1, and the second electrode of the 40th transistor T40 is connected to the fifth power supply terminal.

[0265] In some embodiments, the gate-cascaded output circuit 45 includes a forty-first transistor T41 and a forty-second transistor T42.

[0266] Among them, the control electrode of the forty-first transistor T41 is connected to the first pull-up node PU1, the first electrode of the forty-first transistor T41 is connected to the cascaded clock signal terminal CLKX, and the second electrode of the forty-first transistor T41 is connected to the gate cascaded signal output terminal CR1.

[0267] The control electrode of the forty-second transistor T42 is connected to the first pull-down node PD1, the first electrode of the forty-second transistor T42 is connected to the fifth power supply terminal, and the second electrode of the forty-second transistor T42 is connected to the gate cascade signal output terminal CR1.

[0268] In some embodiments, the second gate drive output circuit 46 includes a forty-third transistor T43 and a forty-fourth transistor T44.

[0269] Among them, the control electrode of the forty-third transistor T43 is connected to the first pull-up node PU1, the first electrode of the forty-third transistor T43 is connected to the second drive clock signal terminal CLK2, and the second electrode of the forty-third transistor T43 is connected to the second gate drive signal output terminal OUT2.

[0270] The control electrode of the forty-fourth transistor T44 is connected to the first pull-down node PD1, the first electrode of the forty-fourth transistor T44 is connected to the sixth power supply terminal, and the second electrode of the forty-fourth transistor T44 is connected to the second gate drive signal output terminal OUT2.

[0271] In some embodiments, the second shift register further includes a twelfth capacitor C12, the first end of which is connected to the first pull-up node PU1, and the second end of which is connected to the second gate drive signal output terminal OUT2.

[0272] In some embodiments, the second shift register further includes a first noise reduction circuit 48; the first noise reduction circuit 48 is connected to a first pull-up node PU1, a first pull-down node PD1, and a fifth power supply terminal, and is configured to write a fifth operating voltage provided by the fifth power supply terminal to the first pull-up node PU1 in response to voltage control at the first pull-down node PD1. In this embodiment, the first noise reduction circuit 48 can reduce noise from the first pull-up node PU1 to maintain the stability of the voltage at the first pull-up node PU1.

[0273] Optionally, the first noise reduction circuit 48 includes a forty-seventh transistor T47; the control electrode of the forty-seventh transistor T47 is connected to the first pull-down node PD1, the first electrode of the forty-seventh transistor T47 is connected to the fifth power supply terminal, and the second electrode of the forty-seventh transistor T47 is connected to the first pull-up node PU1.

[0274] In some embodiments, the second shift register further includes a second noise reduction circuit 49. The second noise reduction circuit 49 is connected to a first pull-down node PD1, a sensing cascade node H, a third clock signal terminal CKC, and a fifth power supply terminal. The second noise reduction circuit 49 is configured to write a fifth operating voltage provided by the fifth power supply terminal to the first pull-down node PD1 in response to control of the voltage at the sensing cascade node H and the signal provided by the third clock signal terminal CKC. In this embodiment, the second noise reduction circuit 49 can reduce noise from the first pull-down node PD1 to maintain the stability of the voltage at the first pull-down node PD1.

[0275] Optionally, the second noise reduction circuit includes a forty-eighth transistor T48 and a forty-ninth transistor T49. The control electrode of the forty-eighth transistor T48 is connected to the third clock signal terminal CKC, the first electrode of the forty-eighth transistor T48 is connected to the first pull-down node PD1, and the second electrode of the forty-eighth transistor T48 is connected to the first electrode of the forty-ninth transistor T49. The control electrode of the forty-ninth transistor T49 is connected to the sensing cascade node H, and the second electrode of the forty-ninth transistor T49 is connected to the fifth power supply terminal.

[0276] In some embodiments, the second shift register further includes a third noise reduction circuit 50, which is connected to the display signal input terminal STU1, the first pull-down node PD1, and the fifth power supply terminal. The third noise reduction circuit 50 is configured to write a fifth operating voltage provided by the fifth power supply terminal to the first pull-down node PD1 in response to the control of the signal provided by the display signal input terminal STU1. In this embodiment, the third noise reduction circuit can reduce noise from the first pull-down node PD1 to maintain the stability of the voltage at the first pull-down node PD1.

[0277] Optionally, the third noise reduction circuit 50 includes: a fiftieth transistor T50; the control electrode of the fiftieth transistor T50 is connected to the display signal input terminal STU1, the first electrode of the fiftieth transistor T50 is connected to the fifth power supply terminal, and the second electrode of the fiftieth transistor T50 is connected to the first pull-down node PD1.

[0278] The following will be discussed in conjunction with the accompanying drawings. Figure 23 The operation of the second shift register shown is described in detail. The fourth operating voltage provided by the fourth power supply terminal is a high-level voltage VGH, the fifth operating voltage provided by the fifth power supply terminal is a low-level operating voltage VGL1, and the sixth operating voltage provided by the sixth power supply terminal is a low-level operating voltage VGL2. The fifth operating voltage VGL1 is slightly lower than the sixth operating voltage VGL2.

[0279] Figure 24 for Figure 23 The following is a timing diagram of one operation of the second shift register, as shown: Figure 23 and Figure 24 As shown, the operation of this second shift register includes the following 7 stages:

[0280] During the sensing cascading phase t0 (during the blank period of the previous frame), the signal provided by the display signal input terminal STU1 is at a low level, the signal provided by the sensing signal input terminal STU2 is at a high level, the signal provided by the display reset signal terminal STD is at a low level, the signal provided by the third clock signal terminal CKC is at a low level, the signal provided by the random signal terminal OE is at a high level, the signal provided by the sensing reset signal terminal SRST is at a high level, the signal provided by the cascading clock signal terminal CLKX is at a high level, and the signal provided by the second drive clock signal terminal CLK2 is at a high level.

[0281] At this time, the thirty-third transistor T33 is turned on under the control of the high-level signal provided by the random signal terminal OE. The high-level signal provided by the sensing signal input terminal STU2 is written to the sensing cascade node H through the thirty-third transistor T33, and the voltage at the sensing cascade node H is in a high-level state. At the same time, the thirty-fourth transistor T34 is turned on under the control of the voltage at the sensing cascade node H. The low-level signal provided by the third clock signal terminal CKC is written to the sensing precharge node N (i.e., the first terminal of the thirty-fifth transistor T35) through the thirty-fourth transistor T34. Meanwhile, the thirty-fifth transistor T35 is turned off under the control of the low-level signal provided by the third clock signal terminal CKC, so the sensing precharge node N and the first pull-up node PU1 are disconnected.

[0282] The thirty-sixth transistor T36 is turned on under the control of the high-level signal provided by the sensing reset signal terminal SRST, so that the fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-up node PU1 through the thirty-sixth transistor T36. At this time, the first pull-up node PU1 is in a low-level state.

[0283] Since both the display signal input terminal STU1 and the display reset signal terminal STD provide low-level signals, both the thirty-first transistor T31 and the thirty-second transistor T32 are turned off.

[0284] Since the voltage at the first pull-up node PU1 is at a low level, transistors T39, T40, and T43 are all off. Simultaneously, within the pull-down control circuit, under the control of the fourth operating voltage VGH provided by the fourth power supply, transistors T37 and T38 are turned on. The fourth operating voltage VGH is written to the first pull-down node PD1 through transistor T38, making the voltage at PD1 high. At this time, transistor T44 is turned on under the control of the voltage at the first pull-down node PD1 (which is currently high). The sixth operating voltage VGL2 provided by the sixth power supply is written to the second gate drive signal output terminal OUT2 through transistor T44, resulting in a low-level signal output from OUT2.

[0285] During the precharge phase t1, the signal provided by the display signal input terminal STU1 is at a high level, the signal provided by the sensing signal input terminal STU2 is initially at a low level and then switches to a high level after a period of time, the signal provided by the display reset signal terminal STD is at a low level, the signal provided by the third clock signal terminal CKC is at a low level, the signal provided by the random signal terminal OE is at a low level, the signal provided by the sensing reset signal terminal SRST is at a low level, and the signal provided by the second drive clock signal terminal CLK2 is at a low level.

[0286] Meanwhile, since both the signal provided by the random signal terminal OE and the signal provided by the sensing reset signal terminal SRST are at a low level, both the thirty-third transistor T33 and the thirty-sixth transistor T36 are turned off, and the sensing cascade node H is in a floating state. The voltage of the sensing cascade node H remains at the high level of the previous stage. It should be noted that since the thirty-third transistor T33 is turned off, whether the signal provided by the sensing signal input terminal STU2 is at a high level or a low level will not affect the voltage of the sensing cascade node H.

[0287] In some embodiments, an eleventh capacitor C11 is provided in the second shift register. The first end of the eleventh capacitor C11 is connected to the sensing cascade node H, and the second end of the eleventh capacitor C11 is connected to the fifth power supply terminal. The eleventh capacitor C11 can maintain the stability of the voltage at the sensing cascade node H after the sensing cascade stage t0 ends and when the sensing cascade node H is in a floating state; since the signal provided by the third clock signal terminal CKC is in a low level state, the thirty-fifth transistor T35 remains in the off state.

[0288] At the same time, since the signal provided by the display signal input terminal STU1 is at a high level and the signal provided by the display reset signal terminal STD is at a low level, the thirty-first transistor T31 is turned on and the thirty-second transistor T32 is turned off. The fourth operating voltage VGH provided by the fourth power supply terminal can be written to the first pull-up node PU1 through the thirty-first transistor T31, and the voltage at the first pull-up node PU1 is at a high level.

[0289] Under the control of the voltage at the first pull-up node PU1, transistors 39 (T39), 40 (T40), and 43 (T43) are turned on. The fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-down node PD1 through transistor 39 (T39) and to the control electrode of transistor 38 (T38) through transistor 40 (T40). At this time, transistor 38 (T38) is turned off, and transistor 37 (T37) is equivalent to a resistor. The voltage at the first pull-down node PD1 is low, and transistors 47 (T47) and 44 (T44) are both turned off. At the same time, the low-level signal provided by the second drive clock signal terminal CLK2 is written to the corresponding second gate drive signal output terminal OUT2 through transistor 43 (T43), that is, the second gate drive signal output terminal OUT2 outputs a low-level signal.

[0290] In addition, the fiftieth transistor T50 is turned on under the control of the high-level signal provided by the display signal input terminal STU1, and the fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-down node PD1 through the fiftieth transistor T50, thereby performing noise reduction processing on the first pull-down node PD1 to maintain the stability of the voltage at the first pull-down node PD1.

[0291] During the display output phase t2, the signal provided by the display signal input terminal STU1 is at a low level, the signal provided by the sensing signal input terminal STU2 is initially at a high level and then switches to a low level after a period of time, the signal provided by the display reset signal terminal STD is at a low level, the signal provided by the third clock signal terminal CKC is at a low level, the signal provided by the random signal terminal OE is at a low level, the signal provided by the sensing reset signal terminal SRST is at a low level, and the signal provided by the second drive clock signal terminal CLK2 is initially at a high level and then switches to a low level after a period of time.

[0292] Since the signals provided by the random signal terminal OE and the sensing reset signal terminal SRST are both at a low level, the thirty-third transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascade node H is in a floating state, and the voltage at the sensing cascade node H remains at a high level as in the previous stage (the signal provided by the sensing input signal terminal will not affect the voltage at the sensing cascade node H); since the signal provided by the third clock signal terminal CKC is at a low level, the thirty-fifth transistor T35 remains in a turned-off state.

[0293] Since the signals provided by the display signal input terminal STU1 and the display reset signal terminal STD are both at a low level, the thirty-first transistor T31 and the thirty-second transistor T32 are both in the off state. The first pull-up node PU1 is in the floating state and maintains the high level state of the previous stage. At this time, the thirty-ninth transistor T39, the fortieth transistor T40 and the forty-third transistor T43 remain in the conducting state, the first pull-down node PD1 remains in the low level state, and the forty-seventh transistor T47 and the forty-fourth transistor T44 are both cut off. The signal provided by the second drive clock signal terminal CLK2 is written to the second gate drive signal output terminal OUT2 through the forty-third transistor T43.

[0294] Depend on Figure 24 It can be seen that at the initial moment of the display driving phase t2, the signal provided by the second driving clock signal terminal CLK2 switches from a low level to a high level, and the second gate driving signal output terminal OUT2 outputs a high level signal. At the same time, under the bootstrap effect of the twelfth capacitor C12, the voltage at the first pull-up node PU1 is pulled up to a higher state. In this embodiment, assuming that the voltage corresponding to the high level state of the signals provided by the second driving clock signal terminal CLK2 and the third clock signal terminal CKC is VGH, and the voltage corresponding to the low level state is VGL (approximately 0V), then at the display precharge phase t1, the voltage at the first pull-up node PU1 is approximately VGH, while at the initial moment of the display driving phase t2, the voltage at the first pull-up node PU1 can be pulled up to approximately 2VGH. After a period of time, the signal provided by the second drive clock signal terminal CLK2 switches from a high level to a low level, and the second gate drive signal output terminal OUT2 outputs a low level signal. At the same time, under the bootstrap effect of the twelfth capacitor C12, the voltage at the first pull-up node PU1 drops to the level at the initial moment of the display drive stage t2, that is, drops to VGH. At this time, the pull-up node PU is still in a high level state.

[0295] During the display reset phase t3, the signal provided by the display signal input terminal STU1 is at a low level, the signal provided by the sensing signal input terminal STU2 is at a low level, the signal provided by the display reset signal terminal STD is at a high level, the signal provided by the third clock signal terminal CKC is at a low level, the signal provided by the random signal terminal OE is at a low level, the signal provided by the sensing reset signal terminal SRST is at a low level, and the signal provided by the second drive clock signal terminal CLK2 is initially at a low level and then switches to a high level after a period of time.

[0296] At this time, since the signals provided by the random signal terminal OE and the sensing reset signal terminal SRST are both at a low level, the thirty-third transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascade node H is in a floating state, and the voltage of the sensing cascade node H remains at a high level as in the previous stage; since the signal provided by the third clock signal terminal CKC is still at a low level, the thirty-fifth transistor T35 remains in a turned-off state.

[0297] Since the signal provided by the display signal input terminal STU1 is at a low level, the thirty-first transistor T31 is turned off. Since the signal provided by the display reset signal terminal STD is at a high level, the thirty-second transistor T32 is turned on. The fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-up node PU1 through the thirty-second transistor T32, and the voltage at the first pull-up node PU1 is pulled down to a low level.

[0298] Since the voltage of the first pull-up node PU1 is low, transistors T39, T40, and T43 are all off. Because transistor T43 is off, the signal provided by the second drive clock signal terminal CLK2 cannot be written to the second gate drive signal output terminal OUT2. Within the pull-down control circuit, the 37th transistor T37 and the 38th transistor T38 are turned on under the control of the fourth operating voltage VGH provided by the fourth power supply terminal. The fourth operating voltage VGH provided by the fourth power supply terminal is written to the first pull-down node PD1 through the turned-on 38th transistor T38, and the voltage at the first pull-down node PD1 is at a high level. At this time, both the 44th transistor T44 and the 47th transistor T47 are turned on. The fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-up node PU1 through the turned-on 47th transistor T47, thereby reducing noise at the first pull-up node PU1. At the same time, the sixth operating voltage VGL2 provided by the sixth power supply terminal is written to the second gate drive signal output terminal OUT2 through the 44th transistor T44, that is, the second gate drive signal output terminal OUT2 outputs a low-level signal.

[0299] During the sensing precharge phase t4, the signal provided by the display signal input terminal STU1 is at a low level, the signal provided by the sensing signal input terminal STU2 is at a low level, the signal provided by the display reset signal terminal STD is at a low level, the signal provided by the third clock signal terminal CKC is at a high level, the signal provided by the random signal terminal OE is at a low level, the signal provided by the sensing reset signal terminal SRST is at a low level, and the signal provided by the second drive clock signal terminal CLK2 is at a low level.

[0300] At this time, since both the signal provided by the random signal terminal OE and the signal provided by the sensing reset signal terminal SRST are at a low level, the thirty-third transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascade node H is in a floating state, and the voltage of the sensing cascade node H remains at a high level as in the previous stage; correspondingly, the thirty-fourth transistor T34 remains on. At the same time, since the signal provided by the third clock signal terminal CKC is at a high level, the thirty-fifth transistor T35 is turned on. The high-level signal provided by the third clock signal terminal CKC is sequentially written to the first pull-up node PU1 through the turned-on thirty-fourth transistor T34, the sensing precharge node N, and the thirty-fifth transistor T35, and the voltage at the first pull-up node PU1 is at a high level.

[0301] Since the signals provided by the display signal input terminal STU1 and the display reset signal terminal STD are both at a low level, the thirty-first transistor T31 and the thirty-second transistor T32 are both cut off.

[0302] Since the voltage at the first pull-up node PU1 is high, transistors T39, T40, and T43 are all turned on. The fifth operating voltage VGL1 provided by the fifth power supply is written to the first pull-down node PD1 through transistor T39 and to the control electrode of transistor T38 through transistor T40. At this time, transistor T38 is turned off and transistor T37 is equivalent to a resistor. The voltage at the first pull-down node PD1 is low, and transistors T47 and T44 are both turned off. Simultaneously, the low-level signal provided by the second drive clock signal terminal CLK2 is written to the corresponding second gate drive signal output terminal OUT2 through transistor T43, that is, the second gate drive signal output terminal OUT2 outputs a low-level signal.

[0303] Furthermore, since the signal provided by the third clock signal terminal CKC is at a high level, the voltage at the sensing cascade node H is at a high level. Therefore, both the forty-eighth transistor T48 and the forty-ninth transistor T49 are turned on, and the fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-down node PD1, thereby reducing noise in the first pull-down node PD1 to maintain the stability of the voltage at the first pull-down node PD1.

[0304] During the sensing output phase t5, the signal provided by the display signal input terminal STU1 is at a low level, the signal provided by the sensing signal input terminal STU2 is at a low level, the signal provided by the display reset signal terminal STD is at a low level, the signal provided by the third clock signal terminal CKC is at a low level, the signal provided by the random signal terminal OE is at a low level, the signal provided by the sensing reset signal terminal SRST is at a low level, and the signal provided by the second drive clock signal terminal CLK2 is initially at a high level and then at a low level after a period of time.

[0305] At this time, since the signals provided by the random signal terminal OE and the sensing reset signal terminal SRST are both at a low level, the thirty-third transistor T33 and the thirty-sixth transistor T36 are both turned off, the sensing cascade node H is in a floating state, the voltage of the sensing cascade node H remains at a high level as in the previous stage, and the thirty-fourth transistor T34 remains in a conducting state; since the signal provided by the third clock signal terminal CKC is at a low level, the thirty-fifth transistor T35 is turned off, and the signal provided by the third clock signal terminal CKC will not affect the voltage at the first pull-up node PU1.

[0306] Since the signals provided by the display signal input terminal STU1 and the display reset signal terminal STD are both at a low level, the thirty-first transistor T31 and the thirty-second transistor T32 are both cut off. The first pull-up node PU1 is in a floating state and maintains the high level state of the previous stage. At this time, the thirty-ninth transistor T39, the fortieth transistor T40 and the forty-third transistor T43 remain on, the first pull-down node PD1 remains at a low level, and the forty-seventh transistor T47 and the forty-fourth transistor T44 remain off. The signal provided by the second drive clock signal terminal CLK2 is written to the corresponding second gate drive signal output terminal OUT2 through the on-conducting forty-third transistor T43.

[0307] At the initial moment of the sensing output phase t5, the signal provided by the second driving clock signal terminal CLK2 switches from a low level to a high level, and the second gate drive signal output terminal OUT2 outputs a high-level signal. Simultaneously, under the bootstrap effect of the twelfth capacitor C12, the voltage at the first pull-up node PU1 is pulled up to a higher state. In this embodiment, assuming that the voltage corresponding to the high level state of the signals provided by the second driving clock signal terminal CLK2 and the third clock signal terminal CKC is VGH, and the voltage corresponding to the low level state is VGL (approximately 0V), then at the sensing precharge phase t4, the voltage at the first pull-up node PU1 is approximately VGH, while at the initial moment of the sensing drive phase t5, the voltage at the first pull-up node PU1 can be pulled up to approximately 2VGH. After a period of time, the signal provided by the second drive clock signal terminal CLK2 switches from a high level to a low level, and the second gate drive signal output terminal OUT2 outputs a low level signal. At the same time, under the bootstrap effect of the twelfth capacitor C12, the voltage at the first pull-up node PU1 drops to the level at the initial moment of the sensing drive phase t5, that is, drops to VGH. At this time, the first pull-up node PU1 is still in a high level state.

[0308] During the sensing reset phase t6, the signal provided by the display signal input terminal STU1 is at a low level, the signal provided by the sensing signal input terminal STU2 is at a low level, the signal provided by the display reset signal terminal STD is at a low level, the signal provided by the third clock signal terminal CKC is at a low level, the signal provided by the random signal terminal OE is at a high level, the signal provided by the sensing reset signal terminal SRST is at a high level, and the signal provided by the second drive clock signal terminal CLK2 is at a low level.

[0309] Since both the random signal terminal OE and the sensing reset signal terminal SRST are at a high level, transistors T33 (33) and T36 (36) are turned on. The low-level signal provided by the sensing signal input terminal STU2 is written to the sensing cascade node H through transistor T33, resulting in a low-level voltage at sensing cascade node H. Transistor T34 (34) is turned off, thus resetting sensing cascade node H. Since the signal provided by the third clock signal terminal CKC is at a low level, transistor T35 (35) is turned off.

[0310] Since the thirty-sixth transistor T36 is turned on, the fifth operating voltage VGL1 provided by the fifth power supply terminal is written to the first pull-up node PU1 through the thirty-second transistor T32. The voltage at the first pull-up node PU1 is in a low-level state, thereby resetting the first pull-up node PU1.

[0311] Since the signal provided by the display signal input terminal STU1 is at a low level and the signal provided by the display reset signal terminal STD is at a low level, both the thirty-first transistor T31 and the thirty-second transistor T32 are turned off.

[0312] Since the voltage at the first pull-up node PU1 is at a low level, the thirty-ninth transistor T39, the fortieth transistor T40, and the forty-third transistor T43 are all turned off. In the pull-down control circuit, the first working voltage VDD provided by the fourth power supply is written to the first pull-down node PD1 through the thirty-eighth transistor T38, and the voltage at the first pull-down node PD1 is at a high level. At this time, the forty-seventh transistor T47 and the forty-fourth transistor T44 are turned on. The fifth working voltage VGL1 provided by the fifth power supply is written to the first pull-up node PU1 through the forty-seventh transistor T47 to reduce noise in the first pull-up node PU1. The sixth working voltage VGL2 provided by the sixth power supply is written to the second gate drive signal output terminal OUT2 through the forty-fourth transistor T44, that is, the second gate drive signal output terminal OUT2 outputs a low-level signal.

[0313] Therefore, the second shift register can output a high-level (active level) signal during the display driving period and the blank period in a frame, respectively, to meet the driving requirements of the sensing transistor in the corresponding row pixel unit.

[0314] In this embodiment, during the time period between the end of the display reset phase t3 and the start of the sensing precharge phase t4, the voltage at the first pull-up node PU1 needs to be kept at a low level (inactive level). By setting the aforementioned forty-seventh transistor T47, the pull-down control circuit and the forty-seventh transistor T47 can form a positive feedback loop to strengthen the voltage at the first pull-up node PU1. Specifically, when the voltage at the first pull-up node PU1 is at a low level, the pull-down control circuit controls the voltage at the first pull-down node PD1 to be at a high level. At this time, the forty-seventh transistor T47 is turned on, and the fifth operating voltage VGL1 is written to the first pull-up node PU1 through the forty-seventh transistor T47 to strengthen the low-level state of the pull-up node (voltage magnitude is VGL1), thereby achieving the purpose of noise reduction.

[0315] It should be noted that in each stage of the above driving process, the operating state of the forty-first transistor T41 in the gate cascade output circuit 45 is the same as the operating state of the forty-third transistor T43 in the second gate drive output circuit 46 (both are simultaneously turned on or off), and the operating state of the forty-second transistor T42 in the gate cascade output circuit 45 is the same as the operating state of the forty-fourth transistor T44 in the second gate drive output circuit 46 (both are simultaneously turned on or off). The waveform of the signal provided by the cascade clock signal terminal CLKX can be the same as or different from the waveform of the signal provided by the second drive clock signal terminal CLK2.

[0316] Figure 25A This is a timing diagram of the cascaded clock signal terminal, the second drive clock signal terminal, the gate cascaded signal output terminal, and the second gate drive signal output terminal in an embodiment of this disclosure, as shown below. Figure 25A As shown, the waveform of the signal provided by the cascaded clock signal terminal CLKX can be the same as the waveform of the signal provided by the second drive clock signal terminal CLK2. At this time, the waveforms of the signals output by the gate cascaded signal output terminal CR1 and the second gate drive signal output terminal OUT2 are the same.

[0317] Figure 25B This is another timing diagram of the cascaded clock signal terminal, the second drive clock signal terminal, the gate cascaded signal output terminal, and the second gate drive signal output terminal in an embodiment of this disclosure, as shown below. Figure 25B As shown, the waveform of the signal provided by the cascaded clock signal terminal CLKX during the display driving period is the same as that of the signal provided by the second driving clock signal terminal CLK2 during the display driving period. However, the waveform of the signal provided by the cascaded clock signal terminal CLKX during the blank period is different from that of the signal provided by the second driving clock signal terminal CLK2 during the blank period. For example, the start time of the signal provided by the cascaded clock signal terminal CLKX being in an active level state during the blank period is the same as the start time of the signal provided by the second driving clock signal terminal CLK2 being in an active level state, and the duration of the signal provided by the cascaded clock signal terminal CLKX being in an active level state during the blank period can be less than the duration of the signal provided by the second driving clock signal terminal CLK2 being in an active level state during the blank period.

[0318] In practical applications, when the start time of the signal provided by the cascade clock signal terminal CLKX being at an effective level during the blank period is the same as the start time of the signal provided by the second drive clock signal terminal CLK2 being at an effective level during the blank period, the period during which the signal provided by the cascade clock signal terminal CLKX is at an effective level during the blank period will inevitably overlap with the period during which the signal provided by the random signal terminal OE of the second shift register corresponding to the next pixel unit to be externally compensated and sensed will be at an effective level during the blank period (the start time of the signal provided by the second drive clock signal terminal CLK2 being at an effective level during the blank period must be within the period during which the signal provided by the random signal terminal OE of the second shift register corresponding to the next pixel unit to be externally compensated and sensed will be at an effective level during the blank period). Therefore, the sensing cascade signal output by the second shift register of this stage and in an effective level state can be written to the sensing cascade node H in the next stage second shift register during the aforementioned overlapping period to ensure sensing cascade.

[0319] It should be noted that those skilled in the art should know that in some embodiments, the second shift register may optionally exclude the first noise reduction circuit, the second noise reduction circuit, and / or the third noise reduction circuit.

[0320] In this embodiment of the disclosure, taking the m-th row of pixel units as an example of the pixel unit row requiring external compensation sensing, the second gate drive signal output terminal OUT2 of the second shift register corresponding to the m-th row of pixel units will output an effective level signal to the second gate line configured for the m-th row of pixel units during the blank period. To ensure the smooth progress of the external compensation sensing process of the m-th row of pixel units, it is necessary to make the light emission control drive signal output terminal of the first shift register corresponding to the m-th row of pixel units output an effective level signal to the light emission control signal line configured for the m-th row of pixel units. Based on this principle, in this embodiment, the second gate drive signal output terminal OUT2 of the second shift register corresponding to the m-th row pixel unit can be used as the forced output control terminal of the first shift register corresponding to the m-th row pixel unit. This ensures that the forced output control terminal of the first shift register corresponding to the m-th row pixel unit always receives a valid level signal during the external compensation sensing process of the m-th row pixel unit, and the light emission control drive signal output terminal of the first shift register corresponding to the m-th row pixel unit always outputs a valid level signal during the external compensation sensing process of the m-th row pixel unit, thereby ensuring the normal operation of the external compensation sensing process of the m-th row pixel unit. In other words, within the first gate drive circuit, the forced output control terminal connected to any first shift register is the second gate drive signal output terminal OUT2 configured in the second shift register of the same row pixel unit as the first shift register.

[0321] Similarly, when the period during which the signal provided by the cascaded clock signal terminal CLKX is at an effective level completely covers the period during which the signal provided by the second drive clock signal terminal CLK2 is at an effective level during the blank period, the gate cascaded signal output terminal CR1 of the second shift register corresponding to the m-th row pixel unit can be used as the forced output control terminal CSD of the first shift register corresponding to the m-th row pixel unit. In other words, within the first gate drive circuit, the forced output control terminal connected to any first shift register is the gate cascaded signal output terminal CR1 configured for the second shift register of the same row pixel unit as the first shift register.

[0322] Furthermore, when the forced output control terminal includes a first control terminal CP1 and a second control terminal CP2, the first control terminal CP1 configured in the first shift register corresponding to the m-th row pixel unit can be the sensing cascade node H inside the second shift register corresponding to the m-th row pixel unit, and the second control terminal CP2 configured in the first shift register corresponding to the m-th row pixel unit can be the pre-configured fourth clock signal terminal CP2.

[0323] Figure 25C This is a timing diagram of the sensing cascade node, the fourth clock signal terminal, and the second gate drive signal output terminal in an embodiment of this disclosure, as follows: Figure 25C As shown, in one optional implementation, the signal provided by the fourth clock signal terminal CKD is at an effective level during the blank period and at an ineffective level during other periods. The overlapping period between the effective level period of the signal provided by the fourth clock signal terminal CKD and the effective level period of the sensing cascade node H inside the second shift register corresponding to the m-th row pixel unit completely covers the period during which the second gate drive signal output terminal OUT2 of the second shift register corresponding to the m-th row pixel unit outputs an effective level signal during the blank period. This ensures that during the period when the second gate drive signal output terminal OUT2 of the second shift register corresponding to the m-th row pixel unit outputs an effective level signal during the blank period, the light emission control drive signal output terminal of the first shift register corresponding to the m-th row pixel unit will continuously output an effective level signal. In other words, within the first gate drive circuit, the first control terminal CP1 and the second control terminal CP2 connected to any one of the first shift registers are respectively the sensing cascade node H inside the second shift register corresponding to the same row pixel unit as the first shift register and the pre-configured fourth clock signal terminal CKD. Of course, the duration of the fourth clock signal terminal being in an active level state can be less than the duration of the blank period; for example, the duration of the fourth clock signal terminal being in an active level state is only the period corresponding to the sensing output stage t5, or the duration of the fourth clock signal terminal being in an active level state is only the period corresponding to the sensing output stage t5 plus at least a portion of the period in the sensing precharge stage t4.

[0324] Figure 26 This is a schematic diagram of another circuit structure of the second shift register provided in the embodiments of this disclosure, as shown below. Figure 26 As shown, Figure 26 The second shift register shown also includes a first gate drive output circuit 47; wherein the first gate drive output circuit 47 is connected to a first pull-up node PU1, a first pull-down node PD1, a first gate drive signal output terminal OUT1, a first drive clock signal terminal CLK1 and a sixth power supply terminal. The first gate drive output circuit 47 is configured to write the signal provided by the first drive clock signal terminal CLK1 to the first gate drive signal output terminal OUT1 in response to the control of the voltage at the first pull-up node PU1, and to write the sixth operating voltage provided by the sixth power supply terminal to the first gate drive signal output terminal OUT1 in response to the control of the voltage at the first pull-down node PD1.

[0325] In this embodiment, the second shift register can not only provide a gate drive signal to the second gate line configured in the corresponding row of pixel units, but also simultaneously provide a gate drive signal to the first gate line configured in the corresponding row of pixel units. In other words, the second gate drive circuit can be used to drive both the first and second gate lines simultaneously.

[0326] In some embodiments, the first gate drive output circuit 47 includes a forty-fifth transistor T45 and a forty-sixth transistor T46.

[0327] Among them, the control electrode of the forty-fifth transistor T45 is connected to the first pull-up node PU1, the first electrode of the forty-fifth transistor T45 is connected to the first drive clock signal terminal CLK1, and the second electrode of the forty-fifth transistor T45 is connected to the first gate drive signal output terminal OUT1.

[0328] The control electrode of the forty-sixth transistor T46 is connected to the first pull-down node PD1, the first electrode of the forty-sixth transistor T46 is connected to the sixth power supply terminal, and the second electrode of the forty-sixth transistor T46 is connected to the first gate drive signal output terminal OUT1.

[0329] In some embodiments, the second shift register further includes a thirteenth capacitor C13, the first end of which is connected to the first pull-up node PU1, and the second end of which is connected to the first gate drive signal output terminal OUT1.

[0330] Figure 26 The driving process of the second shift register shown is... Figure 23 The driving process of the second shift register shown is the same, and the specific process will not be repeated here. It should be noted that at each stage of the driving process, the operating state of the forty-fifth transistor T45 in the first gate drive output circuit is the same as the operating state of the forty-third transistor T43 in the second gate drive output circuit 46 (both are simultaneously turned on or off), and the operating state of the forty-sixth transistor T46 in the first gate drive output circuit is the same as the operating state of the forty-fourth transistor T44 in the second gate drive output circuit 46 (both are simultaneously turned on or off).

[0331] Figure 27 This is a timing diagram of the first driving clock signal terminal, the second driving clock signal terminal, the first gate driving signal output terminal, and the second gate driving signal output terminal in an embodiment of this disclosure, as shown below. Figure 27 As shown, since the gate drive signals required for the first and second gate lines configured in the same row of pixel units are different, the signals provided by the first driving clock signal terminal CLK1 and the second driving clock signal terminal CLK2 are different. Specifically, the waveforms of the signals provided by the first driving clock signal terminal CLK1 and the second driving clock signal terminal CLK2 are the same during the display driving period, but the waveforms of the signals provided by the first driving clock signal terminal CLK1 and the second driving clock signal terminal CLK2 at the active level during the blank period are different.

[0332] Figure 28 This is a schematic diagram of another circuit structure of the second shift register provided in the embodiments of this disclosure, as shown below. Figure 28 As shown, in some embodiments, the second shift register is configured with a fourth gate drive signal output terminal OUT4, which is connected to the corresponding second gate line. That is, one second shift register can provide a gate drive signal to the second gate line configured for two rows of pixel units.

[0333] The second shift register also includes a second display precharge reset circuit 51, a second sensing precharge reset circuit 53, a second pull-down control circuit 54, and a fourth gate drive output circuit 56; the second display precharge reset circuit 51, the second sensing precharge reset circuit 53, the second pull-down control circuit 54, and the fourth gate drive output circuit 56 are connected to the second pull-up node PU2, and the second pull-down control circuit 54 and the fourth gate drive output circuit 56 are connected to the second pull-down node PD2.

[0334] The second display precharge reset circuit 51 is connected to the display signal input terminal STU1, the display reset signal terminal STD, and the fifth power supply terminal. The second display precharge reset circuit 51 is configured to write the signal provided by the display signal input terminal STU1 to the second pull-up node PU2 in response to the control of the signal provided by the display signal input terminal STU1, and to write the fifth operating voltage provided by the fifth power supply terminal to the second pull-down node PD2 in response to the control of the signal provided by the display reset signal terminal STD.

[0335] The second sensing precharge reset circuit 53 is connected to the sensing precharge signal terminal, the third clock signal terminal CKC, the sensing reset signal terminal SRST, and the fifth power supply terminal. The second sensing precharge reset circuit 53 is configured to write the voltage at the sensing precharge node N to the second pull-up node PU2 in response to the control of the signal provided by the third clock signal terminal CKC, and to write the fifth operating voltage provided by the fifth power supply terminal to the second pull-up node PU2 in response to the control of the signal provided by the sensing reset signal terminal SRST.

[0336] The second pull-down control circuit 54 is connected to the seventh power supply terminal and the fifth power supply terminal. The second pull-down control circuit 54 is configured to write a voltage that is inversely phase to the voltage at the second pull-down node PD2.

[0337] The fourth gate drive output circuit 56 is connected to the fourth drive clock signal terminal CLK4 and the sixth power supply terminal. The fourth gate drive output circuit 56 is configured to write the signal provided by the fourth drive clock signal terminal CLK4 to the fourth gate drive signal output terminal OUT4 in response to the control of the voltage at the second pull-up node PU2, and to write the sixth operating voltage provided by the sixth power supply terminal to the fourth gate drive signal output terminal OUT4 in response to the control of the voltage at the second pull-down node PD2.

[0338] In some embodiments, the second shift register further includes a first gate drive output circuit 47 and a third gate drive output circuit 57. A detailed description of the first gate drive output circuit 47 can be found in the previous embodiments and will not be repeated here. The third gate drive circuit 57 will be described in detail below.

[0339] The third gate drive output circuit 57 is connected to the second pull-up node PU2, the second pull-down node PD2, the third gate drive signal output terminal OUT3, the third drive clock signal terminal CLK3, and the sixth power supply terminal. The third gate drive output circuit 57 is configured to write the signal provided by the third drive clock signal terminal CLK3 to the third gate drive signal output terminal OUT3 in response to the voltage control at the second pull-up node PU2, and to write the sixth operating voltage provided by the sixth power supply terminal to the third gate drive signal output terminal OUT3 in response to the voltage control at the second pull-down node PD2. The first gate drive signal output terminal OUT1 and the third gate drive signal output terminal OUT3 are respectively connected to the corresponding first gate lines.

[0340] In this embodiment of the disclosure, each stage of the second shift register in the second gate driving circuit can correspond to two rows of pixel units. The second gate driving output circuit 46 and the fourth gate driving output circuit 56 can respectively provide gate driving signals to the second gate lines configured in the corresponding row of pixel units, and the first gate driving output circuit 47 and the third gate driving output circuit 57 can respectively provide gate driving signals to the first gate lines configured in the corresponding row of pixel units.

[0341] In some embodiments, the second display precharge reset circuit 51 includes a fifty-first transistor T51 and a fifty-second transistor T52.

[0342] Among them, the control electrode of the fifty-first transistor T51 is connected to the display signal input terminal STU1, the first electrode of the fifty-first transistor T51 is connected to the control electrode of the fifty-first transistor T51, and the second electrode of the fifty-first transistor T51 is connected to the second pull-up node PU2.

[0343] The control terminal of the 52nd transistor T52 is connected to the display reset signal terminal STD, the first terminal of the 52nd transistor T52 is connected to the second pull-up node PU2, and the second terminal of the 52nd transistor T52 is connected to the fifth power supply terminal.

[0344] In some embodiments, the sensing precharge reset circuit includes a fifty-fifth transistor T55 and a fifty-sixth transistor T56.

[0345] Among them, the control terminal of the 55th transistor T55 is connected to the third clock signal terminal CKC, the first terminal of the 55th transistor T55 is connected to the sensing precharge node N, and the second terminal of the 55th transistor T55 is connected to the second pull-up node PU2.

[0346] The control terminal of the 56th transistor T56 is connected to the sense reset signal terminal SRST, the first terminal of the 56th transistor T56 is connected to the second pull-up node PU2, and the second terminal of the 56th transistor T56 is connected to the fifth power supply terminal.

[0347] In some embodiments, the second pull-down control circuit 54 includes a fifty-seventh transistor T57, a fifty-eighth transistor T58, a fifty-ninth transistor T59, and a sixtieth transistor T60.

[0348] The control electrode of the 57th transistor T57 is connected to the 7th power supply terminal, the first electrode of the 57th transistor T57 is connected to the control electrode of the 57th transistor T57, and the second electrode of the 57th transistor T57 is connected to the control electrode of the 58th transistor T58.

[0349] The control terminal of the 58th transistor T58 is connected to the first terminal of the 60th transistor T60. The first terminal of the 58th transistor T58 is connected to the seventh power supply terminal. The second terminal of the 58th transistor T58 is connected to the second pull-down node PD2.

[0350] The control electrode of the 59th transistor T59 is connected to the second pull-up node PU2, the first electrode of the 59th transistor T59 is connected to the second pull-down node PD2, and the second electrode of the 59th transistor T59 is connected to the fifth power supply terminal.

[0351] The control electrode of the 60th transistor T60 is connected to the second pull-up node PU2, and the second electrode of the 60th transistor T60 is connected to the fifth power supply terminal.

[0352] In some embodiments, the third gate drive output circuit 57 includes a sixty-fifth transistor T65 and a sixty-sixth transistor T66.

[0353] Among them, the control electrode of the sixty-fifth transistor T65 is connected to the first pull-up node PU1, the first electrode of the sixty-fifth transistor T65 is connected to the third drive clock signal terminal CLK3, and the second electrode of the sixty-fifth transistor T65 is connected to the third gate drive signal output terminal OUT3.

[0354] The control electrode of the sixty-sixth transistor T66 is connected to the second pull-down node PD2, the first electrode of the sixty-sixth transistor T66 is connected to the sixth power supply terminal, and the second electrode of the sixty-sixth transistor T66 is connected to the third gate drive signal output terminal OUT3.

[0355] In some embodiments, the fourth gate drive output circuit 56 includes a sixty-third transistor T63 and a sixty-fourth transistor T64.

[0356] Among them, the control electrode of the sixty-third transistor T63 is connected to the second pull-up node PU2, the first electrode of the sixty-third transistor T63 is connected to the fourth drive clock signal terminal CLK4, and the second electrode of the sixty-third transistor T63 is connected to the fourth gate drive signal output terminal OUT4.

[0357] The control electrode of the sixty-fourth transistor T64 is connected to the second pull-down node PD2, the first electrode of the sixty-fourth transistor T64 is connected to the sixth power supply terminal, and the second electrode of the sixty-fourth transistor T64 is connected to the fourth gate drive signal output terminal OUT4.

[0358] In some embodiments, the second shift register further includes a fourteenth capacitor C14, the first end of which is connected to the second pull-up node PU2, and the second end of which is connected to the fourth gate drive signal output terminal OUT4.

[0359] In some embodiments, the second shift register further includes a fifteenth capacitor C15, the first end of which is connected to the second pull-up node PU2, and the second end of which is connected to the third gate drive signal output terminal OUT3.

[0360] In some embodiments, the second shift register further includes a fourth noise reduction circuit 58. The fourth noise reduction circuit 58 is connected to the second pull-up node PU2, the second pull-down node PD2, and the fifth power supply terminal. The fourth noise reduction circuit 58 is configured to write a fifth operating voltage provided by the fifth power supply terminal to the second pull-up node PU2 in response to voltage control at the second pull-down node PD2. In this embodiment, the fourth noise reduction circuit 58 can reduce noise from the second pull-up node PU2 to maintain voltage stability at the second pull-up node PU2.

[0361] Optionally, the fourth noise reduction circuit 58 includes a sixty-seventh transistor T67; the control electrode of the sixty-seventh transistor T67 is connected to the second pull-down node PD2, the first electrode of the sixty-seventh transistor T67 is connected to the fifth power supply terminal, and the second electrode of the sixty-seventh transistor T67 is connected to the second pull-up node PU2.

[0362] In some embodiments, the second shift register further includes a fifth noise reduction circuit 59. The fifth noise reduction circuit 59 is connected to the second pull-down node PD2, the sensing cascade node H, the third clock signal terminal CKC, and a fifth power supply terminal. The fifth noise reduction circuit 59 is configured to write a fifth operating voltage provided by the fifth power supply terminal to the second pull-down node PD2 in response to control of the voltage at the sensing cascade node H and the signal provided by the third clock signal terminal CKC. In this embodiment, the fifth noise reduction circuit 59 can reduce noise from the second pull-down node PD2 to maintain the stability of the voltage at the second pull-down node PD2.

[0363] Optionally, the fifth noise reduction circuit 59 includes a sixty-eighth transistor T68 and a sixty-ninth transistor T69. The control electrode of the sixty-eighth transistor T68 is connected to the third clock signal terminal CKC, the first electrode of the sixty-eighth transistor T68 is connected to the second pull-down node PD2, and the second electrode of the sixty-eighth transistor T68 is connected to the first electrode of the sixty-ninth transistor T69. The control electrode of the sixty-ninth transistor T69 is connected to the sensing cascade node H, and the second electrode of the sixty-ninth transistor T69 is connected to the fifth power supply terminal.

[0364] In some embodiments, the second shift register further includes a sixth noise reduction circuit 60, which is connected to the display signal input terminal STU1, the second pull-down node PD2, and the fifth power supply terminal. The sixth noise reduction circuit 60 is configured to write a fifth operating voltage provided by the fifth power supply terminal to the second pull-down node PD2 in response to the control of the signal provided by the display signal input terminal STU1. In this embodiment, the sixth noise reduction circuit 60 can reduce noise from the second pull-down node PD2 to maintain the stability of the voltage at the second pull-down node PD2.

[0365] Optionally, the sixth noise reduction circuit 60 includes: a seventieth transistor T70; the control electrode of the seventieth transistor T70 is connected to the display signal input terminal STU1, the first electrode of the seventieth transistor T70 is connected to the fifth power supply terminal, and the second electrode of the fiftieth transistor T50 is connected to the second pull-down node PD2.

[0366] Figure 28 The driving timing of the second shift register shown can be found in [reference needed]. Figure 24 As shown in the diagram, the specific process will not be elaborated here. Specifically, in each stage, the voltage at the first pull-up node PU1 remains consistent with the voltage at the second pull-up node PU2, and the voltage at the first pull-down node PD1 remains consistent with the voltage at the second pull-down node PD2.

[0367] Figure 29 This is a schematic diagram of another circuit structure of the second shift register provided in the embodiments of this disclosure, as shown below. Figure 29 As shown, the second shift register also includes a blank valid output circuit 61.

[0368] The blank valid output circuit 61 is connected to the second pull-up node PU2, the second pull-down node PD2, the blank valid clock signal terminal CLKY, the blank valid signal output terminal CR2, and the sixth power supply terminal. The blank valid output circuit 61 is configured to write the signal provided by the blank valid clock signal terminal CLKY to the blank valid signal output terminal CR2 in response to the voltage control at the second pull-up node PU2, and to write the sixth operating voltage provided by the sixth power supply terminal to the blank valid signal output terminal CR2 in response to the voltage control at the second pull-down node PD2.

[0369] In some embodiments, the blank valid output circuit 61 includes a sixty-first transistor T61 and a sixty-second transistor T62.

[0370] Among them, the control electrode of the sixty-first transistor T61 is connected to the second pull-up node PU2, the first electrode of the sixty-first transistor T61 is connected to the blank valid clock signal terminal CLKY, and the second electrode of the sixty-first transistor T61 is connected to the blank valid signal output terminal CR2.

[0371] The control electrode of the sixty-second transistor T62 is connected to the second pull-down node PD2, the first electrode of the sixty-second transistor T62 is connected to the fifth power supply terminal, and the second electrode of the sixty-second transistor T62 is connected to the blank valid signal output terminal CR2.

[0372] Figure 29 The driving timing of the second shift register shown can be found in [reference needed]. Figure 24 As shown in the diagram, the specific process will not be repeated here. Specifically, in each stage, the operating state of the sixty-first transistor T61 in the blank valid output circuit 61 is the same as the operating state of the forty-third transistor T43 in the second gate drive output circuit 46 (both are simultaneously turned on or off), and the operating state of the sixty-second transistor T62 in the blank valid output circuit 61 is the same as the operating state of the forty-fourth transistor T44 in the second gate drive output circuit 46 (both are simultaneously turned on or off).

[0373] In some embodiments, the blank valid clock signal terminal CLKY provides an invalid level signal during the display driving period and an valid level signal during the blank period. In other embodiments, the blank valid clock signal terminal provides an invalid level signal during the display driving period and provides a signal with the same waveform as the signal provided by the second driving clock signal terminal CLK2 during the blank period.

[0374] Within the first gate drive circuit 200, any forced output control terminal CSD connected to any of the first shift registers includes: a blank valid signal output terminal CR2 configured in the second shift register corresponding to the same row of pixel units as the first shift register. For details on the underlying principles, please refer to the preceding content; they will not be repeated here.

[0375] Since the voltages of the first pull-up node PU1 and the second pull-up node PU2 are always consistent, and the voltages of the first pull-down node PD1 and the second pull-down node PD2 are always consistent, the blank valid output circuit 61 can also be configured to connect to the first pull-up node PU1 and the second pull-up node. In this case, the blank valid output circuit 61 is configured to write the signal provided by the blank valid clock signal terminal to the blank valid signal output terminal in response to the voltage control at the first pull-up node PU1, and to write the sixth operating voltage provided by the sixth power supply terminal to the blank valid signal output terminal CR1 in response to the voltage control at the first pull-down node PD1. No corresponding diagram is provided for this situation.

[0376] Figure 30 This is a schematic diagram of a circuit structure in an embodiment of the present disclosure where two pixel units located in adjacent rows share the same light-emitting control transistor, as shown below. Figure 30 As shown, in this embodiment, each pixel unit may include an independent light-emitting control transistor (ETFT), or two pixel units in adjacent rows may share the same ETFT. By sharing the ETFT, the number of transistors in the display area can be effectively reduced, and the number of first shift registers within the first gate driving circuit 200 can also be effectively reduced. Specifically, compared to the scheme where each pixel unit may include an independent ETFT, sharing the same ETFT between two pixel units in adjacent rows halves the number of first shift registers within the first gate driving circuit 200.

[0377] Of course, the pixel unit in this embodiment can also adopt other circuit structures. Specific examples will not be listed here.

[0378] The display device provided in this disclosure can be any product or component with display function, such as a flexible wearable device, mobile phone, tablet computer, television set, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0379] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.< / m> < / m>

Claims

1. A shift register, characterized by, The application relates to a light-emitting driving circuit, which comprises the following parts: a voltage regulating circuit connected with a light-emitting signal input end, a first clock signal end, a second clock signal end, a first node and a second node, and configured to adjust the voltage at the first node and the second node in response to the signals provided by the light-emitting signal input end, the first clock signal end and the second clock signal end; a light-emitting cascade output circuit connected with a first power supply end, a second power supply end, a light-emitting cascade signal output end, the first node and the second node, and configured to write the second working voltage provided by the second power supply end into the light-emitting cascade signal output end in response to the voltage at the first node, and write the first working voltage provided by the first power supply end into the light-emitting cascade signal output end in response to the voltage at the second node; a first light-emitting driving output circuit connected with the first power supply end, the second power supply end, a light-emitting control driving signal output end, the second node and a sixth node, and configured to write the second working voltage provided by the second power supply end into the light-emitting control driving signal output end in response to the voltage at the sixth node, and write the first working voltage provided by the first power supply end into the light-emitting control driving signal output end in response to the voltage at the second node; a second light-emitting driving output circuit connected with the first power supply end, the light-emitting control driving signal output end and a forced output control end, and configured to write the first working voltage provided by the first power supply end into the light-emitting control driving signal output end in response to the signal provided by the forced output control end; a node control circuit between the sixth node and the first node, and connected with the first node through the node control circuit; the node control circuit is also connected with the second power supply end and the forced output control end, and is configured to disconnect the sixth node from the first node and write the second working voltage provided by the second power supply end into the sixth node in response to the signal provided by the forced output control end.

2. The shift register of claim 1, wherein, The node control circuit comprises a first writing sub-circuit, a second writing sub-circuit, a twenty-fourth transistor and a twenty-fifth transistor; the first writing sub-circuit is connected with the second power supply end, the forced output control end and the control electrode of the twenty-fourth transistor, and is configured to write the second working voltage provided by the second power supply end into the control electrode of the twenty-fourth transistor in response to the signal provided by the forced output control end; the first writing sub-circuit comprises a twenty-sixth transistor; the second writing sub-circuit is connected with the second power supply end, the forced output control end and the sixth node, and is configured to write the second working voltage provided by the second power supply end into the sixth node in response to the signal provided by the forced output control end; the first electrode of the twenty-fourth transistor is connected with the first node, and the second electrode of the twenty-fourth transistor is connected with the sixth node. A control electrode of the twenty-fifth transistor is connected with the first power supply end or the second clock signal end, a first electrode of the twenty-fifth transistor is connected with the control electrode of the twenty-fifth transistor, and a second electrode of the twenty-fifth transistor is connected with a second electrode of the twenty-sixth transistor.

3. The shift register of claim 2, wherein, The second write sub-circuit comprises a twenty-seventh transistor; A control electrode of the twenty-sixth transistor is connected with the forced output control end, a first electrode of the twenty-sixth transistor is connected with the second power supply end, and a second electrode of the twenty-sixth transistor is connected with a control electrode of the twenty-fourth transistor. A control electrode of the twenty-seventh transistor is connected with the forced output control end, a first electrode of the twenty-seventh transistor is connected with the second power supply end, and a second electrode of the twenty-seventh transistor is connected with the sixth node.

4. The shift register of claim 2, wherein, The forced output control end comprises a first control end and a second control end; The first write sub-circuit comprises two twenty-sixth transistors connected in series between the second power supply end and the control electrode of the twenty-fourth transistor, and the second write sub-circuit comprises two twenty-seventh transistors connected in series between the second power supply end and the sixth node; A control electrode of one of the two twenty-sixth transistors is connected with the first control end, and a control electrode of the other of the two twenty-sixth transistors is connected with the second control end. A control electrode of one of the two twenty-seventh transistors is connected with the first control end, and a control electrode of the other of the two twenty-seventh transistors is connected with the second control end.

5. The shift register of claim 1, wherein, Further comprising a twenty-eighth transistor; A control electrode of the twenty-eighth transistor is connected with the second node, a first electrode of the twenty-eighth transistor is connected with the second power supply end, and a second electrode of the twenty-eighth transistor is connected with the sixth node.

6. The shift register of claim 1, wherein, The second light-emitting driving output circuit comprises a twenty-third transistor; A control electrode of the twenty-third transistor is connected with the forced output control end, a first electrode of the twenty-third transistor is connected with the first power supply end, and a second electrode of the twenty-third transistor is connected with the light-emitting control driving signal output end.

7. The shift register of claim 1, wherein, The forced output control end comprises a first control end and a second control end; The second light-emitting driving output circuit comprises two twenty-third transistors connected in series between the first power supply end and the light-emitting control driving signal output end, A control electrode of one of the two twenty-third transistors is connected with the first control end, and a control electrode of the other of the two twenty-third transistors is connected with the second control end.

8. The shift register of claim 1, wherein, The voltage regulating circuit comprises: A first input circuit, connected with a light-emitting signal input end, a first clock signal end and the second node, configured to write a signal provided by the light-emitting signal input end to the second node in response to a signal provided by the first clock signal end; The second input circuit is connected with the first clock signal end, the first power supply end and the second node, and is configured to write the first working voltage provided by the first power supply end to the third node in response to the control of the signal provided by the first clock signal end, and write the signal provided by the first clock signal end to the third node in response to the control of the voltage at the second node; The first voltage control circuit is connected with the second clock signal end, the second power supply end, the first node, the second node and the third node, and is configured to write the signal provided by the second clock signal end to the first node in response to the control of the voltage at the third node and the signal provided by the second clock signal end, and write the second working voltage provided by the second power supply end to the first node in response to the control of the voltage at the second node; The second voltage control circuit is connected with the second clock signal end and the second power supply end, and is configured to write the second working voltage provided by the second power supply end to the second node in response to the control of the voltage at the third node and the signal provided by the second clock signal end.

9. The shift register of claim 8, wherein, The first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor, the second voltage control circuit includes a seventh transistor and an eighth transistor, the light-emitting cascade output circuit includes a ninth transistor and a tenth transistor, and the first light-emitting drive output circuit includes a twenty-first transistor and a twenty-second transistor; The control electrode of the first transistor is connected with the first clock signal end, the first electrode of the first transistor is connected with the light-emitting signal input end, and the second electrode of the first transistor is connected with the second node; The control electrode of the second transistor is connected with the first clock signal end, the first electrode of the second transistor is connected with the second power supply end, and the second electrode of the second transistor is connected with the third node; The control electrode of the third transistor is connected with the second node, the first electrode of the third transistor is connected with the third node, and the second electrode of the third transistor is connected with the first clock signal end; The control electrode of the fourth transistor is connected with the third node, the first electrode of the fourth transistor is connected with the second clock signal end, and the second electrode of the fourth transistor is connected with the fourth node; The control electrode of the fifth transistor is connected with the second clock signal end, the first electrode of the fifth transistor is connected with the fourth node, and the second electrode of the fifth transistor is connected with the first node; The control electrode of the sixth transistor is connected with the second node, the first electrode of the sixth transistor is connected with the first node, and the second electrode of the sixth transistor is connected with the second power supply end; The first end of the third capacitor is connected with the third node, and the second end of the third capacitor is connected with the fourth node; The control electrode of the seventh transistor is connected with the third node, the first electrode of the seventh transistor is connected with the second power supply end, and the second electrode of the seventh transistor is connected with the first electrode of the eighth transistor. The control electrode of the eighth transistor is connected with the second clock signal end, and the second electrode of the eighth transistor is connected with the second node; The control electrode of the ninth transistor is connected with the first node, the first electrode of the ninth transistor is connected with the second power supply end, and the second electrode of the ninth transistor is connected with the light-emitting cascade signal output end; The control electrode of the tenth transistor is connected with the second node, the first electrode of the tenth transistor is connected with the light-emitting cascade signal output end, and the second electrode of the tenth transistor is connected with the first power supply end; The control electrode of the twenty-first transistor is connected with the sixth node, the first electrode of the twenty-first transistor is connected with the second power supply end, and the second electrode of the twenty-first transistor is connected with the light-emitting control driving signal output end; The control electrode of the twenty-second transistor is connected with the second node, the first electrode of the twenty-second transistor is connected with the light-emitting control driving signal output end, and the second electrode of the twenty-second transistor is connected with the first power supply end.

10. The shift register of claim 8, wherein, The voltage regulating circuit further comprises a first leakage prevention circuit, the first input circuit, the second input circuit and the second node control voltage are connected to a fifth node, the first leakage prevention circuit is located between the fifth node and the second node, and the first input circuit, the second input circuit and the second voltage control circuit are connected with the second node through the first leakage prevention circuit; The first leakage prevention circuit is further connected with the first power supply end and a third power supply end, and the first leakage prevention circuit is configured to write a third working voltage provided by the third power supply end to a first leakage prevention node under the control of the voltage at the second node, the first leakage prevention node being located between the second node and the fifth node; And / or, the voltage regulating circuit further comprises a second leakage prevention circuit, the output circuit is connected with the second power supply end through the second leakage prevention circuit, and the light-emitting cascade output circuit is connected with the second leakage prevention circuit to a second leakage prevention node; The second leakage prevention circuit is further connected with the first node, the first power supply end and the second power supply end, and the second leakage prevention circuit is further connected with the light-emitting cascade signal output end or the light-emitting control driving signal output end, and the second leakage prevention circuit is configured to write a first working voltage provided by the first power supply end to a second leakage prevention node in response to the control of the voltage at the light-emitting cascade signal output end or the light-emitting control driving signal output end; And / or, the voltage regulating circuit further comprises a light-emitting global reset circuit, the light-emitting global reset circuit is connected with a light-emitting global reset signal end, the first power supply end and the second node, and is configured to write a first working voltage provided by the first power supply end to the second node in response to the control of a signal provided by the light-emitting global reset signal end.

11. The shift register of claim 10, wherein, The first leakage prevention circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor; The control electrode of the eleventh transistor is connected with the first power supply end, the first electrode of the eleventh transistor is connected with the fifth node, and the second electrode of the eleventh transistor is connected with the first leakage prevention node; The control electrode of the twelfth transistor is connected with the first power supply end, the first electrode of the twelfth transistor is connected with the first anti-leakage node, and the second electrode of the twelfth transistor is connected with the second node; The control electrode of the thirteenth transistor is connected with the second node, the first electrode of the thirteenth transistor is connected with the third power supply end, and the second electrode of the thirteenth transistor is connected with the first anti-leakage node; The second anti-leakage circuit comprises a fourteenth transistor and a fifteenth transistor; The control electrode of the fourteenth transistor is connected with the first node, the first electrode of the fourteenth transistor is connected with the second power supply end, and the second electrode of the fourteenth transistor is connected with the second anti-leakage node; The control electrode of the fifteenth transistor is connected with the light-emitting cascade signal output end or the light-emitting control driving signal output end, the first electrode of the fifteenth transistor is connected with the first power supply end, and the second electrode of the fifteenth transistor is connected with the second anti-leakage node; The light-emitting global reset circuit comprises a sixteenth transistor; The control electrode of the sixteenth transistor is connected with the light-emitting global reset signal end, the first electrode of the sixteenth transistor is connected with the second node, and the second electrode of the sixteenth transistor is connected with the first power supply end.

12. A gate drive circuit, characterized by Comprise: A plurality of first shift registers in cascade, wherein each of the first shift registers is the shift register according to any one of claims 1 to 11; The signal input end of the first shift register at the first stage is connected with a light-emitting start signal line, and the first shift register at each stage other than the first stage is connected with the light-emitting cascade signal output end of the first shift register at the previous stage; The light-emitting control driving signal output end of each of the first shift registers is connected with a corresponding light-emitting control signal line.

13. A display device comprising: Comprise: A display area and a peripheral area located at the periphery of the display area, wherein the display area comprises a plurality of pixel units arranged in an array, each row of pixel units is configured with a corresponding light-emitting control signal line, and the light-emitting control signal line is connected with the control electrode of a light-emitting control transistor in the corresponding pixel unit; The peripheral area comprises a first gate drive circuit, and the first gate drive circuit is the gate drive circuit according to claim 12.

14. The display device of claim 13, wherein, Each row of pixel units is further configured with a corresponding second gate line, and the second gate line is connected with the control electrode of a sensing transistor in the corresponding pixel unit; The peripheral area further comprises a second gate drive circuit, and the second gate drive circuit comprises: a plurality of second shift registers in cascade, wherein each of the second shift registers is configured with a second gate driving signal output end, and the second gate driving signal output end is connected with the corresponding second gate line; The second shift register comprises a first display pre-charge reset circuit, a sensing cascade circuit, a first sensing pre-charge reset circuit, a first pull-down control circuit, a gate cascade output circuit and a second gate driving output circuit; The sensing cascade circuit and the first sensing pre-charge reset circuit are connected to a sensing cascade node, the first display pre-charge reset circuit, the first sensing pre-charge reset circuit, the first pull-down control circuit, the gate cascade output circuit and the second gate drive output circuit are connected to a first pull-up node, the first pull-down control circuit, the gate cascade output circuit and the second gate drive output circuit are connected to a first pull-down node; The first display pre-charge reset circuit is connected with a display signal input end, a display reset signal end and a fifth power supply end, and is configured to write a signal provided by the display signal input end into the first pull-up node under the control of the signal provided by the display signal input end, and write a fifth working voltage provided by the fifth power supply end into the first pull-down node under the control of a signal provided by the display reset signal end; The sensing cascade circuit is connected with a sensing signal input end and a random signal end, and is configured to write a signal provided by the sensing signal input end into the sensing cascade node under the control of a signal provided by the random signal end; The first sensing pre-charge reset circuit is connected with a third clock signal end, a sensing reset signal end and a fifth power supply end, and is configured to write a signal provided by the third clock signal end into a sensing pre-charge node under the control of a voltage at the sensing cascade node, write a voltage at the sensing pre-charge node into the first pull-up node under the control of a signal provided by the third clock signal end, and write a fifth working voltage provided by the fifth power supply end into the first pull-up node under the control of a signal provided by the sensing reset signal end; The first pull-down control circuit is connected with a fourth power supply end and a fifth power supply end, and is configured to write a voltage opposite to a voltage at the first pull-up node into the first pull-down node; The gate cascade output circuit is connected with a cascade clock signal end, a fifth power supply end and a gate cascade signal output end, and is configured to write a signal provided by the cascade clock signal end into the gate cascade signal output end under the control of a voltage at the first pull-up node, and write a fifth working voltage provided by the fifth power supply end into the gate cascade signal output end under the control of a voltage at the first pull-down node; The second gate drive output circuit is connected with a second drive clock signal end and a sixth power supply end, and is configured to write a signal provided by the second drive clock signal end into the second gate drive signal output end under the control of a voltage at the first pull-up node, and write a sixth working voltage provided by the sixth power supply end into the second gate drive signal output end under the control of a voltage at the first pull-down node.

15. The display device of claim 14, wherein, In the first gate drive circuit, the forced output control end connected with any one of the first shift registers comprises a second gate drive signal output end or a gate cascade signal output end configured by a second shift register corresponding to a same row of pixel units as the first shift registers. Alternatively, the first shift register is the shift register in claim 5 or 8, and in the first gate drive circuit, the first control end and the second control end connected to any one of the first shift registers are respectively the sensing cascade node inside the second shift register corresponding to the same row of pixel units and a fourth clock signal end configured in advance.

16. The display device of claim 14, wherein, The second shift register is configured with a fourth gate drive signal output end connected to the corresponding second gate line. The second shift register further comprises a second display pre-charge reset circuit, a second sensing pre-charge reset circuit, a second pull-down control circuit and a fourth gate drive output circuit; the second display pre-charge reset circuit, the second sensing pre-charge reset circuit, the second pull-down control circuit and the fourth gate drive output circuit are connected to a second pull-up node, and the second pull-down control circuit and the fourth gate drive output circuit are connected to a second pull-down node. The second display pre-charge reset circuit is connected to a display signal input end, a display reset signal end and a fifth power supply end, and is configured to write the signal provided by the display signal input end into the second pull-up node in response to the control of the signal provided by the display signal input end, and write the fifth working voltage provided by the fifth power supply end into the second pull-down node in response to the control of the signal provided by the display reset signal end. The second sensing pre-charge reset circuit is connected to a sensing pre-charge signal end, a third clock signal end, a sensing reset signal end and a fifth power supply end, and is configured to write the voltage at the sensing pre-charge node into the second pull-up node in response to the control of the signal provided by the third clock signal end, and write the fifth working voltage provided by the fifth power supply end into the second pull-up node in response to the control of the signal provided by the sensing reset signal end. The second pull-down control circuit is connected to a seventh power supply end and a fifth power supply end, and is configured to write a voltage opposite to the voltage at the second pull-up node into the second pull-down node. The fourth gate drive output circuit is connected to a fourth drive clock signal end and a sixth power supply end, and is configured to write the signal provided by the fourth drive clock signal end into the fourth gate drive signal output end in response to the control of the voltage at the second pull-up node, and write the sixth working voltage provided by the sixth power supply end into the fourth gate drive signal output end in response to the control of the voltage at the second pull-down node.

17. The display device of claim 16, wherein, The second shift register further comprises a blank valid output circuit. The blank valid output circuit is connected to the first pull-up node, the first pull-down node, a blank valid clock signal end, a blank valid signal output end and a sixth power supply end, and is configured to write the signal provided by the blank valid clock signal end into the blank valid signal output end in response to the control of the voltage at the first pull-up node, and write the sixth working voltage provided by the sixth power supply end into the blank valid signal output end in response to the control of the voltage at the first pull-down node. Alternatively, the blank valid output circuit is connected with the second pull-up node, the second pull-down node, a blank valid clock signal terminal, a blank valid signal output terminal and a sixth power terminal, and is configured to write a signal provided by the blank valid clock signal terminal to the blank valid signal output terminal in response to a voltage at the second pull-up node, and write a sixth working voltage provided by the sixth power terminal to the blank valid signal output terminal in response to a voltage at the second pull-down node. In the first gate driving circuit, the forced output control terminal connected with any one of the first shift registers comprises a blank valid signal output terminal configured by a second shift register corresponding to a same row of pixel units as the first shift register.

18. A display device according to claim 16 or 17, characterized in that Each row of pixel units is further configured with a corresponding first gate line connected with a control electrode of a data writing transistor in the pixel unit. The second shift register further comprises a first gate driving output circuit and a third gate driving output circuit. The first gate driving output circuit is connected with the first pull-up node, the first pull-down node, a first gate driving signal output terminal, a first driving clock signal terminal and a sixth power terminal, and is configured to write a signal provided by the first driving clock signal terminal to the first gate driving signal output terminal in response to a voltage at the first pull-up node, and write a sixth working voltage provided by the sixth power terminal to the first gate driving signal output terminal in response to a voltage at the first pull-down node. The third gate driving output circuit is connected with the second pull-up node, the second pull-down node, a third gate driving signal output terminal, a third driving clock signal terminal and a sixth power terminal, and is configured to write a signal provided by the third driving clock signal terminal to the third gate driving signal output terminal in response to a voltage at the second pull-up node, and write a sixth working voltage provided by the sixth power terminal to the third gate driving signal output terminal in response to a voltage at the second pull-down node. The first gate driving signal output terminal and the third gate driving signal output terminal are connected with corresponding first gate lines, respectively.

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