Low power management circuit, electronic system and low power management method

Abstract

The application provides a low-power consumption management circuit, comprising: a sleep wake-up control module, which is used for generating a low-power consumption control signal according to a low-power consumption sleep instruction and generating a wake-up control signal according to a wake-up instruction; a power consumption control module, which is used for sequentially generating a plurality of turn-off control signals according to the low-power consumption control signal and sequentially generating a plurality of turn-on control signals according to the wake-up control signal; an isolation control module, which is used for isolating and processing stored data according to the corresponding turn-off control signal; a reset control module, which is used for generating or releasing a FLASH controller reset signal and a FLASH memory reset signal according to the low-power consumption control signal and the wake-up control signal; and a clock control module, which is used for generating a CPU clock according to the wake-up control signal and a received FLASH power-on initialization completion signal. Through the low-power consumption management circuit provided by the application, the problem of a large static current in a low-power consumption state existing in the prior low-power consumption technology is solved.

Description

Technical Field

[0001] This invention relates to low-power chip technology, and in particular to a low-power management circuit, electronic system, and low-power management method. Background Technology

[0002] Most existing low-power technologies for chips shut down the analog oscillator in the circuit, but the low-dropout linear regulator (LDO) is not completely shut down. Instead, it retains a portion of the power output to the FLASH memory to maintain its operation in sleep mode. The reason is that if the FLASH memory is completely shut down and then powered on again, the uncertain state of the data at the FLASH memory interface can easily cause timing disorders in the digital circuits, thereby affecting the normal operation of the central processing unit (CPU).

[0003] However, this is a relatively conservative circuit design. Its drawback is that the static current of the chip is often too large in the low-power state, ranging from a few microamps to tens of microamps. It does not achieve a true low-power chip design, and therefore cannot meet the needs of many low-power industrial application scenarios. This not only limits the user's usage scenarios, but also increases additional cost. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a low-power management circuit, electronic system and low-power management method to solve the problem of large static current in the low-power state of existing chip low-power technology.

[0005] To achieve the above and other related objectives, the present invention provides a low-power management circuit, which includes: a sleep-wake control module, a power consumption control module, an isolation control module, a reset control module, and a clock control module; wherein,

[0006] The sleep-wake control module is used to receive low-power sleep instructions and wake-up instructions, and generate low-power control signals according to the low-power sleep instructions and wake-up control signals according to the wake-up instructions.

[0007] The power consumption control module is connected to the output terminal of the sleep-wake control module and is used to generate multiple shutdown control signals in sequence according to the low power consumption control signal, and to generate multiple turn-on control signals in sequence according to the wake-up control signal.

[0008] The isolation control module is connected to the output of the power consumption control module and is used to isolate the received stored data according to the corresponding shutdown control signal.

[0009] The reset control module is connected to the output of the sleep-wake control module and is used to generate a FLASH controller reset signal and a FLASH memory reset signal in sequence according to the low power control signal, and to release the FLASH memory reset signal and the FLASH controller reset signal in sequence according to the wake-up control signal.

[0010] The clock control module is connected to the output of the sleep-wake control module and is used to generate a CPU clock based on the wake-up control signal and the received FLASH power-on initialization completion signal.

[0011] Optionally, the reset control module is further configured to generate a power-on reset signal during the initial power-on phase of the low-power management circuit. In this case, the power consumption control module is also connected to the output terminal of the reset control module and is configured to perform a power-on reset operation based on the power-on reset signal.

[0012] Optionally, the clock control module is further configured to perform clock switching control on the sleep-wake control module and the power consumption control module according to the low-power control signal and the wake-up control signal.

[0013] Optionally, the clock control module is also used to control the clock switching of some peripherals.

[0014] Optionally, the clock control module generates a high-frequency system clock, a low-frequency power management clock, a high-frequency FLASH clock, and a high-frequency digital circuit clock according to the wake-up control signal, and generates a low-frequency system clock and a low-frequency power management clock according to the low-power control signal, while simultaneously turning off the high-frequency FLASH clock and the high-frequency digital circuit clock.

[0015] Optionally, the plurality of shutdown control signals include at least: a storage state shutdown control signal, a high-frequency oscillator shutdown control signal, a storage data shutdown control signal, a FLASH memory power supply shutdown control signal, a digital circuit power supply shutdown control signal, and a bandgap reference source shutdown control signal; and / or, the plurality of turn-on control signals include at least: a bandgap reference source turn-on control signal, a digital circuit power supply turn-on control signal, a FLASH memory power supply turn-on control signal, a storage data turn-on control signal, a storage state turn-on control signal, and a high-frequency oscillator turn-on control signal.

[0016] Optionally, the isolation control module is implemented using AND gates.

[0017] The present invention also provides an electronic system comprising at least the low-power management circuitry described in any of the preceding claims.

[0018] Optionally, the electronic system further includes: a central processing unit, a bandgap reference source, a low-dropout linear regulator, a FLASH controller, a FLASH memory, a high-frequency oscillator, and digital circuitry; wherein,

[0019] The central processing unit is connected to the input terminal of the sleep-wake control module, the output terminal of the clock control module, and the output terminal of the isolation control module. It is used to generate low-power sleep instructions and wake-up instructions, and to receive CPU clock and stored data.

[0020] The bandgap reference source is connected to the output terminal of the power consumption control module and is used to turn on and off according to the bandgap reference source control signal, and to generate a bandgap reference when it is turned on.

[0021] The low-dropout linear regulator is connected to the output of the bandgap reference source and the output of the power consumption control module. It is used to control the power supply of the FLASH memory according to the FLASH memory power supply control signal and to control the power supply of the digital circuit according to the digital circuit power supply control signal.

[0022] The FLASH controller is connected to the output of the reset control module and is used to perform a reset operation according to the FLASH controller reset signal and to control the FLASH memory to work.

[0023] The FLASH memory is connected to the output terminal of the power consumption control module, the output terminal of the reset control module, the output terminal of the low dropout linear regulator, and the input terminal of the isolation control module. It is used to turn on or off according to the storage status control signal, the FLASH memory reset signal, and the FLASH memory power supply control signal, and outputs the stored data when it is turned on.

[0024] The high-frequency oscillator is connected to the output of the power consumption control module and is used to turn on and off according to the high-frequency oscillator control signal, and to generate a high-frequency clock when it is turned on.

[0025] The digital circuit is connected to the output terminal of the low-dropout linear regulator and is used to turn the circuit on and off according to the power supply control signal of the digital circuit.

[0026] Optionally, the sleep-wake control module, the power consumption control module, the FLASH controller, the FLASH memory, and the digital circuit are all connected to the output of the clock control module, and the clock switching control of each part is performed through the clock control module.

[0027] The present invention also provides a low-power management method based on the low-power management circuit described in any of the preceding claims, the method comprising:

[0028] Upon receiving the low-power sleep command, the device sequentially shuts down each peripheral device using a step-by-step shutdown method and enters low-power mode.

[0029] Upon receiving a wake-up command, the device sequentially powers on each peripheral in a step-by-step manner, exits low-power mode, and enters normal operating mode.

[0030] In low-power mode, the isolation control module isolates the stored data output from the FLASH memory.

[0031] As described above, the low-power management circuit, electronic system, and low-power management method of the present invention, through a newly designed low-power management circuit structure, enable the complete shutdown of the power supply provided by the LDO to the FLASH memory in low-power mode, thereby making the static current of the chip in low-power mode approach 0, achieving true low power consumption, and meeting the needs of various low-power industrial application scenarios. Attached Figure Description

[0032] Figure 1 The diagram shown is a schematic of an electronic system including a low-power management circuit according to the present invention.

[0033] Figure 2 Displayed as Figure 1 The timing diagram of the electronic system shown is shown.

[0034] Component designation explanation

[0035] 100 Low-power management circuit

[0036] 101 Sleep-Wake Control Module

[0037] 102 Power Consumption Control Module

[0038] 103 Isolation Control Module

[0039] 104 Reset Control Module

[0040] 105 Clock Control Module

[0041] 200 Central Processing Units

[0042] 300 bandgap reference source

[0043] 400 Low Dropout Linear Regulator

[0044] 500 FLASH Controller

[0045] 600 FLASH memory

[0046] 700 high-frequency oscillator

[0047] 800 digital circuits Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please see Figure 1 and Figure 2 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] like Figure 1 As shown, this embodiment provides a low-power management circuit 100, which includes: a sleep-wake control module 101, a power control module 102, an isolation control module 103, a reset control module 104, and a clock control module 105.

[0051] The sleep-wake control module 101 is used to receive low-power sleep instructions and wake-up instructions, and generate low-power control signals according to the low-power sleep instructions and wake-up control signals according to the wake-up instructions.

[0052] Specifically, the central processing unit (CPU) sends a signal SLEEPDEEP. When SLEEPDEEP = 1, it indicates that the CPU has issued a low-power sleep command; when SLEEPDEEP = 0, it indicates that the CPU has issued a wake-up command. The sleep-wake control module 101 generates and outputs a signal PWREN based on the SLEEPDEEP signal. When SLEEPDEEP = 1, the sleep-wake control module 101 outputs a signal PWREN = 0, indicating the generation of the low-power control signal; when SLEEPDEEP = 0, the sleep-wake control module 101 outputs a signal PWREN = 1, indicating the generation of the wake-up control signal.

[0053] The power consumption control module 102 is connected to the output terminal of the sleep-wake control module 101, and is used to generate multiple shutdown control signals in sequence according to the low power consumption control signal to turn off each peripheral device in a step-by-step shutdown manner, and to generate multiple turn-on control signals in sequence according to the wake-up control signal to turn on each peripheral device in a step-by-step turn-on manner.

[0054] Furthermore, the power consumption control module 102 is also used to perform a power-on reset operation based on a power-on reset signal during the initial power-on phase of the circuit; wherein, the power consumption control module 102 receives a signal PORRST_N, when the signal PORRST_N = 0, it represents the generation of a power-on reset signal and the power consumption control module 102 performs a power-on reset operation, and when the signal PORRST_N = 1, it represents the release of the power-on reset signal.

[0055] Specifically, the plurality of shutdown control signals include at least: a storage state shutdown control signal, a high-frequency oscillator shutdown control signal, a storage data shutdown control signal, a FLASH memory power supply shutdown control signal, a digital circuit power supply shutdown control signal, and a bandgap reference source shutdown control signal; and / or, the plurality of turn-on control signals include at least: a bandgap reference source turn-on control signal, a digital circuit power supply turn-on control signal, a FLASH memory power supply turn-on control signal, a storage data turn-on control signal, a storage state turn-on control signal, and a high-frequency oscillator turn-on control signal.

[0056] More specifically, the power consumption control module 102 generates and outputs signals FLASHDPSTB, FIOSC_PD, ISOAND_N, VSUB15_ENH, LDO15_STANDBY, and BGEN_N based on the signal PWREN; for example, FLASHDPSTB = 1 represents the generation of a storage state shutdown control signal, and FLASHDPSTB = 0 represents the generation of a storage state enable control signal; FIOSC_PD = 1 represents the generation of a high-frequency oscillator shutdown control signal, and FIOSC_PD = 0 represents the generation of a high-frequency oscillator enable control signal; ISOAND_N = 0 represents the generation of a high-frequency oscillator enable control signal; The following signals represent the generation of a data storage shutdown control signal and a data storage enable control signal: ISOAND_N = 1; VSUB15_ENH = 0; LDO15_STANDBY = 1; LDO15_STANDBY = 0; and BGEN_N = 1. The signals represent the generation of a FLASH memory power supply shutdown control signal and a FLASH memory power supply enable control signal.

[0057] When the signal PWREN = 0, the power consumption control module 102 sequentially outputs the signals FLASHDPSTB = 1, FIOSC_PD = 1, ISOAND_N = 0, VSUB15_ENH = 0, LDO15_STANDBY = 1, and BGEN_N = 1. Specifically, after the output signal FLASHDPSTB = 1, at least two low-speed clock cycles (approximately 62.5 μs) are passed before the output signal FIOSC_PD = 1; after the output signal FIOSC_PD = 1, at least two low-speed clock cycles (approximately 62.5 μs) are passed before the output signal ISOAND_N = 0; after the output signal ISOAND_N = 0, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal VSUB15_ENH = 0; after the output signal VSUB15_ENH = 0, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal LDO15_STANDBY = 1; after the output signal LDO15_STANDBY = 1, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal BGEN_N = 1.

[0058] When the signal PWREN=1, the power consumption control module 102 sequentially outputs the signals BGEN_N=0, LDO15_STANDBY=0, VSUB15_ENH=1, ISOAND_N=1, FLASHDPSTB=0, and FIOSC_PD=0. Specifically, after the output signal BGEN_N = 0, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal LDO15_STANDBY = 0; after the output signal LDO15_STANDBY = 0, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal VSUB15_ENH = 1; after the output signal VSUB15_ENH = 1, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal ISOAND_N = 1; after the output signal ISOAND_N = 1, at least one low-speed clock cycle (approximately 31.25 μs) is passed before the output signal FLASHDPSTB = 0; and after the output signal FLASHDPSTB = 0, at least two low-speed clock cycles (approximately 62.5 μs) are passed before the output signal FIOSC_PD = 0.

[0059] The isolation control module 103 is connected to the output of the power consumption control module 102 and is used to isolate the received stored data according to the corresponding shutdown control signal. This is to prevent timing disorders of digital circuits caused by the uncertain state of interface data when the FLASH memory is powered on again, thereby affecting the normal operation of the central processing unit. The isolation control module 103 receives the stored data output by the FLASH memory, and when the signal ISOAND_N = 0 output by the power consumption control module 102, the isolation control module 103 isolates the stored data.

[0060] Specifically, the isolation control module 103 is implemented using AND gates. When the signal ISOAND_N output by the power consumption control module 102 is 0, the isolation control module 103 performs a logical AND operation between the stored data and "0" to fix all the stored data as "0", thereby achieving data isolation and ensuring data stability. When the signal ISOAND_N output by the power consumption control module 102 is 1, the isolation control module 103 performs a logical AND operation between the stored data and "1", which is equivalent to restoring the stored data uploaded from the FLASH memory to the central processing unit.

[0061] The reset control module 104 is connected to the output terminal of the sleep-wake control module 101. It is used to generate a FLASH controller reset signal and a FLASH memory reset signal in sequence according to the low power control signal, so as to cooperate with the low dropout linear regulator to completely power off the FLASH memory, and release the FLASH memory reset signal and the FLASH controller reset signal in sequence according to the wake-up control signal, so as to restore the circuit to normal working mode.

[0062] Furthermore, the reset control module 104 is also used to generate a power-on reset signal in the initial stage of power-on of the low-power management circuit; wherein, the reset control module 104 generates and outputs a signal PORRST_N, when the signal PORRST_N = 0, it represents the generation of a power-on reset signal, and when the signal PORRST_N = 1, it represents the release of the power-on reset signal.

[0063] Specifically, the reset control module 104 generates and outputs signals FLASHDIG_RSTN and FLASHANA_RSTN based on the signal PWREN; for example, signal FLASHDIG_RSTN = 0 represents the generation of a FLASH controller reset signal, signal FLASHDIG_RSTN = 1 represents the release of a FLASH controller reset signal, signal FLASHANA_RSTN = 0 represents the generation of a FLASH memory reset signal, and signal FLASHANA_RSTN = 1 represents the release of a FLASH memory reset signal.

[0064] When signal PWREN = 0, the reset control module 104 sequentially outputs signals FLASHDIG_RSTN = 0 and FLASHANA_RSTN = 0. Specifically, after outputting signal FLASHDIG_RSTN = 0, at least one low-speed clock cycle (approximately 31.25 μs) is elapsed before outputting signal FLASHANA_RSTN = 0, and the interval between signal FLASHDIG_RSTN = 0 and signal FLASHDPSTB = 1 is at least one low-speed clock cycle (approximately 31.25 μs).

[0065] When signal PWREN = 1, the reset control module 104 sequentially outputs signals FLASHANA_RSTN = 1 and FLASHDIG_RSTN = 1. Specifically, after outputting signal FLASHANA_RSTN = 1, at least one low-speed clock cycle (approximately 31.25 μs) is elapsed before outputting signal FLASHDIG_RSTN = 1, and the interval between signal FLASHANA_RSTN = 1 and signal FLASHDPSTB = 0 is at least one low-speed clock cycle (approximately 31.25 μs).

[0066] The clock control module 105 is connected to the output of the sleep / wake control module 101 and is used to generate a CPU clock based on the wake-up control signal and the received FLASH power-on initialization completion signal. When the signal PWREN = 1 and the signal FLASH_OK = 1, the clock control module 105 outputs the CPU clock CPU_CLK and provides it to the central processing unit; while when the signal PWREN = 0, the clock control module 105 does not output or outputs 0, that is, it turns off the CPU clock. The signal FLASH_OK = 1 indicates that the FLASH memory has completed the power-on initialization operation.

[0067] Furthermore, the clock control module 105 is also used to perform clock switching control on the sleep-wake control module 101 and the power consumption control module 102 according to the low-power control signal and the wake-up control signal. Even further, the clock control module 105 is also used to perform clock switching control on some peripherals, such as FLASH controllers, FLASH memory, and digital circuits.

[0068] Specifically, the clock control module 105 generates a high-frequency system clock, a low-frequency power management clock, a high-frequency FLASH clock, and a high-frequency digital circuit clock according to the wake-up control signal, and generates a low-frequency system clock and a low-frequency power management clock according to the low-power control signal, while simultaneously turning off the high-frequency FLASH clock and the high-frequency digital circuit clock.

[0069] More specifically, when the signal PWREN = 1, the clock control module 105 outputs a high-frequency system clock and provides it to the sleep-wake control module 101, outputs a low-frequency power management clock and provides it to the power control module 102, outputs a high-frequency FLASH clock and provides it to the FLASH controller and FLASH memory, and outputs a high-frequency digital circuit clock and provides it to the digital circuit. When the signal PWREN = 0, the clock control module 105 outputs a low-frequency system clock and provides it to the sleep-wake control module 101, outputs a low-frequency power management clock and provides it to the power control module 102, and at the same time, the clock control module 105 does not output or outputs 0 to turn off the high-frequency FLASH clock and the high-frequency digital circuit clock.

[0070] Correspondingly, such as Figure 1 As shown, this embodiment also provides an electronic system, which includes at least the low-power management circuit 100 described above. The relevant description of the low-power management circuit 100 can be found above and will not be repeated here.

[0071] Furthermore, the electronic system also includes: a central processing unit 200, a bandgap reference source 300, a low dropout linear regulator (LDO) 400, a FLASH controller 500, a FLASH memory 600, a high-frequency oscillator 700, and digital circuitry 800.

[0072] The central processing unit 200 is connected to the input terminal of the sleep-wake control module 101, the output terminal of the clock control module 105, and the output terminal of the isolation control module 103. It is used to generate low-power sleep instructions and wake-up instructions, and to receive CPU clock and stored data.

[0073] Specifically, the central processing unit 200 generates and outputs a SLEEPDEEP signal to the sleep-wake control module 101. When the signal SLEEPDEEP = 1, it represents the generation of a low-power sleep command; when the signal SLEEPDEEP = 0, it represents the generation of a wake-up command. The central processing unit 200 receives the CPU clock CPU_CLK output by the clock control module 105. When the clock control module 105 outputs the CPU clock CPU_CLK, the central processing unit 200 operates normally. When the clock control module 105 has no output or the output is 0, the central processing unit 200 enters a low-power mode. After resuming operation, the central processing unit 200 also receives the stored data output by the isolation control module 103.

[0074] The bandgap reference source 300 is connected to the output terminal of the power consumption control module 102 and is used to turn on and off according to the bandgap reference source control signal, and generate a bandgap reference when it is turned on.

[0075] Specifically, the bandgap reference source 300 is controlled by the signal BGEN_N output by the power consumption control module 102. When the signal BGEN_N = 1, the bandgap reference source 300 is turned off. When the signal BGEN_N = 0, the bandgap reference source 300 is turned on and provides the bandgap reference voltage POWER to the low dropout linear regulator 400.

[0076] The low-dropout linear regulator 400 is connected to the output terminal of the bandgap reference source 300 and the output terminal of the power consumption control module 102. It is used to control the power supply of the FLASH memory 600 according to the FLASH memory power supply control signal and to control the power supply of the digital circuit 800 according to the digital circuit power supply control signal.

[0077] Specifically, the low-dropout linear regulator 400 can generate voltages in multiple different voltage domains, and the FLASH memory 600 and the digital circuit 800 are powered by voltages in different voltage domains generated by the low-dropout linear regulator 400. The low-dropout linear regulator 400 is controlled by the signals VSUB15_ENH and LDO15_STANDBY output by the power consumption control module 102; when VSUB15_ENH = 0, the power supply to the FLASH memory 600 in the low-dropout linear regulator 400 is turned off, and when VSUB15_ENH = 1, the power supply to the FLASH memory 600 in the low-dropout linear regulator 400 is turned on; when LDO15_STANDBY = 1, the power supply to the digital circuit 800 in the low-dropout linear regulator 400 is turned off, and when LDO15_STANDBY = 0, the power supply to the digital circuit 800 in the low-dropout linear regulator 400 is turned on.

[0078] The FLASH controller 500 is connected to the output terminal of the reset control module 104 and is used to perform a reset operation according to the FLASH controller reset signal and to control the operation of the FLASH memory.

[0079] Specifically, the FLASH controller 500 is controlled by the signal FLASHDIG_RSTN output by the reset control module 104. When the signal FLASHDIG_RSTN = 0, the FLASH controller 500 performs a reset operation. When the signal FLASHDIG_RSTN = 1, the FLASH controller 500 works normally and controls the FLASH memory to work.

[0080] The FLASH memory 600 is connected to the output terminal of the power consumption control module 102, the output terminal of the reset control module 104, the output terminal of the low dropout linear regulator 400, and the input terminal of the isolation control module 103. It is used to turn on or off according to the storage status control signal, the FLASH memory reset signal, and the FLASH memory power supply control signal, and outputs the stored data when it is turned on.

[0081] Specifically, the FLASH memory 600 is simultaneously controlled by the signal FLASHDPSTB output by the power consumption control module 102, the signal FLASHANA_RSTN output by the reset control module 104, and the signal FLASH_1.5V output by the low dropout linear regulator 400. When FLASHDPSTB = 1, FLASHANA_RSTN = 0, and FLASH_1.5V is invalid, the FLASH memory is completely turned off. When FLASHDPSTB = 0, FLASHANA_RSTN = 1, and FLASH_1.5V is valid, the FLASH memory is turned on, and after power-on, it outputs stored data to the isolation control module 103. It should be noted that even when the FLASH memory is completely turned off, its interface data will still be output to the isolation control module 103; in this embodiment, this interface data is also referred to as stored data.

[0082] The high-frequency oscillator 700 is connected to the output terminal of the power consumption control module 102 and is used to turn on and off according to the high-frequency oscillator control signal, and generate a high-frequency clock when it is turned on.

[0083] Specifically, the high-frequency oscillator 700 is controlled by the signal FIOSC_PD output by the power consumption control module 102. When the signal FIOSC_PD = 1, the high-frequency oscillator 700 is turned off, and when the signal FIOSC_PD = 0, the high-frequency oscillator 700 is turned on and generates a high-frequency clock.

[0084] The digital circuit 800 is connected to the output terminal of the low dropout linear regulator 400 and is used to turn the circuit on and off according to the power supply control signal of the digital circuit.

[0085] Specifically, when the signal DIG_1.5V is invalid, that is, when the low-dropout linear regulator 400 shuts down the power supply to the digital circuit 800, the digital circuit 800 is turned off; when the signal DIG_1.5V is valid, that is, when the low-dropout linear regulator 400 turns on the power supply to the digital circuit 800, the digital circuit 800 is turned on.

[0086] Furthermore, the sleep-wake control module 101, the power consumption control module 102, the FLASH controller 500, the FLASH memory 600, and the digital circuit 800 are all connected to the output terminal of the clock control module 105, and the clock switching control of each part is performed through the clock control module 105.

[0087] Specifically, the clock control module 105 is used to generate various clocks, such as: generating a CPU clock CPU_CLK for use by the central processing unit 200. This clock is a high-frequency oscillator clock in normal operating mode and is turned off in low-power mode; generating a system clock SYS_CLK for use by the sleep / wake control module 101. This clock is a high-frequency oscillator clock in normal operating mode and switches to a low-frequency oscillator clock (generally 32KHz) in low-power mode; generating a power management clock PWR_CLK for use by the power control module 102. This clock always maintains a low-frequency oscillator clock in both normal operating mode and low-power mode; generating a FLASH clock FLASH_CLK for use by the FLASH controller 500 and the FLASH memory 600. This clock is a high-frequency oscillator clock in normal operating mode and is turned off in low-power mode; and generating a digital circuit clock DIG_CLK for use by the digital circuit 800. This clock is a high-frequency oscillator clock in normal operating mode and is turned off in low-power mode. It should be noted that after receiving the wake-up command, the system clock SYS_CLK, FLASH clock FLASH_CLK, and digital circuit clock DIG_CLK are restored in succession. Subsequently, after the clock control module 105 receives the FLASH power-on initialization completion signal from the FLASH memory 600, it restarts the CPU clock CPU_CLK, and the central processing unit 200 resumes normal operation.

[0088] This embodiment also provides a low-power management method based on the low-power management circuit 100 described above, the method comprising:

[0089] 1) Upon receiving the low-power sleep command (SLEEPDEEP=1), the peripherals are shut down sequentially using a step-by-step shutdown method, and the system enters a low-power mode to ensure more linear circuit switching and avoid large current fluctuations. In the low-power mode, the isolation control module isolates the stored data output from the FLASH memory.

[0090] Combination Figure 1 and Figure 2 The specific process is as follows:

[0091] 1-1) The power control module 102 outputs the signal FLASHDPSTB=1, causing the FLASH memory 600 to enter a low-power mode;

[0092] 1-2) After two low-speed clock cycles (approximately 62.5 μs), the power consumption control module 102 outputs the signal FIOSC_PD = 1, turning off the high-frequency oscillator 700;

[0093] 1-3) After two more low-speed clock cycles (approximately 62.5 μs), the power consumption control module 102 outputs the signal ISOAND_N = 0 to isolate the stored data output by the FLASH memory 600;

[0094] 1-4) After another low-speed clock cycle (approximately 31.25μs), the power consumption control module 102 outputs the signal VSUB15_ENH = 0, turning off the 1.5V power supply provided by the low-dropout linear regulator 400 to the FLASH memory 600;

[0095] 1-5) After another low-speed clock cycle (approximately 31.25μs), the power consumption control module 102 outputs the signal LDO15_STANDBY = 1, turning off the 1.5V power supply provided by the low-dropout linear regulator 400 to the digital circuit 800.

[0096] 1-6) Finally, after one low-speed clock cycle (approximately 31.25 μs), the power consumption control module 102 outputs signal BGEN_N = 1, turning off the bandgap reference source 300.

[0097] After the above series of low-power processes, the static current of the system approaches zero in low-power mode, achieving complete low power consumption.

[0098] Simultaneously, in low-power mode, the FLASH controller 500 and the FLASH memory 600 are reset, and the low-dropout linear regulator 400 completes the power-off of the FLASH section. Apart from this, all other reset signals of the system remain in the released state (i.e., maintained at a high level). After the FLASHDPSTB signal is pulled high, the reset signal FLASHDIG_RSTN of the FLASH controller 500 changes from high to low after one low-speed clock cycle, approximately 31.25μs, to reset the FLASH controller 500. Then, after another low-speed clock cycle, approximately 31.25μs, the reset signal FLASHANA_RSTN of the FLASH memory 600 changes from high to low to reset the FLASH memory 600.

[0099] In low-power mode, the high-frequency oscillator 700 is turned off, while the low-frequency oscillator remains operational (typically 32kHz). The power management clock PWR_CLK remains the low-frequency oscillator clock, the system clock SYS_CLK is switched to the low-frequency oscillator clock to reduce power consumption, and the CPU clock CPU_CLK, digital circuit clock DIG_CLK, and FLASH clock FLASH_CLK are all turned off to reduce power consumption.

[0100] 2) Upon receiving a wake-up command (SLEEPDEEP=0), the peripherals are turned on sequentially in a step-by-step manner, exiting the low-power mode and entering the normal working mode to ensure a more linear circuit switching and avoid large current fluctuations.

[0101] Combination Figure 1 and Figure 2 The specific process is as follows:

[0102] 2-1) When the power consumption control module 102 outputs the signal BGEN_N = 0, the bandgap reference source 300 is awakened and resumes providing the bandgap reference voltage to the low dropout linear regulator 400;

[0103] 2-2) After one low-speed clock cycle (approximately 31.25μs), the power consumption control module 102 outputs the signal LDO15_STANDBY = 0, the 1.5V power supply provided by the low-dropout linear regulator 400 to the digital circuit 800 is awakened, and the power supply to the digital circuit 800 is restored.

[0104] 2-3) After another low-speed clock cycle (approximately 31.25μs), the power consumption control module 102 outputs the signal VSUB15_ENH = 1, turning on the low dropout linear regulator 400 to provide 1.5V power to the FLASH memory 600;

[0105] 2-4) After another low-speed clock cycle (approximately 31.25μs), the power consumption control module 102 outputs the signal ISOAND_N=1, disabling the isolation of the stored data and releasing the output data path of the FLASH memory 600.

[0106] 2-5) After another low-speed clock cycle (approximately 31.25μs), the power consumption control module 102 outputs the signal FLASHDPSTB=0, and the FLASH memory 600 is woken up to resume program read and write.

[0107] 2-6) After two more low-speed clock cycles (approximately 62.5 μs), the power consumption control module 102 outputs the signal FIOSC_PD = 0, and the high-frequency oscillator 700 resumes operation.

[0108] Simultaneously, upon receiving the wake-up command, the system clock SYS_CLK first resumes operation, switching back from a low-frequency oscillator clock to a high-frequency oscillator clock. Subsequently, the FLASH clock FLASH_CLK and the digital circuit clock DIG_CLK also resume operation, switching back to high-frequency oscillator clocks. Finally, after the clock control module receives the FLASH power-on initialization completion signal (FLASH_OK=1), the CPU clock CPU_CLK resumes operation as a high-frequency oscillator clock, and the CPU resumes operation. Thus, the clock wake-up operation is completed.

[0109] During low-power sleep mode, after the FLASH memory 600 is woken up (FLASHDPSTB=0), after one low-speed clock cycle, approximately 31.25μs, the reset signal FLASHANA_RSTN of the FLASH memory 600 is released; after another low-speed clock cycle, approximately 31.25μs, the reset signal FLASHDIG_RSTN of the FLASH controller 500 is released; at this point, the FLASH part has completed the wake-up operation.

[0110] In summary, the low-power management circuit, electronic system, and low-power management method of this invention, through a newly designed low-power management circuit structure, enable the complete shutdown of the power supply from the LDO to the FLASH memory in low-power mode. This allows the quiescent current of the chip in low-power mode to approach zero, achieving true low power consumption and meeting the needs of various low-power industrial applications. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low-power management circuit, characterized in that, The low-power management circuit includes: a sleep-wake control module, a power consumption control module, an isolation control module, a reset control module, and a clock control module; wherein, The sleep-wake control module is used to receive low-power sleep instructions and wake-up instructions, and generate low-power control signals according to the low-power sleep instructions and wake-up control signals according to the wake-up instructions. The power consumption control module is connected to the output terminal of the sleep-wake control module and is used to generate multiple shutdown control signals in sequence according to the low power consumption control signal, and to generate multiple turn-on control signals in sequence according to the wake-up control signal. The isolation control module is connected to the output of the power consumption control module and is used to isolate the received stored data according to the corresponding shutdown control signal. The reset control module is connected to the output of the sleep-wake control module and is used to generate a FLASH controller reset signal and a FLASH memory reset signal in sequence according to the low power control signal, and to release the FLASH memory reset signal and the FLASH controller reset signal in sequence according to the wake-up control signal. The clock control module is connected to the output of the sleep-wake control module and is used to generate a CPU clock based on the wake-up control signal and the received FLASH power-on initialization completion signal.

2. The low-power management circuit according to claim 1, characterized in that, The reset control module is also used to generate a power-on reset signal in the initial stage of power-on of the low-power management circuit. At this time, the power consumption control module is also connected to the output terminal of the reset control module to perform a power-on reset operation according to the power-on reset signal.

3. The low-power management circuit according to claim 1, characterized in that, The clock control module is also used to perform clock switching control on the sleep-wake control module and the power consumption control module according to the low power control signal and the wake-up control signal.

4. The low-power management circuit according to claim 3, characterized in that, The clock control module is also used to control the clock switching of some peripherals.

5. The low-power management circuit according to claim 4, characterized in that, The clock control module generates a high-frequency system clock, a low-frequency power management clock, a high-frequency FLASH clock, and a high-frequency digital circuit clock according to the wake-up control signal, and generates a low-frequency system clock and a low-frequency power management clock according to the low-power control signal, while simultaneously turning off the high-frequency FLASH clock and the high-frequency digital circuit clock.

6. The low-power management circuit according to claim 1, characterized in that, The plurality of said shutdown control signals include at least: a storage state shutdown control signal, a high-frequency oscillator shutdown control signal, a storage data shutdown control signal, a FLASH memory power supply shutdown control signal, a digital circuit power supply shutdown control signal, and a bandgap reference source shutdown control signal; and / or, The plurality of said turn-on control signals include at least: a bandgap reference source turn-on control signal, a digital circuit power supply turn-on control signal, a FLASH memory power supply turn-on control signal, a stored data turn-on control signal, a stored status turn-on control signal, and a high-frequency oscillator turn-on control signal.

7. The low-power management circuit according to claim 1, characterized in that, The isolation control module is implemented using AND gates.

8. An electronic system, characterized in that, The electronic system includes at least the low-power management circuitry as described in any one of claims 1-7.

9. The electronic system according to claim 8, characterized in that, The electronic system also includes: a central processing unit, a bandgap reference source, a low-dropout linear regulator, a FLASH controller, FLASH memory, a high-frequency oscillator, and digital circuitry; wherein, The central processing unit is connected to the input terminal of the sleep-wake control module, the output terminal of the clock control module, and the output terminal of the isolation control module. It is used to generate low-power sleep instructions and wake-up instructions, and to receive CPU clock and stored data. The bandgap reference source is connected to the output terminal of the power consumption control module and is used to turn on and off according to the bandgap reference source control signal, and to generate a bandgap reference when it is turned on. The low-dropout linear regulator is connected to the output of the bandgap reference source and the output of the power consumption control module. It is used to control the power supply of the FLASH memory according to the FLASH memory power supply control signal and to control the power supply of the digital circuit according to the digital circuit power supply control signal. The FLASH controller is connected to the output of the reset control module and is used to perform a reset operation according to the FLASH controller reset signal and to control the FLASH memory to work. The FLASH memory is connected to the output terminal of the power consumption control module, the output terminal of the reset control module, the output terminal of the low dropout linear regulator, and the input terminal of the isolation control module. It is used to turn on or off according to the storage status control signal, the FLASH memory reset signal, and the FLASH memory power supply control signal, and outputs the stored data when it is turned on. The high-frequency oscillator is connected to the output of the power consumption control module and is used to turn on and off according to the high-frequency oscillator control signal, and to generate a high-frequency clock when it is turned on. The digital circuit is connected to the output terminal of the low-dropout linear regulator and is used to turn the circuit on and off according to the power supply control signal of the digital circuit.

10. The electronic system according to claim 9, characterized in that, The sleep-wake control module, the power consumption control module, the FLASH controller, the FLASH memory, and the digital circuit are all connected to the output of the clock control module, and the clock switching control of each part is performed through the clock control module.

11. A low-power management method based on the low-power management circuit as described in any one of claims 1-7, characterized in that, The method includes: Upon receiving the low-power sleep command, the device sequentially shuts down each peripheral device using a step-by-step shutdown method and enters low-power mode. Upon receiving a wake-up command, the device sequentially powers on each peripheral in a step-by-step manner, exits low-power mode, and enters normal operating mode. In low-power mode, the isolation control module isolates the stored data output from the FLASH memory.

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