A control method and control device of an optical module

Abstract

The application relates to a control method, a control device, equipment and a storage medium of an optical module, which are used for controlling and managing the optical module in a switch system through a programmed CPLD. The control method comprises a power-on starting control step, which comprises the following steps: when a delay output circuit in the CPLD receives an optical module in-position signal, a high level is output according to a first preset time delay, which is used for controlling the power-on of the optical module; when the power-on time of the optical module reaches a second preset time, an optical module configuration circuit in the CPLD pulls up an optical module reset signal, which is used for controlling the normal starting of the optical module. Through the technical scheme, the problems of low CPU utilization rate, slow and unstable operation speed of the CPU when the CPU is used to manage the optical module in the switch can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switch optical module, in particular to a control method and control device of optical module. BACKGROUND

[0002] At present, the optical module is one of important components in the switch system, which undertakes the task of transmitting optical signal in the switch system. The number and quality of the optical module of the switch directly affect the transmission performance quality and stability of the switch. The control and management of the optical module is one of important functions in the switch system.

[0003] The traditional switch system uses CPU (Central Processor Unit) or MCU (Micro Control Unit) to realize the management of the optical module, including monitoring, power supply control, realizing hot plug function and the like of the optical module; in this working mode, the CPU needs to judge the in-place state of the optical module in real time, which will increase the usage rate of the CPU and reduce the running speed of the CPU of the switch system.

[0004] When the CPU is used to control the power supply of the optical module, the control CPU sends a fixed time delay signal for realizing the time sequence control of the optical module, which is difficult to operate and unstable. SUMMARY

[0005] In order to solve the above technical problems, the present application provides a control method, control device, equipment and storage medium of optical module, which is used to solve the problems of low CPU usage rate, slow and unstable running speed of the CPU in the management of the optical module in the switch system.

[0006] In order to achieve the above purpose, the present application provides a control method of optical module, which is used to control and manage the optical module in the switch system through the programmed CPLD, and the control method comprises a power-on starting control step, which comprises:

[0007] When the delay output circuit in the CPLD receives the in-place signal of the optical module, the high level is output according to the first preset time delay, which is used to control the power-on of the optical module;

[0008] When the power-on time of the optical module reaches the second preset time, the optical module configuration circuit in the CPLD pulls up the optical module reset signal, which is used to control the normal starting of the optical module.

[0009] Further, the control method further comprises an in-place monitoring step, which comprises:

[0010] The in-position monitoring circuit in the CPLD monitors the in-position signal pin of the optical module in real time; the debouncing circuit in the in-position monitoring circuit performs voltage debouncing on the in-position pin signal on the in-position signal pin;

[0011] When the debounced in-position pin signal is changed from the out-of-position state to the in-position state and the in-position state is maintained for a first preset clock, the in-position monitoring circuit determines that the optical module is in position and outputs the optical module in-position signal to the delay output circuit;

[0012] When the debounced in-position pin signal is changed from the in-position state to the out-of-position state and the out-of-position state is maintained for a second preset clock, the in-position monitoring circuit determines that the optical module is out of position and outputs the optical module out-of-position signal to the delay output circuit.

[0013] Further, when the delay output circuit in the CPLD receives the optical module in-position signal, a high level is output with a first preset time delay, specifically including:

[0014] When the first precision delay circuit in the delay output circuit receives the optical module in-position signal, it is determined whether the maintenance time of the optical module in-position signal meets the first delay time; if so, a high voltage is output for controlling the second precision delay circuit in the delay output circuit to start working;

[0015] When the second precision delay circuit is started, a high voltage is output with a second delay time for controlling the power-on of the optical module.

[0016] Further, the control method further includes a power-off control step, which includes:

[0017] When the delay output circuit receives the optical module out-of-position signal, a low level is output for controlling the power-off of the optical module;

[0018] When the optical module is powered off, the optical module configuration circuit pulls down the optical module reset signal and clears the timing register; wherein the timing register is used to time the power-on time of the optical module.

[0019] Further, the control method further includes an upper layer communication control step, which includes:

[0020] When the optical module reset signal is pulled high for a third preset time, the register interface in the CPLD sends optical module ready notification information to the CPU.

[0021] Further, the control method further includes an optical module information management step, which includes at least the following: the CPLD accesses and obtains the configuration information of the optical module through an integrated circuit bus;

[0022] When the optical module is in place and stable, the CPLD reads voltage and current information of the optical module;

[0023] The CPLD judges the compatibility of the optical module;

[0024] The CPLD periodically monitors the temperature of the optical module; when the temperature of the optical module is too high, an interrupt signal is sent through the upper CPU.

[0025] Further, the first preset time is 100 ms, and the second preset time is 200 ms.

[0026] The application also provides a control device of an optical module for realizing the control method of the optical module, and the control device comprises a delay output circuit in the CPLD and an optical module configuration circuit in the CPLD.

[0027] The delay output circuit is used for outputting a high level in a first preset time when receiving an optical module in place signal, so as to control power-on of the optical module.

[0028] The optical module configuration circuit is used for pulling up an optical module reset signal when power-on time of the optical module reaches a second preset time, so as to control normal start of the optical module.

[0029] The application further provides a computer device comprising a memory, a processor and a computer program, wherein the computer program is stored in the memory and can be run on the processor, and the processor realizes the following steps when executing the computer program:

[0030] When the delay output circuit in the CPLD receives an optical module in place signal, a high level is output in a first preset time, so as to control power-on of the optical module.

[0031] When power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal, so as to control normal start of the optical module.

[0032] The application further provides a computer readable storage medium, which stores a computer program, and the computer program realizes the following steps when being executed by a processor:

[0033] When the delay output circuit in the CPLD receives an optical module in place signal, a high level is output in a first preset time, so as to control power-on of the optical module.

[0034] When power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal, so as to control normal start of the optical module.

[0035] The above technical solution of the present application has the following technical effects compared with the prior art:

[0036] In the present application, the optical module in the switch system is controlled and managed by the programmed CPLD; in order to improve the stability and reliability of the optical module during hot plugging, the power-on starting control step is implemented;

[0037] The programmed CPLD can include a delay output circuit and an optical module configuration circuit.

[0038] In the power-on starting control step, when the delay output circuit receives the optical module in-place signal, the delay output circuit outputs a high level according to the first preset time delay, for controlling the power-on of the optical module.

[0039] When the power-on time of the optical module reaches the second preset time, the optical module configuration circuit pulls up the optical module reset signal, for controlling the normal starting of the optical module.

[0040] Thus, the CPLD can be used to automatically identify and configure the working state of the optical module; that is, when the optical module is in place, the high level is outputted with delay, for controlling the power-on of the optical module; and after the power-on is stable, the optical module is reset, for controlling the normal starting of the optical module; the use of the CPLD delay control improves the control precision and response efficiency.

[0041] Therefore, the CPLD circuit can identify and control the insertion of the optical module, control the power supply of the optical module, and ensure the safety and reliability of the optical module during working.

[0042] Meanwhile, the management workload of the upper-layer controller CPU of the switch on the optical module can be effectively reduced, and the CPU utilization rate is improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0044] Figure 1 is a flowchart of the control method of the optical module in the first embodiment of the present application;

[0045] Figure 2 is a structural block diagram of the control device of the optical module in the second embodiment of the present application;

[0046] Figure 3 is an internal structure diagram of the computer device in the second embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0048] Example 1:

[0049] like Figure 1 As shown, this embodiment of the invention provides a control method for an optical module, used to control and manage optical modules in a switch system through a programmed CPLD. The control method includes a power-on startup control step, which includes:

[0050] When the delayed output circuit in the CPLD receives the optical module in-situ signal, it outputs a high level after a first preset time delay to control the optical module to power on.

[0051] When the power-on time of the optical module reaches the second preset time, the optical module configuration circuit in the CPLD pulls the optical module reset signal high to control the normal startup of the optical module.

[0052] In a specific embodiment, the optical modules in the switch system are controlled and managed by a programmed CPLD; in order to improve the stability and reliability of the optical modules during hot-swapping, a power-on start-up control step is used.

[0053] The programmed CPLD may include a delayed output circuit and an optical module configuration circuit;

[0054] In the power-on startup control step, when the delay output circuit receives the optical module in-situ signal, the delay output circuit outputs a high level after a first preset time delay, in order to control the optical module to power on.

[0055] When the power-on time of the optical module reaches the second preset time, the optical module configuration circuit pulls the optical module reset signal high to control the normal startup of the optical module.

[0056] Therefore, the optical module's working status can be automatically identified and configured via CPLD; that is, when the optical module is in place, a high level is output after a delay to control the optical module to power on; and after the power-on is stable, the optical module is reset and its normal startup is controlled; using CPLD delay control improves control accuracy and response efficiency.

[0057] Therefore, the CPLD circuit can identify and control the insertion of the optical module and control the power supply of the optical module, ensuring the safety and reliability of the optical module during operation;

[0058] At the same time, the management workload of the upper controller CPU of the switch on the optical module can be effectively reduced, and the CPU utilization is improved.

[0059] In the actual embodiment, the signal of the debouncing circuit can be received by the delay output circuit (i.e., the delay circuit); after receiving the in-situ judgment of the debouncing circuit, the high level is output for 100 ms to control the power-on of the optical module.

[0060] When the optical module is not powered on, the reset signal of the optical module remains low; after 200 ms after the optical module is powered on, the optical module reset signal is pulled high to enable the optical module to start normally.

[0061] In practice, CPU, which stands for Central Processor Unit, represents the central processing unit; CPLD, which stands for Complex Programmable Logic Device, represents programmable logic device; MCU, which stands for Micro Control Unit, represents microcontroller.

[0062] CPLD is the abbreviation of Complex Programmable Logic Device, which is a kind of digital circuit device used to realize certain logic function. CPLD is composed of one or more programmable logic units (Programmable Logic Blocks, PLBs), each of which usually contains one or more programmable logic gates, flip-flops and other digital circuit components. By programming the CPLD, these programmable components can be connected together to realize complex digital circuit functions such as counters, state machines, data selectors, etc.

[0063] CPLD is usually used in applications that require low delay, high speed and reliability, such as communication equipment, digital signal processing, controllers, instruments and test equipment, etc. CPLD can also be used to realize protocol conversion, data conversion, timing generation, etc.

[0064] In order to improve the stability and reliability of the optical module during hot plug, the control method of the above optical module automatically realizes the power supply control of the optical module, the working state control of the optical module, and the hot plug function, which is realized by hardware circuit.

[0065] That is, the working state of the optical module is automatically identified and configured by the CPLD circuit. The workload of the upper controller (i.e., CPU, Central Processor Unit) of the switch on the optical module is effectively reduced, and the CPU utilization is effectively improved.

[0066] The CPLD circuit is used for identifying and controlling the insertion and extraction of the optical module, controlling power supply of the optical module, ensuring safety and reliability of the optical module, and effectively improving the availability and flexibility of the system during operation.

[0067] In a preferred embodiment, the first preset time is 100 ms, and the second preset time is 200 ms.

[0068] In a preferred embodiment, the control method further comprises a presence monitoring step, which comprises:

[0069] S11A presence monitoring circuit in the CPLD monitors a presence signal pin of the optical module in real time; a debouncing circuit in the presence monitoring circuit performs voltage debouncing processing on the presence pin signal on the presence signal pin;

[0070] S12When the debounced presence pin signal is changed from an un-presence state to a presence state, and the presence state is maintained for a first preset clock, the presence monitoring circuit determines that the optical module is present, and outputs an optical module presence signal to a delay output circuit.

[0071] S13When the debounced presence pin signal is changed from a presence state to an un-presence state, and the un-presence state is maintained for a second preset clock, the presence monitoring circuit determines that the optical module is not present, and outputs an optical module un-presence signal to the delay output circuit.

[0072] In an actual embodiment, the optical module presence monitoring circuit monitors the presence signal pin of the optical module in real time, performs debouncing processing on the input signal of the optical module presence pin, and inputs the debounced signal to the delay output circuit for a delay time, and then supplies power to the optical module.

[0073] The debouncing circuit and the delay circuit are not symmetrical in judging the presence and un-presence:

[0074] When the debouncing circuit monitors that the presence pin signal of the optical module is changed from a presence state to an un-presence state, if the un-presence state is maintained for 3 clocks, it is determined that the optical module is not present.

[0075] When the debouncing circuit monitors that the presence pin signal of the optical module is changed from an un-presence state to a presence state, and the presence state is maintained for 16 clocks, the debouncing circuit determines that the optical module is present.

[0076] In a preferred embodiment, S21 specifically comprises:

[0077] S211When the first precision delay circuit in the delay output circuit receives the optical module presence signal, it is determined whether the maintenance time of the optical module presence signal meets the first delay time; if it meets, a high voltage is outputted, which is used for controlling the second precision delay circuit in the delay output circuit to start working;

[0078] S212 When the second precision delay circuit is turned on, a high voltage is output according to a second delay time, for controlling power-on of the optical module.

[0079] In an actual embodiment, the output of the in-place signal is connected to the delay circuit; in order to save circuit resources, delay circuits of different precisions are cascaded, and the 100ns precision delay circuit is directly connected to the debounce circuit;

[0080] When the optical module is in place, the delay circuit starts counting, and outputs a high level after 50 clock rising edges; if the debounce circuit judges that the module is not in place during the counting, the counting is immediately emptied, and a low level is output.

[0081] The output is connected to another delay circuit of the same type but different precision, and the delay circuit realizes 150ms delay and then supplies power to the optical module.

[0082] In a preferred embodiment, the control method further comprises a power-off control step, which comprises:

[0083] S41 When the delay output circuit receives the optical module not-in-place signal, a low level is output, for controlling power-off of the optical module;

[0084] S42 When the optical module is powered off, the optical module configuration circuit pulls down the optical module reset signal and clears the timing register; wherein the timing register is used for timing the power-on time of the optical module.

[0085] In an actual embodiment, the delay output circuit (i.e. the delay circuit) receives the signal of the debounce circuit; when the not-in-place judgment of the debounce circuit is received, the timing register is immediately cleared, and a low level is output to control power-off of the optical module.

[0086] When the optical module is not powered on, the reset signal of the optical module remains low; 200ms after the optical module is powered on, the optical module reset signal is pulled high to enable normal startup of the optical module; when the circuit stops supplying power to the optical module, the optical module reset signal is pulled low, and the timing register is cleared.

[0087] In a preferred embodiment, the control method further comprises an upper-layer communication control step, which comprises:

[0088] S3 When the optical module reset signal is pulled high for a third preset time, the register interface in the CPLD sends optical module ready notification information to the CPU.

[0089] In actual embodiments, in the register interface module, the register interface provides an upper layer controller (CPU) to control the optical module power supply, reset signal interface. When the optical module reset signal is pulled high for 2s, the optical module considers that the internal MCU of the optical module has been started, writes a specific register, and synchronously notifies the CPU that the optical module is ready.

[0090] In a preferred embodiment, the control method further comprises an optical module information management step, which comprises at least one of the following:

[0091] The CPLD accesses and obtains the configuration information of the optical module through the integrated circuit bus;

[0092] When the optical module is in place and stable, the CPLD reads the voltage and current information of the optical module;

[0093] The CPLD judges the compatibility of the optical module;

[0094] The CPLD regularly monitors the temperature of the optical module; when the temperature of the optical module is too high, an interrupt signal is sent through the upper CPU.

[0095] In actual embodiments, the circuit can also access more related information about the optical module through i2c; after the optical module is in place and stable, the voltage and current information of the optical module is read, the compatibility of the optical module is judged, the temperature of the optical module is regularly monitored, and an interrupt is sent to the CPU when the temperature of the optical module is too high.

[0096] In actual embodiments, the above-mentioned optical module control method can be realized by managing the hardware circuit of the optical module, and the management mode includes the following:

[0097] 1. Monitoring function: The hardware monitors the interrupt signal of the optical module; when the interrupt occurs, the signal is reported to the upper processor.

[0098] 2. Optical module configuration function: It can reset the optical module according to the in-place state of the optical module, control the light-emitting of the optical module laser, etc.

[0099] 3. Hot plug control circuit: used to control the safe insertion and removal operation of the optical module, to avoid damage to the switch system and the optical module.

[0100] The main module design of the circuit is as follows:

[0101] 1) Optical module in-place monitoring circuit

[0102] The circuit monitors the in-place signal pin of the optical module in real time, and performs debouncing processing on the input signal of the optical module in-place pin. After the debounced signal is input into the delay output circuit for a period of time, the optical module is powered.

[0103] The de-bouncing circuit and the delay circuit are not symmetrical in judging the in-place and not-in-place.

[0104] When the de-bouncing circuit monitors that the in-place pin signal of the optical module changes from the in-place state to the not-in-place state, if the not-in-place state lasts for 3 clocks, the judging module is not in place.

[0105] When the de-bouncing circuit monitors that the in-place signal pin of the optical module changes from the not-in-place state to the in-place state, and the in-place state lasts for 16 clocks, the de-bouncing circuit judges that the optical module is in place.

[0106] The delay output circuit (i.e. the delay circuit) receives the signal of the de-bouncing circuit; when receiving the in-place judgment of the de-bouncing circuit, the delay output circuit outputs a high level for 100 ms to control the power-on of the optical module; when receiving the not-in-place judgment of the de-bouncing circuit, the delay output circuit immediately clears the timing register and outputs a low level to control the power-off of the optical module.

[0107] 2) Timing sequence of the optical module configuration signal

[0108] When the optical module is not powered on, the reset signal of the optical module remains low.

[0109] After 200 ms of the power-on of the optical module, the reset signal of the optical module is pulled high to make the optical module start normally.

[0110] When the circuit stops supplying power to the optical module, the reset signal of the optical module is pulled low and the timing register is cleared.

[0111] 3) Register interface module

[0112] The register interface provides the interface of the upper controller (CPU) controlling the power supply and the reset signal of the optical module. When the reset signal of the optical module is pulled high for 2 s, the optical module considers that the internal MCU of the optical module has started, writes a high specific register, and synchronously notifies the CPU that the optical module is ready.

[0113] The specific implementation scheme of the de-bouncing circuit and the delay circuit is as follows:

[0114] In order to ensure real-time monitoring of the in-place information of the optical module, the clock of the in-place de-bouncing circuit of the optical module is set to 20 ns.

[0115] When the rising edges of 3 continuous clocks are all detected as high of the in-place signal of the optical module, the de-bouncing circuit judges that the optical module is not in place.

[0116] When the rising edges of 16 continuous clocks are all detected as low of the in-place signal of the optical module, the de-bouncing circuit judges that the optical module is in place.

[0117] The output of the in-place signal is connected to a delay circuit; in order to save circuit resources, delay circuits with different precisions are cascaded, and the delay circuit directly connected to the debouncing circuit is a 100ns precision delay circuit;

[0118] When the optical module is in place, the delay circuit starts counting, and outputs a high level after 50 clock rising edges; if the debouncing circuit determines that the module is not in place during the counting, the counting is immediately cleared, and a low level is output.

[0119] The output is connected to another delay circuit of the same type but different precision, and the delay circuit realizes a 150ms delay and then supplies power to the optical module;

[0120] After the optical module is stably powered for 200ms, the reset_n pin of the optical module is pulled high, so that the single-chip microcomputer of the optical module starts to work; after 2s, it is considered that the single-chip microcomputer has been started, and the in-place information of the optical module is transmitted to the CPU through a specific register.

[0121] In summary, the control method of the optical module provided by the embodiment of the application has the following advantages:

[0122] 1) The power-on and power-off processes of the optical module are not symmetrical through the debouncing circuit and the delay circuit;

[0123] When the optical module is pulled out, the circuit can power off the optical module in 1ms, ensuring the stability of the switch system when the optical module is pulled out.

[0124] The optical module is powered for 150ms after being in place and stable, which can avoid the repeated switching of the power supply and ensure the stability and safety of the optical module.

[0125] 2) The time sequence control of the optical module is realized through the cascade of delay circuits with different precisions, which saves circuit resources while ensuring the accuracy of the circuit and the stability of the system.

[0126] 3) The real-time control and delay control of the related modules are realized through the CPLD, which improves the CPU usage efficiency of the switch system.

[0127] It can be seen that the control method of the optical module has the following beneficial effects:

[0128] Through the stable and reliable optical module control hardware circuit, the in-place state of the optical module can be monitored in real time;

[0129] Compared with the traditional MCU directly controlling the optical module, the CPLD circuit can automatically power the optical module and configure the related information of the optical module (such as initializing the optical module), which assists the upper controller to complete the real-time processing of the simple module, and can effectively improve the usage efficiency of the upper controller.

[0130] Compared with the traditional method, the above design is more stable in the aspect of hot plug function, and effectively improves the flexibility and stability of the switch system.

[0131] It should be noted that the above control method of the optical module can also be applied to other hot plug modules requiring specific timing; using the above hardware circuit, the power supply, initial information configuration and state monitoring of the module can be automatically completed, which can effectively improve the efficiency of the processor and the stability of the system.

[0132] It should be noted that although each step in the flowchart is displayed in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise stated herein, there is no strict order limitation for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0133] Embodiment two:

[0134] As shown in Figure 2 The application embodiment further provides a control device of the optical module for implementing the above control method of the optical module, the control device comprising a delay output circuit in the CPLD, an optical module configuration circuit in the CPLD;

[0135] The delay output circuit is configured to output a high level according to a first preset time delay when receiving the optical module in-place signal, for controlling power-on of the optical module.

[0136] The optical module configuration circuit is configured to pull up the optical module reset signal when the power-on time of the optical module reaches a second preset time, for controlling normal start of the optical module.

[0137] In a preferred embodiment, the control device further comprises an in-place monitoring unit comprising an in-place monitoring circuit in the CPLD;

[0138] The in-place monitoring circuit is configured to monitor the in-place signal pin of the optical module in real time; a debouncing circuit in the in-place monitoring circuit is configured to perform voltage debouncing processing on the in-place pin signal on the in-place signal pin.

[0139] When the debounced in-place pin signal is changed from the out-of-place state to the in-place state and the in-place state is maintained for a first preset clock, the in-place monitoring circuit is configured to determine that the optical module is in place and output the optical module in-place signal to the delay output circuit.

[0140] When the de-burred in-situ pin signal is changed from the in-situ state to the out-of-situ state and the out-of-situ state is maintained for a second preset clock, the in-situ monitoring circuit is used to determine that the optical module is out of situ and output an optical module out-of-situ signal to the delay output circuit.

[0141] In a preferred embodiment, the delay output circuit comprises a first precision delay circuit and a second precision delay circuit.

[0142] The first precision delay circuit is used to determine whether the maintenance time of the optical module in-situ signal meets a first delay time when the optical module in-situ signal is received, and output a high voltage for controlling the second precision delay circuit in the delay output circuit to start working if the maintenance time meets the first delay time.

[0143] The second precision delay circuit is used to output a high voltage for controlling the power-on of the optical module according to a second delay time after starting working.

[0144] In a preferred embodiment, the control device further comprises a power-off control unit comprising the delay output circuit and an optical module configuration circuit.

[0145] The delay output circuit is used to output a low voltage for controlling the power-off of the optical module when the optical module out-of-situ signal is received.

[0146] The optical module configuration circuit is used to pull down the optical module reset signal and clear a timing register when the optical module is powered off, wherein the timing register is used to time the power-on time of the optical module.

[0147] In a preferred embodiment, the control device further comprises an upper-layer communication control unit comprising a register interface in the CPLD, and the register interface is used to:

[0148] When the optical module reset signal is pulled high for a third preset time, the CPU is informed of a ready notification information of the optical module.

[0149] In a preferred embodiment, the control device further comprises an optical module information management unit used for at least one of the following:

[0150] The CPLD accesses and acquires the configuration information of the optical module through an integrated circuit bus;

[0151] When the optical module is in situ and stable, the CPLD reads the voltage and current information of the optical module;

[0152] The CPLD determines the compatibility of the optical module;

[0153] The CPLD periodically monitors the temperature of the optical module, and sends an interrupt signal to the upper-layer CPU when the temperature of the optical module is too high.

[0154] For specific limitations on the aforementioned apparatus, please refer to the limitations on the method described above, which will not be repeated here.

[0155] Each module in the aforementioned device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0156] Among them, such as Figure 3 As shown, the aforementioned computer device can be a terminal, comprising a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. The display screen can be an LCD screen or an e-ink display screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse, etc.

[0157] It is understood that the structures shown in the above figures are merely block diagrams of some structures related to the present invention and do not constitute a limitation on the computer device to which the present invention is applied. Specific computer devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0158] The implementation of all or part of the processes in the methods of the above embodiments can be accomplished by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods.

[0159] Any reference to storage, memory or a database herein can thus include a non-transitory and / or transitory memory. Non-transitory memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), and / or flash memory. Transitory memory can include random access memory (RAM), and / or an external cache memory. By way of illustration, and not limitation, RAM is available at various speeds such as, for example, Low Power Double Data Rate (LPDDR), Double Data Rate (DDR), and / or Double Data Rate 2 (DDR2). Non-limiting examples of a database can include a relational, columnar, correlation, and / or object database.

[0160] It is noted that the foregoing examples have been provided merely for the purposes of illustration and are not intended to limit the application of the application. Other freely selectable variations, modifications, and alternatives are possible in light of the foregoing teachings. It is therefore to be understood that, within the scope of the claims and their equivalents, the application can be practiced otherwise than as specifically described. While the application has been described with reference to exemplary embodiments, it is to be understood that the application is not limited to the disclosed exemplary embodiments. Rather, it is the intention that additions, deletions, modifications, and substitutions not specifically described are to be considered as falling within the scope of the claims and their equivalents.

Claims

1. A control method of an optical module, characterized by, The application discloses a control method for controlling and managing an optical module in a switch system through a programmed CPLD, and the programmed CPLD comprises an in-position monitoring circuit, a delay output circuit and an optical module configuration circuit. The in-position monitoring circuit monitors an in-position signal pin of the optical module in real time; a debouncing circuit in the in-position monitoring circuit performs voltage debouncing processing on the in-position pin signal on the in-position signal pin. When the debouncing circuit monitors that the in-position pin signal of the optical module after debouncing is changed from an out-of-position state to an in-position state and the in-position state is maintained for a first preset clock, the debouncing circuit judges that the optical module is in position and outputs an optical module in-position signal to the delay output circuit. When the debouncing circuit monitors that the in-position pin signal of the optical module after debouncing is changed from the in-position state to the out-of-position state and the out-of-position state is maintained for a second preset clock, the debouncing circuit judges that the optical module is out of position and outputs an optical module out-of-position signal to the delay output circuit. When a first precision delay circuit in the delay output circuit receives the optical module in-position signal, whether the maintaining time of the optical module in-position signal satisfies a first delay time is judged; if yes, a high voltage is outputted, which is used for controlling a second precision delay circuit in the delay output circuit to start working. When the second precision delay circuit starts working, the high voltage is outputted according to a second delay time, which is used for controlling power-on of the optical module. When the power-on time of the optical module reaches a second preset time, an optical module reset signal is pulled high by the optical module configuration circuit, which is used for controlling normal starting of the optical module.

2. The control method of the optical module according to claim 1, characterized by, The control method further comprises a power-off control step, which comprises: When the delay output circuit receives the optical module out-of-position signal, a low voltage is outputted, which is used for controlling power-off of the optical module. When the optical module is powered off, the optical module reset signal is pulled low by the optical module configuration circuit and a timing register is cleared; wherein the timing register is used for timing the power-on time of the optical module.

3. The control method of the optical module according to claim 2, characterized by, The control method further comprises an upper-layer communication control step, which comprises: When the optical module reset signal is pulled high for a third preset time, a register interface in the CPLD sends optical module ready notification information to a CPU.

4. The control method of the optical module according to claim 1, characterized by, The control method further comprises an optical module information management step, which comprises at least one of the following: The CPLD accesses and acquires configuration information of the optical module through an integrated circuit bus; When the optical module is in position and stable, the CPLD reads voltage and current information of the optical module; The CPLD judges the compatibility of the optical module; The CPLD periodically monitors the temperature of the optical module; When the temperature of the optical module is too high, an interrupt signal is sent through the upper-layer CPU.

5. The control method of the light module according to claim 1, characterized by, The second preset time is 200 ms.

6. A control device of an optical module, characterized by comprising: The application further discloses a control device for realizing the control method of the optical module, and the control device comprises an in-position monitoring circuit in a CPLD, a delay output circuit in the CPLD and an optical module configuration circuit in the CPLD. The in-situ monitoring circuit is used for monitoring the in-situ signal pin of the optical module in real time; a debouncing circuit in the in-situ monitoring circuit performs voltage debouncing on the in-situ pin signal on the in-situ signal pin; when the debouncing circuit monitors that the in-situ pin signal of the optical module after debouncing changes from an out-of-situ state to an in-situ state, and the in-situ state is maintained for a first preset clock, the debouncing circuit determines that the optical module is in-situ, and outputs an optical module in-situ signal to the delay output circuit; When the debouncing circuit monitors that the in-situ pin signal of the optical module after debouncing changes from an in-situ state to an out-of-situ state, and the in-situ state is maintained for a second preset clock, the debouncing circuit determines that the optical module is out-of-situ, and outputs an optical module out-of-situ signal to the delay output circuit; The delay output circuit is used for: when a first precision delay circuit in the delay output circuit receives the optical module in-situ signal, determining whether the maintenance time of the optical module in-situ signal satisfies a first delay time; If yes, a high voltage is outputted for controlling a second precision delay circuit in the delay output circuit to start working. The optical module configuration circuit is used for: when the power-on time of the optical module reaches a second preset time, pulling up an optical module reset signal for controlling the optical module to start normally.

7. A computer device comprising a memory, a processor and a computer program, the computer program being stored on the memory and being executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the control method of the optical module according to any one of claims 1-5.

8. A computer-readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the control method of the optical module according to any one of claims 1-5.

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