Amplifier and control method thereof, electronic device

Abstract

The application provides an amplifier and a control method thereof and an electronic device, and aims to improve the linearity of the amplifier. The amplifier comprises a first amplification circuit, a second amplification circuit, a first diode, a first adjustable bias voltage end, a first load, a node, a signal input end, a signal output end, a power voltage end, a second adjustable bias voltage end and a ground end. The input end of the first amplification circuit is coupled with the signal input end and the first adjustable bias voltage end. The output end of the first amplification circuit is coupled with the input end of the second amplification circuit. The output end of the second amplification circuit is coupled with the first load and the signal output end. One end of the first amplification circuit is coupled with the ground end. The control end of the second amplification circuit is coupled with the second adjustable bias voltage end. The output end of the first amplification circuit and the input end of the second amplification circuit are coupled with the node. The positive pole of the first diode is coupled with the node. The negative pole of the first diode is coupled with the ground end. The other end of the first load is coupled with the power voltage end.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to an amplifier and a control method thereof, and an electronic device. BACKGROUND

[0002] With the development of wireless communication systems, amplifiers have been widely used in various electronic devices, such as wireless transceivers, for amplifying signals. In some electronic devices, it is required that the amplifier should have high linearity and other characteristics to avoid the quality of the output signal deteriorating. Therefore, improving the linearity of the amplifier is an urgent problem to be solved in the field of amplifier research. SUMMARY

[0003] Embodiments of the present application provide an amplifier and a control method thereof, and an electronic device, for improving the linearity of the amplifier.

[0004] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0005] In a first aspect, an amplifier is provided, which comprises a first amplification circuit, a second amplification circuit, a first diode, a first adjustable bias voltage terminal, a first load, a node, a signal input terminal, a signal output terminal, a power voltage terminal, a second adjustable bias voltage terminal and a ground terminal. The input terminal of the first amplification circuit is coupled to the signal input terminal and the first adjustable bias voltage terminal, the first adjustable bias voltage terminal provides an adjustable first bias voltage for the first amplification circuit, the output terminal of the first amplification circuit is coupled to the input terminal of the second amplification circuit, and the output terminal of the second amplification circuit is coupled to one end of the first load and the signal output terminal; one end of the first amplification circuit is also coupled to the ground terminal; the control terminal of the second amplification circuit is coupled to the second adjustable bias voltage terminal, and the second adjustable bias voltage terminal provides an adjustable second bias voltage for the second amplification circuit; wherein the input terminal of the first amplification circuit receives a radio frequency signal provided by the signal input terminal, the first amplification circuit amplifies the radio frequency signal and outputs the amplified signal to the input terminal of the second amplification circuit, the input terminal of the second amplification circuit receives the signal output by the output terminal of the first amplification circuit, and the second amplification circuit amplifies the signal and provides the amplified signal to the signal output terminal; the output terminal of the first amplification circuit and the input terminal of the second amplification circuit are coupled to the node, the positive electrode of the first diode is coupled to the node, and the negative electrode of the first diode is coupled to the ground terminal; the other end of the first load is coupled to the power voltage terminal. Since the positive electrode of the first diode is coupled to the node and the negative electrode is coupled to the ground terminal, the first diode is in forward conduction. On this basis, since the third-order transconductance characteristics of the diode and the third-order transconductance characteristics of the transistor can be complementary, the linear characteristics of the first diode and the linear characteristics of the first amplification circuit (mainly composed of a transistor) can be complementary. By means of the adjustable first bias voltage provided by the first adjustable bias voltage terminal and the adjustable second bias voltage provided by the second adjustable bias voltage terminal, the linear characteristics of the first amplification circuit and the linear characteristics of the first diode can be further matched. Therefore, by arranging the first amplification circuit and the first diode in the amplifier, the performance of the amplifier can be optimized, and the overall linearity of the amplifier can be improved.

[0006] In a possible implementation of the first aspect, the amplifier further comprises a second load, and the second load and the first diode are connected in series between the node and the ground terminal. Here, the third-order transconductance characteristics of the first amplification circuit can be complemented by the common third-order transconductance characteristics of the first diode and the second load.

[0007] In a possible implementation of the first aspect, the second load is a variable resistor. In this way, the third-order transconductance characteristics of the adjustment circuit (i.e., the first diode and the second load) can be adjusted more quickly and flexibly by adjusting the second bias voltage provided by the second adjustable bias voltage terminal and adjusting the resistance value of the variable resistor R.

[0008] In a possible implementation of the first aspect, the amplifier further includes a second diode, a positive electrode of the second diode being coupled to the node, and a negative electrode of the second diode being coupled to the ground terminal; the first diode and the second diode are connected in series or in parallel between the node and the ground terminal. Since the positive electrode of the second diode is coupled to the node and the negative electrode of the second diode is coupled to the ground terminal, the second diode always works in the saturation region. In the case where the amplifier does not include the second load, the second bias voltage provided by the second adjustable bias voltage terminal can adjust the third-order transconductance characteristic of the first diode and the first diode as a whole. In the case where the amplifier includes the second load, the second bias voltage provided by the second adjustable bias voltage terminal and the resistance value of the second load together adjust the third-order transconductance characteristic of the first diode, the first diode and the second load as a whole.

[0009] In a possible implementation of the first aspect, the amplifier further includes a third load, one end of the third load being coupled to the first amplification circuit, and the other end of the third load being coupled to the ground terminal. The third load can be used to adjust the gain of the amplifier.

[0010] In a possible implementation of the first aspect, the third load is an inductor.

[0011] In a possible implementation of the first aspect, the first amplification circuit includes a first transistor, a gate of the first transistor being coupled to the signal input terminal and the first adjustable bias voltage terminal respectively, a first pole of the first transistor being coupled to the node, and a second pole of the first transistor being coupled to the ground terminal; wherein one of the first pole and the second pole of the first transistor is a source, and the other is a drain.

[0012] In a possible implementation of the first aspect, the second amplification circuit includes a second transistor, a gate of the second transistor being coupled to the second adjustable bias voltage terminal, a first pole of the second transistor being coupled to the signal output terminal, and a second pole of the second transistor being coupled to the node; wherein one of the first pole and the second pole of the second transistor is a source, and the other is a drain.

[0013] In a possible implementation of the first aspect, the amplifier further includes a first bias voltage generation circuit, an output terminal of the first bias voltage generation circuit being coupled to the first adjustable bias voltage terminal, for providing the first adjustable bias voltage terminal with a first bias voltage. The first bias voltage generation circuit can provide the first adjustable bias voltage terminal with a suitable first bias voltage as required.

[0014] In a possible implementation of the first aspect, the amplifier further includes a second bias voltage generation circuit, an output terminal of the second bias voltage generation circuit being coupled to the second adjustable bias voltage terminal, for providing the second adjustable bias voltage terminal with a second bias voltage. The second bias voltage generation circuit can provide the second adjustable bias voltage terminal with a suitable second bias voltage as required.

[0015] In a possible implementation of the first aspect, the amplifier further includes a feedback circuit coupled to the signal input terminal and the signal output terminal respectively, configured to feedback the signal amplified by the first amplification circuit and the second amplification circuit. The feedback circuit can broaden the working bandwidth of the amplifier.

[0016] In a possible implementation of the first aspect, the feedback circuit includes a feedback capacitor and a feedback resistor connected in series.

[0017] In a second aspect, an amplifier is provided, which includes a first amplification circuit, a second amplification circuit, an adjusting circuit, a first adjustable bias voltage terminal, a first load, a node, a signal input terminal, a signal output terminal, a power voltage terminal, a second adjustable bias voltage terminal and a ground terminal. The first amplification circuit is coupled to the node, the signal input terminal, the ground terminal and the first adjustable bias voltage terminal respectively; the second amplification circuit is coupled to the node, the signal output terminal and the second adjustable bias voltage terminal respectively; the adjusting circuit is coupled to the node and the ground terminal respectively; one end of the first load is coupled to the power voltage terminal, and the other end is coupled to the signal output terminal; wherein one of the third-order transconductance coefficient of the first amplification circuit working in the saturation region and the third-order transconductance coefficient of the adjusting circuit working in the saturation region is positive, and the other is negative. Since the first amplification circuit works in the saturation region, the actual third-order transconductance coefficient g 3M of the first amplification circuit and the actual third-order transconductance coefficient g 3D of the adjusting circuit can be accurately fitted and covered. Based on this, in the amplifier provided in the embodiments of the present application, since one of the third-order transconductance coefficient g3M of the first amplification circuit working in the saturation region and the third-order transconductance coefficient g3D of the adjusting circuit working in the saturation region is positive, and the other is negative, one of the actual third-order transconductance coefficient g3M of the first amplification circuit working in the saturation region and the actual third-order transconductance coefficient g3D of the adjusting circuit working in the saturation region is positive, and the other is negative, so the actual third-order transconductance coefficient g3M of the first amplification circuit working in the saturation region and the actual third-order transconductance coefficient g3D of the adjusting circuit working in the saturation region can be nonlinearly superimposed and offset, thereby improving the overall linearity of the amplifier.

[0018] In a possible implementation of the second aspect, the absolute value of the third-order transconductance coefficient of the first amplification circuit working in the saturation region is equal to the absolute value of the third-order transconductance coefficient of the adjusting circuit working in the saturation region. In this way, the sum g 3M of the actual third-order transconductance coefficient g 3D of the first diode and the actual third-order transconductance coefficient g 3 of the second diode tends to 0, thereby further improving the overall linearity of the amplifier.

[0019] Thirdly, an electronic device is provided, comprising a fourth load, a processor, and the amplifier provided in the first aspect; the fourth load is coupled to the signal output terminal of the amplifier, and the processor is coupled to the amplifier. Refer to the relevant description in the first aspect above; further details are omitted here.

[0020] Fourthly, a method for controlling an amplifier is provided, wherein the amplifier includes: a first amplifier circuit, a second amplifier circuit, a first diode, a first adjustable bias voltage terminal, a first load, a node, a signal input terminal, a signal output terminal, a power supply voltage terminal, a second adjustable bias voltage terminal, and a ground terminal; the input terminal of the first amplifier circuit is coupled to both the signal input terminal and the first adjustable bias voltage terminal, the first adjustable bias voltage terminal providing an adjustable first bias voltage to the first amplifier circuit; the output terminal of the first amplifier circuit is coupled to the input terminal of the second amplifier circuit, and the output terminal of the second amplifier circuit is coupled to one end of the first load and the signal output terminal; one end of the first amplifier circuit is also coupled to the ground terminal; the control terminal of the second amplifier circuit is coupled to the second adjustable bias voltage terminal, the second adjustable bias voltage terminal providing an adjustable second bias voltage to the second amplifier circuit; wherein the input terminal of the first amplifier circuit receives a radio frequency signal provided by the signal input terminal, and the first amplifier circuit transmits... The frequency signal is amplified and output to the input terminal of the second amplifier circuit. The input terminal of the second amplifier circuit receives the signal output from the output terminal of the first amplifier circuit. The second amplifier circuit amplifies the signal and provides it to the signal output terminal. The output terminal of the first amplifier circuit and the input terminal of the second amplifier circuit are coupled to a node. The anode of the first diode is coupled to the node, and the cathode of the first diode is coupled to the ground terminal. The other end of the first load is coupled to the power supply voltage terminal. The amplifier control method includes: the first adjustable bias voltage terminal receiving a first bias voltage to make the first amplifier circuit operate in the saturation region; the second adjustable bias voltage terminal receiving a second bias voltage; wherein, the first bias voltage is used to make the third-order transconductance coefficient of the first amplifier circuit operate in the saturation region, which is called the first third-order transconductance coefficient; the second bias voltage is used to make the third-order transconductance coefficient of the first diode operate in the saturation region, which is called the second third-order transconductance coefficient. One of the first third-order transconductance coefficient and the second third-order transconductance coefficient is positive, and the other is negative. Refer to the relevant description in the second aspect above; it will not be repeated here.

[0021] In a possible implementation of the fourth aspect, the absolute value of the first third-order transconductance coefficient of the first amplifier circuit operating in the saturation region is equal to the absolute value of the second third-order transconductance coefficient of the first diode operating in the saturation region. Thus, the actual third-order transconductance coefficient g of the first amplifier circuit is... 3M And the actual third-order transconductance coefficient g of the first diode 3D The sum of g 3 The linearity tends to 0, which can further improve the overall linearity of the amplifier.

[0022] In a possible implementation of the fourth aspect, the amplifier further comprises: a second load; the second load and the first diode are connected in series between the node and the ground terminal; wherein the second load is a variable resistor. The second bias voltage is used to operate the first diode and the second load in the saturation region, and the third-order transconductance coefficient of the second bias voltage is a second third-order transconductance coefficient. In this way, the second third-order transconductance coefficient can be adjusted by adjusting the second bias voltage and adjusting the resistance value of the variable resistor. In this way, the size of the second third-order transconductance coefficient can be adjusted more quickly and more flexibly. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A structural schematic diagram of an amplifier provided by the related art;

[0024] Figure 2 A relationship curve of the bias voltage V GS and the third-order transconductance coefficient g 3A , the third-order transconductance coefficient g 3B , and the third-order transconductance coefficient g 3A , and the third-order transconductance coefficient g 3B ;

[0025] Figure 3 A structural schematic diagram of an amplifier provided by an embodiment of the present application;

[0026] Figure 4 A structural schematic diagram of an amplifier provided by another embodiment of the present application;

[0027] Figure 5 A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0028] Figure 6a A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0029] Figure 6b A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0030] Figure 6c A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0031] Figure 7 A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0032] Figure 8 A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0033] Figure 9 A structural schematic diagram of an amplifier provided by yet another embodiment of the present application;

[0034] Figure 10 A flowchart of a control method of an amplifier provided for an embodiment of the present application is shown in the figure;

[0035] Figure 11 A structural diagram of an electronic device provided for an embodiment of the present application is shown in the figure.

[0036] Reference numerals: 1-amplifier; 2-fourth load; 10-first amplification circuit; 20-second amplification circuit; 30-regulation circuit; 40-first load; 50-third load; 60-feedback circuit; 301-second load. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0038] Hereinafter, the terms “first”, “second”, and the like are used only for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first”, “second”, and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of “a plurality of” is two or more.

[0039] In the embodiments of the present application, the words “exemplary” or “for example” are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of “exemplary” or “for example” is intended to present relevant concepts in a specific manner.

[0040] In the embodiments of the present application, “and / or” describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character “ / ” generally represents a “or” relationship between the associated objects before and after it.

[0041] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term “coupling” can be a mode of electrical connection for realizing signal transmission. “Coupling” can be a direct electrical connection, or an indirect electrical connection through an intermediate medium. For example, a connection realized through a resistor, an inductor, or other electrical elements.

[0042] With the development of wireless communication systems, amplifiers have been widely used in various electronic devices for amplifying signals. In some electronic devices, it is required that the amplifier should have high linearity and other characteristics to avoid the quality of the output signal from deteriorating.

[0043] For any memoryless analog and radio frequency circuit, its nonlinear small signal model can be used to characterize the input and output characteristics of the circuit (mainly considering up to the third order) as follows:

[0044] y(t)≈α1x(t)+α2x 2 (t)+α3x 3 (t)

[0045] Where x(t) is the input signal of the circuit, and y(t) is the output signal of the circuit.

[0046] Referring to the above characterization, the output current (i.e. drain-source current) i ds of a single transistor is related to the input voltage (i.e. gate-source voltage) v gs The expression is:

[0047] i ds =g1v gs +g2v 2 gs +g3v 3 gs

[0048] Where g1 is the small signal linear transconductance coefficient, g2 is the second order transconductance coefficient, and g3 is the third order transconductance coefficient.

[0049] The linearity IIP3 of a single transistor is related to the small signal linear transconductance coefficient g1 and the third order transconductance coefficient g3, and the amplitude A IIP3 of the linearity IIP3 of the transistor can be represented as:

[0050]

[0051] A IIP3 can represent the linearity IIP3 of the transistor, and the greater the value of A IIP3 , the higher the linearity IIP3 of the transistor. In order to obtain higher linearity of the transistor, the third order transconductance coefficient g3 can be made to tend to 0.

[0052] In order to improve the linearity of the existing amplifier, the related technology provides an amplifier, such as Figure 1As shown, the amplifier comprises a transistor MA, a transistor MB, a capacitor C, an inductor L, a signal input terminal RFIN, a signal output terminal RFOUT, a bias voltage terminal Vbias1, a bias voltage terminal Vbias2, a power voltage terminal VDD and a ground terminal GND. The gate of the transistor MA is coupled with the signal input terminal RFIN and the bias voltage terminal Vbias1 respectively, the first pole of the transistor MA is coupled with the signal output terminal RFOUT, and the second pole of the transistor MA is coupled with the ground terminal GND. The gate of the transistor MB is coupled with the first end of the capacitor C and the bias voltage terminal Vbias2, the first pole of the transistor MB is coupled with the signal output terminal RFOUT, and the second pole of the transistor MB is coupled with the ground terminal GND. The second end of the capacitor C is coupled with the signal input terminal RFIN and the bias voltage terminal Vbias1 respectively. The signal output terminal RFOUT is further coupled with one end of the inductor L, and the other end of the inductor L is coupled with the power voltage terminal VDD. Here, the first pole of the transistor MA and the transistor MB is the source, and the second pole is the drain; or, the first pole of the transistor MA and the transistor MB is the drain, and the second pole is the source.

[0053] For Figure 1 the amplifier as shown, the transistor MA and the transistor MB can be regarded as a whole, so that the amplitude A of the linearity IIP3 of the amplifier IIP3 is wherein g1 in the formula is equal to the sum of the small-signal linear transconductance coefficients g 1A and g 1B of the transistor MA and the transistor MB, i.e. g1=g 1A +g 1B , g3 in the formula is equal to the sum of the third-order transconductance coefficients g 3A and g 3B of the transistor MA and the transistor MB, i.e. g3=g 3A +g 3B . Based on this, making the sum g3 of the third-order transconductance coefficient g 3A of the transistor MA and the third-order transconductance coefficient g 3B of the transistor MB tend to 0, the linearity of the amplifier can be higher.

[0054] For Figure 1 the amplifier as shown, the size of the bias voltage V GS provided by the bias voltage terminal Vbias1 will affect the third-order transconductance coefficient g 3A of the transistor MA, and the size of the bias voltage V GS provided by the bias voltage terminal Vbias2 will affect the third-order transconductance coefficient g 3B of the transistor MB. Figure 2 The bias voltage V GS and the third-order transconductance coefficient g3A Third-order transconductance coefficient g 3B and the third-order transconductance coefficient g 3A and third-order transconductance coefficient g 3B The relationship curve between g and g3, Figure 2 The horizontal axis represents the bias voltage V provided by bias voltage terminals Vbias1 and Vbias2. GS The vertical axis represents the third-order transconductance coefficient g. 3A Third-order transconductance coefficient g 3B and the third-order transconductance coefficient g 3A and third-order transconductance coefficient g 3B The sum of g3. (By) Figure 2 The provided relationship curves show that, with different bias voltages V GS The choice of _____ causes the transistor MA to operate in the strong inversion region, which can also be called the saturation region. Figure 2 The bias voltage V shown GS With the third-order transconductance coefficient g 3A The position of the peak in the relationship curve, that is Figure 2 The position indicated by the dashed coil is such that transistor MB operates in the weak inversion region, i.e. Figure 2 The bias voltage V shown GS With the third-order transconductance coefficient g 3B The trough position in the relationship curve, that is Figure 2 The position indicated by the dashed coil indicates that at a certain bias voltage V GS Within the region, the third-order transconductance coefficient g 3A and third-order transconductance coefficient g 3B The sum of g3 approaches 0, which can improve the linearity of the amplifier.

[0055] However, as the above analysis shows, the amplifiers provided by related technologies improve linearity by requiring transistor MA to operate in the strong inversion region and transistor MB to operate in the weak inversion region. Generally speaking, when the transistor operates in the strong inversion region, research results indicate that the bias voltage V... GS The simulated curve of the relationship between the third-order transconductance coefficient g3 and the actual test curve show a good fit; however, when the transistor operates in the weak inversion region, according to the research results, the bias voltage V GS The simulated relationship curve for the third-order transconductance coefficient g3 differs significantly from the actual measured relationship curve. (Reference) Figure 2 In other words, the bias voltage V GS With the third-order transconductance coefficient g 3A The simulated relationship curve at the peak position is relatively consistent with the actual measured relationship curve at the peak position, but the bias voltage V GSWith the third-order transconductance coefficient g 3B The simulated relationship curve deviates from the actual tested relationship curve at the trough position. The trough position of the actual tested relationship curve may shift to the left or right. Therefore, the theoretically calculated value at a certain bias voltage V... GS Within the region, the third-order transconductance coefficient g 3A and third-order transconductance coefficient g 3B The sum of g3 tends towards 0; however, in reality, due to the bias voltage V... GS With the third-order transconductance coefficient g 3B The actual test relationship curve is offset at the trough position, therefore, at a certain theoretically calculated bias voltage V GS Within the region, the actual third-order transconductance coefficient g 3A and third-order transconductance coefficient g 3B The sum of g3 may not equal 0, which may result in the amplifier's linearity not being improved or only slightly.

[0056] To improve the linearity of an amplifier, embodiments of this application provide an amplifier, which may be, for example, a low-noise amplifier (LNA), a power amplifier (PA), a trans-impedance amplifier (TIA), or a variable gain amplifier (VGA).

[0057] like Figure 3 As shown, the amplifier 1 provided in the embodiments of this application includes: a first amplification circuit 10, a second amplification circuit 20, an adjustment circuit 30, a first adjustable bias voltage terminal Vb1, a first load 40, node A, a signal input terminal RFIN, a signal output terminal RFOUT, a power supply voltage terminal VDD, a second adjustable bias voltage terminal Vb2, and a ground terminal GND.

[0058] The input terminal of the first amplification circuit 10 is coupled with the signal input terminal RFIN and the first adjustable bias voltage terminal Vb1, the first adjustable bias voltage terminal Vb1 provides the first adjustable bias voltage Vb1 for the first amplification circuit 10, the output terminal of the first amplification circuit 10 is coupled with the input terminal of the second amplification circuit 20, the output terminal of the second amplification circuit 20 is coupled with one terminal of the first load 40 and the signal output terminal RFOUT, one terminal of the first amplification circuit 10 is also coupled with the ground terminal GND, the control terminal of the second amplification circuit 20 is coupled with the second adjustable bias voltage terminal Vb2, the second adjustable bias voltage terminal Vb2 provides the second adjustable bias voltage Vb2 for the second amplification circuit 20, wherein the input terminal of the first amplification circuit 10 receives the radio frequency signal provided by the signal input terminal RFIN, the first amplification circuit 10 amplifies the radio frequency signal and outputs the amplified signal to the input terminal of the second amplification circuit 20, the input terminal of the second amplification circuit 20 receives the signal outputted by the output terminal of the first amplification circuit 10, the second amplification circuit 20 amplifies the signal and provides the amplified signal to the signal output terminal RFOUT, the output terminal of the first amplification circuit 10 and the input terminal of the second amplification circuit 20 are coupled at the node A, one terminal of the adjusting circuit 30 is coupled with the node A and the other terminal is coupled with the ground terminal GND. The other terminal of the first load 40 is coupled with the power voltage terminal VDD, wherein the third order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region and the third order transconductance coefficient g 3D of the adjusting circuit 30 working in the saturation region are positive and negative. Here, the third order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region is positive and the third order transconductance coefficient g 3D of the adjusting circuit 30 working in the saturation region is negative; or the third order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region is negative and the third order transconductance coefficient g 3D of the adjusting circuit 30 working in the saturation region is positive.

[0059] It should be understood that the third order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region can be adjusted by the first bias voltage Vb1 provided by the first adjustable bias voltage terminal Vb1, the voltage of the node A can be adjusted by the second bias voltage provided by the second adjustable bias voltage terminal Vb2, so as to adjust the third order transconductance coefficient g 3D of the adjusting circuit 30 working in the saturation region, so that the third order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region and the third order transconductance coefficient g 3D of the adjusting circuit 30 working in the saturation region are positive and negative.

[0060] On this basis, the first adjustable bias voltage terminal Vb1 can be coupled with the output terminal of the first bias voltage generating circuit, and the first bias voltage Vb1 is provided for the first adjustable bias voltage terminal Vb1 through the first bias voltage generating circuit. The first bias voltage generating circuit can provide appropriate first bias voltage Vb1 for the first adjustable bias voltage terminal Vb1 as required. On this basis, the first bias voltage generating circuit can be integrated in the amplifier, and the first bias voltage generating circuit can also be additionally and independently arranged with respect to the amplifier. Similarly, the second adjustable bias voltage terminal Vb2 can be coupled with the output terminal of the second bias voltage generating circuit, and the second bias voltage Vb2 is provided for the second adjustable bias voltage terminal Vb2 through the second bias voltage generating circuit. The second bias voltage generating circuit can provide appropriate second bias voltage Vb2 for the second adjustable bias voltage terminal Vb2 as required. On this basis, the second bias voltage generating circuit can be integrated in the amplifier, and the second bias voltage generating circuit can also be additionally and independently arranged with respect to the amplifier.

[0061] It should be noted that, with reference to Figure 3 In the amplifier 1, the second amplification circuit 20 is coupled with the node A, the signal output terminal RFOUT and the second adjustable bias voltage terminal Vb2 respectively, and the second amplification circuit 20 is equivalent to a switch for controlling the conduction or disconnection of the node A and the signal output terminal RFOUT under the control of the second adjustable bias voltage terminal Vb2. Since the second amplification circuit 20 is equivalent to a switch, the second amplification circuit 20 will not affect the linearity of the amplifier 1, and the linearity of the amplifier 1 is mainly related to the linearity of the first amplification circuit 10 and the linearity of the adjustment circuit 30. Based on the above, the amplitude A IIP3 of the linearity IIP3 of the amplifier is IIP3 The greater the value of the linearity IIP3 of the amplifier 1, the higher the linearity IIP3 of the amplifier, and the amplitude A IIP3 of the linearity IIP3 of the amplifier is In the embodiment of the present application, the first amplification circuit 10 and the adjustment circuit 30 can be regarded as a whole, so that g1 is equal to the sum of the small signal linear transconductance coefficient g 1M of the first amplification circuit 10 and the small signal linear transconductance coefficient g 1D of the adjustment circuit 30, i.e. g1=g 1M +g 1D , and g3 is equal to the sum of the third order transconductance coefficient g 3M of the first amplification circuit 10 and the third order transconductance coefficient g 3D of the adjustment circuit 30, i.e. g3=g 3M +g 3D .

[0062] It should be understood that according to the research results, when the electronic device works in the saturation region, the bias voltage VGS The simulated relationship curve between the first bias voltage Vb1 and the third transconductance coefficient g3 can be accurately fitted and covered by the actual test relationship curve. Therefore, when the first amplifier circuit 10 operates in the saturation region, the first bias voltage Vb1 and the third transconductance coefficient g3 are closely related. 3M The simulated relationship curve can be accurately fitted and covered by the actual test relationship curve. When the adjustment circuit 30 is working in the saturation region, the second bias voltage Vb2 and the third transconductance coefficient g 3D The simulated relationship curves and the actual test relationship curves can be accurately fitted and covered. Based on this, in the amplifier 1 provided in this application embodiment, since the third transconductance coefficient g3M of the first amplification circuit 10 operates in the saturation region and the third transconductance coefficient g of the adjustment circuit 30 operates in the saturation region, 3D One is positive and the other is negative. Therefore, the actual third-order transconductance coefficient g3M of the first amplifier circuit 10 when operating in the saturation region and the actual third-order transconductance coefficient g3D of the adjustment circuit 30 when operating in the saturation region are both positive and negative. 3D Nonlinear superposition and cancellation can be performed, thereby reducing the third-order transconductance coefficient g of the first amplifier circuit 10. 3M and the third transconductance coefficient g of the regulating circuit 30 3D The sum of g3 decreases, and thus, according to the amplifier's linearity, the amplitude A of IIP3... IIP3 formula It can be seen that the linearity of the amplifier is related to the amplitude A of IIP3. IIP3 This increase ensures that the overall linearity of amplifier 1 is effectively improved.

[0063] It should be noted that the third-order transconductance coefficient g of the first amplifier circuit 10 operating in the saturation region 3M The absolute value of the third-order transconductance coefficient g3D of the first amplifier circuit 10 operating in the saturation region can be equal to or unequal to the absolute value of the third-order transconductance coefficient g3M of the first amplifier circuit 10 operating in the saturation region. 3 The third transconductance coefficient g3D of the regulating circuit 30 operating in the saturation region can be -0.2 A / N. 3 For example, the third-order transconductance g3M of the first amplifier circuit 10 operating in the saturation region can be 0.2 A / N. 3 The third-order transconductance coefficient g3D of the regulating circuit 30 operating in the saturation region can be -0.1 A / N. 3 .

[0064] To further improve the overall linearity of amplifier 1, in some examples, the third transconductance coefficient g of the first amplifier circuit 10 operates in the saturation region.3M The absolute value and the third transconductance coefficient g of the regulating circuit 30 operating in the saturation region 3D Their absolute values ​​are equal.

[0065] Since the first amplifier circuit 10 operates in the saturation region, the first bias voltage Vb1 and the third transconductance coefficient g 3M The simulated relationship curve can be accurately fitted and covered by the actual test relationship curve. When the adjustment circuit 30 is working in the saturation region, the second bias voltage Vb2 and the third transconductance coefficient g 3D The simulated relationship curve can be accurately fitted and covered by the actual test relationship curve. Therefore, when the first amplifier circuit 10 operates in the saturation region, the third transconductance coefficient g 3M The absolute value and the third transconductance coefficient g of the regulating circuit 30 operating in the saturation region 3D When the absolute values ​​are equal, the actual third-order transconductance coefficient g of the first amplifier circuit 10 when it is operating in the saturation region is... 3M The absolute value of the third-order transconductance coefficient g3D of the first amplifier circuit 10 when it is operating in the saturation region is equal to the absolute value of the actual third-order transconductance coefficient g3D of the first amplifier circuit 10 when it is operating in the saturation region. 3M The third transconductance coefficient g of the regulating circuit 30 operating in the saturation region 3D One is positive and the other is negative, therefore the actual third-order transconductance coefficient g of the first amplifier circuit 10 is... 3M And the actual third-order transconductance coefficient g of the regulating circuit 30 3D The sum of g3 approaches 0, thus, according to the amplifier's linearity, the amplitude A of IIP3... IIP3 formula It can be seen that the overall linearity of amplifier 1 can be further improved.

[0066] In some examples, such as Figure 3 As shown, the amplifier 1 also includes a first capacitor C1, one end of which is coupled to the signal input terminal RFIN, and the other end is coupled to the first amplifier circuit 10.

[0067] In some examples, such as Figure 3 As shown, the amplifier 1 also includes a second capacitor C2, one end of which is coupled to the signal output terminal RFOUT, and the other end is coupled to the second amplifier circuit 20.

[0068] The function of the first capacitor C1 and the second capacitor C2 mentioned above is to block the DC signal and allow the AC signal to pass through.

[0069] In some examples, such as Figure 4As shown, the first amplification circuit 10 includes a first transistor M1, a gate of the first transistor M1 is coupled with a signal input end RFIN and a first adjustable bias voltage end Vb1 respectively, a first pole of the first transistor M1 is coupled with a node A, and a second pole of the first transistor M1 is coupled with a ground end GND; wherein one of the first pole and the second pole of the first transistor M1 is a source, and the other is a drain.

[0070] The second pole of the first transistor M1 is coupled with the ground end GND, which can be that the second pole of the first transistor M1 is directly coupled with the ground end GND, or that the second pole of the first transistor M1 is indirectly coupled with the ground end GND through other electrical elements.

[0071] It should be noted that the first pole of the first transistor M1 can be the source, and the second pole can be the drain; or the first pole of the first transistor M1 can be the drain, and the second pole can be the source.

[0072] Here, the first transistor M1 can be a P-type tube or an N-type tube. In the case of the P-type tube, when the first adjustable bias voltage end Vb1 provides a low-level signal, the first transistor M1 is turned on. In the case of the N-type tube, when the first adjustable bias voltage end Vb1 provides a high-level signal, the first transistor M1 is turned on.

[0073] In addition, the first transistor M1 can be one of an enhancement mode (E-mode) transistor, a depletion mode (D-mode) transistor, or a cascode transistor.

[0074] In addition, the size of the first transistor M1 can be designed as needed.

[0075] On this basis, in some other examples, in addition to the first transistor M1, the first amplification circuit 10 can also include one or more other transistors in series or parallel with the first transistor M1.

[0076] In some examples, as shown, the second amplification circuit 20 includes a second transistor M2, a gate of the second transistor M2 is coupled with a second adjustable bias voltage end Vb2, a first pole of the second transistor M2 is coupled with a signal output end RFOUT, and a second pole of the second transistor M2 is coupled with the node A; wherein one of the first pole and the second pole of the second transistor M2 is a source, and the other is a drain. Figure 4 It should be noted that the first pole of the second transistor M2 can be the source, and the second pole can be the drain; or the first pole of the second transistor M2 can be the drain, and the second pole can be the source.

[0077]

[0078] ​Here, the second transistor M2 can be an N-type transistor. In the case where the second transistor M2 is an N-type transistor, when the second adjustable bias voltage terminal Vb2 provides a high-level signal, the second transistor M2 is turned on.

[0079] In addition, the second transistor M2 can be one of an enhancement mode transistor, a depletion mode transistor, or a common-source common-gate transistor.

[0080] In addition, the size of the second transistor M2 can be designed as needed.

[0081] On this basis, in other examples, in addition to the second transistor M2, the second amplification circuit 20 described above can also include one or more other transistors in series or parallel with the second transistor M2.

[0082] In some examples, the materials of the first transistor M1 and the second transistor M2 described above can include a group III-V compound.

[0083] The first load 40 described above can be one or more of an inductor Ld, a capacitor, or a resistor, for example, Figure 4 Taking the inductor Ld as the first load 40 for example.

[0084] The adjustment circuit 30 described above can exemplarily adopt the following implementation manners:

[0085] The first kind: as shown in Figure 4 The adjustment circuit 30 includes a first diode D1, the positive electrode of the first diode D1 is coupled with the node A, and the negative electrode of the first diode D1 is coupled with the ground terminal GND.

[0086] The "negative electrode of the first diode D1 is coupled with the ground terminal GND" can be that the negative electrode of the first diode D1 is directly coupled with the ground terminal GND, or that the negative electrode of the first diode D1 is indirectly coupled with the ground terminal GND through other electronic elements.

[0087] Here, when the first diode D1 is in the on state, based on the different types of the first diode D1, the positive electrode can be the signal input terminal, and the negative electrode can be the signal output terminal, that is, the signal flows from the positive electrode to the negative electrode; or the negative electrode can be the signal input terminal, and the positive electrode can be the signal output terminal, that is, the signal flows from the negative electrode to the positive electrode.

[0088] In addition, the threshold voltage Vth of the first diode D1 can be a positive number or a negative number.

[0089] Furthermore, the first diode D1 can be, for example, a Schottky diode or a common silicon diode. When the first diode D1 is a Schottky diode and the first transistor M1 is an enhancement-mode transistor, the first diode D1 and the first transistor M1 can be fabricated simultaneously using the same process, thereby simplifying the amplifier fabrication process.

[0090] Based on this, the first diode D1 can be either an enhancement-mode diode or a depletion-mode diode.

[0091] In this embodiment, the size of the first diode D1 is not limited and can be designed as needed.

[0092] Because the positive terminal of the first diode D1 is coupled to node A and the negative terminal is coupled to ground GND, the first diode D1 always operates in the saturation region. The third transconductance g of the first diode D1 operating in the saturation region can be adjusted by the second bias voltage provided by the second adjustable bias voltage terminal Vb2. 3D Size.

[0093] The second type: such as Figure 5 As shown, the regulating circuit 30 includes a first diode D1 and a second load 301. The positive terminal of the first diode D1 is coupled to node A, and the negative terminal of the first diode D1 is coupled to ground GND. The second load 301 and the first diode D1 are connected in series between node A and ground GND.

[0094] When the regulating circuit 30 includes a first diode D1 and a second load 301, the third-order transconductance coefficient g of the first diode D1 and the second load 301 operating in the saturation region can be adjusted jointly by the second bias voltage Vb2 provided by the second adjustable bias voltage terminal Vb2 and the second load 301. 3D The size of the value is such that the actual third-order transconductance coefficient g when the first amplifier circuit 10 operates in the saturation region. 3M The actual third-order transconductance coefficient g when the regulating circuit 30 operates in the saturation region. 3D Nonlinear superposition and cancellation can be performed to achieve the actual third-order transconductance coefficient g of the first amplifier circuit 10. 3M And the actual third-order transconductance coefficient g of the regulating circuit 30 3D The goal is for the sum of g3 to approach 0.

[0095] Here, the resistance value of the second load 301 can be fixed, and in this case, the value of the second load 301 is not limited. The resistance value of the second load 301 can also be variable, and in this case, the range of the resistance value of the second load 301 is not limited.

[0096] In addition, the second load 301 can be, for example, an inductor, a capacitor, or a resistor, etc. In order to be able to flexibly adjust the size of the third-order transconductance coefficient g 3D of the adjusting circuit 30 (i.e., the first diode D1 and the second load 301) working in the saturation region, in some examples, the resistance of the second load 301 is variable, for example, as shown in Figure 5 , the second load 301 is a variable resistor R, so that the size of the third-order transconductance coefficient g 3D of the adjusting circuit 30 (i.e., the first diode D1 and the second load 301) working in the saturation region can be adjusted more quickly and more flexibly by adjusting the second bias voltage Vb2 provided by the second adjustable bias voltage terminal Vb2 and adjusting the resistance of the variable resistor R, so that the actual third-order transconductance coefficient g 3M of the first amplification circuit 10 and the actual third-order transconductance coefficient g 3D of the adjusting circuit 30 tend to 0.

[0097] In examples, as shown in Figure 5 , when the third-order transconductance coefficient g 3M of the first transistor M1 working in the saturation region is positive within a certain bias region (i.e., the first bias voltage Vb1 is within a certain range), the third-order transconductance coefficient g 3D of the first diode D1 and the variable resistor R working in the saturation region as a whole can be made negative by adjusting the second bias voltage Vb2 provided by the second adjustable bias voltage terminal Vb2 and adjusting the resistance of the variable resistor R, and the sum of the third-order transconductance coefficient g 3M of the first transistor M1 and the third-order transconductance coefficient g 3D of the first diode D1 and the variable resistor R working in the saturation region as a whole tends to 0.

[0098] Thirdly, the adjusting circuit 30 further includes the first diode D1 and the second diode D2, the positive electrode of the first diode D1 is coupled with the node A, and the negative electrode of the first diode D1 is coupled with the ground terminal GND; the positive electrode of the second diode D2 is coupled with the node A, and the negative electrode of the second diode D2 is coupled with the ground terminal GND; the first diode D1 and the second diode D2 can be connected in series between the node A and the ground terminal GND as shown in Figure 6a , or the first diode D1 and the second diode D2 can be connected in parallel between the node A and the ground terminal GND as shown in Figure 6b .

[0099] The second diode D2 can refer to the above explanation and description of the first diode D1, which will not be repeated here. The type of the first diode D1 and the type of the second diode D2 can be the same or different. The size of the first diode D1 and the size of the second diode D2 can be the same or different.

[0100] It should be noted that in the third implementation manner, the adjusting circuit 30 can include the second load 301 or can not include the second load 301. In the case that the adjusting circuit 30 includes the second load 301 and the first diode D1 and the second diode D2 are connected in parallel between the node A and the ground terminal GND, the first diode D1 and the second diode D2 can be connected in series with the second load 301 as shown in FIG. 4B, or the first diode D1 and the second load 301 can be connected in series with the second diode D2 as shown in FIG. 4C. Figure 6b Figure 6c

[0101] Since the anode of the second diode D2 is coupled with the node A and the cathode of the second diode D2 is coupled with the ground terminal GND, the second diode D2 always works in the saturation region.

[0102] In the case that the adjusting circuit 30 does not include the second load 301, the second bias voltage Vb2 provided by the second adjustable bias voltage terminal Vb2 can adjust the third-order transconductance coefficient g 3D of the adjusting circuit 30 (i.e., the first diode D1 and the second diode D2 as a whole) working in the saturation region. In the case that the adjusting circuit 30 includes the second load 301, the second bias voltage Vb2 provided by the second adjustable bias voltage terminal Vb2 and the resistance value of the second load 301 together adjust the third-order transconductance coefficient g 3D of the adjusting circuit 30 (i.e., the first diode D1, the second diode D2 and the second load 301 as a whole) working in the saturation region.

[0103] It should be understood that the adjusting circuit 30 includes but is not limited to the first diode D1 and the second diode D2, and can further include one or more other diodes, and the connection relationship of the one or more other diodes can refer to the above-mentioned second diode D2, which will not be described herein again.

[0104] On this basis, the adjusting circuit 30 includes but is not limited to the second load 301, and can further include one or more other loads, and the one or more other loads can be connected in series with the first diode D1 between the node A and the ground terminal GND or can be connected in series with other diodes in the adjusting circuit 30 between the node A and the ground terminal GND. In the case that the adjusting circuit 30 includes a plurality of second loads 301, the resistance values of the plurality of second loads 301 can be the same or can not be the same.

[0105] Hereinafter, the adjusting circuit 30 in the above-mentioned second implementation manner is taken as an example for description.

[0106] In some examples, as shown in FIG. 4D, the adjusting circuit 30 can further include a third diode D3 connected in series with the first diode D1 between the node A and the ground terminal GND. Figure 7 ​​As shown, the amplifier 1 further includes a third load 50, one end of which is coupled to the first amplifier circuit 10, and the other end is coupled to the ground terminal GND. When the first amplifier circuit 10 includes a first transistor M1, one end of the third load 50 is coupled to the second terminal of the first transistor M1, and the other end is coupled to the ground terminal GND.

[0107] Here, the third load 50 can be, for example, one or more of an inductor Ld, a capacitor, or a resistor. Figure 7 The diagram is illustrated using the third load 50 as an inductor Ls.

[0108] When amplifier 1 includes a third load 50, the third load 50 can be used to adjust the gain of amplifier 1.

[0109] To broaden the operating bandwidth of amplifier 1, in some examples, such as Figure 8 As shown, the amplifier 1 also includes a feedback circuit 60, which is coupled to the signal input terminal RFIN and the signal output terminal RFOUT, respectively, and is used to provide feedback on the signal amplified by the first amplifier circuit 10 and the second amplifier circuit 20, so as to widen the operating bandwidth of the amplifier 1.

[0110] When amplifier 1 includes a first capacitor C1, the feedback circuit 60 is coupled to the signal input terminal RFIN through the first capacitor C1. When amplifier 1 includes a second capacitor C2, the feedback circuit 60 is coupled to the signal output terminal RFOUT through the second capacitor C2.

[0111] In some examples, such as Figure 9 As shown, the feedback circuit 60 includes a feedback capacitor Cf and a feedback resistor Rf connected in series.

[0112] right Figure 9 The linearity of the provided amplifier 1 and Figure 9 The linearity of the amplifier after removing the first diode D1 and the variable resistor R was tested. By comparison, it can be seen that in the structure of amplifier 1... Figure 9 The structure shown has an adjustment circuit 30 in amplifier 1, which includes a first diode D1 and a variable resistor R. Compared to not having an adjustment circuit 30, the linearity of amplifier 1 is improved by at least about 6 dB.

[0113] Embodiments of this application also provide a method for controlling an amplifier, wherein the amplifier can be, for example, the amplifier described above, and the method for controlling the amplifier can be as follows: Figure 10 As shown, it includes the following steps:

[0114] S10, the first adjustable bias voltage terminal Vb1 receives the first bias voltage Vb1 so that the first amplifier circuit 10 operates in the saturation region.

[0115] S11, the second adjustable bias voltage terminal Vb2 receives the second bias voltage Vb2; wherein the first bias voltage Vb1 is used to make the first amplification circuit 10 work in the third-order transconductance coefficient g 3M is the first third-order transconductance coefficient g 3M ; the second bias voltage Vb2 is used to make the first diode D1 work in the third-order transconductance coefficient g 3D is the second third-order transconductance coefficient g 3D , the first third-order transconductance coefficient g 3M and the second third-order transconductance coefficient g 3D One of them is positive and one is negative.

[0116] It should be noted that steps S10 and S11 can be executed simultaneously; or first execute step S10, and then execute step S11, or first execute step S11, and then execute step S10.

[0117] Because the first amplification circuit 10 works in the saturation region, the analog simulation relationship curve of the first bias voltage Vb1 and the third-order transconductance coefficient g 3M and the actual test relationship curve can be accurately fitted and covered, and the first diode D1 works in the saturation region, the analog simulation relationship curve of the second bias voltage Vb2 and the third-order transconductance coefficient g 3D and the actual test relationship curve can be accurately fitted and covered, so when the first third-order transconductance coefficient g 3M , that is, the third-order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region and the second third-order transconductance coefficient g 3D , that is, the third-order transconductance coefficient g 3D of the first diode D1 working in the saturation region, one of them is positive and one is negative, the actual third-order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region and the actual third-order transconductance coefficient g 3D of the first diode D1 working in the saturation region, one of them is positive and one is negative, so that the actual third-order transconductance coefficient g 3M of the first amplification circuit 10 working in the saturation region and the actual third-order transconductance coefficient g 3D of the first diode D1 working in the saturation region can be nonlinearly superimposed and offset, so that the sum g3 of the third-order transconductance coefficient g 3M of the first amplification circuit 10 and the third-order transconductance coefficient g 3D of the first diode D1 is reduced, thereby improving the overall linearity of the amplifier 1.

[0118] Here, in some examples, the first third-order transconductance coefficient g 3Mthe absolute value of the second third-order transconductance coefficient g 3D of the first diode D1 operating in the saturation region. Thus the actual third-order transconductance coefficient g 3M of the first amplification circuit 10 and the actual third-order transconductance coefficient g 3D of the regulating circuit 30 are equal. Thus the sum g3 of the actual third-order transconductance coefficients of the first amplification circuit 10 and the regulating circuit 30 tends to 0, so that the overall linearity of the amplifier 1 can be further improved.

[0119] In the case where the amplifier 1 further comprises a second load 301 and the second load 301 is a variable resistor R, the second bias voltage Vb2 is used to make the third-order transconductance coefficient of the first diode D1 and the second load 301 operating in the saturation region be a second third-order transconductance coefficient g 3D . Thus the second third-order transconductance coefficient can be adjusted by adjusting the second bias voltage and adjusting the resistance value of the variable resistor. Thus the size of the second third-order transconductance coefficient can be adjusted more quickly and more flexibly. Thus the second third-order transconductance coefficient g 3D can be adjusted by adjusting the second bias voltage Vb2 and adjusting the resistance value of the variable resistor R, so that the size of the second third-order transconductance coefficient g 3D can be adjusted more quickly and more flexibly.

[0120] Embodiments of the present application also provide an electronic device, as shown in Figure 11 which comprises the above-mentioned amplifier 1 and a fourth load 2 coupled with the signal output end RFOUT of the amplifier 1. The electronic device can further comprise a processor coupled with the amplifier.

[0121] It should be noted that the electronic device provided in the embodiments of the present application can be any electronic device containing an amplifier, for example, a mobile phone, a pad, a personal digital assistant (PDA), a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, and a vehicle-mounted device, and the like, different types of user equipment or terminal devices; the electronic device can also be a network device such as a base station. The electronic device can also be a transceiver or a gain amplification unit, and the like. The embodiments of the present application do not specially limit the specific form of the electronic device. The above is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An amplifier characterized by, include: The circuit comprises a first amplifier circuit, a second amplifier circuit, a first diode, a first adjustable bias voltage terminal, a first load, a node, a signal input terminal, a signal output terminal, a power supply voltage terminal, a second adjustable bias voltage terminal, and a ground terminal. The input terminal of the first amplifier circuit is coupled to both the signal input terminal and the first adjustable bias voltage terminal. The first adjustable bias voltage terminal provides an adjustable first bias voltage to the first amplifier circuit. The output terminal of the first amplifier circuit is coupled to the input terminal of the second amplifier circuit. The output terminal of the second amplifier circuit is coupled to one end of the first load and the signal output terminal. One end of the first amplifier circuit is also coupled to the ground terminal. The control terminal of the second amplifier circuit is coupled to the second adjustable bias voltage terminal, which provides an adjustable second bias voltage to the second amplifier circuit. The input terminal of the first amplifier circuit receives the radio frequency signal provided by the signal input terminal, amplifies the radio frequency signal, and outputs it to the input terminal of the second amplifier circuit. The input terminal of the second amplifier circuit receives the signal output by the output terminal of the first amplifier circuit, amplifies the signal, and provides it to the signal output terminal. The output terminal of the first amplifier circuit and the input terminal of the second amplifier circuit are coupled to the node; the positive terminal of the first diode is coupled to the node; and the negative terminal of the first diode is coupled to the ground terminal. The other end of the first load is coupled to the power supply voltage terminal.

2. The amplifier of claim 1, wherein The amplifier also includes a second load, which is connected in series with the first diode between the node and the ground terminal.

3. The amplifier of claim 2, wherein, The second load is a variable resistor.

4. The amplifier of any one of claims 1-3, wherein, The amplifier further includes a second diode, the positive terminal of which is coupled to the node, and the negative terminal of which is coupled to the ground terminal; The first diode and the second diode are connected in series or in parallel between the node and the ground terminal.

5. The amplifier of any one of claims 1-3, wherein, The amplifier also includes a third load, one end of which is coupled to one end of the first amplifier circuit and the other end of which is coupled to the ground terminal.

6. The amplifier according to claim 5, characterized in that, The third load is an inductor.

7. The amplifier according to any one of claims 1-3, characterized in that, The first amplifier circuit includes a first transistor, the gate of the first transistor is coupled to the signal input terminal and the first adjustable bias voltage terminal, the first electrode of the first transistor is coupled to the node, and the second electrode of the first transistor is coupled to the ground terminal. In this transistor, one of the first electrode and the other of the second electrode is the source and the other is the drain.

8. The amplifier according to any one of claims 1-3, characterized in that, The second amplifier circuit includes a second transistor, the gate of the second transistor is coupled to the second adjustable bias voltage terminal, the first terminal of the second transistor is coupled to the signal output terminal, and the second terminal of the second transistor is coupled to the node; In this transistor, one of the first electrode and the other of the second electrode is the source and the other is the drain.

9. The amplifier according to any one of claims 1-3, characterized in that, The amplifier further includes a first bias voltage generating circuit, the output of which is coupled to the first adjustable bias voltage terminal to provide a first bias voltage to the first adjustable bias voltage terminal.

10. The amplifier according to any one of claims 1-3, characterized in that, The amplifier further includes a second bias voltage generating circuit, the output of which is coupled to the second adjustable bias voltage terminal to provide a second bias voltage to the second adjustable bias voltage terminal.

11. The amplifier according to any one of claims 1-3, characterized in that, The amplifier further includes a feedback circuit, which is coupled to the signal input terminal and the signal output terminal respectively, and is used to provide feedback on the signal amplified by the first amplification circuit and the second amplification circuit.

12. The amplifier according to claim 11, characterized in that, The feedback circuit includes a feedback capacitor and a feedback resistor connected in series.

13. An electronic device, characterized in that, Includes a fourth load, a processor, and an amplifier as described in any one of claims 1-12; The fourth load is coupled to the signal output terminal of the amplifier, and the processor is coupled to the amplifier.

14. A method for controlling an amplifier, characterized in that, The amplifier includes: a first amplifier circuit, a second amplifier circuit, a first diode, a first adjustable bias voltage terminal, a first load, a node, a signal input terminal, a signal output terminal, a power supply voltage terminal, a second adjustable bias voltage terminal, and a ground terminal; The input terminal of the first amplifier circuit is coupled to both the signal input terminal and the first adjustable bias voltage terminal, with the first adjustable bias voltage terminal providing an adjustable first bias voltage for the first amplifier circuit. The output terminal of the first amplifier circuit is coupled to the input terminal of the second amplifier circuit, and the output terminal of the second amplifier circuit is coupled to one end of the first load and the signal output terminal. One end of the first amplifier circuit is also coupled to the ground terminal. The control terminal of the second amplifier circuit is coupled to the second adjustable bias voltage terminal, with the second adjustable bias voltage terminal providing an adjustable second bias voltage for the second amplifier circuit. The input terminal of the first amplifier circuit receives the radio frequency signal provided by the signal input terminal, amplifies the radio frequency signal, and outputs it to the input terminal of the second amplifier circuit. The input terminal of the second amplifier circuit receives the signal output by the output terminal of the first amplifier circuit, amplifies the signal, and provides it to the signal output terminal. The output terminal of the first amplifier circuit and the input terminal of the second amplifier circuit are coupled to the node; the positive terminal of the first diode is coupled to the node; and the negative terminal of the first diode is coupled to the ground terminal. The other end of the first load is coupled to the power supply voltage terminal; The control method includes: The first adjustable bias voltage terminal receives a first bias voltage so that the first amplifier circuit operates in the saturation region; The second adjustable bias voltage terminal receives a second bias voltage; wherein, the first bias voltage is used to make the third transconductance coefficient of the first amplifier circuit operate in the saturation region as the first third transconductance coefficient; the second bias voltage is used to make the third transconductance coefficient of the first diode operate in the saturation region as the second third transconductance coefficient, wherein one of the first third transconductance coefficient and the second third transconductance coefficient is positive and the other is negative.

15. The control method according to claim 14, characterized in that, The amplifier further includes a second load, wherein the second load and the first diode are connected in series between the node and the ground terminal; wherein the second load is a variable resistor; The second bias voltage is used to make the third-order transconductance coefficient of the first diode and the second load operate in the saturation region as the second third-order transconductance coefficient.

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