A test structure and a measurement method for measuring overlay error

Abstract

The application discloses a test structure and a measurement method for measuring overlay error, the test structure comprising a plurality of measurement units, each of the measurement units comprising a first PMOS, an NMOS and a second PMOS connected in series, the NMOS forming an NP boundary with the first and second PMOS respectively, wherein the NP boundary has a predefined bias amount relative to the active area of the first and second PMOS, and the predefined bias amount of different measurement units is different, and the first and second PMOS output first and second threshold voltages respectively, which are used to determine the overlay error from the plurality of predefined bias amounts by the first and second threshold voltages. The technical scheme of the application can accurately measure the process offset information of the real 3D chip below the wafer surface, and can reflect the overlay error information of the commonly used or basic gate real design structure, and the test structure can be customized based on the design structure of the key device and the overlay precision measurement is performed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of SOC chip testing, and in particular to a test structure and a measurement method for measuring overlay error. BACKGROUND

[0002] Overlay accuracy refers to the alignment accuracy between the current layer and the previous layer of a wafer in a photolithography manufacturing process. Since an integrated circuit chip is manufactured by stacking multiple layers of structures, the overlay accuracy between the layers of structures directly affects the effectiveness and yield of the integrated circuit chip. The error in the alignment between the current layer and the previous layer of the wafer during the exposure process of the chip forms an overlay error (OVL).

[0003] For some design structures, photomask lithography is the main cause of overlay error. For example, a 3D fin field effect transistor (FinFET) process, which has a relatively complex manufacturing process, generally needs to apply multiple photomask lithography to complete. In the prior art, for the overlay error caused by photomask lithography, the measurement method mainly used is an optical measurement method, which measures the alignment error between the current layer OVL mark and the previous layer OVL mark, as shown in FIG. 1. Figure 1

[0004] However, the method based on optical measurement has the disadvantage that the measurement structure is a special OVL pad, which cannot represent the overlay error information of other commonly used or basic gate real design structures. Moreover, the method based on optical measurement can only see the overlay error information on the surface of the wafer, and for a real 3D chip, the optical measurement method cannot reflect the process offset information below the surface of the wafer. SUMMARY

[0005] Therefore, the present application provides a test structure and a measurement method for measuring overlay error, which aims to accurately measure the real overlay error information of the wafer in the three-dimensional layer.

[0006] In a first aspect, the present application provides a test structure for measuring overlay error, the test structure comprising a plurality of measurement units, each of the measurement units comprising a first PMOS, an NMOS and a second PMOS connected in series, the NMOS forming a NP boundary with the first PMOS and the second PMOS respectively, wherein the NP boundary has a predefined bias amount relative to the active area of the first PMOS and the second PMOS, and the predefined bias amount of different measurement units is different; the first PMOS and the second PMOS output a first threshold voltage and a second threshold voltage respectively, for determining the overlay error from a plurality of predefined bias amounts by the difference between the first threshold voltage and the second threshold voltage. ​

[0007] Preferably, a source of the first PMOS is coupled to a source of the NMOS, a drain of the NMOS is coupled to a drain of the second PMOS; sources of the first PMOS and the second PMOS are grounded; drains of the first PMOS and the second PMOS receive first and second input voltages respectively, the first and second PMOS output first and second threshold voltages respectively.

[0008] Preferably, values of the first and second threshold voltages output by the first and second PMOS of each measurement unit vary with the predefined bias, the overlay error is determined by an absolute value of a difference between the first and second threshold voltages.

[0009] Preferably, the first PMOS and the NMOS form a first NP boundary, the second PMOS and the NMOS form a second NP boundary, and when the predefined bias is 0, a distance between the first NP boundary and an active region of the first PMOS is equal to a distance between the second NP boundary and an active region of the second PMOS.

[0010] Preferably, a region width of the NMOS in each measurement unit is the same.

[0011] The present application also provides, in a second aspect, a method for measuring a wafer overlay error, comprising:

[0012] a plurality of measurement units are grouped into a test structure, the measurement unit comprising a first PMOS, an NMOS and a second PMOS connected in series, so that the NMOS forms NP boundaries with the first PMOS and the second PMOS respectively, a predefined bias of the NP boundaries relative to active regions of the first and second PMOS is set, and the predefined bias of different measurement units is set to be different from each other;

[0013] for each measurement unit, a first threshold voltage and a second threshold voltage output by the first PMOS and the second PMOS respectively are measured;

[0014] an absolute value of a difference between the first threshold voltage and the second threshold voltage corresponding to each measurement unit is calculated;

[0015] a target measurement unit in which the absolute value reaches a minimum is determined from the plurality of measurement units, and a predefined bias corresponding to the target measurement unit is determined as the wafer overlay error.

[0016] Preferably, the grouping of a plurality of measurement units into a test structure further comprises:

[0017] The source of the first PMOS is coupled to the source of the NMOS, and the drain of the NMOS is coupled to the drain of the second PMOS; the sources of the first PMOS and the second PMOS are grounded; the drains of the first PMOS and the second PMOS respectively receive a first input voltage and a second input voltage, wherein the first PMOS and the second PMOS respectively output the first threshold voltage and the second threshold voltage.

[0018] Preferably, the values of the first threshold voltage and the second threshold voltage of each measurement unit change with the predefined biasing amount.

[0019] Preferably, the forming of the NMOS with the first PMOS and the second PMOS into NP boundaries respectively further comprises:

[0020] The first PMOS and the NMOS form a first NP boundary, the second PMOS and the NMOS form a second NP boundary, and when the predefined biasing amount is 0, the distance between the first NP boundary and the active region of the first PMOS is set to be equal to the distance between the second NP boundary and the active region of the second PMOS.

[0021] Preferably, the method further comprises:

[0022] The region width of the NMOS in each measurement unit is set to be the same.

[0023] It can be seen that the test structure and the measurement method for measuring overlay error of the present application overcome the limitation of the conventional optical measurement method that can only see the overlay error on the wafer surface, can accurately measure the process offset information of the real 3D chip below the wafer surface, can reflect the overlay error information of the commonly used or basic gate real design structure, no longer uses a special OVL Pad, but can customize a test structure (TSK) based on the design structure of a key device, for example, can customize a test structure (TSK) based on specific NMOS and PMOS boundary conditions and perform overlay precision measurement. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0025] Figure 1 A schematic diagram showing the principle of an overlay error measurement method based on optical measurement according to the prior art is shown.

[0026] Figure 2 A cross-sectional schematic view of a test structure for measuring overlay error according to the present application is shown.

[0027] Figure 3 A top view of a test structure for measuring overlay error according to the present application is shown.

[0028] Figure 4 A circuit diagram of a test structure for measuring overlay error according to the present application is shown.

[0029] Figure 5 A cross-sectional schematic view of a measurement cell with zero bias according to the present application is shown.

[0030] Figure 6 A top view of a measurement cell corresponding to Figure 5 is shown.

[0031] Figure 7 A cross-sectional schematic view of a measurement cell with first bias according to the present application is shown.

[0032] Figure 8 A top view of a measurement cell corresponding to Figure 7 is shown.

[0033] Figure 9 A cross-sectional schematic view of a measurement cell with second bias according to the present application is shown.

[0034] Figure 10 A top view of a measurement cell corresponding to Figure 9 is shown.

[0035] Figure 11 An exemplary plot of gate threshold voltage difference versus different bias is shown.

[0036] Figure 12 A flow chart of a measurement method for measuring overlay error according to the present application is shown. DETAILED DESCRIPTION

[0037] For better understanding of the above technical solutions, the above technical solutions will be described in detail below in conjunction with the drawings in the specification and specific embodiments.

[0038] It should be clear that the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. In order to more clearly illustrate the present invention, many technical details are described in the following specific embodiments. Those skilled in the art should understand that the present invention can also be implemented without some of the details. In addition, in order to highlight the main purpose of the present invention, some methods, means, components and their applications well known to those skilled in the art are not described in detail, but this does not affect the implementation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0039] The main purpose of the present invention is to provide a test structure and measurement method for measuring overlay error, which can not only measure the planar overlay error of the wafer, but also reflect the overall overlay error of the wafer at the three-dimensional level and accurately measure the overlay accuracy of basic / common gate design structures.

[0040] Example 1

[0041] In one aspect, the present invention provides a test structure for measuring overlay error. Figure 2 A schematic cross-sectional view of a test structure according to the present invention is shown.

[0042] The test structure provided by the present invention places a series of TSK measurement units with NMOS and PMOS connected in series. In each measurement unit, an NMOS is connected in series with two adjacent PMOS devices, which are respectively called the first PMOS, NMOS and the second PMOS. Figure 3 A top view of the test structure for measuring overlay error according to the present invention is shown. The boundary between NMOS and PMOS is called NP boundary. The initial value of the distance between the NP boundary of the layer and the active area AA (active area) of two adjacent PMOS can be set to X. Then, different predefined bias values ​​(X1, X2, ..., Xn) are set for each measurement unit in the test structure to change the distance between the NP boundary of the layer and the active area AA (active area) of two adjacent PMOS. After the bias values ​​of all measurement units are set, the gate threshold voltage output values ​​of the PMOS on both sides of the NMOS under the above-mentioned different bias values ​​can be measured by external tools, which are the first threshold voltage and the second threshold voltage ( Figure 3 Respectively expressed as V1 and V2), and calculate the measured voltage output value gap (V1, V2), that is, |V2-V1|, so as to determine the overlay error between the current layer pattern and the previous layer pattern from multiple predefined bias values ​​according to the absolute value of the voltage output difference of each measuring unit.

[0043] See also Figure 4In the circuit diagram shown, the NMOS device in the center is connected in series with two PMOS devices on the left and right, namely PMOS1 and PMOS2. The source of PMOS1 is coupled to the source of the NMOS device, and the drain of the NMOS device is coupled to the drain of PMOS2. The sources of PMOS1 and PMOS2 are both grounded. The drains of PMOS1 and PMOS2 receive a first input voltage Vdp1 and a second input voltage Vdp2, respectively. The gates of PMOS1 and PMOS2 output a first threshold voltage V1 and a second threshold voltage V2, respectively.

[0044] Figure 5 A schematic cross-sectional view of a measurement cell with a bias of zero is shown. W represents the width of the NMOS region. X represents the distance between the NP boundary and the active areas of the PMOS on either side. The boundary between the first PMOS and NMOS on the left is called the first NP boundary, and the boundary between the second PMOS and NMOS on the right is called the second NP boundary. That is, the distance from the first NP boundary to the active area of ​​the first PMOS is equal to the distance from the second NP boundary to the active area of ​​the second PMOS. Figure 6 is with Figure 5 The corresponding top view shows that the distance between the NP boundary and the active areas of the PMOS on both sides is equal, both are X0, and the bias amount is 0 at this time.

[0045] Figure 7 The schematic diagram of the measurement unit is shown in Figure 1. The NP boundary is at Figure 5 On the basis of , the whole is offset to the right, and the size of the offset is X1. Figure 7 The NP boundary is shown horizontally offset from the dashed line to the solid line. The NMOS region width W can be set to the same in each measurement cell. Since the NMOS region width W remains constant across all measurement cells, the distance X1,1 between the NP boundary and the active area of ​​the PMOS on the left is different from the distance X1,2 between the NP boundary and the active area of ​​the PMOS on the right. Therefore, the difference between the distances X1,1 and X1,2 is equal to twice the offset X1. Figure 8 is with Figure 7 The corresponding top view shows the positional relationship of the internal components of the measurement unit when the predefined offset is X1.

[0046] Figure 9 A schematic diagram of a measurement unit according to another embodiment is shown with an offset of X2. The NP boundary is horizontally offset from the dashed line position to the solid line position, resulting in a distance of X2,1 from the NP boundary to the active area of ​​the left PMOS. This distance is different from the distance X2,2 from the active area of ​​the right PMOS. The difference between the two is equal to twice the offset X2. Figure 10 is with Figure 9The corresponding top view shows the position relationship of the internal components of the measurement unit when the predefined bias is X2. It can be understood by those skilled in the art that the NP boundary will not overlap with the active area of ​​the adjacent PMOS, that is, the predefined bias should not exceed Figure 2 The initial value X of the distance between the NP boundary and the active area of ​​the adjacent PMOS is shown.

[0047] Due to the metal boundary effect, when semiconductor manufacturing processes enter the high-k metal gate (HKMG) process, the threshold voltages of NMOS and PMOS are adjusted using two metals with different work functions. This creates a proximity effect at the N / P junction, causing the NMOS / PMOS to deviate from the predetermined gate voltage. Therefore, the offset of the corresponding measurement unit when the absolute value of the two PMOS gate threshold voltage gaps (V1, V2) adjacent to the NMOS, namely |V2-V1|, is minimized, is the actual overlay zero error point, thereby determining the actual overlay error on the wafer. By measuring the PMOS gate threshold voltage, three-dimensional error measurement can be achieved, overcoming the limitations of planar measurement methods.

[0048] The values ​​of the first threshold voltage V1 and the second threshold voltage V2 vary with the predefined offset amount. Figure 11 An exemplary graph shows the relationship between the absolute value of |V2-V1| and different offsets X1, X2, X3, and X4. If the value of |V2-V1| reaches a minimum value (e.g., 5V) at offset X2, then offset X2 is determined to be the actual zero overlay error point. In other words, during the exposure process, when the alignment error between the layer pattern and the previous layer pattern is X2, the overlay error on the wafer is determined.

[0049] In practical applications, in order to eliminate the influence of local process variation on measurement error, multiple groups of NMOS / PMOS can be placed when designing TSK. Although the above example uses the PMOS-NMOS-PMOS series structure as an example to illustrate the measurement unit, those skilled in the art will understand that the MOS tube being tested can be PMOS or NMOS. That is, the measurement unit can also connect NMOS-PMOS-NMOS in series, thereby changing the offset of the NP boundary between the PMOS and the two adjacent NMOS relative to the active area of ​​the NMOS, and determining the actual overlay zero error point based on the offset corresponding to the minimum absolute value of the two NMOS gate threshold voltages. This overlay accuracy test structure is mainly used in gate-related process.

[0050] Example 2

[0051] Another aspect of the present invention also includes a method for measuring the overlay error of the test structure based on the above-mentioned embodiment 1.Figure 12 The flowchart of the method for measuring overlay error shown in FIG. 1 includes the following specific steps:

[0052] Step S101: assembling a plurality of measurement units into a test structure, the measurement units including a first PMOS, an NMOS, and a second PMOS connected in series, such that the NMOS forms an NP boundary with the first PMOS and the second PMOS, respectively; setting a predefined offset of the NP boundary relative to an active region of the first PMOS and the second PMOS; and setting the predefined offset of different measurement units to be different.

[0053] See also Figure 2 and Figure 3 The cross-sectional view and top view of the test structure of the present invention are respectively shown. The boundary between an NMOS and two adjacent PMOSs is called an NP boundary. Specifically, the first PMOS (PMOS1) and the NMOS form a first NP boundary, and the second PMOS (PMOS2) and the NMOS form a second NP boundary. The initial value of the distance between the NP boundary and the active area AA (active area) of the two adjacent PMOSs can be set to X, and then a different predefined offset (X1, X2, ..., Xn) is set for each measurement unit in the test structure to change the distance between the NP boundary and the two adjacent active areas AA (active area).

[0054] Step S102 : For each measurement unit, measuring a first threshold voltage and a second threshold voltage outputted by the first PMOS and the second PMOS, respectively.

[0055] See also Figure 4 In the circuit diagram shown, when multiple measurement units are combined into a test structure, the source of PMOS1 is coupled to the source of NMOS, and the drain of NMOS is coupled to the drain of PMOS2. The sources of PMOS1 and PMOS2 are both grounded. The drains of PMOS1 and PMOS2 are used to receive a first input voltage Vdp1 and a second input voltage Vdp2, respectively. The gates of PMOS1 and PMOS2 output a first threshold voltage V1 and a second threshold voltage V2, respectively. For each measurement unit Ti (i∈[1,N], N is the number of measurement units) of the test structure, the first threshold voltage V1i and the second threshold voltage V2i output by the first PMOS and the second PMOS are measured, wherein the predefined offset of the measurement unit Ti is Xi.

[0056] Step S103 : calculating the absolute value of the difference between the first threshold voltage and the second threshold voltage corresponding to each measurement unit.

[0057] The absolute value of the threshold voltage difference corresponding to each measurement unit Ti, |V2i-V1i|, is calculated, and the minimum value min(|V2i-V1i|) of the absolute value in all measurement units is determined. According to the metal boundary effect, after the semiconductor manufacturing process enters the high-K metal gate (HKMG) process, the threshold voltages of NMOS and PMOS are adjusted by two different work function metals, which produces a proximity effect at the NP boundary, thereby causing the phenomenon that NMOS / PMOS deviates from the intended gate voltage. Therefore, the bias amount of the measurement unit corresponding to the minimum absolute value |V2-V1| of the threshold voltage gap (V1, V2) of the two PMOS gates adjacent to the NMOS is the actual overlay zero error point.

[0058] In step S104, a target measurement unit with the minimum absolute value is determined from the plurality of measurement units, and a predefined bias amount corresponding to the target measurement unit is determined as the overlay error of the wafer.

[0059] The target measurement unit Ta with the minimum absolute value is determined, i.e., a = argmin(|V2i-V1i|), and the target bias amount Xa corresponding to the measurement unit Ta is determined as the overlay error of the wafer. The values of the first threshold voltage and the second threshold voltage of each measurement unit change with the predefined bias amount. Referring to Figure 11 An exemplary curve is given. If the value of |V2-V1| reaches the minimum value (e.g., 5V) in the case of the bias amount X2, the bias amount X2 is determined as the actual overlay error of the wafer.

[0060] It can be seen that the test structure and the measurement method for measuring overlay error provided by the present application have the following advantages compared with the prior art:

[0061] The test structure and the measurement method for measuring overlay error provided by the present application overcome the limitation that the conventional optical measurement method can only see the overlay error on the surface of the wafer, can accurately measure the process offset information of the real 3D chip below the wafer surface, can reflect the overlay error information of the commonly used or basic gate real design structure, no longer uses a special OVL Pad, but can customize a TSK test structure based on the design structure of a key device and perform overlay precision measurement, and can be applied to the overlay precision measurement of the gate related level of the FinFET process of each technology node.

[0062] The above describes a plurality of embodiment schemes provided by the embodiments of the present application. The optional modes introduced by each embodiment scheme can be combined with each other and cross-referenced in the case of no conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiment schemes disclosed and disclosed by the embodiments of the present application.

[0063] Although the embodiments of the present application have been disclosed as above, the present application is not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the scope of protection of the present application should be defined by the scope of claims.

Claims

1. A test structure for measuring overlay error, characterized in that: The test structure includes multiple measurement units, each of which includes a first PMOS, an NMOS, and a second PMOS connected in series in sequence, the NMOS forming an NP boundary with the first PMOS and the second PMOS, respectively, wherein the NP boundary has a predefined offset relative to the active area of ​​the first PMOS and the second PMOS, and the predefined offset of different measurement units is different; the first PMOS and the second PMOS respectively output a first threshold voltage and a second threshold voltage, which are used to determine the overlay error from multiple predefined offsets through the difference between the first threshold voltage and the second threshold voltage.

2. The test structure for measuring overlay error according to claim 1, wherein: The source of the first PMOS is coupled to the source of the NMOS, and the drain of the NMOS is coupled to the drain of the second PMOS; the sources of the first PMOS and the second PMOS are grounded; the drains of the first PMOS and the second PMOS receive a first input voltage and a second input voltage, respectively, and the first PMOS and the second PMOS output a first threshold voltage and a second threshold voltage, respectively.

3. The test structure for measuring overlay error according to claim 2, wherein: The values ​​of the first threshold voltage and the second threshold voltage respectively output by the first PMOS and the second PMOS of each measurement unit change with the predefined offset, and the overlay error is determined by the absolute value of the difference between the first threshold voltage and the second threshold voltage.

4. The test structure for measuring overlay error according to claim 1, wherein: The first PMOS and the NMOS form a first NP boundary, the second PMOS and the NMOS form a second NP boundary, and when the predefined bias amount is 0, the distance between the first NP boundary and the active area of ​​the first PMOS is equal to the distance between the second NP boundary and the active area of ​​the second PMOS.

5. The test structure for measuring overlay error according to claim 1, wherein: The NMOS regions in each measurement unit have the same width.

6. A method for measuring wafer overlay error, characterized in that: include: A test structure is formed by forming a plurality of measurement units, the measurement units including a first PMOS, an NMOS, and a second PMOS connected in series so that the NMOS forms an NP boundary with the first PMOS and the second PMOS, respectively; predefined offsets are set for the NP boundaries relative to active regions of the first PMOS and the second PMOS, and the predefined offsets are set to be different for different measurement units; For each measuring unit, measuring a first threshold voltage and a second threshold voltage outputted by the first PMOS and the second PMOS respectively; Calculating the absolute value of the difference between the first threshold voltage and the second threshold voltage corresponding to each measurement unit; A target measurement unit having the smallest absolute value is determined from the multiple measurement units, and a predefined offset corresponding to the target measurement unit is determined as the overlay error of the wafer.

7. The method for measuring wafer overlay error according to claim 6, wherein: The forming of the plurality of measurement units into a test structure further comprises: The source of the first PMOS is coupled to the source of the NMOS, and the drain of the NMOS is coupled to the drain of the second PMOS; the sources of the first PMOS and the second PMOS are grounded; and the drains of the first PMOS and the second PMOS are used to receive a first input voltage and a second input voltage, respectively, wherein the first PMOS and the second PMOS output the first threshold voltage and the second threshold voltage, respectively.

8. The method for measuring wafer overlay error according to claim 7, wherein: The values ​​of the first threshold voltage and the second threshold voltage of each measurement unit change with the predefined offset amount.

9. The method for measuring wafer overlay error according to claim 6, wherein: The step of forming an NP boundary between the NMOS, the first PMOS, and the second PMOS further includes: The first PMOS and the NMOS form a first NP boundary, the second PMOS and the NMOS form a second NP boundary, and when the predefined bias amount is 0, the distance between the first NP boundary and the active area of ​​the first PMOS is set to be equal to the distance between the second NP boundary and the active area of ​​the second PMOS.

10. The method for measuring wafer overlay error according to claim 6, wherein: Also includes: The region width of the NMOS in each measurement unit is set to be the same.

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