A reference circuit and chip
By employing a mirror relationship and a zero-point compensation module in the reference circuit, the stability problem caused by load current variation was solved, and the system stability was improved under different load capacitance conditions.
Patent Information
- Application Number
- CN202310242462.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-03-09
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2043-03-09
AI Technical Summary
The existing reference circuit is not stable enough when faced with changes in load current, especially when the load capacitance is different. How to improve the stability of the VREF circuit has become an urgent problem to be solved.
By employing the mirror relationship between the first and second amplification units, combined with a feedback unit and a zero-point compensation module, the system outputs signals through mirroring and pushes the poles to higher frequencies. It utilizes a unity-gain buffer to improve system stability and provides a left-half-plane zero through the zero-point compensation module to enhance loop stability.
This improves the stability of the reference circuit, ensuring the stability and accuracy of the output signal under load changes, and enhancing the overall stability of the system.
Smart Images
Figure CN116560442B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, specifically to a reference circuit and a chip. Background Technology
[0002] The reference circuit (VREF circuit) typically receives an input voltage with poor driving capability (such as a reference signal VBG) and provides an output voltage signal with strong driving capability (i.e., the reference voltage VREF), which is then used as a reference by load circuits such as ADCs (analog-to-digital converters), DACs (digital-to-analog converters), or comparators. In some applications, due to the current variation characteristics of the load circuit, the VREF circuit often needs to provide both source (current sourcing) and sink (current sinking) capabilities.
[0003] In addition, due to noise and load capacity considerations, the output of VREF circuits is usually connected to an external load capacitor. However, different load capacitors often require consideration of different loop stability conditions. How to improve the stability of VREF circuits has become an urgent problem to be solved. Summary of the Invention
[0004] This application provides a reference circuit and chip that can improve circuit stability.
[0005] This application provides a reference circuit, comprising: a first amplification unit, wherein a first input terminal of the first amplification unit is used to receive an input signal, and an output terminal of the first amplification unit is used to output a control signal; a second amplification unit, wherein a first input terminal of the second amplification unit is connected to the output terminal of the first amplification unit and is used to receive the control signal, a first output terminal of the second amplification unit is used to output a reference signal, a second output terminal of the second amplification unit is used to output a first feedback signal, and a second output terminal of the second amplification unit is connected to a second input terminal of the second amplification unit and is used to feed the first feedback signal back to the second input terminal of the second amplification unit, wherein the current flowing through the second output terminal of the second amplification unit has a mirror relationship with the current flowing through the first output terminal of the second amplification unit; and a feedback unit, wherein the feedback unit is connected to the output terminal of the second amplification unit and the second input terminal of the first amplification unit and is used to generate a corresponding second feedback signal according to the reference signal and feed the second feedback signal back to the second input terminal of the first amplification unit.
[0006] In some embodiments, the first amplification unit includes: a differential amplification module, wherein a first input terminal of the differential amplification module is used to receive an input signal, a second input terminal of the differential amplification module is used to receive a second feedback signal, and an output terminal of the differential amplification module is used to output a control signal; and a zero-point compensation module, wherein the zero-point compensation module is connected to the output terminal of the differential amplification module.
[0007] In some embodiments, the zero-point compensation module includes: a first resistor, the first end of which is connected to the output terminal of the differential amplifier module; and a first capacitor, the first end of which is connected to the second end of the first resistor, and the second end of the first capacitor is grounded.
[0008] In some embodiments, the second amplification unit includes: an input stage for receiving a control signal and a first feedback signal, and converting the control signal and the first feedback signal as differential inputs into a first voltage signal and a second voltage signal; an output stage for receiving the first voltage signal and the second voltage signal, and outputting a reference signal under the bias of the first voltage signal and the second voltage signal; and a mirror module connected to the output stage to form a current mirror circuit, the mirror module for receiving the first voltage signal and the second voltage signal, and outputting a first feedback signal under the bias of the first voltage signal and the second voltage signal.
[0009] In some embodiments, the input stage is a rail-to-rail input stage.
[0010] In some embodiments, the output level is a class AB output level.
[0011] In some embodiments, the output stage includes a first transistor and a second transistor. The first transistor is a P-type transistor, and the second transistor is an N-type transistor. The source of the first transistor is used to receive a power supply signal, and the gate of the first transistor is used to receive a first voltage signal. The drain of the second transistor is connected to the drain of the first transistor and outputs a reference signal. The gate of the second transistor is used to receive a second voltage signal, and the source of the second transistor is grounded. The mirror module includes a third transistor and a fourth transistor. The third transistor is a P-type transistor, and the fourth transistor is an N-type transistor. The third transistor is connected to the first transistor to form a P-type current mirror, and the fourth transistor is connected to the second transistor to form an N-type current mirror. The drain of the third transistor is connected to the drain of the fourth transistor and outputs a first feedback signal.
[0012] In some embodiments, the output stage further includes a second resistor and a third resistor, the first end of the second resistor being connected to the drain of the first transistor, the first end of the third resistor being connected to the second end of the second resistor and outputting a reference signal, and the second end of the third resistor being connected to the drain of the second transistor.
[0013] In some embodiments, the reference circuit further includes a clamping module connected to the mirror module for clamping the first feedback signal.
[0014] In some embodiments, the clamping module includes: a fifth transistor, which is an N-type transistor, the drain of which is used to receive a power supply voltage; a sixth transistor, which is a P-type transistor, the source of which is connected to the source of the fifth transistor and is used to receive a first feedback signal, the drain of which is grounded; and a bias module, which is connected to the gate of the fifth transistor and the gate of the sixth transistor and is used to provide a bias voltage to the fifth transistor and the sixth transistor.
[0015] In some embodiments, the clamping module further includes: a fourth resistor, the first end of which is used to receive a power supply voltage, and the second end of which is connected to the drain of a fifth transistor; a fifth resistor, the first end of which is connected to the source of a fifth transistor; and a sixth resistor, the first end of which is connected to the second end of the fifth resistor and is used to receive a first feedback signal, and the second end of which is connected to the source of a sixth transistor.
[0016] In some embodiments, the bias module includes: a seventh transistor, which is a P-type transistor, the source of which receives a power supply signal, and the gate of which receives a first bias signal; an eighth transistor, which is also a P-type transistor, the source of which is connected to the drain of the seventh transistor, and the gate of which receives a second bias signal; a ninth transistor, which is an N-type transistor, the drain of which is connected to the drain of the eighth transistor, and the gate of which receives a third bias signal; a tenth transistor, the drain of which is connected to the source of the ninth transistor, the gate of which is connected to the drain of the eighth transistor, and the source of which is grounded; and an eleventh transistor, which is a P-type transistor, the source of which receives a power supply signal, and the gate of which receives a first bias signal. The gate of the eleventh transistor is used to receive the first bias signal, and the drain of the eleventh transistor is connected to the gate of the fifth transistor; the twelfth transistor is an N-type transistor, and its drain is connected to the drain of the eleventh transistor. The gate of the twelfth transistor is used to receive the third bias signal, and its source is grounded; the seventh resistor has its first terminal used to receive the power supply signal; the thirteenth transistor is an N-type transistor, and its drain is connected to the second terminal of the seventh resistor. The gate of the thirteenth transistor is used to receive the third bias signal, and its source is connected to the gate of the sixth transistor; the fourteenth transistor is an N-type transistor, and its drain is connected to the source of the thirteenth transistor. The gate of the fourteenth transistor is connected to the drain of the eighth transistor, and its source is grounded.
[0017] This application also provides a chip that integrates the reference circuit described above.
[0018] The reference circuit provided in this application includes: a first amplification unit, wherein a first input terminal of the first amplification unit is used to receive an input signal, and an output terminal of the first amplification unit is used to output a control signal; a second amplification unit, wherein a first input terminal of the second amplification unit is connected to the output terminal of the first amplification unit and is used to receive the control signal, a first output terminal of the second amplification unit is used to output a reference signal, a second output terminal of the second amplification unit is used to output a first feedback signal, and a second output terminal of the second amplification unit is connected to the second input terminal of the second amplification unit and is used to feed the first feedback signal back to the second input terminal of the second amplification unit, wherein the current flowing through the second output terminal of the second amplification unit has a mirror relationship with the current flowing through the first output terminal of the second amplification unit; and a feedback unit, wherein the feedback unit is connected to the output terminal of the second amplification unit and the second input terminal of the first amplification unit and is used to generate a corresponding second feedback signal according to the reference signal and feed the second feedback signal back to the second input terminal of the first amplification unit. In the above manner, in a VREF circuit with NMOS and PMOS as outputs, by mirroring the output reference signal and inputting it to the inverting input of the second amplification unit, a unity-gain buffer is formed, which simultaneously pushes the gate poles of the NMOS and PMOS to a higher frequency outside the overall loop unity-gain bandwidth, thereby improving system stability.
[0019] In a further embodiment, a zero-point compensation module is added to the output stage of the first amplification unit to provide a left half-plane zero. This zero-point is used to compensate for the influence of the output pole of the first amplification unit 1 on the loop stability, thereby improving the system stability. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a schematic diagram of an embodiment of the reference circuit provided in this application;
[0022] Figure 2 yes Figure 1 A schematic diagram of the structure of an embodiment of the first amplification unit OP1;
[0023] Figure 3 yes Figure 1 A schematic diagram of the structure of an embodiment of the second amplification unit OP2;
[0024] Figure 4 yes Figure 3 A schematic diagram of the structure of an embodiment of the input level 21;
[0025] Figure 5 yes Figure 1 A schematic diagram of another embodiment of the second amplification unit OP2;
[0026] Figure 6 yes Figure 5 A schematic diagram of the structure of one embodiment of the middle clamping module 24;
[0027] Figure 7 This is a schematic diagram of the structure of an embodiment of the chip provided in this application. Detailed Implementation
[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0029] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0030] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0031] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0032] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0033] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the reference circuit provided in this application. The reference circuit 100 includes a first amplification unit OP1, a second amplification unit OP2, and a feedback unit.
[0034] The first amplification unit OP1 has a first input terminal for receiving an input signal and an output terminal for outputting a control signal VINT. The second amplification unit OP2 has a first input terminal connected to the output terminal of OP1 for receiving the control signal VINT, a first output terminal for outputting a reference signal VREF, and a second output terminal for outputting a first feedback signal VO. The second output terminal of OP2 is connected to its second input terminal for feeding back the first feedback signal VO to its second input terminal. The current flowing through the second output terminal of OP2 is a mirror image of the current flowing through its first output terminal. A feedback unit is connected to the output terminal of OP2 and the second input terminal of OP1 for generating a corresponding second feedback signal VFB based on the reference signal VREF and feeding back the second feedback signal VFB to the second input terminal of OP1. Optionally, the input signal received at the first input terminal of OP1 can be a reference signal VBG, a power supply voltage signal VDD, or other input signals; this application does not limit this.
[0035] Optionally, in one embodiment, the first input terminal and the second input terminal of the first amplification unit OP1 are respectively a positive input terminal (+) and an inverting input terminal (-), and the first input terminal and the second input terminal of the second amplification unit OP2 are respectively a positive input terminal (+) and an inverting input terminal (-). In other embodiments, the first input terminal and the second input terminal of the first amplification unit OP1 may also be respectively an inverting input terminal (-) and a positive input terminal (+), and / or the first input terminal and the second input terminal of the second amplification unit OP2 may also be respectively an inverting input terminal (-) and a positive input terminal (+).
[0036] Optionally, in one embodiment, the feedback unit includes resistors Ra and Rb, which form a voltage divider resistor string to divide the reference signal VREF output by the second amplification unit OP2. The voltage at the connection node between resistors Ra and Rb is fed back to the second input terminal of the first amplification unit OP1 as a second feedback signal VFB.
[0037] Understandably, the load connected to the reference circuit 100 can have both capacitive and resistive characteristics. Figure 1 In this context, capacitor CL and resistor RL represent the equivalent capacitance and equivalent resistance of the load, respectively. In one embodiment, a filter capacitor may also be connected between the output of the reference circuit 100 and ground to make the output reference signal VREF smoother and more stable.
[0038] In this embodiment, the first amplification unit OP1 and the second amplification unit OP2 can be error amplifiers. The first amplification unit OP1 is a single-stage operational amplifier with differential input and single-ended output, used to generate high gain and high output impedance. The second amplification unit OP2, as a two-stage operational amplifier, provides high drive capability and achieves loop compensation. Optionally, the second amplification unit OP2 can adopt rail-to-rail input and / or class AB output. Rail-to-rail input means that the swing of the operational amplifier's input voltage is very close to the power supply voltage, allowing for a wide input common-mode voltage range under low power supply voltage or single power supply voltage. Rail-to-rail input can achieve zero crossover distortion, suitable for driving ADCs without causing differential linear attenuation, enabling high-precision applications. Class AB output allows for a large dynamic output current with a small static bias current, improving the operational amplifier's drive output capability.
[0039] The principle of the above circuit is explained below:
[0040] Resistors Ra and Rb divide the output reference signal VREF to obtain the second feedback signal VFB, thereby realizing the function of detecting the reference signal VREF. The first amplification unit OP1 compares the input signal (such as the reference signal VBG) which has no load-carrying capacity with the second feedback signal VFB and outputs a control signal VINT. The control signal VINT dynamically adjusts the voltage value of the reference signal VREF through the second amplification unit OP2. Specifically, when the reference signal VREF is higher than the set value, the voltage value of the second feedback signal VFB increases, the voltage value of the control signal VINT decreases, and the voltage value of the reference signal VREF is reduced to the set value through the second amplification unit OP2; conversely, when the voltage value of the reference signal VREF is lower than the set value, the voltage value of the second feedback signal VFB decreases, the voltage value of the control signal VINT increases, and the voltage value of the reference signal VREF is increased to the set value through the second amplification unit OP2.
[0041] Understandably, since the VREF circuit simultaneously provides both source (current pulling) and sink (current sinking), the output stage of the second amplification unit OP2 includes both N-type power transistors (such as MOSFETs) and P-type power transistors. In this embodiment, the first feedback signal VO is obtained by mirroring the reference signal VREF. The first feedback signal VO is input to the second input terminal of the second amplification unit OP2 to form a unity-gain buffer. This pushes the gate poles of the N-type power transistors and the P-type power transistors used for output to higher frequencies outside the overall loop unity-gain bandwidth, thereby improving system stability.
[0042] The first amplification unit OP1 and the second amplification unit OP2 will be described below. In the following circuit, the first bias signal VBP, the second bias signal VBPCAS, the third bias signal VBNCAS, and the fourth bias signal VBN are used to provide the corresponding bias voltage.
[0043] like Figure 2 As shown, Figure 2 yes Figure 1 A schematic diagram of the structure of an embodiment of the first amplification unit OP1, which includes a differential amplification module 11 and a zero-point compensation module 12.
[0044] The first input terminal of the differential amplifier module 11 is used to receive an input signal (such as a reference signal VBG), the second input terminal of the differential amplifier module 11 is used to receive a second feedback signal VFB, and the output terminal of the differential amplifier module 11 is used to output a control signal VINT. The zero-point compensation module 12 is connected to the output terminal of the differential amplifier module 11. The zero-point compensation module 12 provides a left-half-plane zero point for the output signal of the differential amplifier module 11. This zero point can compensate for the influence of the output poles of the differential amplifier module 11 on loop stability, thereby improving loop stability.
[0045] Specifically, in the differential amplifier module 11, the gates of the input transistors MN11 and MN12 are respectively the first input terminal and the second input terminal of the first amplifier unit OP1. Specifically, the gate of input transistor MN11 is used to receive an input signal (such as a reference signal VBG). The drain of input transistor MN11 is connected to the gates of MP11 and MP15, and the drain of MP12. The source of input transistor MN11 is connected to the source of MN12 and the drain of MN13. The gate of input transistor MN12 is used to receive a second feedback signal VFB. The drain of input transistor MN12 is connected to the gates of MP13 and MP17, and the drain of MP14. The gate of MN13 is used to receive a fourth bias signal VBN. The source of MN13, along with the second terminal of MN15, MN17, and the first capacitor C1, is connected to ground. The gate of MP12, along with the gates of MP14, MP16, and MP18, is used for... The source of MP12 is connected to the drain of MP11, receiving the second bias signal VBPCAS. The source of MP11, along with the sources of MP13, MP15, and MP17, are used to receive the power supply signal VDD. The source of MP14 is connected to the drain of MP13. The gate of MN15 is connected to the drain of MN14, the drain of MP16, and the gate of MN17. The drain of MN15 is connected to the source of MN14. The gates of MN14 and MN16 receive the third bias signal VBNCAS. The source of MP16 is connected to the drain of MP15. The drain of MN17 is connected to the source of MN16. The drain of MN16, the drain of MP18, and the first terminal of the first resistor R1 serve as the output terminal of the first amplification unit OP1. The source of MP18 is connected to the drain of MP17. The second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1.
[0046] Specifically, the zero-point compensation module 12 includes the first resistor R1 and the first capacitor C1 mentioned above.
[0047] The principle of the above circuit is explained below:
[0048] MN11 and MN12 form a differential input, converting the input differential voltage signal into a differential current signal; MN13 serves as the tail current, providing a suitable quiescent operating point for the circuit; MP11, MP12, MP15, and MP16 form a set of wide-swing cascode current mirrors, used to mirror the current signal generated by input transistor MN11; MP13, MP14, MP17, and MP18 form a set of wide-swing cascode current mirrors, mirroring the current signal generated by input transistor MN12 to the output branch; MN14 to MN17 form a set of wide-swing cascode current mirrors, further mirroring the current generated by the MP15 branch (i.e., the current generated by input transistor MN11) to the output branch, realizing the differential-to-single-ended conversion function. MN16, MN17, MP17, and MP18 are cascode structures, providing high output impedance for the op-amp output stage and increasing the op-amp gain. The first resistor R1 and the first capacitor C1 of the zero-point compensation module 12 are connected in series to provide a left half-plane zero point. This zero point is used to compensate for the influence of the output pole of the first amplification unit OP1 on the loop stability and improve the system stability.
[0049] like Figure 3 As shown, Figure 3 yes Figure 1 A schematic diagram of an embodiment of the second amplification unit OP2 is shown. The second amplification unit OP2 includes an input stage 21, an output stage 22, and a mirror module 23.
[0050] The input stage 21 receives the control signal VINT and the first feedback signal VO, and converts the control signal VINT and the first feedback signal VO as differential inputs into a first voltage signal VP and a second voltage signal VN. The output stage 22 receives the first voltage signal VP and the second voltage signal VN, and outputs a reference signal VREF under the bias of the first voltage signal VP and the second voltage signal VN. The mirror module 23 is connected to the output stage 22 to form a current mirror circuit. The mirror module 23 receives the first voltage signal VP and the second voltage signal VN, and outputs the first feedback signal VO under the bias of the first voltage signal VP and the second voltage signal VN.
[0051] Optionally, in one embodiment, the output stage 22 includes a first transistor MP214 and a second transistor MN214. The first transistor MP214 is a P-type transistor, and the second transistor MN214 is an N-type transistor. The source of the first transistor MP214 is used to receive a power supply signal VDD, and the gate of the first transistor MP214 is used to receive a first voltage signal VP. The drain of the second transistor MN214 is connected to the drain of the first transistor MP214 and outputs a reference signal VREF. The gate of the second transistor MN214 is used to receive a second voltage signal VN, and the source of the second transistor MN214 is grounded.
[0052] Optionally, in one embodiment, the mirror module 23 includes a third transistor MP213 and a fourth transistor MN213. The third transistor MP213 is a P-type transistor, and the fourth transistor MN213 is an N-type transistor. The source of the third transistor MP213 is used to receive the power supply signal VDD, and the gate of the third transistor MP213 is used to receive the first voltage signal VP. The third transistor MP213 and the first transistor MP214 form a P-type current mirror. The gate of the fourth transistor MN213 is used to receive the second voltage signal VN. The source of the fourth transistor MN213 is grounded, and the fourth transistor MN213 and the second transistor MN214 form an N-type current mirror. The drain of the third transistor MP213 and the drain of the fourth transistor MN213 are connected and output a first feedback signal VO.
[0053] Understandably, mirror module 23, acting as a mirror of output stage 22, is not used for power output and can carry a smaller current to save power consumption. Therefore, the size of the third transistor MP213 can be smaller than the size of the first transistor MP214, and the size of the fourth transistor MN213 can be smaller than the size of the second transistor MN214. That is, the third transistor MP213 mirrors the current of the first transistor MP214 at a ratio less than 1, and the fourth transistor MN213 mirrors the current of the second transistor MN214 at a ratio less than 1. Thus, the first transistor MP214 and the second transistor MN214 are used for power output, carrying a larger current, while the third transistor MP213 and the fourth transistor MN213 are not used for power output and carry a smaller current. Optionally, the size ratio of the third transistor MP213 to the first transistor MP214 is equal to the size ratio of the fourth transistor MN213 to the second transistor MN214, so that the current mirroring ratio between the third transistor MP213 and the first transistor MP214 is the same as the current mirroring ratio between the fourth transistor MN213 and the second transistor MN214. Here, the transistor dimensions include the aspect ratio.
[0054] Further reading Figure 4 , Figure 4 yes Figure 3 A schematic diagram of an embodiment of the input stage 21 is shown below, taking rail-to-rail input as an example. The specific structure of the input stage 21 is as follows:
[0055] The gates of input transistors MN201 and MP202 are connected to VINP. The source of MN201 is connected to the source of MN202 and the drain of MN203. The drain of MN201 is connected to the drain of MP206 and the source of MP207. The gates of input transistors MN202 and MP201 are connected to the second output terminal of the second amplifier unit OP2 to receive the first feedback signal VO. The drain of MN202 is connected to the drain of MP204 and the source of MP205. The gates of MN203 and MN212 receive the fourth bias signal. VBN, the source of MN203 and the sources of MN205, MN207, MN210, and MN212 are grounded together; the source of MP201 is connected to the source of MP202 and the drain of MP203; the drain of MP201 is connected to the source of MN204 and the drain of MN205; the drain of MP202 is connected to the source of MN206 and the drain of MN207; the gate of MP203 and the gates of MP204, MP206, and MP208 receive the first bias signal VBP together; the source of MP203 and the gates of MP204, MP206, and MP208 are grounded together. The sources of P208 and MP210 jointly receive the power supply signal VDD; the gates of MN205, MN207, MN204, and MP205 are connected; the gates of MN204, MN206, and MN211 jointly receive the third bias signal VBNCAS; the gates of MP205, MP207, and MP209 jointly receive the second bias signal VBPCAS; the drain of MN206 is connected to the source of MP208 and the drain of MP212, and is used to output the second voltage signal VN; the drain of MP207... The drain of MN208 and the source of MP212 are connected together and used to output the first voltage signal VP; the gate and drain of MN210 are connected to the source of MN209, the gate and drain of MN209 are connected to the gate of MN208 and the drain of MP209; the source of MP209 is connected to the drain of MP208; the drain of MN212 is connected to the source of MN211; the drain of MN211 is connected to the gate of MP212, the gate of MP211, and the drain of MP211; the source of MP211 is connected to the gate of MP210 and the drain of MP210.
[0056] In combination with the above Figure 3 and Figure 4 The principle of the above circuit is explained as follows:
[0057] MN201, MN202, MP201, and MP202 are two sets of input transistors used to achieve rail-to-rail input of the op-amp. MN203 and MP203 are two sets of tail current transistors, providing a reasonable quiescent operating point for the two sets of input transistors. MP204 and MP206 are mirror transistors used to generate the tail current of the first stage of the op-amp. MP205 and MP207 are cascode transistors used to increase the output impedance of the first stage. MN204, MN205, MN206, and MN207 form a wide-swing cascode current mirror, which mirrors the current signal generated by input transistors MN202 and MP201 to the output branch, and the cascode structure can improve the output impedance. MP208, MP209, MP210, MP211, MP212, MN208, MN209, MN210, MN211, and MN212 form a transconductance linear loop used to provide static bias for the output stage. MP208 and MP209 mirror currents through wide-swing cascode current mirrors. A constant current flows through MN209 and MN210. Based on the current and width-to-length ratio of MN208 and MN209, the VGS (gate-source voltage) of MN208 is designed to be equal to the VGS of MN209. Therefore, the VGS of MN210 is equal to the VGS of MN213 and MN214, meaning that MN213 and MN214 mirror the current of MN210. Similarly, MN211 and MN212 mirror currents through wide-swing cascode current mirrors. A constant current flows through MP210 and MP211. Based on the current and width-to-length ratio of MP211 and MP212, the VGS of MP211 is designed to be equal to the VGS of MP212. Therefore, the VGS of MP210 is equal to the VGS of MP213 and MP214, meaning that MP213 and MP214 mirror the current of MP210. The gates of MP213 and MP214 are connected together, and the gates of MN213 and MN214 are connected together. As long as MP213 and MP214, and MN213 and MN214 are always in the saturation region, that is, the voltages of the first feedback signal VO and the reference signal VREF will not be too high or too low, the function of mirroring the output current can be achieved.
[0058] Furthermore, by feeding the first feedback signal VO back to the second input terminal (inverting input terminal) of the second amplification unit OP2 to form a unity-gain buffer, the node small-signal impedance between the output terminals of the first voltage signal and the second voltage signal can be reduced to:
[0059]
[0060] Where, r o It reduces the small-signal impedance before, r o' is the reduced small-signal impedance, and A is the open-loop gain of the second amplification unit OP2, which means simultaneously pushing the gate poles of the output power transistors MP214 and MN214 to a higher frequency outside the unity-gain bandwidth of the overall loop, thereby improving system stability.
[0061] Optionally, such as Figure 3 As shown, in one embodiment, the output stage 22 further includes a second resistor R2 and a third resistor R3. The first terminal of the second resistor R2 is connected to the drain of the first transistor MP214, and the first terminal of the third resistor R3 is connected to the second terminal of the second resistor R2, outputting a reference signal VREF. The second terminal of the third resistor R3 is connected to the drain of the second transistor MN214. In this embodiment, when the output reference signal VREF is connected to an external capacitor on the PAD, the second resistor R2 and the third resistor R3 can provide ESD (Electro-Static Discharge) protection.
[0062] Understandably, the above Figure 4 The embodiments described are provided as examples. In other embodiments, the input stage 21 may also employ other circuit structures. For example, it may not employ a rail-to-rail input method, that is, MP201, MP202, and MP203 may be removed.
[0063] like Figure 5 As shown, Figure 5 yes Figure 1 A schematic diagram of another embodiment of the second amplification unit OP2 is shown. The second amplification unit OP2 includes an input stage 21, an output stage 22, a mirror module 23, and a clamping module 24. The clamping module 24 is connected to the mirror module 23 and is used to clamp the first feedback signal VO.
[0064] Further reading Figure 6 , Figure 6 yes Figure 5 A schematic diagram of one embodiment of the clamping module 24 is shown. The clamping module 24 includes a fifth transistor MN220, a sixth transistor MP218, and a biasing module.
[0065] Among them, the fifth transistor MN220 is an N-type transistor, and its drain is used to receive the power supply voltage VDD; the sixth transistor MP218 is a P-type transistor, and its source is connected to the source of the fifth transistor MN220 and is used to receive the first feedback signal VO. The drain of the sixth transistor MP218 is grounded; the bias module is connected to the gate of the fifth transistor MN220 and the gate of the sixth transistor MP218, and is used to provide bias voltage to the fifth transistor MN220 and the sixth transistor MP218.
[0066] In some embodiments, the clamping module 24 further includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The first terminal of the fourth resistor R4 is used to receive the power supply voltage VDD, and the second terminal of the fourth resistor R4 is connected to the drain of the fifth transistor MN220. The first terminal of the fifth resistor R5 is connected to the source of the fifth transistor MN220. The first terminal of the sixth resistor R6 is connected to the second terminal of the fifth resistor R5 and is used to receive the first feedback signal VO. The second terminal of the sixth resistor R6 is connected to the source of the sixth transistor MP218.
[0067] Optionally, in one embodiment, the bias module includes a seventh transistor MP215, an eighth transistor MP216, a ninth transistor MN215, a tenth transistor MN216, an eleventh transistor MP217, a twelfth transistor MN217, a seventh resistor R7, a thirteenth transistor MN218, and a fourteenth transistor MN219.
[0068] Among them, the seventh transistor MP215 is a P-type transistor, with its source receiving a power supply signal and its gate receiving a first bias signal VBP; the eighth transistor MP216 is a P-type transistor, with its source connected to the drain of the seventh transistor and its gate receiving a second bias signal VBPCAS; the ninth transistor MN215 is an N-type transistor, with its drain connected to the drain of the eighth transistor MP216 and its gate receiving a third bias signal VBNCAS; the tenth transistor MN216 has its drain connected to the source of the ninth transistor MP216, its gate connected to the drain of the eighth transistor MP216, and its source grounded; the eleventh transistor MP217 is a P-type transistor, with its source receiving a power supply signal VDD and its gate receiving a first bias signal VBPCAS. Signal VBP, the drain of the eleventh transistor MP217 is connected to the gate of the fifth transistor MN220; the twelfth transistor MN217 is an N-type transistor, the drain of the twelfth transistor MN217 is connected to the drain of the eleventh transistor MP217, the gate of the twelfth transistor MN217 is used to receive the third bias signal VBNCAS, and the source of the twelfth transistor MN217 is grounded; the first terminal of the seventh resistor R7 is used to receive the power supply signal VDD; the thirteenth transistor MN218 is an N-type transistor, the drain of the thirteenth transistor MN218 is connected to the second terminal of the seventh resistor R7, the gate of the thirteenth transistor MN218 is used to receive the third bias signal VBNCAS, and the source of the thirteenth transistor MN218 is connected to the gate of the sixth transistor MP218; the fourteenth transistor MN219 is an N-type transistor, the drain of the fourteenth transistor MN219 is connected to the source of the thirteenth transistor MN218, the gate of the fourteenth transistor MN219 is connected to the drain of the eighth transistor MP216, and the source of the fourteenth transistor MN219 is grounded.
[0069] The principle of the above circuit is explained below:
[0070] MP215, MP216, MP217, MP218, MN215, MN216, MN217, MN218, MN219, and MN220 implement the function of clamping the first feedback signal VO of the load. MP217 mirrors a constant current through a current mirror. The gate of MN217 receives the third bias signal VBNCAS and can be regarded as a fixed resistor. The bias voltage of the gate of MN220 is obtained by setting the size of MN217. MP215 and MP216 mirror a constant current through a cascode current mirror, and then mirror the current through a cascode current mirror composed of MN215, MN216, MN218, and MN219. Since the gate voltage of MP218 is equal to the voltage of the third bias signal VBNCAS minus the VGS of MN218, the VGS value is obtained by setting the size of MN218, and then the gate bias voltage of MP218 is set. Its main working principle is as follows: When the reference signal VREF acts as a current source to provide a large current, the voltages of the first voltage signal VP and the second voltage signal VN will decrease. The voltage of the reference signal VREF can remain stable due to the loop effect. However, in this case, the voltage of the first feedback signal VO will increase. At this time, the gate-source voltage difference of MP218 increases, and MP218 turns on to pull down the voltage of the first feedback signal VO. Conversely, when the reference signal VREF acts as a current sink to absorb a large current, the voltages of the first voltage signal VP and the second voltage signal VN will increase. The voltage of the reference signal VREF can still remain stable due to the loop effect. However, in this case, the voltage of the first feedback signal VO will decrease. At this time, the gate-source voltage difference of MN220 increases, and MN220 turns on to pull up the voltage of the reference signal VO.
[0071] In summary, under the action of clamping module 24, the load change provided by reference signal VREF will not cause a large change in the voltage of the first feedback signal VO, which can ensure accurate mirror output current so that the second amplification unit OP2 can work normally as a whole. The gate poles of power transistors MP214 and MN214 can still be pushed away by the unity-gain feedback loop of the second amplification unit OP2, and the loop remains stable.
[0072] It is worth noting that the first amplifier unit OP1 with differential input and single-ended output, and the second amplifier unit OP2 with folded cascode rail-to-rail input stage and transconducting linear loop class AB output stage in this example are just examples; op-amps with other structures can achieve the same function.
[0073] The reference circuit provided in this embodiment includes: a first amplification unit, wherein a first input terminal of the first amplification unit is used to receive an input signal, and an output terminal of the first amplification unit is used to output a control signal; a second amplification unit, wherein a first input terminal of the second amplification unit is connected to the output terminal of the first amplification unit and is used to receive the control signal, a first output terminal of the second amplification unit is used to output a reference signal, a second output terminal of the second amplification unit is used to output a first feedback signal, and a second output terminal of the second amplification unit is connected to the second input terminal of the second amplification unit and is used to feed the first feedback signal back to the second input terminal of the second amplification unit, wherein the current flowing through the second output terminal of the second amplification unit has a mirror relationship with the current flowing through the first output terminal of the second amplification unit; and a feedback unit, wherein the feedback unit is connected to the output terminal of the second amplification unit and the second input terminal of the first amplification unit and is used to generate a corresponding second feedback signal according to the reference signal and feed the second feedback signal back to the second input terminal of the first amplification unit. In the above manner, in a VREF circuit with NMOS and PMOS as outputs, by mirroring the output reference signal and inputting it to the inverting input of the second amplification unit, a unity-gain buffer is formed, which simultaneously pushes the gate poles of the NMOS and PMOS to a higher frequency outside the overall loop unity-gain bandwidth, thereby improving system stability.
[0074] In a further embodiment, a zero-point compensation module is added to the output stage of the first amplification unit to provide a left half-plane zero. This zero-point is used to compensate for the influence of the output pole of the first amplification unit 1 on the loop stability, thereby improving the system stability.
[0075] like Figure 7 As shown, Figure 7 This is a schematic diagram of a chip embodiment provided in this application. The chip 200 integrates a reference circuit 100 as described in the above embodiment.
[0076] Optionally, the chip 200 further integrates an input signal generation circuit for generating an input signal VBG.
[0077] Optionally, the chip 200 may further integrate a functional module, and the reference signal VREF generated by the reference circuit 100 is provided to the functional module. The functional module may be an ADC, ACD, comparator circuit, etc.
[0078] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A reference circuit, characterized in that, The reference circuit includes: The first amplification unit has a first input terminal for receiving an input signal and an output terminal for outputting a control signal. The second amplification unit has a first input terminal connected to the output terminal of the first amplification unit for receiving the control signal, a first output terminal for outputting a reference signal, a second output terminal for outputting a first feedback signal, and a second output terminal connected to the second input terminal for feeding the first feedback signal back to the second input terminal. The current flowing through the second output terminal of the second amplification unit is a mirror image of the current flowing through the first output terminal of the second amplification unit. A feedback unit is connected to the output terminal of the second amplification unit and the second input terminal of the first amplification unit. It is used to generate a corresponding second feedback signal according to the reference signal and feed the second feedback signal back to the second input terminal of the first amplification unit. The second amplification unit includes: An input stage is provided to receive the control signal and the first feedback signal, and to convert the control signal and the first feedback signal as differential inputs into a first voltage signal and a second voltage signal. An output stage is provided for receiving the first voltage signal and the second voltage signal, and for outputting the reference signal under the bias of the first voltage signal and the second voltage signal; A mirror module is connected to the output stage to form a current mirror circuit. The mirror module is used to receive the first voltage signal and the second voltage signal, and output the first feedback signal under the bias of the first voltage signal and the second voltage signal.
2. The reference circuit according to claim 1, characterized in that, The first amplification unit includes: A differential amplifier module, wherein a first input terminal of the differential amplifier module is used to receive the input signal, a second input terminal of the differential amplifier module is used to receive the second feedback signal, and an output terminal of the differential amplifier module is used to output the control signal; A zero-point compensation module is connected to the output of the differential amplifier module.
3. The reference circuit according to claim 2, characterized in that, The zero-point compensation module includes: A first resistor, the first end of which is connected to the output terminal of the differential amplifier module; A first capacitor, the first end of which is connected to the second end of the first resistor, and the second end of the first capacitor is grounded.
4. The reference circuit according to claim 1, characterized in that, The input level is a rail-to-rail input level.
5. The reference circuit according to claim 1, characterized in that, The output level is the class AB output level.
6. The reference circuit according to claim 1, characterized in that, The output stage includes a first transistor and a second transistor. The first transistor is a P-type transistor, and the second transistor is an N-type transistor. The source of the first transistor is used to receive a power supply signal, and the gate of the first transistor is used to receive the first voltage signal. The drain of the second transistor is connected to the drain of the first transistor and outputs the reference signal. The gate of the second transistor is used to receive the second voltage signal, and the source of the second transistor is grounded. The mirror module includes a third transistor and a fourth transistor. The third transistor is a P-type transistor, and the fourth transistor is an N-type transistor. The third transistor is connected to the first transistor to form a P-type current mirror, and the fourth transistor is connected to the second transistor to form an N-type current mirror. The drain of the third transistor is connected to the drain of the fourth transistor and outputs the first feedback signal.
7. The reference circuit according to claim 6, characterized in that, The output stage further includes a second resistor and a third resistor. The first end of the second resistor is connected to the drain of the first transistor, the first end of the third resistor is connected to the second end of the second resistor and outputs the reference signal, and the second end of the third resistor is connected to the drain of the second transistor.
8. The reference circuit according to claim 6, characterized in that, The reference circuit further includes a clamping module, which is connected to the mirror module and is used to clamp the first feedback signal.
9. The reference circuit according to claim 8, characterized in that, The clamping module includes: The fifth transistor is an N-type transistor, and its drain is used to receive the power supply voltage. The sixth transistor is a P-type transistor, the source of which is connected to the source of the fifth transistor and is used to receive the first feedback signal, and the drain of the sixth transistor is grounded. A bias module, which is connected to the gate of the fifth transistor and the gate of the sixth transistor, is used to provide a bias voltage to the fifth transistor and the sixth transistor.
10. The reference circuit according to claim 9, characterized in that, The clamping module also includes: The fourth resistor has a first end for receiving power supply voltage and a second end connected to the drain of the fifth transistor. The fifth resistor, the first end of which is connected to the source of the fifth transistor; A sixth resistor, the first end of which is connected to the second end of the fifth resistor and is used to receive the first feedback signal, and the second end of which is connected to the source of the sixth transistor.
11. The reference circuit according to claim 9, characterized in that, The bias module includes: The seventh transistor is a P-type transistor, the source of which is used to receive a power supply signal, and the gate of which is used to receive a first bias signal. The eighth transistor is a P-type transistor, the source of which is connected to the drain of the seventh transistor, and the gate of which is used to receive a second bias signal. The ninth transistor is an N-type transistor, the drain of the ninth transistor is connected to the drain of the eighth transistor, and the gate of the ninth transistor is used to receive a third bias signal. The tenth transistor has its drain connected to the source of the ninth transistor, its gate connected to the drain of the eighth transistor, and its source grounded. The eleventh transistor is a P-type transistor. The source of the eleventh transistor is used to receive a power supply signal, the gate of the eleventh transistor is used to receive the first bias signal, and the drain of the eleventh transistor is connected to the gate of the fifth transistor. The twelfth transistor is an N-type transistor, the drain of the twelfth transistor is connected to the drain of the eleventh transistor, the gate of the twelfth transistor is used to receive the third bias signal, and the source of the twelfth transistor is grounded. The seventh resistor, the first end of which is used to receive a power signal; The thirteenth transistor is an N-type transistor. The drain of the thirteenth transistor is connected to the second terminal of the seventh resistor. The gate of the thirteenth transistor is used to receive the third bias signal. The source of the thirteenth transistor is connected to the gate of the sixth transistor. The fourteenth transistor is an N-type transistor. The drain of the fourteenth transistor is connected to the source of the thirteenth transistor, the gate of the fourteenth transistor is connected to the drain of the eighth transistor, and the source of the fourteenth transistor is grounded.
12. A chip, characterized in that, The chip integrates a reference circuit as described in any one of claims 1-11.
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