An off-chip driver

Abstract

An off-chip driver (OCD) device includes a signal transition detector, a front-end driver, a first main driver, a second main driver, a first impedance supplier, and a second impedance supplier. The signal transition detector detects a transition state of an input signal to generate decision information. The front-end driver generates a control signal according to the decision information, and generates a driving signal according to the input signal. The first main driver and the second main driver generate an output signal to a pad according to the driving signal. The first impedance supplier adjusts a first resistance value between the first main driver and the pad according to a first control signal. The second impedance supplier adjusts a second resistance value between the second main driver and the pad according to a second control signal.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an off-chip driving device, and more specifically, an off-chip driving device that can increase the response time of signal conversion. Background Technology

[0002] As the operating speed of memory components increases, the amplitude of transmitted signals decreases in high-speed data transmission modes due to channel effects. Please refer to [reference needed]. Figure 8 This figure illustrates the waveform of a high-speed data transmission mode in the prior art. Figure 8 In this example, an input data IND is received based on the frequency signal CLK, while an ideal output data IDEALD is expected to be received by the receiver. It can be seen that if the period of the frequency signal CLK becomes increasingly shorter, a large signal conversion offset will occur in the actual output data ACTD. Therefore, signal distortion will occur in the external driver device operating in high-speed data transmission mode. Thus, improving the signal distortion of the external driver device in high-speed data transmission mode is an important goal for designers in this field. Summary of the Invention

[0003] This disclosure provides an external chip driving device with high transmission time.

[0004] The chip external driving device includes a chip external driving device. The chip external driving (OCD) component includes a signal transition detector, a front-end driver, a first main driver, a second main driver, a first impedance supply, and a second impedance supply. The signal transition detector detects the transition state of the input signal to generate decision information. The front-end driver is coupled to the signal transition detector, generates a first control signal and a second control signal based on the decision information, and generates a first drive signal and a second drive signal based on the input signal. The first main driver is coupled to the front-end driver and a power supply terminal, and receives the first drive signal. The second main driver is coupled to the front-end driver and a reference ground terminal, and receives the second drive signal. The first and second main drivers generate output signals to a pad based on the first and second drive signals. The first impedance supply is connected in series between the first main driver and the pad, providing and adjusting a first resistance value between the first main driver and the pad according to the first control signal. The second impedance supply is connected in series between the second main driver and the pad, providing and adjusting a second resistance value between the second main driver and the pad according to the second control signal.

[0005] Therefore, this disclosure provides an external chip driver that allows adjustment of the resistance between the driver and the pads when the input signal is switched. That is, when the output signal of the external chip driver is switched, the resistance values ​​of the charging and discharging paths can be reduced at the instant of signal switching, thereby reducing the response time in the output signal.

[0006] It should be understood that the foregoing general description and the following detailed description are exemplary and intended to provide a further explanation of the claimed disclosure. Attached Figure Description

[0007] The best understanding of the various embodiments disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the art, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A schematic diagram of an external chip driving device according to an embodiment of the present disclosure is shown;

[0009] Figures 2A to 2D The main driver of an external chip driving device according to different embodiments of the present disclosure is shown;

[0010] Figure 3A and Figure 3B An impedance supply for an external driving device according to different embodiments of the present disclosure is shown;

[0011] Figure 4A and Figure 4B An impedance supply for an external driving device according to other embodiments of the present disclosure is shown;

[0012] Figure 5A Based on this disclosure Figure 4A Waveform diagram of the impedance supply in the embodiment;

[0013] Figure 5B Based on this disclosure Figure 4B Waveform diagram of the impedance supply in the embodiment;

[0014] Figure 6A and Figure 6B An impedance supply for an external driving device according to other embodiments of the present disclosure is shown;

[0015] Figure 7 A schematic diagram of a portion of the circuitry of an external chip driving device according to an embodiment of the present disclosure is shown;

[0016] Figure 8 The waveform diagram of the high-speed data transmission mode in the current technology is shown.

[0017] Explanation of icon numbers:

[0018] 100, 700: External driver components for chips

[0019] 110: Signal Conversion Detector

[0020] 120: Front Side Driver

[0021] 130, 160, 201, 202, 203, 204, 711, 714: Main drive

[0022] 140, 150, 301, 302, 401, 402, 601, 602, 712, 713: Impedance Suppliers

[0023] 7211-721L, 7241-724K: Auxiliary drivers

[0024] 722, 723: Auxiliary impedance supply

[0025] ACTD: Actual Output Data

[0026] CLK: Frequency signal

[0027] CTN, CTNB: Second control signals

[0028] CTP: First Control Signal

[0029] CTPB: Inverted signal

[0030] DND: Second drive signal

[0031] DNDA1-DNDAK, UPDA1-UPDAL: Auxiliary drive signals

[0032] DS1: First Decision Signal

[0033] DS2: Second Decision Signal

[0034] ED1, ED3: First end

[0035] ED2, ED4: Second end

[0036] IDEALD: Ideal Output Data

[0037] IN, IN0, IN1: Input signals

[0038] IND: Input data

[0039] LG11, LG11-LG1N, LG21, LG21-LG2M: Logic Circuits

[0040] MN21-MN2M, MP11-MP1N: Transistors

[0041] MUX11, MUX11-MUX1N, MUX21, MUX21-MUX2M: Multitasking

[0042] NSL1, NSL1-NSLM, NSL1-NSLN, PSL1, PSL1-PSLN: Selection signals

[0043] OUT, PD1, PU1: Output signals

[0044] PD: solder pad

[0045] PD1-PDM, PU1-PUN: Output signals

[0046] R1, R10-R1N, R11-R1N, R2, R20-R2M, R21-R2M, r2: Resistors

[0047] SW11, SW21, SW11-SW1N, SW21-SW2M: Switches

[0048] UPD: First drive signal

[0049] VDD: Power supply voltage

[0050] VSS: Reference ground voltage Detailed Implementation

[0051] The following discloses numerous different embodiments or instances of various features for implementing the provided objectives. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and not to illustrate relationships between the various embodiments and / or configurations discussed.

[0052] The present preferred embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0053] Please refer to Figure 1 , Figure 1This is a schematic diagram of an external chip driving device according to an embodiment of the present disclosure. The external chip driving device 100 includes a signal transition detector 110, a front-end driver 120, a main driver 130, 160, and impedance suppliers 140 and 150. The signal transition detector 110 receives an input signal IN and is used to detect the transition state of the input signal IN0 to generate decision information. The decision information may include a first decision signal DS1 and a second decision signal DS2. The first decision signal DS1 is used to indicate that the input signal IN0 transitions from a first logic value to a second logic value, and the second decision signal DS2 is used to indicate that the input signal IN0 transitions from a second logic value to a first logic value, wherein the first logic value can be logic 0 and the second logic value can be logic 1.

[0054] In some embodiments, the signal transition detector 110 can detect the transition state of the input signal IN0 to generate a first decision signal DS1 and a second decision signal DS2. When the input signal IN0 is detected to transition from logic 0 to logic 1, the signal transition detector 110 can generate a first pulse on the first decision signal DS1. When the input signal IN0 is detected to transition from logic 1 to logic 0, the signal transition detector 110 can generate a second pulse on the second decision signal DS2. The first pulse can be a positive pulse, and the second pulse can be a negative pulse.

[0055] Front-end driver 120 is coupled to signal transition detector 110. Front-end driver 120 receives input signal IN1, first decision signal DS1, and second decision signal DS2, and generates a first control signal CTP, a second control signal CTN, a first drive signal UPD, and a second drive signal DND based on the first decision signal DS1, the second decision signal DS2, and the input signal IN1. Specifically, front-end driver 120 can generate the first drive signal UPD and the second drive signal DND based on the input signal IN1. Taking the external driving device 100 in non-inverting drive mode as an example: If the input signal IN1 is at logic 0, front-end driver 120 can generate the first drive signal UPD and the second drive signal DND, both of which are logic 1. If the input signal IN1 is at logic 1, front-end driver 120 can generate the first drive signal UPD and the second drive signal DND, both of which are logic 0. In this way, the output signal OUT in the external driving device 100 can be at the same logic value as the input signal IN1.

[0056] On the other hand, taking the external driver device 100 in inverted drive mode as an example: If the input signal IN1 is at logic 0, the front-end driver 120 can generate a first drive signal UPD and a second drive signal DND, both of which are logic 0. If the input signal IN1 is at logic 1, the front-end driver 120 can generate a first drive signal UPD and a second drive signal DND, both of which are logic 1. In this way, the output signal OUT in the external driver device 100 can be at the same logic value as the input signal IN1.

[0057] On the other hand, the front-end driver 120 can generate a first control signal CTP and a second control signal CTN according to the first decision signal DS1 and the second decision signal DS2, respectively.

[0058] The main driver 130 is coupled to the power supply terminal to receive the power supply voltage VDD. The main driver 130 is also coupled to the front-end driver 120. The main driver 160 is coupled to the reference ground terminal to receive the reference ground voltage VSS. The main driver 160 is also coupled to the front-end driver 120. The main driver 130 receives a first drive signal UPD and provides a drive path to pull the output signal OUT high. The main driver 160 receives a second drive signal DND and provides a drive path to pull the output signal OUT low. An impedance supply 140 is coupled between the pad PD and the main driver 130. An impedance supply 150 is coupled between the pad PD and the main driver 160. The main driver 130 and the impedance supply 140 together provide a pull-up resistor for the external driver device 100. The main driver 160 and the impedance supply 150 together provide a pull-down resistor for the external driver device 100. On the other hand, impedance suppliers 140 and 150 are used for electrostatic discharge (ESD) protection devices and main drivers 130 and 160, respectively. It should be noted that the resistance value in impedance supplier 140 can be adjusted according to the first control signal CTP, while the resistance value in impedance supplier 150 can be adjusted according to the second control signal CTN.

[0059] Specifically, if the input signal IN does not transition between two logic values, the resistance values ​​of impedance suppliers 140 and 150 can remain unchanged. One of the main drivers 130 and 160 is activated to drive the output signal OUT at logic 0 or 1. If the input signal IN transitions from logic 0 to logic 1, main driver 130 is activated, while main driver 160 is disabled. Main driver 130 can pull the output signal OUT high to logic 1 according to the first drive signal UPD, while impedance supplier 140 can decrease its resistance value according to the first control signal CTP.

[0060] Conversely, if the input signal IN transitions from logic 1 to logic 0, the main driver 160 is activated, while the main driver 130 is disabled. The main driver 160 can pull down the output signal OUT to logic 0 according to the second drive signal DND, and the impedance supply 150 can reduce the resistance value according to the second control signal CTN.

[0061] As can be seen, in this embodiment, when the output signal OUT is converted according to the input signal IN, one of the impedance suppliers 140 and 150 can reduce the corresponding resistance value between the pad PD and the main driver 130 or 160. That is, the driving capability of one of the main drivers 130 or 160 is not affected by the impedance supplier 140 or 150, and can convert the output signal OUT to the correct logic value, thereby reducing the conversion delay of the external driving device 100.

[0062] Regarding the hardware structure, in this disclosure, the signal transition detector 110 can be implemented using any signal transition detection circuit existing by those skilled in the art. The front-end driver 120 can be implemented using digital circuitry, constructed using one or more logic gates and output buffers. In some embodiments, the front-end driver 120 may further include ZQ calibration control related circuitry, slew rate control circuitry, and on-die termination (ODT) control circuitry, etc.

[0063] Please refer to Figures 2A to 2D , Figures 2A to 2D This refers to the main driver in an external chip driving device according to different embodiments of this disclosure. Figure 2A In the main driver 201, there are transistor MP <1> Transistor MP <1> The first terminal receives the power supply voltage VDD, and the transistor MP <1> The second terminal can be coupled to the corresponding impedance supply, transistor MP <1> The control terminal receives the first drive signal UPD. Transistor MP <1> It is a P-type transistor. When the first drive signal UPD is logic 0, the transistor MP can be turned on. <1> To make transistor MP <1> The second terminal is driven (pull-up) to the power supply voltage VDD. Conversely, when the first drive signal UPD is logic 1, transistor MP... <1> This is the deadline.

[0064] exist Figure 2B In the main driver 202, there are multiple transistor MP <1> To MP <x>And a resistor R1. Transistor MP <1> To MP <x>It is connected in series with resistor R1 and controlled by the same first drive signal UPD. Transistor MP <1> To MP <x>They can be turned on simultaneously, and the transistor MP can be driven (pulled high) according to the first drive signal UPD. <x>The second terminal is connected to the power supply voltage VDD. Additionally, transistor MP... <1> To MP <x>The transistor MP can be simultaneously turned off based on the first drive signal UPD. <1> To MP <x>The numbering can be determined by the designer and is not restricted here.

[0065] exist Figure 2A and Figure 2B In the middle, both main drivers 201 and 202 are used to implement Figure 1 The main driver 130 is shown. In some embodiments, one resistor may be built into the main driver 201, and another resistor may be built into the main driver 202.

[0066] exist Figure 2C In the main driver 203, transistor MN is included. <1> Transistor MN <1> The first end can be coupled to the corresponding impedance supply, transistor MN <1> The second terminal receives the reference ground voltage VSS, and transistor MN <1> The control terminal receives the second drive signal DND. Transistor MN <1> It can be an N-type transistor, which can turn on transistor MN when the second drive signal DND is logic 1. <1> Transistor MN <1> The first terminal is driven (pull-down) to the reference ground voltage VSS. Conversely, when the second drive signal DND is logic 0, transistor MN1 is turned off.

[0067] exist Figure 2D In the main driver 204, there are multiple transistors MN1 to MN2. <y>and resistor r2. Transistor MN <1> To MN <y>It is connected in series with resistor R2 and controlled by the same second drive signal DND. Transistor MN <1> To MN <y>Simultaneously, they can be turned on, and the first terminal of transistor MN can be driven (pull-down) according to the second drive signal DND. <y>The voltage VSS is adjusted to the reference ground voltage. Furthermore, according to the second drive signal DND, transistor MN... <1> To MN <y>Both can be cut off simultaneously. Transistor MN <1> To MN <y>The quantity can be set by the designer and is not limited here.

[0068] exist Figure 2B and Figure 2D In the embodiment, transistor MP <1> To MP <x>The number and transistor MN <1> To MN <y>The quantities can be the same or different, and there is no restriction here.

[0069] refer to Figure 3A and Figure 3B This illustrates the impedance supply of an external driving device according to different embodiments of the present disclosure. Figure 3A In the impedance supply 301, there is a first terminal ED1 and a second terminal ED2. The first terminal ED1 of the impedance supply 301 is used to couple to the corresponding main driver, such as... Figure 1 The main driver 130 is shown. The second terminal ED2 of the impedance supply 301 is used for coupling to the solder pad.

[0070] Impedance supplier 301 includes N+1 resistors R10-R1N and N switches SW11-SW1N, where N is a positive integer. Resistors R1N-R10 are coupled between the first terminal ED1 and the second terminal ED2. Switches SW11-SW1N are connected in parallel with resistors R11-R1N, respectively. Switches SW11-SW1N can be controlled by the same control signal to be turned on or off. When all switches SW11-SW1N are on, impedance supplier 301 provides minimum resistance (equal to the resistance of resistor R10). Conversely, when all switches SW11-SW1N are off, impedance supplier 301 provides maximum resistance (equal to the sum of the resistances of all resistors R10-R1N).

[0071] exist Figure 3B In the impedance supply 302, there is a first terminal ED3 and a second terminal ED4. The first terminal ED3 of the impedance supply 302 is used for coupling to the solder pad. The second terminal ED4 of the impedance supply 302 is used for coupling to the corresponding main driver, such as... Figure 1 The main drive 160 is shown in the figure.

[0072] Impedance supply 302 includes M+1 resistors R20-R2M and M switches SW21-SW2M, where M is a positive integer. Resistors R20-R2M are coupled between the first terminal ED3 and the second terminal ED4. Switches SW21-SW2M are connected in parallel with resistors R21-R2M. Switches SW21-SW2M can be controlled by the same control signal to turn on or off. When all switches SW21-SW2M are on, impedance supply 302 provides minimum resistance (equal to the resistance of resistor R20). Conversely, when all switches SW21-SW2M are off, impedance supply 302 provides maximum resistance (equal to the sum of the resistances of all resistors R20-R2M).

[0073] exist Figure 3A and Figure 3B In this embodiment, the number of resistors R10-R1N and the number of resistors R20-R2M can be the same or different, and there is no limitation on this.

[0074] refer to Figure 4A and Figure 4B , Figure 4A and Figure 4B An impedance supply for an external driving device according to other embodiments of the present disclosure is shown. Figure 4A In this embodiment, the impedance supply 401 includes N+1 resistors R10-R1N, N switches SW11-SW1N, and N logic circuits LG11-LG1N, where N is a positive integer. Resistors R10-R1N are connected in series between the second terminal ED2 and the first terminal ED1 of the impedance supply 401. Switches SW11-SW1N are formed by transistors MP11-MP1N, and are connected in parallel with resistors R11-R1N. In this embodiment, transistors MP11-MP1N are all P-type transistors. Logic circuits LG11-LG1N are coupled to the control terminals of transistors MP11-MP1N. Logic circuits LG11-LG1N typically receive a first control signal CTP and selection signals PSL1-PSLN respectively. Logic circuits LG11-LG1N generate output signals PU1-PUN respectively. Figure 4A In the circuit, logic circuits LG11-LG1N can all be NAND gates.

[0075] The selection signals PSL1-PSLN can be determined by... Figure 1 The front-end driver 120 in this embodiment generates the signal. Taking logic circuit LG11 as an example, in this embodiment, when the selection signal PSL1 is at logic 0, logic circuit LG11 can generate an output signal PU1 to logic 1 to turn off switch SW11. When the selection signal PSL1 is at logic 1, logic circuit LG11 can invert the first control signal CTP and generate an output signal PU1 to control switch SW11. That is, selection signals PSL1-PSLN can be used to control the number of switches SW11-SW1N that are turned on to adjust the resistance of impedance supply 401.

[0076] exist Figure 4B In this embodiment, the impedance supply 402 includes M+1 resistors R20-R2M, M switches SW21-SW2M, and M logic circuits LG21-LG2M, where M is a positive integer. Resistors R20-R2M are connected in series between the second terminal ED3 and the first terminal ED4 of the impedance supply 402. Switches SW21-SW2M are formed by transistors MN21-MN2M, and are connected in parallel with resistors R21-R2M. In this embodiment, transistors MN21-MN2M are all N-type transistors. Logic circuits LG21-LG2M are coupled to the control terminals of transistors MN21-MN2M. Logic circuits LG21-LG2M typically receive a second control signal CTNB and selection signals NSL1-NSLM. Logic circuits LG21-LG2M generate output signals PD1-PDM. Figure 4B In the logic circuits, LG21-LG2M can all be AND gates.

[0077] The selection signals NSL1-NSLN can be determined by... Figure 1 The front-end driver 120 in this embodiment generates the signal. Taking logic circuit LG21 as an example, in this embodiment, when the selection signal NSL1 is logic 0, logic circuit LG21 can output logic 0 to turn off switch SW21, and when the selection signal NSL1 is logic 1, logic circuit LG21 can output a second control signal CTN to control switch SW21. That is, selection signals NSL1-NSLM can be used to control the number of switches SW21-SW2M that are turned on, thereby adjusting the resistance value of impedance supply 402.

[0078] Please refer to this together. Figure 1 , Figure 4A and Figure 5A ,in Figure 5A Based on this disclosure Figure 4A The waveform diagram of the impedance supply in the embodiment is shown. The external driver device 100 can operate based on the frequency signal CLK. The signal transition detector 110 can detect the transition state of the input signal IN to generate a first decision signal DS1 and a second decision signal DS2. When the input signal IN transitions from logic 0 to logic 1, the signal transition detector 110 generates the first decision signal DS1 with a positive pulse, and when the input signal IN transitions from logic 1 to logic 0, the signal transition detector 110 generates the second decision signal DS2 with a negative pulse. The width of the positive and negative pulses can be determined by the designer of the external driver device 100 and is not particularly limited. It should be noted that in some embodiments, the signal transition detector 110 can be integrated into the front-end driver 120. The designer can decide whether to integrate the signal transition detector 110 into the front-end driver 120 according to design requirements. In addition, the signal transition detector 110 can be designed to operate with or without a frequency signal.

[0079] The front-end driver 120 generates a first control signal CTP based on the first decision signal DS1. Here, the waveforms of the first control signal CTP and the first decision signal DS1 are identical. The front-end driver 120 further generates a selection signal PSL1. Taking logic circuit LG11 as an example, when the selection signal PSL1 is logic 0, the output signal PU1 of logic circuit LG11 remains at logic 1. Thus, the corresponding switch SW11 remains in the off (cut-off) state. Furthermore, when the selection signal PSL1 is at logic 1, the output signal PU1 of logic circuit LG11 is equal to the inverted signal of the first control signal CTP. When the input signal IN transitions from logic 0 to logic 1, a negative pulse on the output signal PU1 can turn on switch SW11.

[0080] Please refer to this together. Figure 1 , Figure 4B and Figure 5B ,in Figure 5B Based on this disclosure Figure 4B The waveform diagram of the impedance supply in this embodiment is shown. The external driver device 100 can operate based on the frequency signal CLK. The signal transition detector 110 can detect the transition state of the input signal IN to generate a first decision signal DS1 and a second decision signal DS2. When the input signal IN transitions from logic 0 to logic 1, the signal transition detector 110 generates the first decision signal DS1 with a positive pulse, and when the input signal IN transitions from logic 1 to logic 0, the signal transition detector 110 generates the second decision signal DS2 with a negative pulse. The width of the positive and negative pulses can be determined by the designer of the external driver device 100 and is not particularly limited.

[0081] The front-end driver 120 generates a second control signal CTN based on the second decision signal DS2. Here, the waveforms of the second control signal CTN and the second decision signal DS2 are identical. The front-end driver 120 further generates a selection signal NSL1. Taking logic circuit LG21 as an example, when the selection signal NSL1 is at logic 0, the output signal PD1 of logic circuit LG21 remains at logic 0. Thus, the corresponding switch SW21 remains in the off state. Furthermore, when the selection signal NSL1 is at logic 1, the output signal PD1 of logic circuit LG21 is equal to the inverted signal CTNB of the second control signal CTN. When the input signal IN transitions from logic 1 to logic 0, a positive pulse on the output signal PD1 can turn on switch SW21.

[0082] refer to Figure 6A and Figure 6B This illustrates an impedance supply for an external driving device according to other embodiments of the present disclosure. Figure 6A In this embodiment, the impedance supply 601 includes N+1 resistors R10-R1N, N switches SW11-SW1N, and N multiplexers MUX11-MUX1N, where N is a positive integer. Resistors R10-R1N are connected in series between the second terminal ED2 and the first terminal ED1 of the impedance supply 601. Switches SW11-SW1N are formed by transistors MP11-MP1N, and are connected in parallel with resistors R11-R1N. In this embodiment, transistors MP11-MP1N are all P-type transistors. Multiplexers MUX11-MUX1N are coupled to the control terminals of transistors MP11-MP1N. Multiplexers MUX11-MUX1N typically receive an inverted signal CTPB and a first control signal CTP, and each receives selection signals PSL1-PSLN. Multiplexers MUX11-MUX1N generate output signals to control switches SW11-SW1N.

[0083] Taking the MUX11 multiplexer as an example, the MUX11 multiplexer selects either the power supply voltage VDD or the inverted signal CTPB based on the selection signal PSL1 to generate the output signal. If the selection signal PSL1 is logic 0, the MUX11 multiplexer outputs the power supply voltage VDD to the control terminal of switch SW11, and switch SW11 can be turned off accordingly. Conversely, if the selection signal PSL1 is logic 1, the MUX11 multiplexer outputs the inverted signal CTPB to control switch SW11, and if the inverted signal CTPB is logic 0, switch SW11 can be turned on. At this time, the input signal of the external driver device can be converted from logic 0 to logic 1.

[0084] exist Figure 6B In this embodiment, the impedance supply 602 includes M+1 resistors R20-R2M, M switches SW21-SW2M, and M multiplexers MUX21-MUX2M, where M is a positive integer. Resistors R20-R2M are connected in series between the second terminal ED3 and the first terminal ED4 of the impedance supply 602. Switches SW21-SW2M are formed by transistors MN21-MN2M, and are connected in parallel with resistors R21-R2M. In this embodiment, transistors MN21-MN2M are all N-type transistors. Multiplexers MUX21-MUX2M are coupled to the control terminals of transistors MN21-MN2M. Multiplexers MUX21-MUX2M are typically connected to an inverted signal CTNB of a second control signal CTN, and are also connected to selection signals NSL1-NSLM. Logic circuits MUX21-MUX2M generate output signals to control switches SW21-SW2M.

[0085] Taking the multiplexer MUX21 as an example, the multiplexer MUX21 selects either the reference ground voltage VSS or the inverted signal CTNB based on the selection signal NSL1 to generate the output signal. If the selection signal NSL1 is logic 0, the multiplexer MUX21 outputs the reference ground voltage VSS to the control terminal of switch SW21, and switch SW21 can be turned off accordingly. Conversely, if the selection signal NSL1 is logic 1, the multiplexer MUX21 outputs the inverted signal CTNB to control switch SW21. If the inverted signal CTNB is logic 1, switch SW21 can be turned on. At this time, the input signal of the external driver device can transition from logic 1 to logic 0.

[0086] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a portion of the circuitry of an external chip driving device according to an embodiment of the present disclosure. Figure 7 The signal transmission detector and front-end driver of the external chip driving device 700 are not shown. The external chip driving device 700 includes main drivers 711 and 714, impedance suppliers 712 and 713, auxiliary drivers 7211-721L and 7241-724K, and auxiliary impedance suppliers 722 and 723. The main driver 711, impedance suppliers 712 and 713, and main driver 714 are connected in series. The coupling terminals of impedance suppliers 712 and 713 are also coupled to the pad PD. Auxiliary drivers 7211-721L are connected in parallel, auxiliary drivers 7241-724K are connected in parallel, and auxiliary impedance suppliers 722 and 723 are connected in series between auxiliary drivers 7211-721L and auxiliary drivers 7241-724K. One coupling terminal of auxiliary impedance suppliers 722 and 723 is also coupled to the pad PD.

[0087] In this embodiment, the main driver 711 is a pull-up driver controlled by a first drive signal UPD. The main driver 714 is a pull-down driver controlled by a second drive signal DND. The auxiliary drivers 7211-721L are pull-up drivers, each controlled by multiple auxiliary drive signals UPDA1-UPDAL. The auxiliary drivers 7241-724K are pull-up drivers, each controlled by multiple auxiliary drive signals DNDA1-DNDAK.

[0088] Impedance supplier 712 receives a selection signal PSL<1:N> and a first control signal CTP. Impedance supplier 712 adjusts the provided resistance value based on the selection signal PSL<1:N>, the first control signal CTP, and the power supply voltage VDD. Impedance supplier 713 receives a selection signal NSL<1:M>, a second control signal CTN, and a reference ground voltage VSS. Impedance supplier 713 adjusts the provided resistance value based on the selection signal NSL<1:M>, the second control signal CTN, and the reference ground voltage VSS.

[0089] Auxiliary impedance supply 722 receives a selection signal APSL<1:N1> and a first control signal CTP. Impedance supply 722 adjusts the provided resistance value based on the selection signal APSL<1:N1>, the first control signal CTP, and the power supply voltage VDD. Auxiliary impedance supply 723 receives a selection signal ANSL<1:M1>, a second control signal CTN, and a reference ground voltage VSS. Impedance supply 713 adjusts the provided resistance value based on the selection signal ANSL<1:M1>, the second control signal CTN, and the reference ground voltage VSS.

[0090] Each of the auxiliary drivers 7211-721L and the main driver 711 can have the same or different circuit structures, as determined by the designer. Similarly, each of the auxiliary drivers 7241-724K and the main driver 714 can have the same or different circuit structures, as determined by the designer. Auxiliary impedance suppliers 722 and 712 can have the same circuit structure. Auxiliary impedance suppliers 723 and 713 can have the same circuit structure. Furthermore, the values ​​of N and N1 can be the same or different, and the values ​​of M and M1 can be the same or different; no particular limitation is made here. In other words, the detailed operation of the auxiliary drivers 7211-721L, auxiliary drivers 7241-724K, and auxiliary impedance suppliers 722 and 723 can be implemented with reference to the above embodiments, and will not be repeated here.

[0091] In this embodiment, auxiliary impedance suppliers 722 and 723 are configured to perform impedance matching and ESD protection functions for the external chip driver 700. Auxiliary drivers 7211-721L and 7241-724K are used to adjust the drive capability of the external chip driver 700. In this embodiment, the main driver 711, impedance supplier 712, auxiliary drivers 7211-721L, and auxiliary impedance supplier 722 form the pull-up resistor required by the external chip driver 700, providing drive current to the external chip driver 700. The main driver 714, impedance supplier 713, auxiliary drivers 7241-724K, and auxiliary impedance supplier 723 form the pull-down resistor required by the external chip driver 700, providing pull-down current to the external chip driver 700.

[0092] In summary, external driver devices can adjust the resistance between the pads and the main driver (the external driver is the output driver stage) during input signal conversion. In other words, when the output signal of the external driver needs to correspond to the input signal conversion, the external driver can increase its driving capability. This reduces the conversion delay, improves the signal conversion slew rate, and increases the overall efficiency of the external driver.< / y> < / x> < / y> < / y> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. A chip external driving device, comprising: Signal transition detectors detect the transition state of input signals to generate decision information; A front-end driver, coupled to the signal transition detector, generates a first control signal and a second control signal based on the decision information, and generates a first drive signal and a second drive signal based on the input signal; The first main driver is coupled to the front-end driver and the power supply terminal, and receives the first drive signal; A second master driver is coupled to the front-end driver and the reference ground terminal and receives the second drive signal, wherein the first master driver and the second master driver generate an output signal to the pad according to the first drive signal and the second drive signal; A first impedance supply, connected in series between the first main driver and the pad, provides and adjusts a first resistance value between the first main driver and the pad according to the first control signal; as well as A second impedance supply, connected in series between the second main driver and the solder pad, provides and adjusts a second resistance value between the second main driver and the solder pad according to the second control signal. The first impedance supplier includes: N+1 first resistors are connected in series between the first main driver and the solder pad, where N is a positive integer; as well as N first switches are connected in parallel with N resistors out of the N+1 first resistors. The N first switches are turned on or off according to the first control signal.

2. The chip external driving device according to claim 1, wherein the second impedance supply comprises: M+1 second resistors are connected in series between the second main driver and the solder pad, where M is a positive integer; as well as M second switches are connected in parallel with M resistors of the M+1 second resistors.

3. The chip external driving device according to claim 2, wherein the front-end driver further generates a first selection signal and a second selection signal, the first impedance supply determines a first target value of the first resistance value according to the first selection signal and the first control signal, and the second impedance supply determines a second target value of the second resistance value according to the second selection signal and the second control signal.

4. The chip external driving device according to claim 3, wherein the first impedance supply comprises: N first logic circuits are coupled to the N first switches, wherein each of the N first logic circuits has two input terminals to receive the first selection signal and the first control signal respectively, and each of the N first logic circuits has an output terminal that is coupled to each of the N first switches.

5. The chip external driving device according to claim 4, wherein the second impedance supply comprises: M second logic circuits are coupled to the M second switches, wherein each of the M second logic circuits has two input terminals, which respectively receive the second selection signal and the inverted signal of the second control signal, and each of the M second logic circuits has an output terminal that is coupled to each of the M second switches.

6. The chip external driving device according to claim 5, wherein each of the M first switches is formed by a P-type transistor, and each of the M second switches is formed by an N-type transistor.

7. The chip external driving device according to claim 5, wherein each of the N first logic circuits is formed by a NAND gate.

8. The chip external driving device according to claim 5, wherein, Each of the M second logic circuits is formed by an AND gate.

9. The chip external driving device according to claim 5, wherein each of the N first logic circuits is formed by a first multiplexer, wherein each of the first multiplexers selects one of a power supply voltage and an inverted signal of the first control signal according to the first selection signal, and each of the first multiplexers controls each of the N first switches.

10. The chip external driving device according to claim 5, wherein each of the M second logic circuits is formed by a second multiplexer, wherein each of the second multiplexers selects one of a ground voltage and a second control signal according to the second selection signal, and each of the second multiplexers controls each of the M second switches.

11. The chip external driving device according to claim 2, wherein the first number of the N first switches to be turned on is determined by a first selection signal, and the second number of the M second switches to be turned on is determined by a second selection signal.

12. The chip external driving device according to claim 1, wherein the decision information includes a first decision signal and a second decision signal, wherein when the input signal changes from a first logic value to a second logic value, the signal transition detector generates a first pulse on the first decision signal, and when the input signal changes from the second logic value to a second logic value, the signal transition detector generates a second pulse on the second decision signal.

13. The chip external driving device according to claim 12, wherein the first logic value is logic 1 and the second logic value is logic 0.

14. The chip external driving device according to claim 12, wherein the first pulse is a positive pulse and the second pulse is a negative pulse.

15. The chip external driving device according to claim 1, further comprising: At least one first auxiliary driver is coupled to the power supply terminal and the front-end driver, and receives at least one first auxiliary drive signal; as well as A first auxiliary impedance supply is connected in series between the first auxiliary driver and the solder pad, and provides and adjusts a first auxiliary resistance value between the first auxiliary driver and the solder pad according to the first auxiliary control signal.

16. The chip external driving device according to claim 1, further comprising: At least one second auxiliary driver is coupled to the reference ground terminal and the front-end driver, and receives at least one second auxiliary drive signal, wherein a first auxiliary driver and the second auxiliary driver generate an auxiliary output signal to the pad according to the first auxiliary drive signal and the second auxiliary drive signal; as well as A second auxiliary impedance supply is connected in series between the second main driver and the solder pad, and provides and adjusts a second auxiliary resistance value between the second auxiliary driver and the solder pad according to the second auxiliary control signal.

17. A chip external driving device, comprising: Signal transition detectors detect the transition state of input signals to generate decision information; A front-end driver, coupled to the signal transition detector, generates a first control signal and a second control signal based on the decision information, and generates a first drive signal and a second drive signal based on the input signal; The first main driver is coupled to the front-end driver and the power supply terminal, and receives the first drive signal; A second master driver is coupled to the front-end driver and the reference ground terminal and receives the second drive signal, wherein the first master driver and the second master driver generate an output signal to the pad according to the first drive signal and the second drive signal; A first impedance supply, connected in series between the first main driver and the pad, provides and adjusts a first resistance value between the first main driver and the pad according to the first control signal; as well as A second impedance supply, connected in series between the second main driver and the solder pad, provides and adjusts a second resistance value between the second main driver and the solder pad according to the second control signal. The second impedance supplier includes: M+1 second resistors are connected in series between the second main driver and the solder pad, where M is a positive integer; as well as M second switches are connected in parallel with M resistors of the M+1 second resistors.

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