Receive circuit suitable for multiple high speed interface standards

Abstract

This disclosure provides a receiving circuit applicable to various high-speed interface standards, and is applied in the field of electronic circuit design technology. The method includes converting an input signal into a common-mode voltage using a modulation resistor circuit, comparing the common-mode voltage with a reference voltage in a common-mode voltage detection circuit, and outputting the input signal after passing through a folded amplifier and a first common-source amplifier if the common-mode voltage is less than the reference voltage; otherwise, outputting the input signal after passing through a second common-source amplifier. Thus, the receiving circuit can still operate normally even when the common-mode voltage changes from 0 volts to the power supply voltage, exhibiting constant transconductance, the ability to detect small swings, low noise, and a low bit error rate.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit design technology, and in particular to a receiving circuit applicable to multiple high-speed interface standards. Background Technology

[0002] Common high-speed interface standards include LVDS, CML, VML, and LVPECL. Traditional interface conversions require DC blocking capacitors and reloading the common-mode voltage, which is cumbersome. Therefore, designing a receiver circuit that can adapt to various interfaces is particularly important. This requires the common-mode voltage to be rail-to-rail, meaning it can vary between 0 volts and the maximum voltage VDD. Traditional rail-to-rail receiver circuits can only use a sleeve-type cascode structure for the output stage, resulting in excessive circuit gain and amplification of noise, which worsens the bit error rate. In addition, the transconductance of the input stage cannot remain constant under different voltages, causing distortion and further deteriorating the bit error rate. Summary of the Invention

[0003] This disclosure provides a receiving circuit and its operating method applicable to various high-speed interface standards.

[0004] According to a first aspect of this disclosure, a receiver circuit suitable for various high-speed interface standards is provided. The circuit includes:

[0005] The core receiving circuit and common-mode voltage detection circuit; among which,

[0006] The core receiving circuit includes a modulation resistor circuit, a folded amplifier, a first common-source amplifier, a second common-source amplifier, a first buffer, a second buffer, and a control voltage node Vc1;

[0007] Furthermore, the first input terminal of the modulation resistor circuit is connected to the positive input voltage node Vin+, the second input terminal is connected to the negative input voltage node Vin-, and the output terminal is connected to the common-mode voltage node COM_IN.

[0008] The first input terminal of the folded amplifier is connected to the positive input voltage node Vin+, the second input terminal is connected to the negative input voltage node Vin-, the first node is connected to the control voltage node Vc1, the second node is connected to the first node of the first common source amplifier, the first node of the first buffer, and the first node of the second buffer, the first output terminal is connected to the first input terminal of the first common source amplifier, and the second output terminal is connected to the second input terminal of the first common source amplifier.

[0009] The first output terminal of the first common-source amplifier is connected to the input terminal of the first buffer, and the second output terminal is connected to the input terminal of the second buffer.

[0010] The first input terminal of the second common-source amplifier is connected to the negative input voltage node Vin-, the second input terminal is connected to the positive input voltage node Vin+, the first node is connected to the control voltage node Vc1, the first output terminal is connected to the input terminal of the first buffer, and the second output terminal is connected to the input terminal of the second buffer.

[0011] The output of the first buffer is connected to the negative output voltage node Vout-, and the output of the second buffer is connected to the positive output voltage node Vout+.

[0012] The common-mode voltage detection circuit includes a bias current supply circuit and a comparison circuit;

[0013] Furthermore, the input terminal of the bias current supply circuit is connected to the common-mode voltage node COM_IN, the first output terminal is connected to the first input terminal of the comparator circuit, and the second output terminal is connected to the second input terminal of the comparator circuit.

[0014] The output of the comparator circuit is connected to the digital output signal node Z.

[0015] In some possible implementations of the first aspect, the modulation resistor circuit includes:

[0016] Resistors R9-R11;

[0017] The first input terminal of the modulation resistor circuit includes one end of resistor R9, the second input terminal includes one end of resistor R10, and the output terminal includes one end of resistor R11.

[0018] The other end of resistor R9 is connected to the other end of resistor R10 and the other end of resistor R11.

[0019] In some possible implementations of the first aspect, the folded amplifier includes:

[0020] PMOS transistors MP2-MP4, MP6-MP10, NMOS transistors MN14-MN15, resistors R3-R4; among them;

[0021] The first input terminal of the folded amplifier includes the gate of MP7, the second input terminal includes the gate of MP8, the first node includes the gates of MP2-MP4, the second node includes the source of MP2-MP4, the first output terminal includes the drain of MN14, and the second output terminal includes the drain of MN15.

[0022] The drain of MP2 is connected to the source of MP6;

[0023] The gate of MP6 is connected to the gates of MP9 and MP10, and the drain is connected to the source of MP7 and MP8.

[0024] The source of MP9 is connected to the drain of MP3, and the drain is connected to the drain of MN14.

[0025] The source of MP10 is connected to the drain of MP4, and the drain is connected to the drain of MN15.

[0026] The drain of MN14 is connected to the drain of MP7, and the drain of MN15 is connected to the drain of MP8.

[0027] The gate of MN14 is connected to the drain of MN14, and the source is connected to one end of resistor R3;

[0028] The gate of MN15 is connected to the drain of MN15, and the source is connected to one end of resistor R4.

[0029] In some possible implementations of the first aspect, the first common-source amplifier includes:

[0030] NMOS transistors MN16-MN17, resistors R1-R2, R5-R6; among which...

[0031] The first input terminal of the first common-source amplifier includes the gate of MN16, the second input terminal includes the gate of MN17, the first node includes one end of resistors R1 and R2, the first output terminal includes the drain of MN16, and the second output terminal includes the drain of MN17.

[0032] The source of MN16 is connected to one end of resistor R5, and the drain is connected to the other end of resistor R1.

[0033] The source of MN17 is connected to one end of resistor R6, and the drain is connected to the other end of resistor R2.

[0034] In some possible implementations of the first aspect, the second common-source amplifier includes:

[0035] NMOS transistors MN3-MN4, MN10-MN11, and resistors R1-R2; among which...

[0036] The first input terminal of the second common-source amplifier includes the gate of MN3, the second input terminal includes the gate of MN4, the first node includes the gate of MN11, the first output terminal includes the drain of MN3, and the second output terminal includes the drain of MN4.

[0037] The drain of MN11 is connected to the source of MN10;

[0038] The sources of MN3 and MN4 are connected to the drain of MN10. The drain of MN3 is connected to the other end of resistor R1, and the drain of MN4 is connected to the other end of resistor R2.

[0039] In some possible implementations of the first aspect, the first buffer includes:

[0040] NMOS tubes MN1 and MN18;

[0041] The input terminal of the first buffer includes the gate of MN1, the first node includes the drain of MN1, and the output terminal includes the source of MN1.

[0042] The source of MN1 is connected to the drain of MN18;

[0043] The second buffer includes NMOS transistors MN2 and MN19;

[0044] The input of the second buffer includes the gate of MN2, the first node includes the drain of MN2, and the output includes the source of MN2.

[0045] The source of MN2 is connected to the drain of MN19.

[0046] In some possible implementations of the first aspect, the bias current supply circuit includes:

[0047] Inverter, PMOS transistors MP11, MP13-MP15, MP19-MP22, resistor R12, NMOS transistors MN20-MN31;

[0048] The input terminal of the bias current supply circuit includes the gate of MN31, the first output terminal includes the source of MN26, and the second output terminal includes the source of MN31.

[0049] The drain of MP11 is connected to the gates of MP13 and MP14, and the gates are connected to the output of the inverter.

[0050] The source of MP13-MP15 and one end of resistor R12 are connected to the voltage node VCC. The drain of MP13 is connected to the gate of MP13 and the source of MP19. The drain of MP14 is connected to the source of MP20. The drain of MP15 is connected to the source of MP21.

[0051] The drain of MN31 is connected to the other end of resistor R12, and the source is connected to the drain of MN29;

[0052] The source of MN29 is connected to the drain of MN30;

[0053] The gate of MP19 is connected to the drain, as well as the gates of MP20 and MP21. The drain of MP19 is also connected to the drain of MN21.

[0054] The drain of MP20 is connected to the drain of MN22, the gate of MN22, the gate of MN23, and the gate of MN26.

[0055] The drain of MP21 is connected to the drain of MN26 and the gates of MN27 and MN29;

[0056] The drain of MN27 is connected to the source of MN26, and the source is connected to the drain of MN28;

[0057] The gate of MN21 is connected to the gate of MN20 and the drain of MN24, and the source is connected to the source of MN20, MN24, MN25, MN28, MN30 and the voltage node GND.

[0058] The gates of MN24 and MP22, and the input of the inverter are connected to the enable terminal EN;

[0059] The drain of MN20 is connected to the drain of MP22;

[0060] The source of MP22 is connected to the bias current terminal IB;

[0061] The drain of MN23 is connected to the source of MN22, and the source is connected to the drain of MN25.

[0062] In some possible implementations of the first aspect, the comparator circuit includes:

[0063] First-stage comparator, second-stage comparator, third-stage buffer, PMOS transistor MP12;

[0064] The first input terminal of the comparator circuit includes the first input terminal of the first-stage comparator, the second input terminal includes the second input terminal of the first-stage comparator, and the output terminal includes the output terminal of the third buffer.

[0065] The first node of the first-stage comparator is connected to the first node of the second-stage comparator;

[0066] The second node of the first-stage comparator is connected to the second node of the second-stage comparator;

[0067] The first output of the first-stage comparator is connected to the first input of the second-stage comparator, and the second output is connected to the second input of the second-stage comparator.

[0068] The output of the second-stage comparator is connected to the drain of MP12;

[0069] The source of MP12 is connected to the voltage node VCC, and the drain is connected to the input of the third buffer.

[0070] In some possible implementations of the first aspect, the first-level comparator includes:

[0071] PMOS transistors MP16, MP23-MP24; NMOS transistors MN32-MN35;

[0072] The first input terminal of the first-stage comparator includes the gate of MP23, the second input terminal includes the gate of MP24, the first node includes the source of MP16, the second node includes the source of MN32-MN35, the first output terminal includes the drain of MP23, and the second output terminal includes the drain of MP24.

[0073] The source of MP23 and MP24 is connected to the drain of MP16, the drain of MP23 is connected to the drain of MN32, and the drain of MP24 is connected to the drain of MN35.

[0074] The drain of MN32 is connected to the gate of MN32 and the drain of MN34;

[0075] The drain of MN35 is connected to the gate of MN35 and the drain of MN33;

[0076] The gate of MN33 is connected to the gate of MN32, and the gate of MN34 is connected to the gate of MN35.

[0077] The second-stage comparator includes...

[0078] PMOS transistors MP17-MP18, NMOS transistors MN36-MN37;

[0079] The first input of the second-stage comparator includes the gate of MN36, the second input includes the gate of MN37, the first node includes the source of MP17 and MP18, the second node includes the source of MN36-MN37, and the output includes the drain of MP18.

[0080] The drain of MP17 is connected to the gates of MP17 and MP18 and the drain of MN36;

[0081] The drain of MP18 is connected to the drain of MN37.

[0082] According to a second aspect of this disclosure, a method for operating a receiver circuit applicable to multiple high-speed interface standards is provided. The method includes:

[0083] The input signal is converted into a common-mode voltage by a modulation resistor circuit. The common-mode voltage is compared with a reference voltage in the common-mode voltage detection circuit. If the common-mode voltage is less than the reference voltage, the input signal is output after passing through a folded amplifier and a first common-source amplifier. If the common-mode voltage is greater than the reference voltage, the input signal is output after passing through a second common-source amplifier.

[0084] In this disclosure, the input signal is converted into a common-mode voltage using a modulation resistor circuit. The common-mode voltage is compared to a reference voltage in a common-mode voltage detection circuit. If the common-mode voltage is less than the reference voltage, the common-mode voltage detection circuit outputs a digital signal 0, and the input signal is output after passing through a folded amplifier and a first common-source amplifier. If the common-mode voltage is greater than the reference voltage, the common-mode voltage detection circuit outputs a digital signal 1, and the input signal is output after passing through a second common-source amplifier. This allows the common-mode voltage to be converted from 0 volts to the power supply voltage, and the transconductance of the receiving circuit remains constant, enabling the detection of small swings, low noise, and a low bit error rate.

[0085] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0086] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0087] Figure 1 The diagram illustrates a circuit structure for converting an LVPECL interface to an LVDS interface according to an embodiment of the present disclosure;

[0088] Figure 2 This diagram illustrates a core receiver circuit structure for a receiver circuit applicable to multiple high-speed interface standards, according to an embodiment of this disclosure.

[0089] Figure 3 A common-mode voltage detection circuit structure diagram of a receiver circuit applicable to multiple high-speed interface standards is shown according to an embodiment of the present disclosure. Detailed Implementation

[0090] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0091] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0092] To address the problems mentioned in the background art, this disclosure provides a receiving circuit applicable to multiple high-speed interface standards. The input signal is converted into a common-mode voltage using a modulation resistor circuit. In a common-mode voltage detection circuit, the common-mode voltage is compared with a reference voltage. If the common-mode voltage is less than the reference voltage, the common-mode voltage detection circuit outputs a digital signal 0, and the input signal is output after passing through a folded amplifier and a first common-source amplifier. If the common-mode voltage is greater than the reference voltage, the common-mode voltage detection circuit outputs a digital signal 1, and the input signal is output after passing through a second common-source amplifier. In this way, the common-mode voltage can be varied from 0 volts to the power supply voltage, and the transconductance of the receiving circuit remains constant, enabling the detection of small swings, low noise, and a low bit error rate.

[0093] The following detailed description, with reference to the accompanying drawings, illustrates a receiving circuit applicable to various high-speed interface standards provided by the present disclosure through specific embodiments.

[0094] Figure 1 A circuit structure for converting an LVPECL interface to an LVDS interface according to an embodiment of the present disclosure is shown.

[0095] like Figure 1 As shown, the circuit for converting an LVPECL interface to an LVDS interface provided in this embodiment includes:

[0096] LVPECL driver, LVDS receiver, resistor R A1 R A2 R B1 R B2 R C1 R C2 R0, Z 01 Z 02 Capacitor C A1 C A2 ;Specifically,

[0097] One end of the LVPECL driver is connected to R A1 R B1 One end, the other end connected to R A2 R B2 One end;

[0098] R B1 The other end is through Z 01 With C A1 One end is connected;

[0099] R B2 The other end is through Z 02 With C A2 One end is connected;

[0100] C A1The other end connects one end of R0 to one end of the LVDS receiver;

[0101] C A2 The other end connects to the other end of R0, the other end of the LVDS receiver, and R C1 and R C2 One end;

[0102] R A1 R A2 R C1 The other end is connected to the ground;

[0103] R C2 The other end is connected to a 3.3V voltage node;

[0104] Furthermore, R B1 R B2 It is an attenuation resistor that can attenuate the swing of an 800mV LVPECL signal to the swing of a 325mV LVDS signal;

[0105] Capacitor C A1 C A2 It is an AC coupling capacitor that can isolate the DC level from the LVPECL driver;

[0106] R C1 R C2 Its function is to reload the common-mode voltage at the input of the LVDS receiver;

[0107] The inclusion of R0 eliminates the need for this resistor in the external circuitry of the LVDS receiver, simplifying the external circuitry of the LVDS receiver.

[0108] Figure 1 The circuit shown can convert LVPECL signals to LVDS signals, but it requires adding a DC blocking capacitor and reloading the common-mode voltage. For conversions between different interfaces, the process is quite cumbersome. Therefore, this application designs a circuit that can adapt to various interfaces, effectively solving the above problems.

[0109] Figure 2 A core receiver circuit structure diagram is shown for a receiver circuit applicable to multiple high-speed interface standards according to an embodiment of this disclosure.

[0110] like Figure 2 As shown, the core receiving circuit provided in this embodiment includes:

[0111] The circuit includes a modulation resistor circuit, a folded amplifier, a first common-source amplifier, a second common-source amplifier, a first buffer, a second buffer, and a control voltage node Vc1; among which,

[0112] The first input terminal of the modulation resistor circuit is connected to the positive input voltage node Vin+, the second input terminal is connected to the negative input voltage node Vin-, and the output terminal is connected to the common-mode voltage node COM_IN.

[0113] The first input terminal of the folded amplifier is connected to the positive input voltage node Vin+, the second input terminal is connected to the negative input voltage node Vin-, the first node is connected to the control voltage node Vc1, the second node is connected to the first node of the first common source amplifier, the first node of the first buffer, and the first node of the second buffer, the first output terminal is connected to the first input terminal of the first common source amplifier, and the second output terminal is connected to the second input terminal of the first common source amplifier.

[0114] The first output terminal of the first common-source amplifier is connected to the input terminal of the first buffer, and the second output terminal is connected to the input terminal of the second buffer.

[0115] The first input terminal of the second common-source amplifier is connected to the negative input voltage node Vin-, the second input terminal is connected to the positive input voltage node Vin+, the first node is connected to the control voltage node Vc1, the first output terminal is connected to the input terminal of the first buffer, and the second output terminal is connected to the input terminal of the second buffer.

[0116] The output of the first buffer is connected to the negative output voltage node Vout-, and the output of the second buffer is connected to the positive output voltage node Vout+.

[0117] In some embodiments, the core receiving circuit further includes matching resistors R7-R8, PMOS transistors MP1 and MP5, and NMOS transistors MN5-MN9 and MN12-MN13.

[0118] In some embodiments, the modulation resistor circuit includes:

[0119] Resistors R9-R11;

[0120] The first input terminal of the modulation resistor circuit includes one end of resistor R9, the second input terminal includes one end of resistor R10, and the output terminal includes one end of resistor R11.

[0121] The other end of resistor R9 is connected to the other end of resistor R10 and the other end of resistor R11.

[0122] Furthermore, the modulation resistor circuit makes the output common-mode voltage signal purer.

[0123] In some embodiments, the folded amplifier includes:

[0124] PMOS transistors MP2-MP4, MP6-MP10, NMOS transistors MN14-MN15, resistors R3-R4;

[0125] The first input terminal of the folded amplifier includes the gate of MP7, the second input terminal includes the gate of MP8, the first node includes the gates of MP2-MP4, the second node includes the source of MP2-MP4, the first output terminal includes the drain of MN14, and the second output terminal includes the drain of MN15.

[0126] The drain of MP2 is connected to the source of MP6;

[0127] The gate of MP6 is connected to the gates of MP9 and MP10, and the drain is connected to the source of MP7 and MP8.

[0128] The source of MP9 is connected to the drain of MP3, and the drain is connected to the drain of MN14.

[0129] The source of MP10 is connected to the drain of MP4, and the drain is connected to the drain of MN15.

[0130] The drain of MN14 is connected to the drain of MP7, and the drain of MN15 is connected to the drain of MP8.

[0131] The gate of MN14 is connected to the drain of MN14, and the source is connected to one end of resistor R3;

[0132] The gate of MN15 is connected to the drain of MN15, and the source is connected to one end of resistor R4.

[0133] In some embodiments, the gate of MP6 is also connected to the drain of MP5, the drain of MN8, and the gate of MN9.

[0134] The gate of the MP5 is connected to its drain.

[0135] The gate of MN8 is connected to its drain.

[0136] In some embodiments, the first common-source amplifier includes:

[0137] NMOS transistors MN16-MN17, resistors R1-R2, R5-R6;

[0138] The first input terminal of the first common-source amplifier includes the gate of MN16, the second input terminal includes the gate of MN17, the first node includes one end of resistors R1 and R2, the first output terminal includes the drain of MN16, and the second output terminal includes the drain of MN17.

[0139] The source of MN16 is connected to one end of resistor R5, and the drain is connected to the other end of resistor R1.

[0140] The source of MN17 is connected to one end of resistor R6, and the drain is connected to the other end of resistor R2.

[0141] In some embodiments, the second common-source amplifier includes:

[0142] NMOS transistors MN3-MN4, MN10-MN11, resistors R1-R2;

[0143] The first input terminal of the second common-source amplifier includes the gate of MN3, the second input terminal includes the gate of MN4, the first node includes the gate of MN11, the first output terminal includes the drain of MN3, and the second output terminal includes the drain of MN4.

[0144] The drain of MN11 is connected to the source of MN10;

[0145] The sources of MN3 and MN4 are connected to the drain of MN10. The drain of MN3 is connected to the other end of resistor R1, and the drain of MN4 is connected to the other end of resistor R2.

[0146] In some embodiments, the first buffer includes:

[0147] NMOS tubes MN1 and MN18;

[0148] The input terminal of the first buffer includes the gate of MN1, the first node includes the drain of MN1, and the output terminal includes the source of MN1.

[0149] The source of MN1 is connected to the drain of MN18;

[0150] The second buffer includes NMOS transistors MN2 and MN19;

[0151] The input of the second buffer includes the gate of MN2, the first node includes the drain of MN2, and the output includes the source of MN2.

[0152] The source of MN2 is connected to the drain of MN19;

[0153] Furthermore, the gate of MN18 is connected to the gate of MN19; specifically,

[0154] The gates of MN18 and MN19 are connected to the bias current terminal IB to provide operating current for the first and second buffers.

[0155] In some embodiments, the drains of MN1 and MN2 are connected to the source of MP1;

[0156] The other ends of resistors R3 and R4 are connected to the sources of MN6, MN7, MN9, MN11, MN12, MN13, MN18, and MN19.

[0157] The other ends of resistors R3 and R4 are also connected to the other ends of resistors R5 and R6;

[0158] The control voltage node Vc1 is connected to the gates of MP1, MN12, and MN13;

[0159] The source of MP5 is connected to the drain of MP1, and the drain of MP5 is connected to the drain of MN8.

[0160] The source of MN8 is connected to the drain of MN9;

[0161] The gates of MN5, MN8, and MN10 and the drains of MN5 and MN7 are all connected to the bias current terminal IB.

[0162] The drain of MN12 is connected to the drains of MP8 and MP10;

[0163] The drain of MN13 is connected to the drains of MP8 and MP10;

[0164] One end of resistor R7 is connected to the positive input voltage node Vin+, and the other end is connected to the negative input voltage node Vin- through resistor R8;

[0165] The source of MN5 is connected to the drain of MN6;

[0166] The gate connection enable terminal EN of MN7.

[0167] In some embodiments, the operation of the core receiving circuit includes:

[0168] The value of the control voltage node Vc1 determines the MOS transistor that operates normally in the core receiving circuit; the input signal is output after passing through the MOS transistor. Furthermore,

[0169] The input signal is converted into a common-mode voltage by a modulation resistor circuit. The common-mode voltage is compared with a reference voltage in the common-mode voltage detection circuit to obtain a digital output signal. The digital output signal determines the magnitude of the control voltage node Vc1.

[0170] Specifically, when the enable terminal EN is low, and the digital output signal is 0, the control voltage node Vc1 is low, MP1-MP4 are working, and MN10-MN13 are not working. MP2 and MP6 are a pair of pseudo-current sources, providing operating current for MP7 and MP8, thereby enabling MP7 and MP8 to work. The signal is input from the gate of MP7 and MP8, passes through the folded amplifier, flows from the drain of MP9 to the gate of MN16 in the first common-source amplifier, flows from the drain of MP10 to the gate of MN17 in the first common-source amplifier, and is output from the source of MN1 in the first buffer and the source of MN2 in the second buffer. When the digital output signal is 1, the control voltage node Vc1 is high, MN10-MN13 are working, MP1-MP4 and MN16-MN17 are not working. MN10 and MN11 are a pair of pseudo current sources, providing working current for MN3 and MN4, thereby enabling MN3 and MN4 to work. The signal is input from the gate of MN3 and MN4, flows from the drain of MN3 in the second common source amplifier to the gate of MN1 in the first buffer, the drain of MN4 in the second common source amplifier flows to the gate of MN2 in the second buffer, and is output from the source of MN1 in the first buffer and the source of MN2 in the second buffer.

[0171] When the enable pin EN is high, the core receiving circuit is not working.

[0172] Figure 3 A common-mode voltage detection circuit structure diagram of a receiver circuit applicable to multiple high-speed interface standards is shown according to an embodiment of the present disclosure.

[0173] like Figure 3 As shown, the common-mode voltage detection circuit provided in this embodiment includes:

[0174] Bias current supply circuit and comparator circuit; wherein,

[0175] The input terminal of the bias current supply circuit is connected to the common-mode voltage node COM_IN, the first output terminal is connected to the first input terminal of the comparator circuit, and the second output terminal is connected to the second input terminal of the comparator circuit.

[0176] The output of the comparator circuit is connected to the digital output signal node Z.

[0177] In some embodiments, the bias current supply circuit includes:

[0178] Inverter, PMOS transistors MP11, MP13-MP15, MP19-MP22, resistor R12, NMOS transistors MN20-MN31;

[0179] The input terminal of the bias current supply circuit includes the gate of MN31, the first output terminal includes the source of MN26, and the second output terminal includes the source of MN31.

[0180] The drain of MP11 is connected to the gates of MP13 and MP14, and the gates are connected to the output of the inverter.

[0181] The source of MP13-MP15 and one end of resistor R12 are connected to the voltage node VCC. The drain of MP13 is connected to the gate of MP13 and the source of MP19. The drain of MP14 is connected to the source of MP20. The drain of MP15 is connected to the source of MP21.

[0182] The drain of MN31 is connected to the other end of resistor R12, and the source is connected to the drain of MN29;

[0183] The source of MN29 is connected to the drain of MN30;

[0184] The gate of MP19 is connected to the drain, as well as the gates of MP20 and MP21. The drain of MP19 is also connected to the drain of MN21.

[0185] The drain of MP20 is connected to the drain of MN22, the gate of MN22, the gate of MN23, and the gate of MN26.

[0186] The drain of MP21 is connected to the drain of MN26 and the gates of MN27 and MN29;

[0187] The drain of MN27 is connected to the source of MN26, and the source is connected to the drain of MN28;

[0188] The gate of MN21 is connected to the gate of MN20 and the drain of MN24, and the source is connected to the source of MN20, MN24, MN25, MN28, MN30 and the voltage node GND.

[0189] The gates of MN24 and MP22, and the input of the inverter are connected to the enable terminal EN;

[0190] The drain of MN20 is connected to the drain of MP22;

[0191] The source of MP22 is connected to the bias current terminal IB;

[0192] The drain of MN23 is connected to the source of MN22, and the source is connected to the drain of MN25.

[0193] In some embodiments, the comparison circuit includes:

[0194] First-stage comparator, second-stage comparator, third-stage buffer, PMOS transistor MP12;

[0195] The first input terminal of the comparator circuit includes the first input terminal of the first-stage comparator, the second input terminal includes the second input terminal of the first-stage comparator, and the output terminal includes the output terminal of the third buffer.

[0196] The first node of the first-stage comparator is connected to the first node of the second-stage comparator;

[0197] The second node of the first-stage comparator is connected to the second node of the second-stage comparator;

[0198] The first output of the first-stage comparator is connected to the first input of the second-stage comparator, and the second output is connected to the second input of the second-stage comparator.

[0199] The output of the second-stage comparator is connected to the drain of MP12;

[0200] The source of MP12 is connected to the voltage node VCC, and the drain is connected to the input of the third buffer.

[0201] In some embodiments, the first-stage comparator includes:

[0202] PMOS transistors MP16, MP23-MP24; NMOS transistors MN32-MN35;

[0203] The first input terminal of the first-stage comparator includes the gate of MP23, the second input terminal includes the gate of MP24, the first node includes the source of MP16, the second node includes the source of MN32-MN35, the first output terminal includes the drain of MP23, and the second output terminal includes the drain of MP24.

[0204] The source of MP23 and MP24 is connected to the drain of MP16, the drain of MP23 is connected to the drain of MN32, and the drain of MP24 is connected to the drain of MN35.

[0205] The drain of MN32 is connected to the gate of MN32 and the drain of MN34;

[0206] The drain of MN35 is connected to the gate of MN35 and the drain of MN33;

[0207] The gate of MN33 is connected to the gate of MN32, and the gate of MN34 is connected to the gate of MN35.

[0208] The second-stage comparator includes...

[0209] PMOS transistors MP17-MP18, NMOS transistors MN36-MN37;

[0210] The first input of the second-stage comparator includes the gate of MN36, the second input includes the gate of MN37, the first node includes the source of MP17 and MP18, the second node includes the source of MN36-MN37, and the output includes the drain of MP18.

[0211] The drain of MP17 is connected to the gates of MP17 and MP18 and the drain of MN36;

[0212] The drain of MP18 is connected to the drain of MN37.

[0213] In some embodiments, the output of the inverter is connected to the gate of MP12;

[0214] The sources of MP13-MP15 are all connected to the sources of MP16-MP18;

[0215] One end of resistor R12 is connected to the source of MP16-MP18;

[0216] The gates of MP13 and MP15 are connected to the gate of MP16;

[0217] The source of MN26 is connected to the gate of MP23;

[0218] The source of MN31 is connected to the gate of MP24;

[0219] The sources of MN20, MN24, MN25, MN28, and MN30 are all connected to the sources of MN32-MN37.

[0220] In some embodiments, the common-mode voltage detection circuit operates by:

[0221] The bias current supply circuit provides current to MN26, MN31, and MP16. The common-mode voltage is input through the gate of MN31 and output from the source of MN31. The common-mode voltage and the reference voltage output from the source of MN26 are sent to the subsequent comparator circuit for comparison. The signal is input through the gates of MP23 and MP24 in the first-stage comparator and output from the drains of MP23 and MP24, becoming a differential analog signal. The differential analog signal is sent to the second-stage comparator, and a single-ended analog signal is output from the drains of MP18 and MN37 in the second-stage comparator. The single-ended analog signal is then passed through a third buffer to output a digital output signal. The magnitude of the digital output signal can represent the relationship between the common-mode voltage and the reference voltage.

[0222] Specifically, when the enable pin EN is low, if the common-mode voltage is less than the reference voltage, the digital output signal is 0; if the common-mode voltage is greater than the reference voltage, the digital output signal is 1.

[0223] When the enable pin EN is high, the bias current supply circuit, the first-stage comparator, and the second-stage comparator are all inactive. MP12 is turned on, and the digital output signal is 1. Since the core receiving circuit is inactive when EN is high, the receiving circuit is also inactive.

[0224] According to the embodiments of this disclosure, the following technical effects are achieved:

[0225] The input signal is converted into a common-mode voltage by a modulation resistor circuit. The common-mode voltage is then compared with a reference voltage in the common-mode voltage detection circuit. If the common-mode voltage is less than the reference voltage, the common-mode voltage detection circuit outputs a digital signal 0, and the input signal is output after passing through a folded amplifier and a first common-source amplifier. If the common-mode voltage is greater than the reference voltage, the common-mode voltage detection circuit outputs a digital signal 1, and the input signal is output after passing through a second common-source amplifier. In this way, the common-mode voltage can be transformed from 0 volts to the power supply voltage, and the transconductance of the receiving circuit remains constant, enabling the detection of small swings, low noise, and a low bit error rate.

[0226] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0227] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0228] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A receiving circuit suitable for multiple high-speed interface standards, characterized in that, The core receiving circuit and the common-mode voltage detection circuit are included. The core receiving circuit includes a modulation resistance circuit, a folded amplifier, a first common-source amplifier, a second common-source amplifier, a first buffer, a second buffer, and a control voltage node Vc1. The first input end of the modulation resistance circuit is connected with a positive input voltage node Vin+, the second input end is connected with a negative input voltage node Vin-, and the output end is connected with a common-mode voltage node COM_IN. The first input end of the folded amplifier is connected with the positive input voltage node Vin+, the second input end is connected with the negative input voltage node Vin-, the first node is connected with the control voltage node Vc1, the second node is connected with the first node of the first common-source amplifier, the first node of the first buffer, and the first node of the second buffer, the first output end is connected with the first input end of the first common-source amplifier, and the second output end is connected with the second input end of the first common-source amplifier. The first output end of the first common-source amplifier is connected with the input end of the first buffer, and the second output end is connected with the input end of the second buffer. The first input end of the second common-source amplifier is connected with the negative input voltage node Vin-, the second input end is connected with the positive input voltage node Vin+, the first node is connected with the control voltage node Vc1, the first output end is connected with the input end of the first buffer, and the second output end is connected with the input end of the second buffer. The output end of the first buffer is connected with a negative output voltage node Vout-, and the output end of the second buffer is connected with a positive output voltage node Vout+. The common-mode voltage detection circuit includes a bias current supply circuit and a comparison circuit. The input end of the bias current supply circuit is connected with the common-mode voltage node COM_IN, the first output end is connected with the first input end of the comparison circuit, and the second output end is connected with the second input end of the comparison circuit. The bias current supply circuit includes an inverter, PMOS tubes MP11, MP13-MP15, MP19-MP22, a resistor R12, and NMOS tubes MN20-MN31. The input end of the bias current supply circuit includes the gate of MN31, the first output end includes the source of MN26, and the second output end includes the source of MN31. The drain of MP11 is connected with the gates of MP13 and MP14, and the gate is connected with the output end of the inverter. The sources of MP13-MP15 and one end of the resistor R12 are connected with a voltage node VCC, the drain of MP13 is connected with the gate of MP13 and the source of MP19, the drain of MP14 is connected with the source of MP20, and the drain of MP15 is connected with the source of MP21. The drain of MN31 is connected with the other end of the resistor R12, and the source is connected with the drain of MN29. The source of MN29 is connected with the drain of MN30. The gate and drain of MP19 are connected with the gates of MP20 and MP21, and the drain of MP19 is also connected with the drain of MN21. The drain of MP20 is connected with the drain of MN22, the gate of MN22, the gate of MN23, and the gate of MN26. ​ The drain of the MP21 is connected to the drain of the MN26, the gate of the MN27 and the MN29; The drain of the MN27 is connected to the source of the MN26, the drain of the MN28; The gate of the MN21 is connected to the gate of the MN20 and the drain of the MN24, the source is connected to the source of the MN20, MN24, MN25, MN28, MN30 and the voltage node GND; The gate of the MN24, the gate of the MP22 and the input of the inverter are connected to the enable terminal EN; The drain of the MN20 is connected to the drain of the MP22; The source of the MP22 is connected to the bias current terminal IB; The drain of the MN23 is connected to the source of the MN22, the drain of the MN25; The output of the comparison circuit is connected to the digital output signal node Z.

2. The circuit of claim 1, wherein, The modulated resistance circuit comprises: Resistors R9-R11; The first input of the modulated resistance circuit comprises one end of the resistor R9, the second input comprises one end of the resistor R10, and the output comprises one end of the resistor R11; The other end of the resistor R9 is connected to the other end of the resistor R10 and the other end of the resistor R11.

3. The circuit of claim 1, wherein, The folded amplifier comprises: PMOS transistors MP2-MP4, MP6-MP10, NMOS transistors MN14-MN15, resistors R3-R4; The first input of the folded amplifier comprises the gate of MP7, the second input comprises the gate of MP8, the first node comprises the gate of MP2-MP4, the second node comprises the source of MP2-MP4, the first output comprises the drain of MN14, and the second output comprises the drain of MN15; The drain of the MP2 is connected to the source of the MP6; The gate of the MP6 is connected to the gate of the MP9, MP10, and the drain is connected to the source of the MP7, MP8; The source of the MP9 is connected to the drain of the MP3, and the drain is connected to the drain of the MN14; The source of the MP10 is connected to the drain of the MP4, and the drain is connected to the drain of the MN15; The drain of the MN14 is connected to the drain of the MP7, and the drain of the MN15 is connected to the drain of the MP8; The gate of the MN14 is connected to the drain of the MN14, and the source is connected to one end of the resistor R3; The gate of the MN15 is connected to the drain of the MN15, and the source is connected to one end of the resistor R4.

4. The circuit of claim 1, wherein, The first common source amplifier comprises: NMOS transistors MN16-MN17, resistors R1-R2, R5-R6; The first input of the first common source amplifier comprises the gate of MN16, the second input comprises the gate of MN17, the first node comprises one end of resistors R1, R2, the first output comprises the drain of MN16, and the second output comprises the drain of MN17; The source of the MN16 is connected to one end of the resistor R5, and the drain is connected to the other end of the resistor R1; The source of the MN17 is connected to one end of the resistor R6, and the drain is connected to the other end of the resistor R2.

5. The circuit of claim 1, wherein, The second common source amplifier comprises: NMOS transistors MN3-MN4, MN10-MN11, resistors R1-R2; The first input end of the second common-source amplifier comprises a gate of MN3, the second input end comprises a gate of MN4, the first node comprises a gate of MN11, the first output end comprises a drain of MN3, and the second output end comprises a drain of MN4; The drain of the MN11 is connected to a source of MN10; The sources of the MN3 and MN4 are connected to a drain of MN10, the drain of MN3 is connected to the other end of the resistor R1, and the drain of MN4 is connected to the other end of the resistor R2.

6. The circuit of claim 1, wherein, The first buffer comprises: NMOS tubes MN1 and MN18; The input end of the first buffer comprises a gate of MN1, the first node comprises a drain of MN1, and the output end comprises a source of MN1; The source of the MN1 is connected to a drain of MN18; The second buffer comprises NMOS tubes MN2 and MN19; The input end of the second buffer comprises a gate of MN2, the first node comprises a drain of MN2, and the output end comprises a source of MN2; The source of the MN2 is connected to a drain of MN19.

7. The circuit of claim 1, wherein, The comparison circuit comprises: a first-stage comparator, a second-stage comparator, a third buffer, and a PMOS tube MP12; The first input end of the comparison circuit comprises a first input end of the first-stage comparator, the second input end comprises a second input end of the first-stage comparator, and the output end comprises an output end of the third buffer; The first node of the first-stage comparator is connected to a first node of the second-stage comparator; The second node of the first-stage comparator is connected to a second node of the second-stage comparator; The first output end of the first-stage comparator is connected to a first input end of the second-stage comparator, and the second output end is connected to a second input end of the second-stage comparator; The output end of the second-stage comparator is connected to a drain of MP12; The source of the MP12 is connected to a voltage node VCC, and the drain is connected to an input end of the third buffer.

8. The circuit of claim 7, wherein, The first-stage comparator comprises: a PMOS tube MP16, PMOS tubes MP23-MP24, and NMOS tubes MN32-MN35; The first input end of the first-stage comparator comprises a gate of MP23, the second input end comprises a gate of MP24, the first node comprises a source of MP16, the second node comprises sources of MN32-MN35, the first output end comprises a drain of MP23, and the second output end comprises a drain of MP24; The sources of the MP23 and MP24 are connected to a drain of MP16, the drain of MP23 is connected to a drain of MN32, and the drain of MP24 is connected to a drain of MN35; The drain of the MN32 is connected to a gate of the MN32 and a drain of the MN34; The drain of the MN35 is connected to a gate of the MN35 and a drain of the MN33; The gate of the MN33 is connected to the gate of the MN32, and the gate of the MN34 is connected to the gate of the MN35; The second-stage comparator comprises a PMOS tube MP17-MP18 and NMOS tubes MN36-MN37; The first input end of the second comparator comprises a gate of MN36, the second input end comprises a gate of MN37, the first node comprises sources of MP17 and MP18, the second node comprises sources of MN36 and MN37, and the output end comprises a drain of MP18; The drain of the MP17 is connected to the gates of MP17 and MP18 and the drain of MN36; The drain of the MP18 is connected to the drain of MN37.

9. A method of operation applied to a receiving circuit suitable for a plurality of high speed interface standards as claimed in any one of claims 1 to 8, characterised by, The method comprises: The input signal is converted into a common-mode voltage through a modulation resistance circuit, the common-mode voltage is compared with a reference voltage in a common-mode voltage detection circuit, if the common-mode voltage is less than the reference voltage, the input signal is output after passing through a folding amplifier and a first common-source amplifier, and if the common-mode voltage is greater than the reference voltage, the input signal is output after passing through a second common-source amplifier.

Images