A CMOS integrated millimeter-wave self-matching receiver front-end circuit

Abstract

The present invention discloses a CMOS integrated millimeter wave self-matching receiver front-end circuit, comprising: a first orthogonal coupler, a second orthogonal coupler, a first passive mixer, a second passive mixer, a first first-stage amplifier, a first second-stage amplifier, a second first-stage amplifier, a second second-stage amplifier, a local oscillator, and an input terminal V RF , input LO IN The first and second stage amplifiers of the present invention are intermediate frequency amplifiers, which use a derivative superposition structure to achieve a high linearity of 4 to 12 dBm. Both the input and output use an orthogonal coupler structure to achieve an input and output port impedance self-matching effect, ensuring good matching between the input and output ends.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a CMOS integrated millimeter wave self-matching receiver front-end circuit. Background Art

[0002] Millimeter-wave communication links are gaining increasing interest and attention due to their typically high data rates (multi-Gb / s). They typically span an extremely wide frequency spectrum, typically between 30 GHz and 300 GHz. High data rates inherently require sufficiently wide bandwidth coverage, and linearity is equally important. Therefore, for millimeter-wave receiver front-end circuits, achieving wide bandwidth and good linearity are the most challenging design specifications. Furthermore, performance indicators such as noise and gain must also meet appropriate levels to meet basic application requirements.

[0003] The following document [1] presents a 60GHz RF receiver front-end circuit. Its advantage is that it achieves a low noise figure by optimizing the width-to-length ratio of the MOS tube. However, the bandwidth of this structure is only 57 to 64GHz, and the IIP3 within the band is even worse, at only -3dBm.

[0004] Reference [2] also provides a diode-tuned 60GHz broadband receiver front-end circuit. Its advantage lies in inserting a low-pass matching circuit between the coupler and mixer and using a varactor diode to achieve image suppression. From 54GHz to 66GHz (excluding 65GHz), it provides 3.1 to 21.4dB of image suppression (IRR) at a gain reduction cost of less than 1.1dB. However, the overall performance is not very good, and the bandwidth is only a few G. It uses the HEMET process and cannot be integrated on a silicon process chip. The power consumption is as high as 278mW, and its application scenarios are very limited.

[0005] Based on the above-mentioned existing technologies, it can be seen that previous technical reports all have the characteristics of narrow bandwidth and cannot meet the growing demand for high-speed millimeter wave communications. Furthermore, the above-mentioned traditional technologies rely on the input impedance of the first-stage low-noise amplifier in matching design. Process deviations inevitably cause matching offsets and even require auxiliary matching of off-chip components. In addition, the image rejection ratio and linearity requirements of millimeter wave communications also make previous technologies incompetent.

[0006] In summary, for this purpose, we propose a CMOS integrated millimeter-wave self-matching receiver front-end circuit. Summary of the Invention

[0007] The purpose of the present invention is to provide a CMOS integrated millimeter wave self-matching receiver front-end circuit to solve the existing problems.

[0008] To achieve the above object, the present invention provides the following technical solution: a CMOS integrated millimeter wave self-matching receiver front-end circuit, comprising: a first orthogonal coupler, a second orthogonal coupler, a first passive mixer, a second passive mixer, a first first-stage amplifier, a first second-stage amplifier, a second first-stage amplifier, a second second-stage amplifier, a local oscillator, and an input terminal V RF , input LO IN ,, first signal, second signal, local oscillator signal LO1, local oscillator signal LO2;

[0009] The input terminal V RF Single-ended input RF signal, the input terminal V RF Connect the input terminal In of the first orthogonal coupler; the iso terminal of the first orthogonal coupler is connected to the resistor R1, the resistor R1 is grounded, and the thru terminal of the first orthogonal coupler is connected to the input terminal V of the second passive mixer in2 The Coupl end of the first orthogonal coupler is connected to the input end V of the first passive mixer in1 ;,

[0010] The input terminal LO IN The single-ended input local oscillator signal generates a pair of differential signals V after passing through Marchand Balun, matching network, and transmission line. LO1 、V LO2 , the output terminal V of the local oscillator signal LO1 The input terminals LO1 and LO2 of the first passive mixer and the second passive mixer are connected respectively. The output terminal V LO2 The first passive mixer input terminal LO2 and the second passive mixer input terminal LO2 are connected respectively.

[0011] The first signal passes through the input terminal of the first passive mixer and is multiplied by the input local oscillator signal LO1 and the local oscillator signal LO2 to obtain an intermediate frequency voltage signal; the output terminal V O1 and the output terminal V O2 They are respectively connected to the negative input terminal V in5 and the positive input terminal V in6 , the output terminal V of the first-stage amplifier of the first path O5 and the output terminal V O6 They are connected to the negative input terminal V of the first second stage amplifier in9 and the positive input terminal V in10 , the output terminal V of the first second stage amplifier O9 and the output terminal V O10 respectively connected to thru2 and thru1 of the second quadrature coupler;

[0012] The second signal passes through the input terminal of the second passive mixer and is multiplied by the input local oscillator signal LO1 and the local oscillator signal LO2 to obtain an intermediate frequency voltage signal; the output terminal V O1 and the output terminal V O2 They are respectively connected to the negative input terminal V in3 and the positive input terminal V in4 , the output terminal V of the first stage amplifier of the second path O3 and the output terminal V O4 are connected to the negative input terminal V in7 and the positive input terminal V in8 , the output terminal V of the second-stage amplifier of the second path O7 and the output terminal V O8 Coupl2 and Coupl1 of the second orthogonal coupler are connected respectively;

[0013] The output terminals iso1 and iso2 of the second orthogonal coupler are connected to one end of the resistor R2 and the resistor R3 respectively, and the other ends of the resistor R2 and the resistor R3 are grounded. The output terminals vo1 and vo2 of the second orthogonal coupler serve as the intermediate frequency output voltage signal BB_I.

[0014] Preferably, the first orthogonal coupler and the second orthogonal coupler have the same structure, and both include: a transformer T1, a capacitor C1, and a capacitor C2;

[0015] The In terminal of the transformer T1 is connected to one end of the capacitor C1, the Coupl terminal of the transformer T1 is connected to the other end of the capacitor C1, the iso terminal of the transformer T1 is connected to one end of the capacitor C2, and the thru terminal of the transformer T1 is connected to the other end of the capacitor C2.

[0016] Preferably, the first passive mixer and the second passive mixer have the same structure, both comprising: an NMOS transistor M n1 、NMOS tube M n2 , capacitor C9, capacitor C 10 , capacitor C 28 , resistor R4, resistor R5, resistor R6;

[0017] The capacitor C 28 One end is connected to the input RF signal RF Q , similarly, the other overlapping input is RF I The capacitor C 28 The other end of the resistor R4 and the NMOS tube M n1 The source end and NMOS tube M n2 The other end of the resistor R4 is connected to the bias DC voltage V RFDCThe NMOS tube M n1 The gate end is connected to one end of the resistor R6 and one end of the capacitor C9, and the other end of the resistor R6 is connected to the bias DC voltage V LODC1 The other end of the capacitor C9 is connected to the local oscillator signal LO p The NMOS tube M n2 The gate terminal is connected to one end of the resistor R5 and the capacitor C 10 One end of the resistor R5 is connected to the bias DC voltage V LODC2 , the capacitor C 10 The other end is connected to the local oscillator signal LO n The NMOS tube M n2 The drain end and NMOS tube M n1 The drain terminal is used as the output signal IF Q Similarly, the other overlapping output is IF I .

[0018] Preferably, the first-stage amplifier of the first path and the first-stage amplifier of the second path have the same structure, both including: NMOS transistor M n3 、NMOS tube M n4 、NMOS tube M n5 、NMOS tube M n6 、NMOS tube M n7 、NMOS tube M n8 、NMOS tube M n9 、NMOS tube M n10 、NMOS tube M n11 、NMOS tube M n12 , resistor R7, resistor R8, resistor R9, resistor R 10 , resistor R 11 , resistor R 13 , resistor R 14 , resistor R 15 , resistor R 16 , capacitor C 11 , capacitor C 12 , capacitor C 13 , capacitor C 14 , capacitor C 15 , capacitor C 16 , capacitor C 17 , capacitor C 18 , capacitor C 19 , capacitor C 29 , capacitor C 30 , inductor L5 and inductor L6;

[0019] The C terminal of the inductor L5 is connected to the power supply voltage V DD , the a end of the inductor L5 and one end of the resistor R7 and the capacitor C 15One end and NMOS tube M n3 The drain end is connected as the output end of the first stage amplifier IF AvOp The NMOS tube M n3 The gate terminal is biased by a DC voltage V bc1 , the NMOS tube M n3 The source end and NMOS tube M n4 The drain end and NMOS tube M n5 The drain end and NMOS tube M n6 The drain end and NMOS tube M n7 The drain end of the NMOS tube M n4 The source end of the inductor L6 and the capacitor C 30 One end of the NMOS tube M n4 The gate terminal and capacitor C 29 One end is connected to the 11 Connect bias DC voltage V b1 ; Also through the capacitor C 14 With capacitor C 11 One end and capacitor C 12 One end and capacitor C 13 One end is connected to the input terminal of the first stage amplifier IF Avn The NMOS tube M n5 The gate terminal and capacitor C 13 The other end is connected through resistor R 10 Connect bias DC voltage V b2 , the NMOS tube M n5 The source end of the NMOS tube M is grounded; n6 The gate terminal and capacitor C 12 The other end is connected to the bias DC voltage V through resistor R9. b3 , the NMOS tube M n6 The source end of the NMOS tube M is grounded; n7 The gate terminal and capacitor C 11 The other end is connected to the bias DC voltage V through resistor R8. b4 , the NMOS tube M n7 The source end is grounded.

[0020] Preferably, the b end of the inductor L5 is connected to the other end of the resistor R7 and the capacitor C 15 The other end and NMOS tube M n8 The drain end is connected as the output end of the first stage amplifier IF AvOn The NMOS tube M n8 The gate terminal is biased by a DC voltage V bc2 , the NMOS tube M n8 The source end and NMOS tube Mn9 The drain end and NMOS tube M n10 The drain end and NMOS tube M n11 The drain end and NMOS tube M n12 The drain end of the NMOS tube M n9 The source end of the inductor L6 and the capacitor C 29 The other end of the inductor L6 is connected to the ground; the NMOS tube M n9 The gate terminal and capacitor C 30 The other end is connected through resistor R 16 Connect bias DC voltage V b1 ; Also through the capacitor C 16 With capacitor C 19 One end and capacitor C 18 One end and capacitor C 17 One end is connected to the input terminal of the first stage amplifier IF Avp The NMOS tube M n10 The gate terminal and capacitor C 17 The other end is connected to the 15 Connect bias DC voltage V b2 , the NMOS tube M n10 The source end of the NMOS tube M is grounded; n11 The gate terminal and capacitor C 18 The other end is connected through resistor R 14 Connect bias DC voltage V b3 , the NMOS tube M n11 The source end of the NMOS tube M is grounded; n12 The gate terminal and capacitor C 19 The other end is connected to the 13 Connect bias DC voltage V b4 , the NMOS tube M n12 The source end is grounded.

[0021] Preferably, the first-way second-stage amplifier and the second-way second-stage amplifier have the same structure, both comprising: an NMOS transistor M n14 、NMOS tube M n15 、NMOS tube M n16 、NMOS tube M n17 、PMOS tube M p1 、PMOS tube M p2 、PMOS tube M p3 、PMOS tube M p4 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , resistor R21 , resistor R 22 , resistor R 23 , resistor R 24 , resistor R 25 , capacitor C 20 , capacitor C 21 , capacitor C 22 , capacitor C 23 , capacitor C 24 , capacitor C 25 , capacitor C 26 , capacitor C 27 and common mode feedback cmfb;

[0022] The capacitor C 26 One end of the capacitor C 27 One end and capacitor C 20 One end and capacitor C 21 One end and capacitor C 22 One end and capacitor C 23 One end and capacitor C 24 One end and capacitor C 25 One end is connected to the input terminal of the second stage amplifier IF Gmp Similarly, the other overlapping input is IF Gmn The capacitor C 27 The other end is connected to the NMOS tube M n14 The gate terminal is connected through the resistor R 18 Connect bias DC voltage V bn1 , the NMOS tube M n14 The source end of the NMOS tube M is grounded; n14 The drain end of the PMOS tube M p1 The drain terminal and resistor R 25 One end and NMOS tube M n15 The drain end and PMOS tube M p2 The drain end and NMOS tube M n16 The drain end and PMOS tube M p3 The drain end and NMOS tube M n17 The drain end of the PMOS tube M p4 The drain end is connected as the output end of the second stage amplifier IF GmOn Similarly, the other overlapping output is IF GmOp The PMOS tube M p1 The source terminal supply voltage V DD , the resistor R 25 The other end is connected to the positive input of the common-mode feedback cmfb, and the negative input of the common-mode feedback cmfb is the power supply voltage V DD / 2, the output terminal V of the common mode feedback cmfb oThrough the resistor R 17 With capacitor C 26 The other end and PMOS tube M p1 Gate connection.

[0023] Preferably, the capacitor C 21 The other end is connected to the NMOS tube M n15 The gate terminal is connected through the resistor R 20 Connect bias DC voltage V bn2 , the NMOS tube M n15 The source end of the PMOS tube M is grounded. p2 The source terminal supply voltage V DD , the capacitor C 20 The other end of the PMOS tube M p2 The gate terminal is connected through the resistor R 19 Connect bias DC voltage V bp1 .

[0024] Preferably, the capacitor C 23 The other end is connected to the NMOS tube M n16 The gate terminal is connected through the resistor R 22 Connect bias DC voltage V bn3 , the NMOS tube M n16 The source end of the PMOS tube M is grounded. p3 The source terminal supply voltage V DD , the capacitor C 22 The other end of the PMOS tube M p3 The gate terminal is connected through the resistor R 21 Connect bias DC voltage V bp2 .

[0025] Preferably, the capacitor C 25 The other end is connected to the NMOS tube M n17 The gate terminal is connected through the resistor R 24 Connect bias DC voltage V bn4 , the NMOS tube M n17 The source end of the PMOS tube M is grounded. p4 The source terminal supply voltage V DD , the capacitor C 24 The other end of the PMOS tube M p4 The gate terminal is connected through the resistor R 23 Connect bias DC voltage V bp3 .

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The first and second stage amplifiers of the present invention are intermediate frequency amplifiers, which adopt a derivative superposition structure to achieve a high linearity of 4 to 12dBm. Both the input and output use an orthogonal coupler structure to achieve an input and output port impedance self-matching effect, ensuring good matching of the input and output ends.

[0028] The input and output ports of the present invention both use orthogonal coupler structures, which realizes self-matching of the input and output ports and ensures a good matching effect.

[0029] The present invention also does not require the addition of any off-chip matching components and networks, thus providing a solution for CMOS integration.

[0030] In the receiving method of the present invention, for a fixed-point intermediate frequency, the upper and lower sideband RF input signals are respectively transmitted to the in and iso ports of the output port, thereby achieving an image suppression effect.

[0031] The present invention adopts a passive mixer pre-positioned architecture, removes the low noise amplifier in the traditional receiver structure, and adopts a derivative superposition linearization circuit structure for the intermediate frequency two-stage amplifier, which reduces the small signal transconductance g m The second-order derivative component of the circuit is effectively improved by the scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a circuit diagram of the present invention;

[0033] Figure 2 The local oscillator matching circuit of the present invention;

[0034] Figure 3 The passive mixer of the present invention;

[0035] Figure 4 is the first-stage amplifier of the present invention;

[0036] Figure 5 is the second stage amplifier of the present invention;

[0037] Figure 6 is the S-parameter signal flow graph of the present invention;

[0038] Figure 7 A graph showing the reflection coefficient results of the circuit input of the present invention;

[0039] Figure 8 This is a diagram showing the circuit gain results of the present invention;

[0040] Figure 9 The second-order derivative result diagram of gm of the transistor of the first-stage amplifier of the circuit of the present invention is shown;

[0041] Figure 10This is a graph showing the image rejection ratio, noise figure, and input compression point results of the circuit of the present invention;

[0042] Figure 11 This is a diagram showing the linearity results of the circuit of the present invention. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0044] The following is combined with Figure 1 To the attached Figure 11 The embodiments of the present invention are described in detail:

[0045] like Figure 1 As shown, a CMOS integrated millimeter wave self-matching receiver front-end circuit includes: a first orthogonal coupler, a second orthogonal coupler, a first passive mixer, a second passive mixer, a first first-stage amplifier, a first second-stage amplifier, a second first-stage amplifier, and a local oscillator;

[0046] The input local oscillator signal is fed single-ended through the input terminal LOIN and generates a pair of differential signals VLO1 and VLO2 after passing through the Marchand Balun, matching network, and transmission line. The output terminal VLO1 of the local oscillator signal is connected to the input terminal LO1 of the first passive mixer and the input terminal LO1 of the second passive mixer. The output terminal VLO2 of the local oscillator signal is connected to the input terminal LO2 of the first passive mixer and the input terminal LO2 of the second passive mixer.

[0047] The first signal is multiplied by the input local oscillator signal LO1 and the local oscillator signal LO2 through the input end of the first passive mixer to obtain an intermediate frequency voltage signal; the output end VO1 and the output end VO2 of the first passive mixer are respectively connected to the negative input end Vin5 and the positive input end Vin6 of the first first-stage amplifier; the output end VO5 and the output end VO6 of the first first-stage amplifier are respectively connected to the negative input end Vin9 and the positive input end Vin10 of the first second-stage amplifier; the output end VO9 and the output end VO10 of the first second-stage amplifier are respectively connected to thru2 and thru1 of the second orthogonal coupler;

[0048] The second signal is multiplied by the input local oscillator signal LO1 and the local oscillator signal LO2 through the input end of the second passive mixer to obtain an intermediate frequency voltage signal; the output end VO1 and the output end VO2 of the second passive mixer are respectively connected to the negative input end Vin3 and the positive input end Vin4 of the second first-stage amplifier; the output end VO3 and the output end VO4 of the second first-stage amplifier are respectively connected to the negative input end Vin7 and the positive input end Vin8 of the second second-stage amplifier; the output end VO7 and the output end VO8 of the second second-stage amplifier are respectively connected to Coupl2 and Coupl1 of the second orthogonal coupler;

[0049] The output terminals iso1 and iso2 of the second orthogonal coupler are grounded through resistors R2 and R3 respectively, and the output terminals vo1 and vo2 of the second orthogonal coupler serve as the intermediate frequency output voltage signal BB_I.

[0050] The present invention realizes self-matching of input impedance through front and rear orthogonal coupler circuits, achieves ultra-wide input matching of 40 to 60 GHz, and realizes a high image suppression ratio; in addition, good linearity is obtained by designing an intermediate frequency amplifier with a linearization circuit.

[0051] See attached Figure 1 As shown, the first orthogonal coupler and the second orthogonal coupler have the same structure, both comprising: a transformer T1, a capacitor C1, and a capacitor C2;

[0052] The In terminal of the transformer T1 is connected to one end of the capacitor C1, the Coupl terminal of the transformer T1 is connected to the other end of the capacitor C1, the iso terminal of the transformer T1 is connected to one end of the capacitor C2, and the thru terminal of the transformer T1 is connected to the other end of the capacitor C2.

[0053] See attached Figure 3 As shown, the first passive mixer and the second passive mixer have the same structure, and both include: an NMOS transistor Mn1, an NMOS transistor Mn2, a capacitor C9, a capacitor C10, a capacitor C28, a resistor R4, a resistor R5, and a resistor R6;

[0054] One end of the capacitor C28 is connected to the input RF signal RFQ. Similarly, another overlapping input end is RFI. The other end of the capacitor C28 is connected to one end of the resistor R4 and the source end of the NMOS transistor Mn1 and the source end of the NMOS transistor Mn2. The other end of the resistor R4 is connected to the bias DC voltage VRFDC. The gate end of the NMOS transistor Mn1 is connected to one end of the resistor R6 and one end of the capacitor C9. The other end of the resistor R6 is connected to the bias DC voltage VLODC1. The other end of the capacitor C9 is connected to the local oscillator signal LOp. The gate end of the NMOS transistor Mn2 is connected to one end of the resistor R5 and one end of the capacitor C10. The other end of the resistor R5 is connected to the bias DC voltage VLODC2. The other end of the capacitor C10 is connected to the local oscillator signal LOn. The drain end of the NMOS transistor Mn2 and the drain end of the NMOS transistor Mn1 serve as the output signal IFQ. Similarly, another overlapping output end is IFI.

[0055] See attached Figure 4 As shown, the first-stage amplifier and the second-stage amplifier have the same structure, and both include: NMOS transistor Mn3, NMOS transistor Mn4, NMOS transistor Mn5, NMOS transistor Mn6, NMOS transistor Mn7, NMOS transistor Mn8, NMOS transistor Mn9, NMOS transistor Mn10, NMOS transistor Mn11, NMOS transistor Mn12, NMOS transistor Mn13, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R13, resistor R14, resistor R15, resistor R16, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, capacitor C18, capacitor C19, and inductor L5;

[0056] The c-terminal of the inductor L5 is connected to the power supply voltage VDD, the a-terminal of the inductor L5 is connected to one end of the resistor R7, one end of the capacitor C15, and the drain end of the NMOS transistor Mn3, serving as the output end IFAvOp of the first-stage amplifier; the gate end of the NMOS transistor Mn3 is connected to the bias DC voltage Vbc1, the source end of the NMOS transistor Mn3 is connected to the drain end of the NMOS transistor Mn4, the drain end of the NMOS transistor Mn5, the drain end of the NMOS transistor Mn6, and the drain end of the NMOS transistor Mn7, the source end of the NMOS transistor Mn4 is connected to the a-terminal of the inductor L6 and one end of the capacitor C30, the gate end of the NMOS transistor Mn4 is connected to one end of the capacitor C29, and is connected to the bias DC voltage Vbc1 through the resistor R11. Vb1; it is also connected to one end of the capacitor C11, one end of the capacitor C12, and one end of the capacitor C13 through the capacitor C14 as the input terminal IFAvn of the first stage amplifier; the gate terminal of the NMOS transistor Mn5 is connected to the other end of the capacitor C13 and is connected to the bias DC voltage Vb2 through the resistor R10, and the source terminal of the NMOS transistor Mn5 is grounded; the gate terminal of the NMOS transistor Mn6 is connected to the other end of the capacitor C12 and is connected to the bias DC voltage Vb3 through the resistor R9, and the source terminal of the NMOS transistor Mn6 is grounded; the gate terminal of the NMOS transistor Mn7 is connected to the other end of the capacitor C11 and is connected to the bias DC voltage Vb4 through the resistor R8, and the source terminal of the NMOS transistor Mn7 is grounded;

[0057] The b-terminal of the inductor L5 is connected to the other end of the resistor R7, the other end of the capacitor C15, and the drain end of the NMOS transistor Mn8, serving as the output end IFAvOn of the first-stage amplifier; the gate end of the NMOS transistor Mn8 is connected to the bias DC voltage Vbc2, the source end of the NMOS transistor Mn8 is connected to the drain end of the NMOS transistor Mn9, the drain end of the NMOS transistor Mn10, the drain end of the NMOS transistor Mn11, and the drain end of the NMOS transistor Mn12, the source end of the NMOS transistor Mn9 is connected to the b-terminal of the inductor L6 and the other end of the capacitor C29, and the c-terminal of the inductor L6 is grounded; the gate end of the NMOS transistor Mn9 is connected to the other end of the capacitor C30 and is connected to the bias DC voltage Vb1 through the resistor R16. ; It is also connected to one end of the capacitor C19, one end of the capacitor C18, and one end of the capacitor C17 through the capacitor C16 as the input terminal IFAvp of the first-stage amplifier; the gate terminal of the NMOS transistor Mn10 is connected to the other end of the capacitor C17 and is connected to the bias DC voltage Vb2 through the resistor R15, and the source terminal of the NMOS transistor Mn10 is grounded; the gate terminal of the NMOS transistor Mn11 is connected to the other end of the capacitor C18 and is connected to the bias DC voltage Vb3 through the resistor R14, and the source terminal of the NMOS transistor Mn11 is grounded; the gate terminal of the NMOS transistor Mn12 is connected to the other end of the capacitor C19 and is connected to the bias DC voltage Vb4 through the resistor R13, and the source terminal of the NMOS transistor Mn12 is grounded.

[0058] See attached Figure 5 As shown, the first-channel second-stage amplifier and the second-channel second-stage amplifier have the same structure, and both include: NMOS transistor Mn14, NMOS transistor Mn15, NMOS transistor Mn16, NMOS transistor Mn17, PMOS transistor Mp1, PMOS transistor Mp2, PMOS transistor Mp3, PMOS transistor Mp4, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, capacitor C20, capacitor C21, capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, and common-mode feedback cmfb;

[0059] One end of the capacitor C26 is connected to one end of the capacitor C27, one end of the capacitor C20, one end of the capacitor C21, one end of the capacitor C22, one end of the capacitor C23, one end of the capacitor C24, and one end of the capacitor C25 as the input end IFGmp of the second-stage amplifier. Similarly, another overlapping input end is IFGmn. The other end of the capacitor C27 is connected to the gate end of the NMOS transistor Mn14 and is connected to the bias DC voltage Vbn1 through the resistor R18. The source end of the NMOS transistor Mn14 is grounded, and the drain end of the NMOS transistor Mn14 is connected to the drain end of the PMOS transistor Mp1, one end of the resistor R25, and the drain end of the NMOS transistor Mn15. The drain of the PMOS transistor Mp2, the drain of the NMOS transistor Mn16, the drain of the PMOS transistor Mp3, and the drain of the NMOS transistor Mn17 are connected to the drain of the PMOS transistor Mp4 to serve as the second-stage amplifier output terminal IFGmOn. Similarly, another overlapping output terminal is IFGmOp. The source terminal of the PMOS transistor Mp1 is connected to the power supply voltage VDD. The other end of the resistor R25 is connected to the positive input terminal of the common-mode feedback cmfb. The negative input terminal of the common-mode feedback cmfb is connected to the power supply voltage VDD / 2. The output terminal Vo of the common-mode feedback cmfb is connected to the other end of the capacitor C26 and the gate terminal of the PMOS transistor Mp1 through the resistor R17.

[0060] The other end of the capacitor C21 is connected to the gate terminal of the NMOS transistor Mn15 and is connected to the bias DC voltage Vbn2 through the resistor R20. The source terminal of the NMOS transistor Mn15 is grounded, and the source terminal of the PMOS transistor Mp2 is connected to the power supply voltage VDD. The other end of the capacitor C20 is connected to the gate terminal of the PMOS transistor Mp2 and is connected to the bias DC voltage Vbp1 through the resistor R19.

[0061] The other end of the capacitor C23 is connected to the gate terminal of the NMOS transistor Mn16 and is connected to the bias DC voltage Vbn3 through the resistor R22. The source terminal of the NMOS transistor Mn16 is grounded, and the source terminal of the PMOS transistor Mp3 is connected to the power supply voltage VDD. The other end of the capacitor C22 is connected to the gate terminal of the PMOS transistor Mp3 and is connected to the bias DC voltage Vbp2 through the resistor R21.

[0062] The other end of the capacitor C25 is connected to the gate terminal of the NMOS transistor Mn17 and is connected to the bias DC voltage Vbn4 through the resistor R24. The source terminal of the NMOS transistor Mn17 is grounded, and the source terminal of the PMOS transistor Mp4 is connected to the power supply voltage VDD. The other end of the capacitor C24 is connected to the gate terminal of the PMOS transistor Mp4 and is connected to the bias DC voltage Vbp3 through the resistor R23.

[0063] The first and second stage amplifiers described in the present invention are intermediate frequency amplifiers, which adopt a derivative superposition circuit structure to achieve a high linearity of 4 to 12 dBm. In addition, the final stage orthogonal coupler is based on the principle of capacitive coupling, so that the output differential signal can be perfectly orthogonal, achieving input impedance self-matching and ensuring good input matching at the input end.

[0064] The four-port quadrature coupler is implemented using lumped LC elements, and the ideal S parameters are shown in (1), where C is the coupling coefficient.

[0065]

[0066] from Figure 6 The signal flow graph shows that if port 4 matches (Γ4 = 0) and Γ L2 =Γ L3 =Γ L , then the input reflection coefficient (Γ IN ) is calculated as

[0067]

[0068] This shows that no matter how the load impedance of the coupled port and the through port changes (any Γ L ), the good matching of the input ports will be maintained as long as the input power is evenly distributed between the coupled port and the through port, which is demonstrated by simulating the S11 of the orthogonal coupler structure loaded with different impedances, as shown in Figure 7 It shows good port self-matching performance and can cover a bandwidth of 40 to 60 GHz. Similarly, due to the reciprocity of the four-port orthogonal coupler, it is easy to prove that there is also good self-matching characteristics at the output port.

[0069] refer to Figure 1For the RF signals input by the upper and lower sidebands, they are transformed by the orthogonal coupler and separated into codirectional and orthogonal dual-path signals. After further mixing and amplification, they are synthesized by the orthogonal coupler at the intermediate frequency, so that the RF signals input by the upper and lower sidebands are transmitted to the in and iso ports respectively. Given the natural isolation advantages of the in and iso ports, the image suppression of the upper and lower sideband signals is also high.

[0070] This embodiment is designed and implemented using a 40nm FD-SOI CMOS process. At a supply voltage of 1.2V, the power consumption is approximately 40mW. The design dimensions of the transistors are shown in Figure 4 and Figure 5 Marked, and the intermediate frequency is 4GHz; Figure 8 The circuit's gain output results at 40-60 GHz RF input frequencies are given. It can be seen that a peak gain of 15 dB is achieved, and the -3 dB gain bandwidth range is approximately 17 GHz. Figure 9 The second-order derivative results of gm of the MOS tube in the intermediate frequency amplifier are given. It can be seen that after the second-order derivatives of gm of several MOS tubes are superimposed, the second-order derivative of the overall gm is eliminated when the bias voltage is 0.5~0.7V, which effectively improves the linearity of the circuit. Figure 10 The results of the circuit's image rejection ratio, noise figure, and input compression point within the bandwidth are given. It can be seen that the image rejection ratio IRR is as high as 20 to 35dB, the noise figure NF is between 9.5 and 13.5dB, and the input compression point P1dB is between -7 and -9dBm. Figure 11 The linearity variation trend with the frequency spacing of the two-tone signal is shown. It can be seen that as the two-tone frequency Δf increases, the linearity gradually improves, and its performance is between 4 and 12 dBm.

[0071] Overall, the present invention provides a receiver front-end circuit that can operate in the 40-60 GHz frequency band. It has the characteristics of a large bandwidth range under port self-matching, high image suppression ratio, high linearity, etc., and can be widely used in millimeter wave communication equipment.

[0072] References:

[0073] Literature [1], [R.Ciocoveanu, R.Weigel and V.Issakov A highly-integrated60GHzreceiver for radar applications in 28nm bulk CMOS, in Proc.IEEEInt.Conf.Microw., Antennas, Commun.Electron.Syst.(COMCAS), Tel-Aviv, Israel, Nov. 2019].

[0074] Reference [2],

J.Kim, W.Choi, Y.Park, and Y.Kwon, 60GHz broadband image rejection receiver using varactor tuning, in Proc.IEEE RadioFreq.Integr.Circuits Symp., May 2010

Claims

1. A CMOS integrated millimeter wave self-matching receiver front-end circuit, characterized in that: include: A first orthogonal coupler, a second orthogonal coupler, a first passive mixer, a second passive mixer, a first first-stage amplifier, a first second-stage amplifier, a second first-stage amplifier, a second second-stage amplifier, a local oscillator, and an input terminal V RF , input LO IN , first signal, second signal, local oscillator signal LO1, local oscillator signal LO2; The input terminal V RF Single-ended input RF signal, the input terminal V RF Connect the input terminal In of the first orthogonal coupler; the iso terminal of the first orthogonal coupler is connected to the resistor R1, the resistor R1 is grounded, and the thru terminal of the first orthogonal coupler is connected to the input terminal V of the second passive mixer in2 The Coupl end of the first orthogonal coupler is connected to the input end V of the first passive mixer in1 ; The input terminal LO IN The single-ended input local oscillator signal generates a pair of differential signals V after passing through Marchand Balun, matching network, and transmission line. LO1 、V LO2 , the output terminal V of the local oscillator signal LO1 The input terminals LO1 and LO2 of the first passive mixer and the second passive mixer are connected respectively. The output terminal V LO2 connected to the input terminal LO2 of the first passive mixer and the input terminal LO2 of the second passive mixer respectively; The first signal passes through the input terminal of the first passive mixer and is multiplied by the input local oscillator signal LO1 and the local oscillator signal LO2 to obtain an intermediate frequency voltage signal; the output terminal V O1 and the output terminal V O2 They are respectively connected to the negative input terminal V in5 and the positive input terminal V in6 , the output terminal V of the first-stage amplifier of the first path O5 and the output terminal V O6 They are connected to the negative input terminal V of the first second stage amplifier in9 and the positive input terminal V in10 , the output terminal V of the first second stage amplifier O9 and the output terminal V O10 respectively connected to thru2 and thru1 of the second quadrature coupler; The second signal passes through the input terminal of the second passive mixer and is multiplied by the input local oscillator signal LO1 and the local oscillator signal LO2 to obtain an intermediate frequency voltage signal; the output terminal V O1 and the output terminal V O2 They are respectively connected to the negative input terminal V in3 and the positive input terminal V in4 , the output terminal V of the first stage amplifier of the second path O3 and the output terminal V O4 are connected to the negative input terminal V in7 and the positive input terminal V in8 , the output terminal V of the second-stage amplifier of the second path O7 and the output terminal V O8 Coupl2 and Coupl1 of the second orthogonal coupler are connected respectively; The output terminals iso1 and iso2 of the second orthogonal coupler are connected to one end of the resistor R2 and the resistor R3 respectively, and the other ends of the resistor R2 and the resistor R3 are grounded. The output terminals vo1 and vo2 of the second orthogonal coupler serve as the intermediate frequency output voltage signal BB_I.

2. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 1, characterized in that: The first orthogonal coupler and the second orthogonal coupler have the same structure. Including: transformer T1, capacitor C1, capacitor C2; The In terminal of the transformer T1 is connected to one end of the capacitor C1, the Coupl terminal of the transformer T1 is connected to the other end of the capacitor C1, the iso terminal of the transformer T1 is connected to one end of the capacitor C2, and the thru terminal of the transformer T1 is connected to the other end of the capacitor C2.

3. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 1, characterized in that: The first passive mixer and the second passive mixer have the same structure and both include: an NMOS transistor M n1 、NMOS tube M n2 , capacitor C9, capacitor C 10 , capacitor C 28 , resistor R4, resistor R5, resistor R6; The capacitor C 28 One end is connected to the input RF signal RF Q Similarly, the other overlapping input is RF I The capacitor C 28 The other end of the resistor R4 and the NMOS tube M n1 The source end and NMOS tube M n2 The other end of the resistor R4 is connected to the bias DC voltage V RFDC The NMOS tube M n1 The gate end is connected to one end of the resistor R6 and one end of the capacitor C9, and the other end of the resistor R6 is connected to the bias DC voltage V LODC1 The other end of the capacitor C9 is connected to the local oscillator signal LO p The NMOS tube M n2 The gate terminal is connected to one end of the resistor R5 and the capacitor C 10 One end of the resistor R5 is connected to the bias DC voltage V LODC2 , the capacitor C 10 The other end is connected to the local oscillator signal LO n The NMOS tube M n2 The drain end and NMOS tube M n1 The drain terminal is used as the output signal IF Q Similarly, the other overlapping output is IF I .

4. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 1, characterized in that: The first-stage amplifier and the second-stage amplifier have the same structure, both including: NMOS transistor M n3 、NMOS tube M n4 、NMOS tube M n5 、NMOS tube M n6 、NMOS tube M n7 、NMOS tube M n8 、NMOS tube M n9 、NMOS tube M n10 、NMOS tube M n11 、NMOS tube M n12 , resistor R7, resistor R8, resistor R9, resistor R 10 , resistor R 11 , resistor R 13 , resistor R 14 , resistor R 15 , resistor R 16 , capacitor C 11 , capacitor C 12 , capacitor C 13 , capacitor C 14 , capacitor C 15 , capacitor C 16 , capacitor C 17 , capacitor C 18 , capacitor C 19 , capacitor C 29 , capacitor C 30 , inductor L5 and inductor L6; The C terminal of the inductor L5 is connected to the power supply voltage V DD , the a end of the inductor L5 and one end of the resistor R7 and the capacitor C 15 One end and NMOS tube M n3 The drain end is connected as the output end of the first stage amplifier IF AvOp The NMOS tube M n3 The gate terminal is biased by a DC voltage V bc1 , the NMOS tube M n3 The source end and NMOS tube M n4 The drain end and NMOS tube M n5 The drain end and NMOS tube M n6 The drain end and NMOS tube M n7 The drain end of the NMOS tube M n4 The source end of the inductor L6 and the capacitor C 30 One end of the NMOS tube M n4 The gate terminal and capacitor C 29 One end is connected to the 11 Connect bias DC voltage V b1 ; Also through the capacitor C 14 With capacitor C 11 One end and capacitor C 12 One end and capacitor C 13 One end is connected to the input terminal of the first stage amplifier IF Avn The NMOS tube M n5 The gate terminal and capacitor C 13 The other end is connected through resistor R 10 Connect bias DC voltage V b2 , the NMOS tube M n5 The source end of the NMOS tube M is grounded; n6 The gate terminal and capacitor C 12 The other end is connected to the bias DC voltage V through resistor R9. b3 , the NMOS tube M n6 The source end of the NMOS tube M is grounded; n7 The gate terminal and capacitor C 11 The other end is connected to the bias DC voltage V through resistor R8. b4 , the NMOS tube M n7 The source end is grounded.

5. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 4, characterized in that: The b end of the inductor L5 is connected to the other end of the resistor R7 and the capacitor C 15 The other end and NMOS tube M n8 The drain end is connected as the output end of the first stage amplifier IF AvOn The NMOS tube M n8 The gate terminal is biased by a DC voltage V bc2 , the NMOS tube M n8 The source end and NMOS tube M n9 The drain end and NMOS tube M n10 The drain end and NMOS tube M n11 The drain end and NMOS tube M n12 The drain end of the NMOS tube M n9 The source end of the inductor L6 and the capacitor C 29 The other end of the inductor L6 is connected to the ground; the NMOS tube M n9 The gate terminal and capacitor C 30 The other end is connected through resistor R 16 Connect bias DC voltage V b1 ; Also through the capacitor C 16 With capacitor C 19 One end and capacitor C 18 One end and capacitor C 17 One end is connected to the input terminal of the first stage amplifier IF Avp The NMOS tube M n10 The gate terminal and capacitor C 17 The other end is connected through resistor R 15 Connect bias DC voltage V b2 , the NMOS tube M n10 The source end of the NMOS tube M is grounded; n11 The gate terminal and capacitor C 18 The other end is connected through resistor R 14 Connect bias DC voltage V b3 , the NMOS tube M n11 The source end of the NMOS tube M is grounded; n12 The gate terminal and capacitor C 19 The other end is connected through resistor R 13 Connect bias DC voltage V b4 , the NMOS tube M n12 The source end is grounded.

6. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 1, characterized in that: The first-way second-stage amplifier and the second-way second-stage amplifier have the same structure, both including: NMOS transistor M n14 、NMOS tube M n15 、NMOS tube M n16 、NMOS tube M n17 、PMOS tube M p1 、PMOS tube M p2 、PMOS tube M p3 、PMOS tube M p4 , resistor R 17 , resistor R 18 , resistor R 19 , resistor R 20 , resistor R 21 , resistor R 22 , resistor R 23 , resistor R 24 , resistor R 25 , capacitor C 20 , capacitor C 21 , capacitor C 22 , capacitor C 23 , capacitor C 24 , capacitor C 25 , capacitor C 26 , capacitor C 27 and common mode feedback cmfb; The capacitor C 26 One end of the capacitor C 27 One end and capacitor C 20 One end and capacitor C 21 One end and capacitor C 22 One end and capacitor C 23 One end and capacitor C 24 One end and capacitor C 25 One end is connected to the input terminal of the second stage amplifier IF Gmp Similarly, the other overlapping input is IF Gmn The capacitor C 27 The other end is connected to the NMOS tube M n14 The gate terminal is connected through the resistor R 18 Connect bias DC voltage V bn1 , the NMOS tube M n14 The source end of the NMOS tube M is grounded; n14 The drain end of the PMOS tube M p1 The drain terminal and resistor R 25 One end and NMOS tube M n15 The drain end and PMOS tube M p2 The drain end and NMOS tube M n16 The drain end and PMOS tube M p3 The drain end and NMOS tube M n17 The drain end of the PMOS tube M p4 The drain end is connected as the output end of the second stage amplifier IF GmOn Similarly, the other overlapping output is IF GmOp The PMOS tube M p1 The source terminal supply voltage V DD , the resistor R 25 The other end is connected to the positive input of the common-mode feedback cmfb, and the negative input of the common-mode feedback cmfb is the power supply voltage V DD / 2, the output terminal V of the common mode feedback cmfb o Through the resistor R 17 With capacitor C 26 The other end and PMOS tube M p1 Gate connection.

7. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 6, characterized in that: The capacitor C 21 The other end is connected to the NMOS tube M n15 The gate terminal is connected through the resistor R 20 Connect bias DC voltage V bn2 , the NMOS tube M n15 The source end of the PMOS tube M is grounded. p2 The source terminal supply voltage V DD , the capacitor C 20 The other end of the PMOS tube M p2 The gate terminal is connected through the resistor R 19 Connect bias DC voltage V bp1 .

8. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 6, characterized in that: The capacitor C 23 The other end is connected to the NMOS tube M n16 The gate terminal is connected through the resistor R 22 Connect bias DC voltage V bn3 , the NMOS tube M n16 The source end of the PMOS tube M is grounded. p3 The source terminal supply voltage V DD , the capacitor C 22 The other end of the PMOS tube M p3 The gate terminal is connected through the resistor R 21 Connect bias DC voltage V bp2 .

9. The CMOS integrated millimeter wave self-matching receiver front-end circuit according to claim 6, characterized in that: The capacitor C 25 The other end is connected to the NMOS tube M n17 The gate terminal is connected through the resistor R 24 Connect bias DC voltage V bn4 , the NMOS tube M n17 The source end of the PMOS tube M is grounded. p4 The source terminal supply voltage V DD , the capacitor C 24 The other end of the PMOS tube M p4 The gate terminal is connected through the resistor R 23 Connect bias DC voltage V bp3 .

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