Inductive pair, high power asymmetric switch and chip, electronic device

Abstract

The application belongs to the technical field of radio frequency switches and provides an inductance pair, a high-power asymmetric switch comprising the inductance pair, a radio frequency transceiver front-end chip, an integrated circuit chip and an electronic device, wherein the first end of a capacitor element and the common end of a low-coupling inductance pair are connected to a first signal end, the second end of the capacitor element is grounded, the first branch end of the low-coupling inductance pair and the first end of a first semiconductor switch module are connected to a second signal end, the second end of the first semiconductor switch module is grounded, the second branch end of the low-coupling inductance pair and the first end of a second semiconductor switch module are connected to the first end of an isolation enhancement module, the second end of the second semiconductor switch module is grounded, and the second end of the isolation enhancement module is connected to a third signal end. The isolation degree is improved by adding the isolation enhancement module, so that the receiving end low-noise amplifier is protected from the influence of power leakage generated by the power amplifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency technology, in particular to an inductor pair, a high-power asymmetric switch comprising the inductor pair, a radio frequency transceiver front-end chip, an integrated circuit chip and an electronic device. BACKGROUND

[0002] When the phased array system is applied, due to the angle adjustment of the radiation beam, the impedance of the antenna end of part of the TR components (radio frequency transceiver front-end components) in the array is mismatched due to signal reflection, and the reflected signal will have an adverse effect on the TR components.

[0003] When the phased array system works in a transmitting state, the power of the power amplifier (PA) at the transmitting end (TX) leaks to the input end of the low noise amplifier (LNA) due to the impedance mismatch of the TR components, and when the isolation degree of the receiving end is not enough, the gate voltage of the low noise amplifier will be increased due to the injection of the leaked power, and in severe cases, the low noise amplifier will be injected into saturation, the junction temperature of the low noise amplifier will rise, and the working stability and reliability will be destroyed. Therefore, a switch with low transmission loss and a switch with high receiving isolation are needed to ensure the performance of the TR components and protect the low noise amplifier of the receiving link.

[0004] Most of the existing radio frequency switches or radio frequency switch chips are composed of switching transistors, lumped parameter elements inductors, lumped parameter elements capacitors, resistors, microstrip lines, etc. Among them, inductors, microstrip lines, capacitors, etc. will generate electromagnetic radiation and other induced magnetic fields or electric fields due to signal excitation, which will affect the arrangement and normal work of other elements. In the design or manufacture of radio frequency switches or radio frequency switch chips, in order to solve the electromagnetic compatibility problem between elements, the existing method is to realize electromagnetic compatibility by maintaining a large arrangement distance between elements, which will result in a larger size of the radio frequency switch or radio frequency switch chip, which is not convenient for high-density integration and cost reduction. In addition, electromagnetic radiation, induced magnetic field or electric field will cause energy loss, which will sacrifice the performance of the radio frequency switch or radio frequency switch chip. In order to realize the popularization of high-frequency wireless communication technology, it is urgent to reduce the cost and improve the performance of components. SUMMARY

[0005] The present application provides an inductor pair, a high-power asymmetric switch, a radio frequency transceiver front-end chip, an integrated circuit chip and an electronic device. At least some embodiments of the present application solve the problem that the power of the power amplifier at the transmitting end leaks to the input end of the low noise amplifier due to impedance mismatch, which easily affects the stability and reliability of the low noise amplifier.

[0006] According to an aspect of an embodiment of the present application, a high-power asymmetric switch is provided, which comprises: a first signal end, a first semiconductor switch module, a second semiconductor switch module, a low-coupling inductor pair, a capacitor element, an isolation enhancement module, a second signal end, and a third signal end;

[0007] A first end of the capacitor element and a common end of the low-coupling inductor pair are connected to the first signal end, and a second end of the capacitor element is grounded.

[0008] A first branch end of the low-coupling inductor pair and a first end of the first semiconductor switch module are connected to the second signal end, and a second end of the first semiconductor switch module is grounded.

[0009] A second branch end of the low-coupling inductor pair and a first end of the second semiconductor switch module are connected to a first end of the isolation enhancement module, and a second end of the second semiconductor switch module is grounded.

[0010] A second end of the isolation enhancement module is connected to the third signal end.

[0011] In an embodiment, the low-coupling inductor pair comprises the first coupling inductor and the second coupling inductor, a first end of the first coupling inductor is connected to the second signal end, a second end of the first coupling inductor and a first end of the second coupling inductor are connected to the first signal end, and a second end of the second coupling inductor is connected to the third signal end.

[0012] The first coupling inductor and the second coupling inductor are spiral inductors, and the magnetic field directions of the induced magnetic fields of the first coupling inductor and the second coupling inductor are opposite, so as to reduce mutual inductance between the first coupling inductor and the second coupling inductor.

[0013] In an embodiment, the spiral direction of the first coupling inductor is opposite to the spiral direction of the second coupling inductor.

[0014] In an embodiment, the first coupling inductor and the second coupling inductor are arranged in axial symmetry.

[0015] In an embodiment, the first semiconductor switch module and the second semiconductor switch module are composed of m*n switch tubes, the m*n switch tubes are arranged in an array, and m and n are positive integers.

[0016] In an embodiment, the first semiconductor switch module comprises a first switch tube and a second switch tube, a first end of the first switch tube and a first end of the second switch tube are connected to the second signal end, and a second end of the first switch tube and a second end of the second switch tube are grounded.

[0017] The second semiconductor switch module includes a third switch tube and a fourth switch tube, a first end of the third switch tube and a first end of the fourth switch tube are connected to a first end of the isolation enhancement module, and a second end of the third switch tube and a second end of the fourth switch tube are connected to ground.

[0018] In an embodiment, the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are any one of CMOS, Bi-CMOS, and HEMT.

[0019] In an embodiment, the isolation enhancement module includes a microstrip line and a third semiconductor switch module.

[0020] A first end of the microstrip line is connected to a second end of the second coupling inductor, a second end of the microstrip line and a first end of the third semiconductor switch module are connected to the third signal end, and a second end of the third semiconductor switch module is grounded.

[0021] According to another aspect of embodiments of the present application, there is provided a low-coupling inductor pair arranged in an integrated circuit chip, the low-coupling inductor pair including a first inductor and a second inductor, one end of the first inductor and one end of the second inductor being connected together as a common end of the low-coupling inductor pair, and the other end of the first inductor and the other end of the second inductor being respectively a first branch end and a second branch end of the low-coupling inductor pair, wherein, when the low-coupling inductor pair is in an operating state, the magnetic field directions of the induced magnetic fields of the first inductor and the second inductor are opposite, so that mutual inductance between the first inductor and the second inductor is at least partially reduced.

[0022] According to still another aspect of embodiments of the present application, there is provided an inductor pair arranged in an integrated circuit chip, the inductor pair including a first inductor and a second inductor, each of the first inductor and the second inductor including a microstrip line having a first end and a second end, the microstrip lines of the first inductor and the second inductor being connected together to form a merged microstrip line having a head end and a tail end, wherein the first end of the microstrip line of the first inductor is the head end of the merged microstrip line, the second end of the microstrip line of the second inductor is the tail end of the merged microstrip line, the second end of the microstrip line of the first inductor and the first end of the microstrip line of the second inductor are connected together as a common end of the inductor pair, and the merged microstrip line is wound into two spiral patterns in the integrated circuit chip, and when the inductor pair is in an operating state, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns are opposite.

[0023] According to another aspect of embodiments of the present application, there is provided a high-power asymmetric switch including the low-coupling inductor pair or the inductor pair as described in any one of the above aspects.

[0024] According to another aspect of the embodiments of the present application, a radio frequency transceiver front-end chip is provided, which comprises the high-power asymmetric switch as described above.

[0025] In one embodiment, the radio frequency transceiver front-end chip further comprises a signal processing end, an antenna access end, a power amplifier, a low-noise amplifier and a low-power switch.

[0026] The common end of the low-power switch is connected to the signal processing end, the first branch end of the low-power switch is connected to the input end of the power amplifier, and the second branch end of the low-power switch is connected to the output end of the low-noise amplifier.

[0027] The output end of the power amplifier is connected to the second signal end of the high-power asymmetric switch, the input end of the low-noise amplifier is connected to the third signal end of the high-power asymmetric switch, and the first signal end of the high-power asymmetric switch is connected to the antenna access end.

[0028] According to another aspect of the embodiments of the present application, an integrated circuit chip is provided, which comprises the low-coupling inductor pair as described above, wherein the common end, the first branch end and the second branch end of the low-coupling inductor pair are connected to other circuit parts of the integrated circuit chip.

[0029] According to another aspect of the embodiments of the present application, an integrated circuit chip is provided, which comprises the inductor pair as described above, wherein the common end, the first branch end and the second branch end of the inductor pair are connected to other circuit parts of the integrated circuit chip, and wherein the first branch end and the second branch end of the inductor pair are the head end and the tail end of the merged microstrip line of the inductor pair, respectively.

[0030] According to another aspect of the embodiments of the present application, an electronic device is provided, which comprises the integrated circuit chip as described above.

[0031] In the embodiments of the inductor pair, the integrated circuit chip, the radio frequency transceiver front-end chip and the electronic device according to the present application, the inductor pair is arranged as a three-terminal (i.e. the common end, the first branch end and the second branch end) inductor pair in the chip and is configured to have opposite magnetic field directions of the induced magnetic fields of the two inductors of the inductor pair in the working state, so that the mutual coupling between the two inductors can be at least partially reduced, the loss caused thereby can be reduced, and thus the two inductors can be arranged relatively close in the chip, so that the size of the chip can be reduced and the cost can be lowered.

[0032] In the high-power asymmetric switch and the radio frequency transceiver front-end chip provided in the embodiments of the present application, the first end of the capacitor element and the common end of the low-coupling inductor pair are connected to the first signal end, and the second end of the capacitor element is grounded; the first branch end of the low-coupling inductor pair and the first end of the first semiconductor switch module are connected to the second signal end, and the second end of the first semiconductor switch module is grounded; the second branch end of the low-coupling inductor pair and the first end of the second semiconductor switch module are connected to the first end of the isolation enhancement module, and the second end of the second semiconductor switch module is grounded; the second end of the isolation enhancement module is connected to the third signal end, and the isolation degree is improved by adding the isolation enhancement module, so as to protect the receiving end low-noise amplifier from the influence of the power leakage generated by the power amplifier. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A principle schematic diagram of the high-power asymmetric switch provided in the embodiments of the present application;

[0034] Figure 2 A schematic diagram of the first semiconductor switch module 410 provided in the embodiments of the present application;

[0035] Figure 3 Another principle schematic diagram of the high-power asymmetric switch provided in the embodiments of the present application;

[0036] Figure 4 Another principle schematic diagram of the high-power asymmetric switch provided in the embodiments of the present application;

[0037] Figure 5 An equivalent impedance matching principle diagram when the semiconductor switch module provided in the embodiments of the present application is turned off;

[0038] Figure 6 An equivalent impedance matching principle diagram when the semiconductor switch module provided in the embodiments of the present application is turned on;

[0039] Figure 7 An equivalent impedance matching principle diagram when the signal link between the first signal end 101 and the second signal end 102 provided in the embodiments of the present application is turned on;

[0040] Figure 8 An equivalent impedance matching principle diagram when the signal link between the first signal end 101 and the third signal end 103 provided in the embodiments of the present application is turned on;

[0041] Figure 9 A schematic diagram of the radio frequency transceiver front-end chip provided in the embodiments of the present application;

[0042] Figures 10A-10D An arrangement schematic diagram of the inductor pair according to the embodiments of the present application;

[0043] Figures 11A-11DA schematic diagram of a corner shape of an inductor pair according to an embodiment of the present application;

[0044] Figure 12 A schematic block diagram of a composition of an integrated circuit chip according to an embodiment of the present application;

[0045] Figure 13 A schematic block diagram of a composition of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0047] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0048] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0049] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0050] In some applications, due to the large transmit power itself, and the high-power switch is designed to emphasize the loss of high power, so the isolation is not enough, and it is easy to cause the power leaked to the low noise amplifier to be relatively high, at this time, the input end of the low noise amplifier will maintain a relatively large power input, and even exceed the maximum input power of the low noise amplifier, which is easy to damage the low noise amplifier.

[0051] The embodiment of the present application provides a high-power asymmetric switch, referring to Figure 1As shown, the high-power asymmetric switch comprises a first signal end 101, a first semiconductor switch module 410, a second semiconductor switch module 420, a low-coupling inductor pair 300, a capacitor element 330, an isolation enhancement module 500, a second signal end 102, and a third signal end 103.

[0052] Specifically, a first end of the capacitor element 330 and a common end of the low-coupling inductor pair 300 are connected to the first signal end 101, and a second end of the capacitor element 330 is grounded.

[0053] A first end of the low-coupling inductor pair 300 and a first end of the first semiconductor switch module 410 are connected to the second signal end 102, and a second end of the first semiconductor switch module 410 is grounded.

[0054] A second end of the low-coupling inductor pair 300 and a first end of the second semiconductor switch module 420 are connected to a first end of the isolation enhancement module 500, a second end of the second semiconductor switch module 420 is grounded, and a second end of the isolation enhancement module 500 is connected to the third signal end 103.

[0055] In the embodiment, a common node of the low-coupling inductor pair 300 and the capacitor element 330 is connected to the first signal end 101, a common node of the low-coupling inductor pair 300 and the first semiconductor switch module 410 is connected to the second signal end 402, a common node of the low-coupling inductor pair 300 and the second semiconductor switch module 420 is connected to the first end of the isolation enhancement module 500, the second end of the isolation enhancement module 500 is connected to the third signal end 103, and the asymmetric switch is formed by adding the isolation enhancement module 500, so as to improve the isolation degree between the power amplifier and the low-noise amplifier in the transmit mode working state, thereby protecting the receiving end low-noise amplifier from the power leakage generated by the power amplifier.

[0056] In the embodiment, the first signal end 101 can be used as a common end, the second signal end 102 and the third signal end 103 can be used as two branch ends, a control end of the first semiconductor switch module 410 is connected to a first switch control signal end 201 for receiving a first switch control signal, and a control end of the second semiconductor switch module 420 is connected to a second switch control signal end 202 for receiving a second switch control signal.

[0057] In one specific application embodiment, the high-power asymmetric switch can be applied in a radio frequency transceiver front-end chip (TR chip), at this time, the first signal end 101 can be connected with an antenna, the second signal end 102 can be connected with an output end of a power amplifier, and the third signal end 103 can be connected with an input end of a low-noise amplifier. By setting the isolation enhancement module 500 at the third signal end 103, the isolation between the power amplifier and the low-noise amplifier can be improved, so as to protect the receiving end low-noise amplifier from the influence of power leakage generated by the power amplifier.

[0058] In one embodiment, the first semiconductor switch module 410 and the second semiconductor switch module 420 can be composed of m*n switch tubes, and the m*n switch tubes are arranged in an array.

[0059] Referring to Figure 2 For example, the switch tubes are arranged in m columns in the lateral direction and n rows in the longitudinal direction, where m and n are positive integers, each column of switch tubes is connected in series, and the control ends of each column of switch tubes are connected to the resistance voltage dividing network 411. The switch tube array 412 is composed of m*n switch tubes, the pressure bearing capacity of the first semiconductor switch module 410 is improved by connecting n switch tubes in series, and the current conduction capacity of the first semiconductor switch module 410 is improved by connecting m columns of switch tubes in parallel, so as to improve the switching power of the first semiconductor switch module 410. Therefore, the radio frequency switch module in the embodiment can be applied to a high-power switch, greatly expanding the application range of the asymmetric high-power switch.

[0060] Specifically, referring to Figure 2 As shown in the figure, the switch tube array 412 includes m*n switch tubes (switch tube Q11, switch tube Q1m, switch tube Qn1, and switch tube Qnm, etc.), the control end of the first switch tube in each column of switch tubes is connected to the resistance voltage dividing network 411, and the conduction range of each column of switch tubes is controlled by inputting a control signal.

[0061] In one embodiment, the resistance voltage dividing network 411 is used to provide a corresponding gate voltage for each switch tube.

[0062] In one embodiment, the conduction voltages of each row of switch tubes are the same.

[0063] In one embodiment, referring to Figure 3 As shown in the figure, the low-coupling inductor pair 300 includes the first coupling inductor 310 and the second coupling inductor 320, the first end of the first coupling inductor 310 is connected to the second signal end 102, the second end of the first coupling inductor 310 and the first end of the second coupling inductor 320 are commonly connected to the first signal end 101, and the second end of the second coupling inductor 320 is connected to the first end of the second semiconductor switch module 420.

[0064] The first coupling inductor 310 and the second coupling inductor 320 are spiral inductors. The magnetic field directions of the induced magnetic fields of the first coupling inductor 310 and the second coupling inductor 320 are opposite to reduce the mutual inductance between the first coupling inductor 310 and the second coupling inductor 320.

[0065] In this embodiment, by setting the first coupling inductor 310 and the second coupling inductor 320 as spiral inductors, and making the magnetic field directions of the induced magnetic fields of the first coupling inductor 310 and the second coupling inductor 320 opposite, the induced magnetic field generates induced eddy currents (currents) in the substrate. The current directions of the induced eddy currents are opposite. By weakening the current of the induced eddy currents, the mutual inductance between the first coupling inductor 310 and the second coupling inductor 320 is reduced, and the loss of the low coupling inductor to 300 is reduced, thereby achieving the purpose of optimizing switching losses.

[0066] In one embodiment, the helical direction of the first coupled inductor 310 is opposite to the helical direction of the second coupled inductor 320.

[0067] In this embodiment, by setting the spiral direction of the first coupling inductor 310 to be opposite to that of the second coupling inductor 320, the signal flow on the first coupling inductor 310 and the second coupling inductor 320 can be reversed, thereby making the magnetic field directions of the induced magnetic fields of the first coupling inductor 310 and the second coupling inductor 320 opposite, thus achieving the purpose of reducing the mutual inductance between the first coupling inductor 310 and the second coupling inductor 320.

[0068] In one embodiment, the first coupling inductor 310 and the second coupling inductor 320 are arranged symmetrically, combined with Figure 3 As shown, the first coupling inductor 310 and the second coupling inductor 320 have symmetrical structures and are arranged axially symmetrically with respect to their central axis.

[0069] In one embodiment, see Figure 3 As shown, the first semiconductor switch module 410 includes a first switch transistor 401 and a second switch transistor 402. The first end of the first switch transistor 401 and the first end of the second switch transistor 402 are connected to the second signal terminal 102. The second end of the first switch transistor 401 and the second end of the second switch transistor 402 are grounded.

[0070] In one embodiment, see Figure 3 As shown, the second semiconductor switch module 420 includes a third switch transistor 403 and a fourth switch transistor 404. The first end of the third switch transistor 403 and the first end of the fourth switch transistor 404 are connected to the first end of the isolation enhancement module 500 (or the second branch end of the low coupling inductor pair 300). The second end of the third switch transistor 403 and the second end of the fourth switch transistor 404 are connected to ground.

[0071] In one embodiment, the first switch tube 401 is symmetrical in structure with the second switch tube 402, and the third switch tube 403 is symmetrical in structure with the fourth switch tube 404.

[0072] In one embodiment, referring to Figure 3 As shown, the isolation enhancement module 500 includes a microstrip line 501 and a third semiconductor switch module 430.

[0073] The first end of the microstrip line 501 is connected to the second end of the second coupling inductor 320, the second end of the microstrip line 501 is connected to the first end of the third semiconductor switch module 430 at the third signal end 103, the second end of the third semiconductor switch module 430 is grounded, and the control end of the third semiconductor switch module 430 is connected to the second switch control signal end 202.

[0074] In one embodiment, the shape of the microstrip line 501 is any one of an arc shape, a rectangular shape, a concave shape, a semicircular shape, and an "L" shape.

[0075] In one embodiment, the microstrip line 501 can be composed of multiple microstrip line structures, the shapes of the multiple microstrip line structures can be different, and the included angle between adjacent microstrip line structures can be designed according to the chip area or impedance design needs.

[0076] In one embodiment, the first switch tube 401, the second switch tube 402, the third switch tube 403, and the fourth switch tube 404 are transistors.

[0077] In one embodiment, the first switch tube 401, the second switch tube 402, the third switch tube 403, and the fourth switch tube 404 are gallium arsenide pHEMTs.

[0078] In one embodiment, referring to Figure 4 As shown, the third semiconductor switch module 430 is a fifth switch tube.

[0079] In one embodiment, the fifth switch tube 430 is a transistor.

[0080] In one embodiment, the third semiconductor switch module 430 is a gallium arsenide pHEMT.

[0081] In one embodiment, the transistor is any one of a CMOS, a Bi-CMOS, and a HEMT.

[0082] In one embodiment, the transistor can be a CMOS, and the CMOS switch device can be a silicon-based CMOS, such as a silicon-based NMOS or PMOS.

[0083] In one embodiment, the transistor can also be a Bi-CMOS, which can be a germanium-silicon Bi-CMOS, such as an HBT or MOS tube in the germanium-silicon Bi-CMOS.

[0084] In one embodiment, the transistor can also be a HEMT, which can be a gallium arsenide pHEMT, an indium phosphide pHEMT, or a gallium nitride HEMT.

[0085] In one embodiment, the first end of the transistor can be a source or a drain.

[0086] In one embodiment, the control ends of the first switch tube 401 and the second switch tube 402 are connected in common, and the control ends of the third switch tube 403, the fourth switch tube 404, and the control end of the third semiconductor switch module 430 are connected in common.

[0087] Specifically, the control ends of the first switch tube 401 and the second switch tube 402 are connected to the first switch control signal end 201 in common, and the control ends of the third switch tube 403, the fourth switch tube 404, and the control end of the third semiconductor switch module 430 are connected to the second switch control signal end 202 in common. At this time, the first switch tube 401 and the second switch tube 402 are simultaneously turned on or turned off, and the control ends of the third switch tube 403, the fourth switch tube 404, and the third semiconductor switch module 430 are simultaneously turned on or turned off.

[0088] Referring to Figure 4 As shown, the first coupling inductance 310 and the second coupling inductance 320 are spiral inductances, and the first coupling inductance 310 and the second coupling inductance 320 together constitute a low-coupling inductance pair 300. The crossing part in the first coupling inductance 310 can be provided through an air bridge, and the crossing part in the second coupling inductance 320 can be provided through an air bridge.

[0089] Figure 5 is an equivalent impedance matching schematic diagram when the semiconductor switch module is turned off, wherein C0 is the equivalent capacitance of the semiconductor module in the off state, and Rc is the parasitic resistance of the semiconductor switch module in the off state.

[0090] Figure 6 is an equivalent impedance matching schematic diagram when the semiconductor switch module is turned on, wherein L0 is the equivalent inductance of the semiconductor switch module in the on state, and RL is the parasitic resistance of the semiconductor switch module in the on state.

[0091] Figure 7The equivalent impedance matching principle diagram for the signal link between the first signal end 101 and the second signal end 102 when it is in the on state, at this time, the first semiconductor switch module 410 is off, and the second semiconductor switch module 420 and the third semiconductor switch module 430 are simultaneously turned on.

[0092] Referring to Figure 7 As shown, the capacitor C1 in series with the resistor R1 is the equivalent circuit when the first semiconductor switch module 410 is off.

[0093] The inductor L1 in series with the resistor R2 is the equivalent circuit when the second semiconductor switch module 420 is on, the inductor L1 is the equivalent inductance when the second semiconductor switch module 420 is on, and the resistor R2 is the parasitic inductance when the second semiconductor switch module 420 is on. Since the resistor R2 is the parasitic resistance when the second semiconductor switch module 420 is on, its impedance is very small, at this time, the second end of the second semiconductor switch module 420 is close to ideal, and the capacitor C4 is the equivalent circuit of the capacitor element 330.

[0094] The inductor L4 is the equivalent inductance of the first coupled inductor 310, the inductor L5 is the equivalent inductance of the second coupled inductor 320, and the inductor L6 is the equivalent inductance of the microstrip line 501.

[0095] The resistor R5 in series with the inductor L3 is the equivalent circuit of the third semiconductor switch module 430, since the resistor R5 is the parasitic resistance when the third semiconductor switch module 430 is on, its impedance is very small, at this time, the third signal end 103 is close to ideal.

[0096] According to Figure 7 As shown, the first signal end 101 and the second signal end 102 form a π-type low-pass filter network, and signals can be transmitted between the two ends, both ends are in the on state; the first signal end 101 and the third signal end 103 form a two-stage L-type inductor network, both ends are in an impedance mismatch state, signals form strong reflection between the first signal end 101 and the third signal end 103, signal propagation is blocked, so both ends are in the off state. The two-stage L reflection structure helps to improve the signal isolation degree of the first signal end 101 and the third signal end 103. Figure 8 The equivalent impedance matching principle diagram for the signal link between the first signal end 101 and the third signal end 103 when it is in the on state, at this time, the first semiconductor switch module 410 is on, and the second semiconductor switch module 420 and the third semiconductor switch module 430 are simultaneously turned off.

[0097] Referring to Figure 8 As shown, the resistor R3 in series with the inductor L2 is the equivalent circuit when the first semiconductor switch module 410 is on, since the resistor R3 is the parasitic resistance when the first semiconductor switch module 410 is on, its impedance is very small, at this time, the second signal end 102 is close to ideal.

[0098] The capacitor C2 in series with the resistor R4 is an equivalent circuit when the second semiconductor switch module 420 is off, and the capacitor C3 in series with the resistor R6 is an equivalent circuit when the third semiconductor switch module 430 is off.

[0099] According to Figure 8 As shown in the figure, the first signal end 101 and the second signal end 102 form an L-shaped inductive network, and the impedance between the two ends is mismatched, the signal input between the two ends is easily reflected, and the signal propagation is blocked, so the two ends are in an off state; the first signal end 101 and the third signal end 103 form a two-stage π-type low-pass network, and the two-stage π-type low-pass network shares the capacitor C2, and the signal can be effectively propagated between the first signal end 101 and the third signal end 103, so the two ends are in an on state.

[0100] The embodiment of the application also provides a radio frequency transceiver front-end chip, comprising: the high-power asymmetric switch as described in any of the above embodiments.

[0101] In one embodiment, referring to Figure 9 As shown in the figure, the radio frequency transceiver front-end chip comprises: a signal processing end 601, a low-power switch 610, an antenna access end 602, a power amplifier 630, a low-noise amplifier 640, and a high-power asymmetric switch 620.

[0102] The common end (port 1) of the low-power switch 610 is connected to the signal processing end 601, the first branch end (port 2) of the low-power switch 610 is connected to the input end of the power amplifier 630, and the second branch end (port 3) of the low-power switch 610 is connected to the output end of the low-noise amplifier 640.

[0103] The output end of the power amplifier 630 is connected to the second signal end (port 5) of the high-power asymmetric switch 620, the input end of the low-noise amplifier 640 is connected to the third signal end (port 6) of the high-power asymmetric switch 620, and the first end (port 4) of the high-power asymmetric switch 620 is connected to the antenna access end 602.

[0104] In a specific application, the power amplifier 630 is arranged at the front end of an antenna, and the communication distance is increased by increasing the radiation power of the transmitter, and the power amplifier 630 and the antenna are combined together to form an active transmitting antenna.

[0105] In a specific application, the low-noise amplifier 640 is arranged at the front end of a receiver, and forms an active receiving antenna after being combined with the antenna. Since the signal fed down by the receiver antenna is relatively weak, for example, the received signal is less than the noise, the small received signal is amplified by the low-noise amplifier and then sent to the signal processing end 601.

[0106] Referring to Figure 9As shown, the common terminal (port 1) of the low-power switch 610 can be connected with a signal processing end 601, which can be connected with a mixer or a beamforming module (or a phase / amplitude modulation module), or a digital-to-analog conversion functional circuit.

[0107] In the embodiment, the high-power asymmetric switch 620 can be the high-power asymmetric switch described in any of the above embodiments.

[0108] In a specific application, the port 1 and the port 2 of the low-power switch 610 and the port 4 (i.e., the first signal terminal 101) and the port 5 (i.e., the second signal terminal 102) of the high-power asymmetric switch 620 are simultaneously turned on or turned off, and the port 1 and the port 3 of the low-power switch 610 and the port 4 (i.e., the first signal terminal 101) and the port 6 (i.e., the third signal terminal 103) of the high-power asymmetric switch 620 are simultaneously turned on or turned off.

[0109] Specifically, when the working mode of the radio frequency transceiver front-end chip is the transmitting mode, the power-on steps are as follows:

[0110] Step A1: the drain of the transistor in the power amplifier 630 is set to a low level, and the gate is set to a negative voltage, so that the transistor is turned off;

[0111] Step A2: under the control of the low-power switch control signal LP-SW, the port 1 and the port 2 of the low-power switch 610 are turned on, and the port 1 and the port 3 are turned off; under the control of the high-power switch control signal HP-SW, the port 4 (i.e., the first signal terminal 101) and the port 5 (i.e., the second signal terminal 102) of the high-power asymmetric switch 620 are turned on, and the port 4 and the port 6 (i.e., the third signal terminal 103) are turned off;

[0112] Step A3: the drain voltage of the transistor in the power amplifier 630 is raised to a working voltage, the gate voltage is set to rise to a normal working voltage, the transistor is normally turned on, the signal is input from the signal processing end 601, the power amplifier 630 performs power amplification, and then transmits the signal through the antenna connected with the antenna access end 602;

[0113] Step A4: the gate voltage of the transistor in the power amplifier 630 is lowered to a negative voltage, and the drain voltage is lowered to a low level, so that the power amplifier 630 is turned off.

[0114] When the working mode of the radio frequency transceiver front-end chip is the receiving mode, the power-on steps are as follows:

[0115] Step B1: the drain of the transistor in the low-noise amplifier 640 is set to a low level, and the gate is set to a negative voltage, so that the transistor is turned off;

[0116] Step B2: Under the control of the low-power switch control signal LP-SW, the port 1 and port 2 of the low-power switch 610 are turned off, and the port 1 and port 3 are turned on. Under the control of the high-power switch control signal HP-SW, the port 4 and port 5 of the high-power asymmetrical switch 620 are turned off, and the port 4 and port 6 are turned on.

[0117] Step B3: The drain voltage of the transistor in the low-noise amplifier 640 rises to the operating voltage, and the gate voltage is set to rise to the normal operating voltage. The transistor is turned on normally. At this time, the antenna signal is received through the antenna connected to the antenna access terminal 602, and after being processed by the low-noise amplifier, it is sent to the signal processing terminal 601.

[0118] Step B4: The gate voltage of the transistor in the low-noise amplifier 640 drops to a negative voltage, the drain voltage drops to a low level, and the low-noise amplifier 640 is turned off.

[0119] In the above embodiments of high-power asymmetric switches and RF transceiver front-end chips, a low-coupling inductor pair 300 is disclosed, which includes a first inductor 310 and a second inductor 320. One end of the first inductor 310 and one end of the second inductor 320 are connected together as a common terminal of the low-coupling inductor pair 300. The other ends of the first inductor 310 and the second inductor 320 serve as a first branch terminal and a second branch terminal of the low-coupling inductor pair 300, respectively. Both the first inductor 310 and the second inductor 320 are helical inductors, and the helical directions of the first inductor 310 and the second inductor 320 are opposite. When the low-coupling inductor pair 300 is in operation, current flows through both the first inductor 310 and the second inductor 320, and the magnetic field directions of the induced magnetic fields they generate are opposite, thereby at least partially reducing the mutual inductance between the first inductor 310 and the second inductor 320. Because the mutual inductance between the first inductor 310 and the second inductor 320 is relatively low, the inductor pair 300 is referred to as a "low-coupling inductor pair".

[0120] It should be understood that the inductor pair 300 with the arrangement or structure described above can be used not only in the high-power asymmetric switches and RF transceiver front-end chips described above, but also in any other suitable circuit / integrated circuit chip to reduce chip size and lower cost.

[0121] Figures 10A-10D A schematic diagram of the arrangement of inductor pairs according to an embodiment of this application is shown. In this embodiment, the inductor pairs are arranged in an integrated circuit chip, which may include one or more wiring layers, and the inductor pairs are arranged in the wiring layers of the integrated circuit chip. Figures 10A-10D In the example, the inductor pair includes a first inductor and a second inductor, both of which are composed of microstrip lines. Figures 10A-10DAs shown, the first inductor is composed of the first microstrip line 710, and the second inductor is composed of the second microstrip line 720. One end of the first microstrip line 710 and one end of the second microstrip line 720 are connected together to form a combined microstrip line. The end point 701 of the first microstrip line 710 and the end point 703 of the second microstrip line 720 are the head end and tail end of the combined microstrip line respectively, and the connection point 702 of the first microstrip line 710 and the second microstrip line 720 is the common end of the first microstrip line 710 and the second microstrip line 720. It should be understood that the naming of the "head end" and the "tail end" is only to distinguish the two end points of the combined microstrip line, and their names can be interchanged.

[0122] The combined microstrip line is wound into two spiral patterns, i.e., a first spiral pattern S1 and a second spiral pattern S2, in the integrated circuit chip. In the integrated circuit chip, the first spiral pattern S1 and the second spiral pattern S2 are arranged such that the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns S1 and S2 are opposite when the inductor pair is in operation.

[0123] As an example, the first microstrip line 710 and the second microstrip line 720 can be wound in opposite directions, so that the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite, thereby making the directions of their respective induced magnetic fields opposite. For example, the spiral direction of one of S1 and S2 is counterclockwise, and the spiral direction of the other is clockwise. Here, the direction from the head end 701 or the tail end 703 to the common end 702 can be referred to as the spiral direction, or the direction from the common end 702 to the head end 701 or the tail end 703 can also be referred to as the spiral direction.

[0124] In one embodiment, the two spiral patterns S1 and S2 do not overlap and are adjacent but at a distance in the direction parallel to the wiring layer of the integrated circuit chip. In the embodiments of the present application, as described below, because the mutual coupling between the two inductors is low, the two spiral patterns S1 and S2 can be arranged as close as possible (but without overlapping portions), thereby reducing the chip size and reducing the cost. In one example, the distance between the two spiral patterns S1 and S2 (such as the distance D shown) can be as small as about 3 microns. Here, the "distance between the two spiral patterns" refers to the distance between the closest microstrip lines of the two spiral patterns. As shown, the distance D is the distance between the adjacent outermost turns of S1 and S2. In practice, the minimum distance between the two spiral patterns is determined by the chip manufacturing process. Figures 10A-10D Figures 10A-10D

[0125] ​​The merged microstrip line (first / second microstrip line) of the embodiments of the present application can be composed of single-layer or multi-layer metal materials. In one example, the merged microstrip line is composed of multi-layer metal materials, each of which is located in a different wiring layer of the integrated circuit chip. The multi-layer metal materials located in different wiring layers are superimposed together to form the merged microstrip line, and are connected through interlayer vias between the layers. In another example, the merged microstrip line is composed of single-layer metal materials, which can be located in the same or different wiring layers of the integrated circuit chip. For example, part of the single-layer metal materials is located in one wiring layer, and the other part is located in one or more different wiring layers. Similarly, the single-layer metal materials located in different wiring layers are connected through vias.

[0126] Figures 10A-10D Four different winding modes of the merged microstrip line are shown, but the spiral directions of the first spiral pattern S1 and the second spiral pattern S2 are opposite. Figures 10A-10D All are schematic diagrams of the inductor pair arrangement viewed from the direction perpendicular to the wiring layer of the integrated circuit chip.

[0127] As shown in Figure 10A , the first spiral pattern S1 is wound by the merged microstrip line from the head end 701 to the common end 702 in the counterclockwise direction, and the second spiral pattern S2 is wound by the merged microstrip line from the tail end 703 to the common end 702 in the clockwise direction. In Figure 10A the example, both from the head end 701 to the common end 702 and from the tail end 703 to the common end 702 are wound from the inside to the outside (i.e. the head end 701 and the tail end 703 are located in the innermost turn, and the turns are wound from the inside to the outside). It can be understood that S1 and S2 can also be wound from the inside to the outside and from the outside to the inside, respectively. In the spiral patterns S1 and S2, when a part of the microstrip line crosses another part, an air bridge can be used to make the part of the microstrip line cross the other part of the microstrip line.

[0128] As shown in Figure 10B , similarly, the first spiral pattern S1 is wound by the merged microstrip line from the head end 701 to the common end 702 in the counterclockwise direction, and the second spiral pattern S2 is wound by the merged microstrip line from the tail end 703 to the common end 702 in the clockwise direction. However, unlike Figure 10A , in Figure 10B the example, both from the head end 701 to the common end 702 and from the tail end 703 to the common end 702 are wound from the outside to the inside (i.e. the head end 701 and the tail end 703 are located in the outermost turn, and the turns are wound from the outside to the inside). It can be understood that S1 and S2 can also be wound from the inside to the outside and from the outside to the inside, respectively. Similarly, when a part of the microstrip line crosses another part (for example Figure 10BWhen a portion of the microstrip line crosses another portion of the microstrip line (e.g., at the crossing points C1, C2, C3, and C4 in FIGS. 1A and 1B), a portion of the microstrip line can cross over another portion of the microstrip line via an air bridge.

[0129] Figure 10A and 10B In the examples of FIGS. 1A and 1B, the microstrip line is wound in a spiral pattern S1 and S2 either from the outside in or from the inside out. However, it is understood that the microstrip line need not always be wound from the inside out or from the outside in when winding the microstrip line in a spiral pattern S1 or S2, but can change direction one or more times. For example, as shown in FIGS. 2A and 2B, the microstrip line can be wound in a spiral pattern S1 or S2 from the inside out in one direction and from the outside in in another direction. Figure 10C and 10D In the first spiral pattern S1 of FIG. 1A, the direction is from the inside out from the start end 701 to the crossing point C5, and from the outside in from the crossing point C5 to the common end 702, but always counterclockwise from the start end 701 to the common end 702; in the second spiral pattern S2 of FIG. 1B, the direction is from the inside out from the end end 702 to the crossing point C7, and from the outside in from the crossing point C7 to the common end 702, but always clockwise from the end end 703 to the common end 702; in the first spiral pattern S1 of FIG. 3A, the direction is from the outside in from the start end 701 to the crossing point C9, and from the inside out from the crossing point C9 to the common end 702, but always counterclockwise from the start end 701 to the common end 702; in the second spiral pattern S2 of FIG. 3B, the direction is from the outside in from the end end 702 to the crossing point C10, and from the inside out from the crossing point C10 to the common end 702, but always clockwise from the end end 703 to the common end 702. Likewise, when a portion of the microstrip line crosses another portion of the microstrip line (e.g., at the crossing points C5-C10 in FIGS. 2A and 2B), a portion of the microstrip line can cross over another portion of the microstrip line via an air bridge. Figure 10C Figure 10C Figure 10D Figure 10D Figure 10C 10D In the first spiral pattern S1 of FIG. 1A, the direction is from the inside out from the start end 701 to the crossing point C5, and from the outside in from the crossing point C5 to the common end 702, but always counterclockwise from the start end 701 to the common end 702; in the second spiral pattern S2 of FIG. 1B, the direction is from the inside out from the end end 702 to the crossing point C7, and from the outside in from the crossing point C7 to the common end 702, but always clockwise from the end end 703 to the common end 702; in the first spiral pattern S1 of FIG. 3A, the direction is from the outside in from the start end 701 to the crossing point C9, and from the inside out from the crossing point C9 to the common end 702, but always counterclockwise from the start end 701 to the common end 702; in the second spiral pattern S2 of FIG. 3B, the direction is from the outside in from the end end 702 to the crossing point C10, and from the inside out from the crossing point C10 to the common end 702, but always clockwise from the end end 703 to the common end 702. Likewise, when a portion of the microstrip line crosses another portion of the microstrip line (e.g., at the crossing points C5-C10 in FIGS. 2A and 2B), a portion of the microstrip line can cross over another portion of the microstrip line via an air bridge.

[0130] In summary, each spiral pattern in S1 and S2 can wind the merged microstrip line from the start end or the end end to the common end in one of the following ways:

[0131] from the inside out;

[0132] from the outside in;

[0133] a combination of the above two.

[0134] ​​​​​In the above example, when a portion of the microstrip line crosses another portion of the microstrip line, the crossing problem is solved by making the portion of the microstrip line cross the other portion of the microstrip line through an air bridge. Other techniques can also be used to solve the crossing problem of the microstrip line. Alternatively, the two portions of the microstrip line that cross each other can be arranged in different layers that are not adjacent. For example, assuming that a segment A of the microstrip line crosses a segment B of the microstrip line, to solve the crossing problem, the segment A of the microstrip line can be arranged in an mth layer (e.g., the first layer) of the integrated circuit chip, and the segment B of the microstrip line can be arranged in an nth layer (e.g., the third layer) that is not adjacent to the mth layer. The portion of the microstrip line that is adjacent to the segment B can be arranged in the same or a different layer of the chip as the segment B, and if in different layers, can be connected through a via between the layers. The reason that the two portions of the microstrip line that cross each other are arranged in different layers that are not adjacent is that if arranged in adjacent layers, the two portions of the microstrip line that cross each other can cause a capacitive effect that can interfere with the circuit. Arranging the two portions of the microstrip line that cross each other in different layers that are not adjacent can reduce the capacitive effect.

[0135] In Figures 10A-10D the example, both spiral patterns S1 and S2 include multiple turns, it is understood that they can also each include one turn.

[0136] Each turn of the spiral patterns S1 and S2 can be any suitable regular or irregular shape, such as circular, elliptical, polygonal, etc. In Figures 10A-10D the example, S1 and S2 are shown as substantially square in shape for each turn, wherein Figure 10A each corner of the square is rounded in Figure 10B each corner of the square is beveled in Figure 10C each corner of the square is a right angle in 10D andeach corner of the square is a right angle bevel, wherein

[0137] Figures 11A-11D schematic diagrams of corner shapes of an inductive pair according to embodiments of the present application are shown. Figure 11A the corner shape is rounded in Figure 11B the corner shape is a right angle in Figure 11C and the corner shape is a right angle bevel, wherein 11D the corner is beveled on both the inside and outside in Figure 11C the corner is beveled only on the outside in Figure 11D When each turn is square or rectangular, at least one corner of the square or rectangle can be shaped as any of Figures 11A-11D

[0138] In Figures 10A-10DIn the example shown in FIG. 7, the length of the microstrip line between the common end 702 and the head end 701 is equal to the length of the microstrip line between the common end 702 and the tail end 703. It is to be understood that the common end 702 can also be located at other positions, such as closer to S1 or S2.

[0139] In Figures 10A-10D the example shown in FIG. 7, the spiral patterns S1 and S2 are arranged in mirror image, i.e. mirror image patterns, in Figures 10A-10D axial symmetry. That is, the spiral patterns S1 and S2 have the same configuration, such as the same number of turns, the same width of the microstrip line, and the same spacing between adjacent turns, except that the patterns are reversed (the winding direction is reversed), and the two are in a symmetric / mirror image relationship about a plane perpendicular to the layout layer located between the two. S1 and S2 can also be arranged in mirror image, for example, S1 and S2 have different configurations, such as different numbers of turns, different widths of the microstrip line, or different spacings between adjacent turns, as long as the induced magnetic field directions of the spiral patterns S1 and S2 wound are opposite.

[0140] In one example, the spiral patterns S1 and S2 can be arranged as follows: the side of the first spiral pattern S1 containing more turns of the microstrip line is adjacent to the side of the second spiral pattern S2 containing more turns of the microstrip line, and the sides of the two containing fewer turns of the microstrip line are far apart, as shown in Figure 10B and 10C In another example, the spiral patterns S1 and S2 can be arranged as follows: the side of the first spiral pattern S1 containing fewer turns of the microstrip line is adjacent to the side of the second spiral pattern S2 containing fewer turns of the microstrip line, and the sides of the two containing more turns of the microstrip line are far apart, as shown in Figure 10A .

[0141] It is to be understood that the arrangement of the first spiral pattern S1 and the second spiral pattern S2 in Figures 10A-10D can be interchangeable.

[0142] In the inductor pair according to the above-described embodiments of the present application, the microstrip lines of the two inductors have a common end, and are arranged as two spiral patterns with opposite spiral directions, so that in the working state when an excitation signal is applied to the inductor pair, the directions of the induced magnetic fields generated by the currents in the two spirals are opposite, thereby at least partially reducing the mutual coupling / mutual inductance between the two inductors.

[0143] In one example, leads can be drawn out from the common end 702 and the head end 701 and the tail end 703 to access the radio frequency signal or connect to other circuit parts. If the leads intersect the merged microstrip line, the leads can cross the merged microstrip line through an air bridge or the merged microstrip line can cross the leads through an air bridge.

[0144] In the above described inductance pair embodiments, the inductance pair is arranged in an integrated circuit chip to have three ports: a common port 702, a head port 701 as a first branch port of the inductance pair, and a tail port 703 as a second branch port of the inductance pair. As previously described, the three ports of the inductance pair can be connected to an excitation signal or other circuitry through leads. For example, a radio frequency excitation signal can be accessed from the common port of the inductance pair, and the radio frequency excitation signal is split at the common port to the first microstrip line (first inductor) and the second microstrip line (second inductor). The radio frequency excitation signal is generally a periodically varying signal, such as a sinusoidal signal. Assume that the excitation signal accessed at the common port is i com = I com sin ωt. The excitation signal is split at the common port 702 into two branches, one branch flowing through the common port 702 to the first spiral pattern S1 of the first branch port (head port) 701, and the other branch flowing through the common port 702 to the second spiral pattern S2 of the second branch port (tail port) 703. Assume that the excitation signal in the first spiral pattern S1 is i1(t), and the excitation signal in the second spiral pattern S2 is i2(t), and that there is no reflection (all three ports of the inductance pair are matched), then i1(t) + i2(t) = I com sin ωt. If the common port is located at the midpoint of the merged microstrip line, and S1 and S2 are patterns that are axisymmetric, then the excitation signals in S1 and S2 are identical at any time, i.e. The excitation signals i1(t) and i2(t) in the inductance pair are periodically varying signals, and the current magnitude varies periodically and non-uniformly, so the induced magnetic field generated is also periodically varying and non-uniform. The varying magnetic field in turn generates an electric field, thereby generating electromagnetic waves. In the case where the excitation signals in S1 and S2 are identical, since the spiral directions of S1 and S2 are opposite, the induced magnetic field generated by S1 at any time is identical in magnitude to the induced magnetic field generated by S2, but the direction of the magnetic field is opposite, and the corresponding induced electric field is also opposite in direction and changes direction periodically. Therefore, the induced magnetic fields generated by S1 and S2 will almost completely cancel out in many regions, and will partially cancel out in some regions, so the corresponding electric field or electromagnetic wave caused by the induced magnetic field will also be partially cancelled out, thereby reducing the loss of the inductance pair.

[0145] If the common port is not located at the midpoint of the merged microstrip line, or S1 and S2 are patterns with different configurations, it can not be guaranteed that the excitation signals in S1 and S2 are identical, so the degree of mutual cancellation of the induced magnetic fields of S1 and S2 is weakened compared to the case where the excitation signals in S1 and S2 are identical, but the induced magnetic fields generated by S1 and S2 at any time will still partially cancel each other out, weakening the electromagnetic radiation intensity, thereby reducing the loss of the inductance pair to some extent.

[0146] It should be noted that, theoretically, the inductive pair with three ports (a common port, a first branch port being the first end of the merged microstrip line, and a second branch port being the second end of the merged microstrip line) as described above is a passive lossless network, and since a passive network is reciprocal, the loss and transmission characteristics of the inductive pair are reciprocal no matter the excitation signal is input from any of the three ports.

[0147] Since the radiation range of the induced electromagnetic field of the low-coupling inductive pair is reduced and the strength is weakened, the arrangement distance between the inductive pair and other elements can be smaller, which is conducive to reducing the occupied area or space of the overall circuit.

[0148] The low-coupling inductive pair or each embodiment of the inductive pair as described above in the present application can be applied to any appropriate circuit, for example, applied to the high-power asymmetric switch as previously described with reference to Figures 1-9 The embodiments of the present application provide a high-power asymmetric switch, which includes any one of the low-coupling inductive pair or each embodiment of the inductive pair as described above, and further includes a first signal port, a first semiconductor switch module, a second semiconductor switch module, a capacitor element, an isolation enhancement module, a second signal port, and a third signal port, wherein:

[0149] The first end of the capacitor element and the common port of the inductive pair are connected to the first signal port, and the second end of the capacitor element is grounded;

[0150] The first branch port of the inductive pair and the first end of the first semiconductor switch module are connected to the second signal port, and the second end of the first semiconductor switch module is grounded;

[0151] The second branch port of the inductive pair and the first end of the second semiconductor switch module are connected to the first end of the isolation enhancement module, and the second end of the second semiconductor switch module is grounded;

[0152] The second end of the isolation enhancement module is connected to the third signal port,

[0153] The first branch port and the second branch port of the inductive pair are respectively the first end and the second end of the merged microstrip line of the inductive pair.

[0154] For other descriptions of the high-power asymmetric switch, please refer to the foregoing description of the high-power asymmetric switch. Figures 1-9 The foregoing description of the high-power asymmetric switch is not repeated here.

[0155] Similarly, the embodiments of the present application also provide a radio frequency transceiver front-end chip comprising the high-power asymmetric switch according to any of the embodiments described above. Details of the radio frequency transceiver front-end chip can be found in the foregoing description, which will not be repeated here. It can be understood that the embodiments of the present application are not limited to the details of the radio frequency transceiver front-end chip described above, on the contrary, any radio frequency transceiver front-end chip using the inductive pair according to the embodiments of the present application falls within the protection scope of the present application.

[0156] It should be understood that the embodiments of the inductive pair provided by the present application are not only applicable to the high-power asymmetric switch or the radio frequency transceiver front-end chip as described above, but also applicable to any other appropriate circuit or chip. Figure 12 A constituent schematic block diagram of an integrated circuit chip according to the embodiments of the present application is shown. As shown in Figure 12 The integrated circuit chip 800 comprises the inductive pair 700, wherein the inductive pair 700 is any of the embodiments of the low-coupling inductive pair or the inductive pair as described above, wherein the common terminal, the first branch terminal and the second branch terminal of the low-coupling inductive pair or the inductive pair are connected to other circuit parts of the integrated circuit chip. The integrated circuit chip 800 can comprise one inductive pair 700, or can comprise a plurality of inductive pairs 700. The integrated circuit chip 800 can be a radio frequency transceiver front-end chip, a chip comprising the high-power asymmetric switch as described above, or any other chip using the inductive pair as described above.

[0157] The integrated circuit chip 800 can be used in an electronic device such as a mobile phone. Figure 13 A constituent schematic block diagram of an electronic device according to the embodiments of the present application is shown. As shown in Figure 13 The electronic device 900 comprises the integrated circuit chip 800, wherein the integrated circuit chip 800 is the integrated circuit chip as described above.

[0158] The electronic device 900 can be any device suitable for applying the integrated circuit chip comprising the inductive pair as described above, for example, can be a wireless device. The wireless device can be a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a base station, etc. The wireless device can also be a cellular phone, a smartphone, a tablet computer, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, etc. The wireless device can be capable of communicating with a wireless communication system, and can be capable of receiving signals from a broadcast station, from one or more satellites, etc. The wireless device can support one or more wireless communication technologies (e.g., 5G, LTE, CDMA2000, WCDMA, TD-SCDMA, GSM, 802.11, millimeter wave, etc.).

[0159] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0160] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0161] The units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place or distributed to multiple functional units. Part or all of the units can be selected to achieve the purpose of the embodiment scheme according to actual needs.

[0162] In addition, each functional unit in each embodiment of the present application can be integrated in one chip unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0163] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A high power asymmetric switch, characterized by, The application is applied to a radio frequency transceiver front-end chip, comprising a first signal terminal, a first semiconductor switch module, a second semiconductor switch module, an inductor pair, a capacitor element, an isolation enhancement module, a second signal terminal and a third signal terminal. The first end of the capacitor element and the common end of the inductor pair are connected to the first signal terminal, and the second end of the capacitor element is grounded; the first branch end of the inductor pair and the first end of the first semiconductor switch module are connected to the second signal terminal, and the second end of the first semiconductor switch module is grounded; the second branch end of the inductor pair and the first end of the second semiconductor switch module are connected to the first end of the isolation enhancement module, and the second end of the second semiconductor switch module is grounded; the second end of the isolation enhancement module is connected to the third signal terminal, and an asymmetric switch is formed by adding the isolation enhancement module; the first branch end and the second branch end of the inductor pair are the head end and the tail end of the combined microstrip line of the inductor pair respectively; The isolation enhancement module comprises a microstrip line and a third semiconductor switch module, and the inductor pair comprises a first inductor and a second inductor, wherein the first end of the microstrip line is connected to the second end of the second inductor, the second end of the microstrip line and the first end of the third semiconductor switch module are connected to the third signal terminal, and the second end of the third semiconductor switch module is grounded; each of the first inductor and the second inductor comprises a microstrip line having a first end and a second end, and the microstrip lines of the first inductor and the second inductor are connected together to form a combined microstrip line having a head end and a tail end, wherein the first end of the microstrip line of the first inductor serves as the head end of the combined microstrip line, the second end of the microstrip line of the second inductor serves as the tail end of the combined microstrip line, and the second end of the microstrip line of the first inductor and the first end of the microstrip line of the second inductor are connected together to serve as the common end of the inductor pair; the combined microstrip line is wound into two spiral patterns in the radio frequency transceiver front-end chip, and when the inductor pair is in an operating state, the directions of the induced magnetic fields caused by the currents in the microstrip lines forming the two spiral patterns are opposite; When the signal link between the first signal terminal and the second signal terminal is conducted, the first semiconductor switch module is turned off, the second semiconductor switch module and the third semiconductor switch module are simultaneously turned on, the first signal terminal and the second signal terminal form a π-type low-pass filter network, signals are transmitted between the first signal terminal and the second signal terminal, the first signal terminal and the second signal terminal are in a conducted state, the first signal terminal and the third signal terminal form a two-stage L-type inductor network, the first signal terminal and the third signal terminal are in an impedance mismatch state, signals form strong reflection between the first signal terminal and the third signal terminal, signal propagation is blocked, and the first signal terminal and the third signal terminal are in an off state. The first inductor and the second inductor are opposite in the current direction of the induced eddy current generated by the substrate, the intersection part in the first inductor is provided by an air bridge, and the intersection part in the second inductor is provided by an air bridge.

2. The high power asymmetric switch of claim 1, wherein, The two spiral patterns are not overlapped and adjacent but at a distance in the direction parallel to the wiring layer of the radio frequency transceiver front-end chip.

3. The high power asymmetric switch of claim 1, wherein, The combined microstrip line is composed of multiple layers of metal materials, and each layer of metal material is located in a different wiring layer of the radio frequency transceiver front-end chip.

4. The high power asymmetric switch of claim 1, wherein, The combined microstrip line is composed of a single layer of metal material, and the single layer of metal material is located in the same or different wiring layers of the radio frequency transceiver front-end chip.

5. The high power asymmetric switch of claim 1, wherein, The spiral directions of the two spiral patterns are opposite.

6. The high power asymmetric switch of claim 1, wherein, One of the two spiral patterns is wound in a clockwise direction by the combined microstrip line from the head end to the common end, and the other of the two spiral patterns is wound in a counterclockwise direction by the combined microstrip line from the tail end to the common end.

7. The high power asymmetric switch according to claim 5 or 6, characterized in that, The winding mode of each of the two spiral patterns is that the combined microstrip line is wound in one of the following modes from the head end or the tail end to the common end: from inside to outside; from outside to inside; a combination of the above two.

8. The high power asymmetric switch of claim 1, wherein, Lead wires are led out from the common end and the head end and the tail end to the two spiral patterns.

9. The high power asymmetric switch of claim 8, wherein, At the intersection of the lead wire and the combined microstrip line, the lead wire crosses the combined microstrip line by an air bridge or the combined microstrip line crosses the lead wire by an air bridge.

10. The high power asymmetric switch of claim 8, wherein, At the intersection of one part and another part of the combined microstrip line, the one part crosses the other part by an air bridge.

11. The high power asymmetric switch of claim 1, wherein, At the intersection of one part and another part of the combined microstrip line, the one part and the other part are arranged in different non-adjacent wiring layers.

12. The high power asymmetric switch of claim 3, wherein, The microstrip line length from the common end to the head end is substantially equal to the microstrip line length from the common end to the tail end.

13. The high power asymmetric switch of claim 3, wherein, The two spiral patterns are mirror images.

14. The high power asymmetric switch of any one of claims 1-6, wherein, The first semiconductor switch module and the second semiconductor switch module each consist of m*n switch tubes, and the m*n switch tubes are arranged in an array, where m and n are positive integers.

15. The high-power asymmetric switch according to any one of claims 1-6, wherein: The first semiconductor switch module includes a first switch tube and a second switch tube, a first end of the first switch tube is connected to a first end of the second switch tube at the second signal end, and a second end of the first switch tube and a second end of the second switch tube are grounded. The second semiconductor switch module includes a third switch tube and a fourth switch tube, a first end of the third switch tube is connected to a first end of the fourth switch tube at the first end of the isolation enhancement module, and a second end of the third switch tube and a second end of the fourth switch tube are grounded.

16. The high power asymmetric switch of claim 15, wherein, The first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are any one of CMOS, Bi-CMOS, and HEMT.

17. The high power asymmetric switch of claim 16, wherein, The third semiconductor switch module includes a fifth switch tube.

18. The high power asymmetric switch of claim 17, wherein, The fifth switch tube is any one of CMOS, Bi-CMOS, and HEMT.

19. An integrated circuit chip, characterized by The high-power asymmetric switch as claimed in any one of claims 1-18, wherein the common terminal, the first branch terminal and the second branch terminal of the inductive pair are connected to other circuit parts of the integrated circuit chip.

20. An integrated circuit chip, characterized by The high-power asymmetric switch as claimed in any one of claims 1-18, wherein the common terminal, the first branch terminal and the second branch terminal of the inductive pair are connected to other circuit parts of the integrated circuit chip, and wherein the first branch terminal and the second branch terminal of the inductive pair are the head terminal and the tail terminal of the merged microstrip line of the inductive pair, respectively.

21. A radio frequency transceiver front-end chip, comprising: The high-power asymmetric switch as claimed in any one of claims 1-18.

22. The radio frequency transceiver front-end chip of claim 21, wherein, The radio frequency transceiver front-end chip further comprises a signal processing terminal, an antenna access terminal, a power amplifier, a low noise amplifier and a low-power switch, wherein: a common terminal of the low-power switch is connected to the signal processing terminal, a first branch terminal of the low-power switch is connected to an input terminal of the power amplifier, and a second branch terminal of the low-power switch is connected to an output terminal of the low noise amplifier; an output terminal of the power amplifier is connected to a second signal terminal of the high-power asymmetric switch, an input terminal of the low noise amplifier is connected to a third signal terminal of the high-power asymmetric switch, and a first signal terminal of the high-power asymmetric switch is connected to the antenna access terminal.

23. An electronic device, comprising: The integrated circuit chip as claimed in claim 20.

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