An anti-interference method, device, equipment and storage medium

Abstract

The application relates to an anti-interference method, device, equipment and storage medium, the method comprises the following steps: acquiring the code length and the coding rate of an LDPC code; if the coding rate is a first preset value, a check matrix is constructed according to the code length and the coding rate, the check matrix comprises a first check matrix and a second check matrix; the to-be-transmitted data is encoded to obtain first encoding output data; the first encoding output data is grouped to obtain first encoding data and second encoding data; the first encoding data and the second encoding data are encoded to obtain second encoding output data and third encoding output data; and the second encoding output data and the third encoding output data are combined to obtain final encoding output data. The application has the technical effect that when there is too much interference in the transmission process of data, errors can still be corrected, and finally the receiving end can receive the original data.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to an anti-interference method, device, equipment and storage medium. BACKGROUND

[0002] With the gradual expansion of the scale of wireless communication and the continuous increase in the number of users, the structure of wireless communication network is becoming more and more complex, and the frequency resource is becoming less and less. Due to the poor channel environment of the wireless communication system, the signal at the receiving end is very weak, the signal-to-noise ratio is extremely low, and it is easy to be interfered from various aspects, which seriously affects the communication quality.

[0003] In the prior art, LDPC code (Low Density Parity Check Code) is usually used for anti-interference. LDPC code is a low-density parity check code, and the error correction capability of the code is very close to the theoretical maximum value (i.e. the Shannon limit). By encoding and decoding the LDPC code, errors occurring in the transmission process of data can be corrected to resist interference.

[0004] However, if the current data is interfered too much due to the poor channel environment during transmission, the error correction by using the LDPC code encoding and decoding technology may not be corrected, and finally the original data cannot be received at the receiving end. SUMMARY

[0005] The present application provides an anti-interference method, device, equipment and storage medium, which can correct errors when there is too much interference in the transmission process of signals, and finally the receiving end can receive the original signal.

[0006] In a first aspect, the present application provides an anti-interference method, which adopts the following technical solution: obtaining the code length and the coding rate of the LDPC code; if the coding rate is a first preset value, constructing a check matrix according to the code length and the coding rate, the check matrix comprising a first check matrix and a second check matrix; encoding the data to be transmitted based on the first check matrix to obtain first encoding output data; grouping the first encoding output data to obtain first encoding data and second encoding data; encoding the first encoding data and the second encoding data based on the second check matrix to obtain second encoding output data and third encoding output data; combining the second encoding output data and the third encoding output data to obtain final encoding output data; and decoding the final encoding output data to obtain the data to be transmitted.

[0007] By adopting the technical scheme, since the LDPC code is a high-efficiency correction code, the first check matrix and the second check matrix are constructed according to the code length and the coding rate of the LDPC code, the first encoding is performed on the to-be-transmitted data by using the first check matrix, and the anti-interference function can be achieved initially; since the data may be disturbed too much in the transmission process, the to-be-transmitted data is encoded again by using the second check matrix, the error code of the disturbed data is split by using the twice encoding, so that the decoding is facilitated, the anti-interference effect is achieved, and when there is too much interference in the transmission process, the error can still be corrected, and finally the original data can be received by the receiving end.

[0008] Optionally, the decoding of the final encoding output data to obtain the to-be-transmitted data comprises: grouping the final encoding output data to obtain third encoding data and fourth encoding data; decoding the third encoding data and the fourth encoding data respectively to obtain third decoding data and fourth decoding data; and merging the third decoding data and the fourth decoding data to obtain final decoding data, wherein the final decoding data is the to-be-transmitted data.

[0009] By adopting the technical scheme, the third encoding data and the fourth encoding data are obtained by grouping the final encoding output data, and when the to-be-transmitted data is decoded after grouping, the complexity of decoding can be reduced, so that the decoding is facilitated, the anti-interference effect is achieved, and when there is too much interference in the transmission process, the error can still be corrected, and finally the original data can be received by the receiving end.

[0010] Optionally, the method further comprises: in response to an exception instruction sent by the receiving end server, inserting zero values into the to-be-transmitted data according to a preset condition, so that the length of the to-be-transmitted data reaches a preset length; constructing a third check matrix according to the code length and the coding rate of the LDPC code; and encoding the to-be-transmitted data of the preset length based on the third check matrix to obtain fourth encoding output data.

[0011] Decoding the fourth encoding output data to obtain the to-be-transmitted data.

[0012] By adopting the technical scheme, when the receiving end server fails to receive the original data sent by the server, an exception instruction can be sent to the server, and when the server receives the exception instruction, the to-be-transmitted data can be inserted with zero values according to preset conditions, and then the to-be-transmitted data is encoded by constructing a third check matrix to obtain fourth encoding output data. As described above, the disturbed error codes can be split by inserting zero values and constructing a third check matrix, so that the disturbed error codes are dispersed, thereby facilitating better decoding and achieving an anti-interference effect. When there is excessive interference in the transmission process of the data, errors can still be corrected, and finally the receiving end can receive the original data.

[0013] Optionally, the decoding of the fourth encoding output data to obtain the to-be-transmitted data comprises: decoding the fourth encoding output data to obtain fourth decoding output data; and removing the zero values in the fourth decoding output data to obtain final output data, wherein the final output data is the to-be-transmitted data.

[0014] By adopting the technical scheme, the inserted zero values are removed during decoding, which can reduce the complexity of decoding, thereby facilitating better decoding and achieving an anti-interference effect. When there is excessive interference in the transmission process of the data, errors can still be corrected, and finally the receiving end can receive the original data.

[0015] Optionally, the method further comprises: obtaining a code length and an encoding rate of the LDPC code; if the encoding rate is a second preset value, grouping the to-be-transmitted data to obtain first block input data and second block input data; encoding the first block input data and the second block input data respectively to obtain first LDPC encoding, second LDPC encoding, third LDPC encoding, fourth LDPC encoding and fifth LDPC encoding; encoding the first LDPC encoding, the second LDPC encoding, the third LDPC encoding, the fourth LDPC encoding and the fifth LDPC encoding respectively to obtain first secondary LDPC encoding, second secondary LDPC encoding, third secondary LDPC encoding, fourth secondary LDPC encoding and fifth secondary LDPC encoding; and decoding the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding respectively to obtain the to-be-transmitted data.

[0016] By adopting the technical scheme, the disturbed error code is split, the continuous error code is dispersed to different positions, and thus the decoding is facilitated, the anti-interference effect is achieved, and when there is too much interference in the data transmission process, the error can still be corrected, and finally the receiving end can receive the original data.

[0017] Optionally, the decoding of the first, second, third, fourth and fifth second-level LDPC codes to obtain the data to be transmitted comprises: decoding the first, second, third, fourth and fifth second-level LDPC codes to obtain LDPC first block decoding, LDPC second block decoding, LDPC third block decoding, LDPC fourth block decoding and LDPC fifth block decoding; combining the LDPC first block decoding, the LDPC second block decoding and the LDPC third block decoding to obtain an LDPC second-level decoding output block 1; combining the LDPC third block decoding, the LDPC fourth block decoding and the LDPC fifth block decoding to obtain an LDPC second-level decoding output block 2; and combining the LDPC second-level decoding output block 1 and the LDPC second-level decoding output block 2 to obtain the final output block data, wherein the final output block data is the data to be transmitted.

[0018] By adopting the technical scheme, the multiple encoding blocks are combined to obtain the final output block data, the complexity of decoding is reduced, the decoding is facilitated, the anti-interference effect is achieved, when there is too much interference in the data transmission process, the error can still be corrected, and finally the receiving end can receive the original data.

[0019] Optionally, if the encoding rate is a first preset value, the check matrix is constructed according to the code length and the encoding rate, the check matrix comprises a first check matrix and a second check matrix, and the construction of the check matrix comprises: obtaining the first check matrix according to the code length and the encoding rate of the LDPC code; obtaining the second check matrix according to the first check matrix and the LDPC encoding rate; and combining the first check matrix and the second check matrix to obtain the check matrix, wherein the check matrix is H=[H a , H b ]; wherein H a is the first check matrix, and H b is the second check matrix.

[0020] By adopting the technical scheme, since the check matrix plays a crucial role in anti-interference, constructing a suitable check matrix facilitates subsequent encoding and decoding, so as to achieve the effect of anti-interference, and ensure that errors can still be corrected when there is excessive interference in the transmission process of data, and finally the receiving end can receive the original data.

[0021] In a second aspect, the present application provides an anti-interference device, which comprises an acquisition module, a construction module, an encoding module, a grouping module, a transmitting module and a decoding module; the acquisition module is configured to acquire a code length and an encoding rate of an LDPC code; the construction module is configured to construct a check matrix according to the code length and the encoding rate if the encoding rate is a first preset value, the check matrix comprising a first check matrix and a second check matrix; the encoding module is configured to encode to-be-transmitted data based on the first check matrix to obtain first encoding output data; the grouping module is configured to group the first encoding output data to obtain first encoding data and second encoding data; the encoding module is further configured to encode the first encoding data and the second encoding data based on the second check matrix to obtain second encoding output data and third encoding output data; the transmitting module is configured to combine the second encoding output data and the third encoding output data to obtain final encoding output data; and the decoding module is configured to decode the final encoding output data to obtain the to-be-transmitted data.

[0022] By adopting the technical scheme, the first check matrix and the second check matrix are constructed based on the code length and the encoding rate of the LDPC code, the to-be-transmitted data is encoded for the first time based on the first check matrix, and the function of anti-interference can be achieved initially; since there may be excessive interference in the transmission process of data, the to-be-transmitted data is encoded again based on the second check matrix, and the error codes that are disturbed can be split and dispersed to different areas through twice encoding, so as to facilitate better decoding and achieve the effect of anti-interference, and ensure that errors can still be corrected when there is excessive interference in the transmission process of data, and finally the receiving end can receive the original data.

[0023] In a third aspect, the present application provides an electronic device, which adopts the following technical scheme: comprising a processor, a memory, a user interface and a network interface, the memory is configured to store instructions, the user interface and the network interface are configured to communicate with other devices, and the processor is configured to execute the instructions stored in the memory to enable the electronic device to execute the computer program of any one of the above anti-interference methods.

[0024] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical scheme: storing a computer program capable of being loaded by a processor and executing any one of the above anti-interference methods.

[0025] To sum up, the present application includes at least one of the following beneficial technical effects:

[0026] 1. The interference error can be split by twice encoding, so as to facilitate better decoding, to achieve the effect of anti-interference, to ensure that the error can be corrected when there is too much interference in the transmission process, and finally the receiving end can receive the original data;

[0027] 2. When the data to be transmitted is grouped and then decoded, the complexity of decoding can be reduced, so as to facilitate better decoding and achieve the effect of anti-interference. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0029] Figure 1 is a flow chart of an anti-interference method provided by an embodiment of the present application;

[0030] Figure 2 is a two-stage LDPC encoding with a coding rate of 1 / 2 provided by an embodiment of the present application;

[0031] Figure 3 is a performance comparison chart of one-stage encoding and two-stage encoding when the 1 / 2 frequency hopping frequency is interfered;

[0032] Figure 4 is a performance comparison chart of one-stage encoding and two-stage encoding when the LDPC encoding rate is 1 / 2 without interference;

[0033] Figure 5 is a flow chart of RATE=1 / 2 LDPC encoding with zero padding;

[0034] Figure 6 is a two-stage LDPC encoding with RATE=2 / 5;

[0035] Figure 7 is a schematic diagram of an anti-interference device provided by an embodiment of the present application;

[0036] Figure 8 is a structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0037] Reference numerals: 1, acquisition module; 2, construction module; 3, encoding module; 4, grouping module; 5, transmitting module; 6, decoding module; 1000, electronic device; 1001, processor; 1002, communication bus; 1003, user interface; 1004, network interface; 1005, memory. DETAILED DESCRIPTION

[0038] In order to enable persons skilled in the art to better understand the technical solutions in the specification, the technical solutions in the specification will be clearly and completely described below in combination with the drawings in the specification. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0039] In the description of the embodiments of the present application, the words such as "exemplary", "for example", or "for instance" are used to mean example, illustration, or description. Any embodiment or design solution described as "exemplary", "for example", or "for instance" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. In fact, the words such as "exemplary", "for example", or "for instance" are intended to present the relevant concept in a specific manner. In addition, unless otherwise specified, the meaning of the term "multiple" is two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for description purposes only, and should not be interpreted as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more features. The terms "include", "contain", "have" and their variants mean "include but are not limited to", unless otherwise specifically emphasized.

[0040] The application scenario of the present application can be applied to the field of unmanned aerial vehicle combat. The server here can be an unmanned aerial vehicle. Each unmanned aerial vehicle can be a transmitting end or a receiving end. Each unmanned aerial vehicle transmits signals to other unmanned aerial vehicles or receives signals transmitted from other unmanned aerial vehicles, thereby realizing signal transmission and reception.

[0041] Before the scheme of the present application is explained, some professional terms are explained.

[0042] LDPC codes: LDPC (Low-Density Parity-Check Code) are a type of block code, an error correction code proposed by Robert Gallager in 1963. LDPC codes are characterized by sparse matrices, high fault tolerance, and simple decoding algorithms, making them widely applicable in high-speed communication and high-error-correction performance applications. LDPC codes employ a sparse matrix approach for encoding and decoding. Their advantages include excellent error correction performance, resistance to channel noise and interference, simple decoding algorithms, and the ability to achieve high speed and reliability in real-time communication.

[0043] The present application will be further described in detail below with reference to the accompanying drawings.

[0044] Figure 1 This is a flowchart of an anti-interference method provided in an embodiment of this application. It should be understood that, although... Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows; unless explicitly stated otherwise, there is no strict order requirement for the execution of these steps, and they can be executed in other orders; and Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0045] This application provides an anti-interference method, such as Figure 1 As shown, the method includes steps S101-S106.

[0046] Step S101: Obtain the code length and encoding rate of the LDPC code.

[0047] In one example, the code length of the LDPC code is determined by the number of columns of the matrix. Generally, the code length of the LDPC code is fixed and can be selected according to actual application requirements. When designing the LDPC code, a suitable code length is usually selected to meet the requirements of the communication system. The coding rate of the LDPC code is determined by the number of rows and columns of the matrix. The coding rate refers to the proportion of effective information in the total codeword length in the LDPC code, and is usually represented by R. The higher the coding rate, the faster the information transmission rate. When designing the LDPC code, a suitable coding rate needs to be selected according to actual application requirements. The coding rate used in the present application is 0.5. It should be noted that, unless otherwise specified, the coding rate of the LDPC code in the present application is always 0.5. For the design of the LDPC code, some LDPC code design software can be used, such as the LDPC code design toolbox in the Communications Toolbox in MATLAB, or open source LDPC code design tools such as GNU Radio, to obtain different coding rates and code lengths by adjusting the number of rows and columns of the matrix. No more details are given here.

[0048] In step S102, if the coding rate is a first preset value, a check matrix is constructed according to the code length and the coding rate, and the check matrix includes a first check matrix and a second check matrix.

[0049] In one example, if the coding rate is a first preset value, a check matrix is constructed according to the code length and the coding rate. The coding rate here can be 0.5, i.e. the first preset value is 0.5. It should be noted that the coding rate includes but is not limited to 0.5. Define the check matrix H = [H a , H b ], H a can be understood as the first check matrix, and H b can be understood as the second check matrix. H a is a matrix of size K*K, where K*K represents the number of rows and columns of the matrix, and the first check matrix is a matrix with equal number of rows and columns; H b is a matrix of size K*(N-K), and since the coding rate is 0.5, N = 2K, and H bThe same is a matrix with equal number of rows and columns. Let u represent an information symbol sequence, which refers to an original binary data sequence that needs to be transmitted in a communication system. In digital communication, the information symbol sequence is usually represented as a binary sequence, where each binary bit represents an information symbol; p represents a parity symbol sequence, which refers to some additional binary symbols added to the information symbol sequence in a communication system for error correction and error detection; c represents a coded codeword sequence, which refers to a series of binary symbol sequences obtained by encoding the information symbol sequence in a communication system, so c = (u, p), then according to the definition of the LDPC code: if the check matrix H is non-singular, then H b is full rank, so c = (u, p).

[0050] Step S103, based on the first check matrix, encoding the data to be transmitted to obtain the first encoding output data; grouping the first encoding output data to obtain the first encoding data and the second encoding data.

[0051] In one example, as Figure 2 shown, Figure 2 is a two-stage LDPC encoding and decoding provided by the embodiment of the application, with a coding rate of 1 / 2. As Figure 2 can be seen, the first-stage encoding input data is encoded by the first check matrix to obtain the LDPC first-stage encoding output, which is the first encoding output data in this case; the first-stage encoding output is grouped to obtain the second-stage LDPC encoding information input 1 and the second-stage LDPC encoding information input 2, where the second-stage LDPC encoding information input 1 is the first encoding data, and the second-stage LDPC encoding information input 2 is the second encoding data.

[0052] Step S104, based on the second check matrix, encoding the first encoding data and the second encoding data to obtain the second encoding output data and the third encoding output data.

[0053] In one example, taking Figure 2 as an example, after obtaining the second-stage LDPC encoding information input 1 and the second-stage LDPC encoding information input 2, the second-stage LDPC encoding information input 1 and the second-stage LDPC encoding information input 2 are encoded by the second check matrix to obtain the LDPC second-stage encoding output 1 and the LDPC second-stage encoding output 2, where the LDPC second-stage encoding output 1 is the second encoding output data; the LDPC second-stage encoding output 2 is the third encoding output data.

[0054] Step S105, combining the second encoding output data and the third encoding output data to obtain the final encoding output data.

[0055] In one example, as shown in Figure 2 , the length of the original data u inputted by two-stage encoding is K, and the length becomes 4K after two-stage encoding. Figure 2 The two-stage decoding in the above embodiment has a performance close to one-stage decoding in one-stage spreading under AWGN, but has a better performance under strong interference. The performance comparison between one-stage decoding and two-stage decoding when RATE=1 / 2 frequency hopping frequency points are interfered is simulated below. The results of two data lengths K=1440 and K=3072 are adopted. 3072 / 6144-2STAGE is K=3072, N=6144, and the number of decoding stages is two stages; 3072 / 61441STAGE is K=3072, N=6144, and the number of decoding stages is one stage. As shown in Figure 3 , Fig. 2 is a performance comparison diagram of one-stage decoding and two-stage decoding when RATE=1 / 2 frequency hopping frequency points are interfered. Figure 3 As can be seen from Figure 3 , the two-stage LDPC decoding can resist the case that 50% of frequency hopping frequency points are interfered. As shown in Figure 4 , Fig. 3 is a performance comparison diagram of one-stage decoding and two-stage decoding when the LDPC decoding rate is 1 / 2 under no interference. When there is no interference, the performance of two-stage decoding is obviously better than that of one-stage decoding. Therefore, the two-stage decoding can be adapted to various environments, and can improve the performance whether there is interference or not. Figure 4

[0056] From the above embodiment, it can be seen that H b is full rank, so there is c=(u, p), and according to H*c T =0, 0=cH T =(u, p)[H a H b ] T =(u, p)[H a T H b T , it is deduced that p=[H b -1 H a ] T ​u; so the first level encoding output c1=(u, p), respectively, u and p again LDPC encoding, the second level output c2=(u, p, p, p2), where p2 is when p as information sequence, relative to p check symbol sequence. The second level encoding is actually re-encoding c, disassembly is u and p respectively encoded to get p and p2. So when c2 through the channel with noise to get c2'=(u', pt1', pt2', p2'), because pt1' and pt2' of the original signal is the same, so as to improve the signal noise performance, using c2'=(u', (pt1'+pt2') / 2, (pt1'+pt2') / 2, p2'), so that in the decoding can better resist noise, through simulation also improved 2dBc performance. Subsequent decoding algorithm generally uses soft decision decoding algorithm mainly includes BP algorithm and its simplified form, LP algorithm, etc. BP algorithm message passing form is log likelihood ratio (LLR), in the iteration process, each time in variable node and check node according to and rule and tanh rule update node information. Until the decoding ends or check equation full meet. BP algorithm is suitable for all kinds of channel, has excellent performance of approaching shannon limit, but the message calculation complexity of check node is very complex.

[0057] Step S106, the final encoding output data decoding, get the data to be transmitted.

[0058] In one example, as Figure 2 shown, the LDPC second level encoding output 1 and LDPC second level encoding output 2 through the channel transmission, here need to explain the information amount of channel transmission is 4K; then through the decoding device decoding, get LDPC first level decoding input 1 and LDPC first level decoding input 2, then again on LDPC first level decoding input 1 and LDPC first level decoding input 2 decoding, get first level decoding output 1 and first level decoding output 2, the first level decoding output 1 and first level decoding output 2 are combined into LDPC second level decoding input, finally output LDPC second level decoding output data, here the whole encoding and decoding work is completed, through the scheme provided by the present application, can guarantee that 50% of the data is still able to correct error when disturbed, restore the original data.

[0059] The final encoding output data decoding, get the data to be transmitted, comprising: the final encoding output data grouping, get the third encoding data and the fourth encoding data; respectively on the third encoding data and the fourth encoding data decoding, get the third decoding data and the fourth decoding data; merge the third decoding data and the fourth decoding data, get the final decoding data, the final decoding data is the data to be transmitted.

[0060] In one example, asFigure 2 As shown, the third encoded data is LDPC first-level decoding input 1, and the fourth encoded data is LDPC first-level decoding input 2; decoding the third encoded data and the fourth encoded data respectively to obtain the third decoded data and the fourth decoded data can be understood as that the third decoded data is the first-level decoding output 1, and the fourth decoded data is the first-level decoding output 2; merging the first-level decoding output 1 and the first-level decoding output 2 to obtain the LDPC second-level decoding input, that is, the final decoded data, which is the to-be-transmitted data.

[0061] The method further includes: in response to the abnormal instruction sent by the receiving end server, inserting a zero value into the to-be-transmitted data according to a preset condition to make the length of the to-be-transmitted data reach a preset length; constructing a third check matrix according to the code length and the encoding rate of the LDPC code; encoding the to-be-transmitted data of the preset length based on the third check matrix to obtain fourth encoded output data; and decoding the fourth encoded output data to obtain the to-be-transmitted data.

[0062] In one example, when the interference is too large, the bit error rate exceeds the range of error correction of the secondary-level decoding and coding, the receiving end server sends an abnormal instruction, the abnormal instruction is an instruction sent by the receiving end when no data or only part of the data is received, and the receiving end is the unmanned aerial vehicle. When the bit error rate exceeds the range of error correction of the secondary-level decoding and coding, the zero value insertion method is used for anti-interference. Figure 5 As shown, Figure 5This is a schematic diagram of the LDPC encoding and decoding process with a rate of 1 / 2, simultaneously filling zero values ​​at intervals. As shown in the diagram, before encoding, a zero (0) bit is added to each isolated bit of data in the information block. Afterward, LDPC-based encoding can be performed on the mixed information and zero-bit block, thereby generating a codeword including a parity block. The parity block is a commonly used verification method for detecting and correcting errors during data transmission. The parity block typically consists of a parity code and a data block. The parity code is a binary bit used to indicate the parity of the number of 1s in all binary bits of the data block (if the number of 1s is even, the parity code is 0; otherwise, it is 1). For example, for an 8-bit data block, if three of its binary bits are 1, the parity code is 1 because 3 is odd. The information block and the zero-bit block can correspond to the information part of the LDPC code, and the parity block can correspond to the parity part of the LDPC code. In information transmission, zero-bit information is also transmitted. This zero-bit information padding and transmission differs from the traditional method of adding zero values ​​to the end of information blocks. This padding information fully intersects with the signal information and is evenly distributed, which is beneficial for the spread of bit error rate and thus more effective in resisting burst errors. Even if half or more of the signal in a sub-block is contaminated by strong interference, the receiver can still correctly decode the correct data due to the large amount of known information. Adding zero values ​​mainly splits continuous errors into individual errors, distributes these individual errors into different data blocks, and then rearranges these data blocks according to certain rules, so that errors that may occur during channel transmission are evenly distributed across the data blocks, thereby increasing the error correction capability of channel coding.

[0063] Decoding the fourth encoded output data to obtain the data to be transmitted includes: decoding the fourth encoded output data to obtain the fourth decoded output data; removing zero values ​​from the fourth decoded output data to obtain the final output data, which is the data to be transmitted.

[0064] In one example, such as Figure 5 As shown, the first decoded output data is the LDPC decoded output. By removing the zero-valued part of the LDPC, the final output data can be obtained. It should be noted that the decoding methods involved in this application all correspond to encoding methods. Different encoding methods correspond to different decoding methods, which will not be elaborated further here.

[0065] The method further comprises: obtaining a code length and a coding rate of the LDPC code; if the coding rate is a second preset value, grouping the data to be transmitted to obtain first block input data and second block input data; encoding the first block input data and the second block input data respectively to obtain first LDPC encoding, second LDPC encoding, third LDPC encoding, fourth LDPC encoding and fifth LDPC encoding; encoding the first LDPC encoding, the second LDPC encoding, the third LDPC encoding, the fourth LDPC encoding and the fifth LDPC encoding respectively to obtain first secondary LDPC encoding, second secondary LDPC encoding, third secondary LDPC encoding, fourth secondary LDPC encoding and fifth secondary LDPC encoding; and decoding the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding respectively to obtain the data to be transmitted.

[0066] In one example, as shown in Figure 6 , Figure 6 is a two-stage LDPC encoding and decoding with RATE = 2 / 5. The present patent can not only be suitable for a coding rate of RATE = 1 / 2, but also be suitable for a coding rate of RATE = 2 / 5 using two-stage encoding and decoding. For details, refer to steps S101-S106. It should be noted that when the LDPC primary encoding block is split, more is not necessarily better. Because the complexity of the LDPC code is high, the decoding difficulty is too high or the decoding is too long. Therefore, when encoding and decoding, the actual situation needs to be considered for splitting, and excessive details will not be described here.

[0067] Decoding the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding respectively to obtain the data to be transmitted comprises: decoding the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding respectively to obtain LDPC first block decoding, LDPC second block decoding, LDPC third block decoding, LDPC fourth block decoding and LDPC fifth block decoding; combining the LDPC first block decoding, the LDPC second block decoding and the LDPC third block decoding to obtain an LDPC second-stage decoding output block 1; combining the LDPC third block decoding, the LDPC fourth block decoding and the LDPC fifth block decoding to obtain an LDPC second-stage decoding output block 2; and combining the LDPC second-stage decoding output block 1 and the LDPC second-stage decoding output block 2 to obtain final output block data, wherein the final output block data is the data to be transmitted.

[0068] In one example, as shown in Figure 6As shown, five LDPC secondary encodings are decoded to obtain five LDPC first-level decodings, the five LDPC first-level decodings are combined to obtain an LDPC second-level decoding output data block, so as to complete the decoding. Generally, when encoding, the data to be transmitted is first encoded once, and then encoded again on the basis of the first encoding; and the decoding process is that the data after the second encoding is first decoded once, and then the decoded data is combined, so that the data required by the final receiving end can be obtained.

[0069] Based on the above method, the application embodiment further discloses an anti-interference device. As shown in Figure 7 Figure 7 is a schematic diagram of an anti-interference device provided by the application embodiment.

[0070] An anti-interference device, the device comprises: an acquisition module 1, a construction module 2, an encoding module 3, a grouping module 4, a transmitting module 5 and a decoding module 6; wherein the acquisition module 1 is used for acquiring the code length and the encoding rate of the LDPC code; the construction module 2 is used for constructing a check matrix according to the code length and the encoding rate if the encoding rate is a first preset value, the check matrix comprising a first check matrix and a second check matrix; the encoding module 3 is used for encoding the data to be transmitted based on the first check matrix to obtain first encoding output data;

[0071] The encoding module 3 is further used for encoding the first encoding data and the second encoding data based on the second check matrix to obtain second encoding output data and third encoding output data; the grouping module 4 is used for grouping the first encoding output data to obtain the first encoding data and the second encoding data; the transmitting module 5 is used for combining the second encoding output data and the third encoding output data to obtain final encoding output data; and the decoding module 6 is used for decoding the final encoding output data to obtain the data to be transmitted.

[0072] It should be noted that: the device provided by the above embodiment only divides the above-mentioned functional modules for example to realize its function, and in actual application, the above-mentioned functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above-described functions. In addition, the device and method embodiments provided by the above embodiments belong to the same concept, and the specific implementation process is described in detail in the method embodiments, which will not be described here.

[0073] In the application embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores instructions, when the instructions are executed, the method in one or more of the above embodiments is executed.

[0074] In the following Figure 8 ​For example, the electronic device structure schematic diagram in the example of the present application is described in detail.

[0075] The present application provides an electronic device structure schematic diagram. As shown in the figure, Figure 8 The electronic device 1000 can include at least one processor 1001, at least one network interface 1004, a user interface 1003, a memory 1005, and at least one communication bus 1002.

[0076] The communication bus 1002 is used to realize the connection and communication between the components.

[0077] The user interface 1003 can include a display screen (Display), a camera (Camera), and can also include a standard wired interface and a wireless interface.

[0078] The network interface 1004 can include a standard wired interface and a wireless interface (such as a WI-FI interface).

[0079] The processor 1001 can include one or more processing cores. The processor 1001 connects various parts of the server through various interfaces and lines, executes various functions of the server and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 1005, and calling data stored in the memory 1005. Optionally, the processor 1001 can be realized in at least one of the hardware forms of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 1001 can be integrated with a combination of one or more of central processing units (Central Processing Unit, CPU), graphics processors (Graphics Processing Unit, GPU), and modems. Among them, the CPU is mainly used to process the operating system, user interface and application programs; the GPU is used to render and draw the content to be displayed on the display screen; and the modem is used to process wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor 1001, but can be realized by a separate chip.

[0080] The memory 1005 can include a random access memory (RAM) and can also include a read-only memory (ROM). Optionally, the memory 1005 includes a non-transitory computer-readable storage medium. The memory 1005 can be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1005 can include a program storage area and a data storage area, where the program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area can store data involved in the various method embodiments described above, etc. The memory 1005 can also be at least one storage device located away from the aforementioned processor 1001. As shown in Figure 8 The memory 1005, as a computer storage medium, can include an operating system, a network communication module, a user interface module, and an application program of an anti-interference method.

[0081] In the electronic device 1000 shown in Figure 8 In the electronic device 1000 shown in

[0082] An electronic device readable storage medium stores instructions. When executed by one or more processors, the electronic device performs the method described in one or more of the above embodiments.

[0083] It should be noted that, for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the described action sequence, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0084] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0085] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the division of the apparatus embodiments is merely illustrative, and the units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0086] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they can be located in one place or distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0087] In addition, the functional units in each embodiment of the present application can be integrated into a processing unit, or each unit can be physically present separately, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0088] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable memory. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a memory and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: a U disk, a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0089] The above is only exemplary embodiments of the present disclosure, which cannot limit the scope of the present disclosure. Any equivalent changes and modifications made in accordance with the teachings of the present disclosure are still within the scope of the present disclosure. Other embodiments of the present disclosure will be readily apparent to those skilled in the art upon considering the specification and practicing the present disclosure. The present application is intended to cover any variations, uses or adaptive changes of the present disclosure that follow the general principles of the present disclosure and include common knowledge or conventional techniques in the art that are not described in the present disclosure. The specification and embodiments are only considered exemplary, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. An anti-jamming method, characterized in that, Applied to a server, the method comprises: acquiring a code length and a coding rate of an LDPC code; if the coding rate is a first preset value, constructing a check matrix according to the code length and the coding rate, the check matrix comprising a first check matrix and a second check matrix; based on the first check matrix, encoding data to be transmitted to obtain first encoding output data, and grouping the first encoding output data to obtain first encoding data and second encoding data; based on the second check matrix, encoding the first encoding data and the second encoding data to obtain second encoding output data and third encoding output data; combining the second encoding output data and the third encoding output data to obtain final encoding output data, and decoding the final encoding output data to obtain data to be transmitted; in response to an exception instruction sent by a receiving end server, inserting zero values into the data to be transmitted according to a preset condition, the preset condition being to add a zero-bit BIT information every other isolated BIT data, so that the length of the data to be transmitted reaches a preset length; constructing a third check matrix according to the code length and the coding rate of the LDPC code; based on the third check matrix, encoding the data to be transmitted of the preset length to obtain fourth encoding output data; decoding the fourth encoding output data to obtain the data to be transmitted; the decoding of the fourth encoding output data to obtain the data to be transmitted comprises decoding the fourth encoding output data to obtain fourth decoding output data; and eliminating the zero values in the fourth decoding output data to obtain final output data, the final output data being the data to be transmitted; If the coding rate is a second preset value, the data to be transmitted is grouped to obtain first block input data and second block input data; the first block input data and the second block input data are encoded respectively to obtain first LDPC encoding, second LDPC encoding, third LDPC encoding, fourth LDPC encoding and fifth LDPC encoding; the first LDPC encoding, the second LDPC encoding, the third LDPC encoding, the fourth LDPC encoding and the fifth LDPC encoding are encoded respectively to obtain first secondary LDPC encoding, second secondary LDPC encoding, third secondary LDPC encoding, fourth secondary LDPC encoding and fifth secondary LDPC encoding; the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding are decoded respectively to obtain the data to be transmitted; the decoding of the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding to obtain the data to be transmitted comprises: decoding the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding to obtain LDPC first block decoding, LDPC second block decoding, LDPC third block decoding, LDPC fourth block decoding and LDPC fifth block decoding; the LDPC first block decoding, the LDPC second block decoding and the LDPC third block decoding are combined to obtain LDPC secondary decoding output block 1; the LDPC third block decoding, the LDPC fourth block decoding and the LDPC fifth block decoding are combined to obtain LDPC secondary decoding output block 2; the LDPC secondary decoding output block 1 and the LDPC secondary decoding output block 2 are combined to obtain final output block data, and the final output block data is the data to be transmitted.

2. The method of claim 1, wherein, The decoding of the final encoding output data to obtain the data to be transmitted comprises: The final encoding output data is grouped to obtain third encoding data and fourth encoding data; The third encoding data and the fourth encoding data are decoded respectively to obtain third decoding data and fourth decoding data; The third decoding data and the fourth decoding data are combined to obtain final decoding data, and the final decoding data is the data to be transmitted.

3. The method of claim 1, wherein, If the coding rate is a first preset value, a check matrix is constructed according to the code length and the coding rate, the check matrix comprises a first check matrix and a second check matrix, and the method comprises: The first check matrix is obtained according to the code length and the coding rate of the LDPC code; The second check matrix is obtained according to the first check matrix and the LDPC coding rate; The first check matrix and the second check matrix are combined to obtain the check matrix, and the check matrix is H=[Ha, Hb]; wherein Ha is the first check matrix, and Hb is the second check matrix.

4. An interference rejection device, characterized by The device comprises an acquisition module (1), a construction module (2), an encoding module (3), a grouping module (4), a transmitting module (5) and a decoding module (6); wherein, The acquisition module (1) is configured to acquire a code length and an encoding rate of an LDPC code; The construction module (2) is configured to, if the encoding rate is a first preset value, construct a check matrix according to the code length and the encoding rate, wherein the check matrix comprises a first check matrix and a second check matrix; The encoding module (3) is configured to encode to-be-transmitted data based on the first check matrix to obtain first encoding output data; The grouping module (4) is configured to group the first encoding output data to obtain first encoding data and second encoding data; The encoding module (3) is further configured to encode the first encoding data and the second encoding data based on the second check matrix to obtain second encoding output data and third encoding output data; The transmitting module (5) is configured to combine the second encoding output data and the third encoding output data to obtain final encoding output data; The decoding module (6) is configured to decode the final encoding output data to obtain to-be-transmitted data, in response to an exception instruction sent by a receiving end server, insert a zero value into the to-be-transmitted data according to a preset condition, wherein the preset condition is to add a zero-bit BIT information every other isolated BIT data, so that the length of the to-be-transmitted data reaches a preset length; construct a third check matrix according to the code length and the encoding rate of the LDPC code; encode the to-be-transmitted data of the preset length based on the third check matrix to obtain fourth encoding output data; decode the fourth encoding output data to obtain the to-be-transmitted data; the decoding of the fourth encoding output data to obtain the to-be-transmitted data comprises decoding the fourth encoding output data to obtain fourth decoding output data; and eliminating the zero value in the fourth decoding output data to obtain final output data, wherein the final output data is the to-be-transmitted data; If the coding rate is a second preset value, the data to be transmitted is grouped to obtain first block input data and second block input data; the first block input data and the second block input data are encoded respectively to obtain first LDPC encoding, second LDPC encoding, third LDPC encoding, fourth LDPC encoding and fifth LDPC encoding; the first LDPC encoding, the second LDPC encoding, the third LDPC encoding, the fourth LDPC encoding and the fifth LDPC encoding are encoded respectively to obtain first secondary LDPC encoding, second secondary LDPC encoding, third secondary LDPC encoding, fourth secondary LDPC encoding and fifth secondary LDPC encoding; the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding are decoded respectively to obtain the data to be transmitted; the decoding of the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding to obtain the data to be transmitted comprises: decoding the first secondary LDPC encoding, the second secondary LDPC encoding, the third secondary LDPC encoding, the fourth secondary LDPC encoding and the fifth secondary LDPC encoding to obtain LDPC first block decoding, LDPC second block decoding, LDPC third block decoding, LDPC fourth block decoding and LDPC fifth block decoding; the LDPC first block decoding, the LDPC second block decoding and the LDPC third block decoding are combined to obtain LDPC secondary decoding output block 1; the LDPC third block decoding, the LDPC fourth block decoding and the LDPC fifth block decoding are combined to obtain LDPC secondary decoding output block 2; the LDPC secondary decoding output block 1 and the LDPC secondary decoding output block 2 are combined to obtain final output block data, and the final output block data is the data to be transmitted.

5. An electronic device, comprising: An electronic device comprising a processor, a memory, a user interface and a network interface, the memory being configured to store instructions, the user interface and the network interface being configured to communicate with other devices, and the processor being configured to execute the instructions stored in the memory to cause the electronic device to perform the method of any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, A computer program stored in a memory and capable of being loaded and executed by a processor to perform the method of any one of claims 1-3.

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