A method for batch fabrication of semiconductor material arm array interface layers
By employing extrusion and organic binder embedding techniques, the fabrication challenges of micro-sized semiconductor material arm arrays have been solved, enabling efficient and low-cost mass production of interface layers, which is suitable for the integrated manufacturing of micro thermoelectric devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CASBOSON TECHNOLOGY (LIYANG) CO LTD
- Filing Date
- 2022-01-28
- Publication Date
- 2026-06-09
AI Technical Summary
Existing technologies struggle to efficiently and cost-effectively fabricate arrays of tiny semiconductor material arms and their interface layers, especially in micro thermoelectric devices. Traditional cutting and picking processes result in low yields, high costs, and uneven interface layer fabrication.
Semiconductor arm arrays were prepared by extrusion and then embedded with organic binders and subsequent processing to achieve the overall embedding of semiconductor arm arrays and the batch preparation of interface layers, including end face planarization and interface layer deposition, and finally the embedding material and attachments were removed.
It enables high-quality, low-cost, and large-scale fabrication of semiconductor material arm arrays, ensuring that the interface layer exists only on the end face without affecting the side face, making it suitable for the integrated fabrication of micro thermoelectric devices.
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Figure CN116568111B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for mass production of interface layers based on semiconductor material arm arrays, belonging to the field of semiconductor materials and devices technology. Background Technology
[0002] Small-sized semiconductor devices have broad application prospects in many fields (such as micro-thermoelectric devices for precise temperature control in micro-region active cooling and self-powering of wearable devices). However, with the miniaturization of semiconductor devices, the fabrication of their core functional components, namely high-density, high-integration n-type and p-type semiconductor material arms and their arrays, faces many difficulties. On the one hand, with the miniaturization of devices, the size of semiconductor material arms has decreased significantly, making their efficient fabrication a major challenge. Traditionally, semiconductor material arms are obtained by cutting semiconductor material blocks. When the material arm size is reduced to the sub-millimeter level, the cutting yield will decrease significantly, while the cutting workload and line loss will increase dramatically, leading to a surge in fabrication difficulty and cost. For brittle thermoelectric semiconductor materials, the cutting process is basically infeasible when the material arm size is less than 0.3 mm. On the other hand, with the miniaturization of devices, it is difficult to efficiently complete the arrangement of material arm arrays using traditional processes. Taking micro-thermoelectric devices as an example, the current common practice is to pick up and transfer the individual n-type and p-type thermoelectric material arms obtained from cutting to a pre-set mold to achieve array arrangement. When the size of thermoelectric arms decreases from the millimeter level to 0.3 mm or even below 0.1 mm, it becomes very difficult and costly to pick up and move hundreds or thousands of thermoelectric arms using traditional methods. At the same time, as the spacing between adjacent thermoelectric arms in the array decreases significantly, the inherent gap between the thermoelectric arms and the pre-set mold will significantly affect the array arrangement accuracy, making it difficult to effectively control the device quality.
[0003] Moreover, existing technologies have several shortcomings in the fabrication of conventional millimeter- or centimeter-scale semiconductor material arm arrays. On one hand, current technologies rely on dicing methods to fabricate semiconductor material arms. Due to the slow dicing speed of a single machine, production capacity is limited, and large-scale production requires the purchase of numerous dicing machines and the deployment of corresponding operators, resulting in high equipment and labor costs. Furthermore, the dicing process causes significant material loss and environmental pollution. On the other hand, existing technologies primarily utilize positioning templates, relying on manual picking and transferring of semiconductor material arms one by one to achieve array arrangement. Therefore, it is difficult to significantly increase production capacity and effectively control product quality.
[0004] Therefore, based on existing technologies, the fabrication of semiconductor material arm arrays is an inefficient, polluting, and labor-intensive process. Existing technologies have many shortcomings in fabricating conventional-sized semiconductor material arm arrays, and are even more difficult in fabricating micro-sized semiconductor material arm arrays. Therefore, developing novel fabrication methods for semiconductor material arm arrays to achieve high-quality, low-cost, and large-scale fabrication is of great value for promoting the development of conventional-sized semiconductor devices and driving the miniaturization of devices.
[0005] Furthermore, in semiconductor devices, the n-type and p-type semiconductor materials, as functional building blocks, need to be connected to the circuit in a certain way to ensure the proper operation of the device. Taking thermoelectric devices as an example, their core functional building blocks are thermoelectric arms, which are usually columnar n-type or p-type semiconductor materials. The n-type and p-type thermoelectric arms are arranged alternately and connected to the metal conductive layers in the upper and lower circuit substrates, forming an overall electrical series and thermal parallel connection. Soldering is typically used to connect the semiconductor material arms to the circuit. To obtain the required interfacial bonding strength and contact performance, the semiconductor material arms must first be metallized, that is, an interface layer must be prepared on the upper and lower end faces of the arms, and then the interface layer and the circuit are connected by solder. Therefore, the preparation of the semiconductor material arm interface layer is a crucial step in the device fabrication process.
[0006] Traditionally, the fabrication of semiconductor material arms is typically based on dicing processes, while the arrangement of the material arm arrays is achieved through pick-and-transfer processes. Taking thermoelectric devices as an example, we can illustrate the negative impact of these processes on the fabrication of the semiconductor material arm interface layer. In the field of thermoelectric devices, the material arms commonly used are in the sub-millimeter to centimeter size range. There are two main methods for fabricating the material arm interface layer: one is to deposit the interface layer on the entire material bulk and then dicing it to obtain material arms with the interface layer; the other is to dicing the material bulk to obtain semiconductor material arms and then batch-depositing the interface layer. The former causes damage and contamination to the interface layer during dicing, while the latter requires clamps to fix the material arms, making it unsuitable for batch fabrication, and it is difficult to avoid metallization on the sides of the material arms during interface layer deposition. In recent years, micro-thermoelectric devices have become a research hotspot due to their broad application prospects in precise micro-area temperature control and self-powering wearable devices. As the size of the material arms decreases, the damage to the interface layer caused by the dicing process becomes more pronounced. At the same time, the number of material arms in micro-thermoelectric devices often reaches hundreds or thousands, with sizes on the micrometer scale. Considering the operational difficulty and cost, traditional processes are not suitable for the batch fabrication of the material arm interface layer. Summary of the Invention
[0007] Therefore, the present invention provides a method for batch fabrication of an interface layer for an arm array of semiconductor materials, comprising:
[0008] (1) Semiconductor material arm arrays were prepared by extrusion method;
[0009] (2) An organic binder is selected as the embedding material and cast into the semiconductor material arm array to achieve the overall embedding of the organic binder. After the embedding material is cured, the end face of the semiconductor material arm array is flattened by physical treatment and / or chemical treatment to obtain a semiconductor material arm array containing the embedding material.
[0010] (3) After depositing an interface layer on the surface of a semiconductor material arm array containing an inlay, the inlay and the interface layer attached to the surface of the inlay are removed, thereby realizing the batch preparation of the interface layer of the semiconductor material arm array.
[0011] For semiconductor materials with a certain degree of plasticity, the inventors first developed a technique for preparing semiconductor material arms and their arrays through an extrusion molding process (extrusion method). Specifically, n-type and p-type materials can be extruded separately using a cavity array mold, and after demolding, an array of n-type and p-type semiconductor material arms connected to the substrate material can be obtained. Compared with existing cutting processes, the extrusion molding process can significantly reduce the difficulty and cost of preparing semiconductor material arms and their arrays. Moreover, since the material arms and their arrays are integrally formed, there is no need for subsequent cumbersome transfer and arrangement of the material arms. This process can not only be used to prepare existing conventional-sized semiconductor arms and their arrays, but is also particularly suitable for preparing micro-semiconductor material arms and their arrays in quantities of hundreds or thousands and in sizes as small as hundreds or even tens of micrometers. However, the following problems still need to be solved to achieve the mass production of the interface layer of the semiconductor material arm array: (1) The end face of the semiconductor material arm needs to meet certain flatness and morphology requirements to ensure reliable bonding between the end face and the interface layer; (2) The height consistency of the semiconductor material arm should meet specific requirements to ensure the parallelism of the upper and lower substrates of the device and avoid interface cold solder joints during device integration; (3) The interface layer should be limited to the end face of the semiconductor material arm and should not affect its side surface. Furthermore, the inventors have creatively achieved the required flatness and morphology of the end face of the material arm and the required consistency of the height of the material arm by performing overall embedding (the embedding material is an organic binder), end face treatment, metallization deposition (interface layer deposition) and de-embedding on the semiconductor material arm array. The interface layer is located only on the end face of the material arm and does not affect its side surface. This method is simple to operate, low in cost, and suitable for the mass production of the interface layer of the semiconductor material arm array.
[0012] Preferably, the extrusion method involves placing a semiconductor block material on the surface of an extrusion die, then sequentially placing the semiconductor block material and the extrusion die into a pressure-resistant sleeve with a matching inner diameter. Extrusion causes the semiconductor block material to undergo plastic deformation, filling the holes arranged in an array on the surface of the extrusion die. After demolding, the semiconductor material arm array is obtained. Preferably, the relative deviation between the diameters of the semiconductor block material and the extrusion die and the inner diameter of the pressure-resistant sleeve is ≤5%, more preferably, the absolute deviation is ≤0.2mm. During extrusion, plastic deformation of the material occurs within the pressure-resistant sleeve. The fact that the diameters of the block material and the extrusion die are comparable to the inner diameter of the pressure-resistant sleeve (relative deviation ≤5% and absolute deviation ≤0.2mm) ensures that the deformation of the block material during extrusion primarily occurs in the pressure direction.
[0013] Preferably, the extrusion die includes: a rigid substrate and an array of holes distributed in the rigid substrate; the rigid substrate is a metal substrate or a ceramic substrate;
[0014] Preferably, the shape of the projection of the hole onto a plane parallel to the surface of the hard substrate is a circle, a rectangle, a triangle, a trapezoid, or a fan, and the shape of the projection onto the plane perpendicular to the surface of the hard substrate is a rectangle or a trapezoid.
[0015] More preferably, when the shape of the projection of the hole in the direction perpendicular to the surface of the hard substrate is trapezoidal, the base angle of the trapezoid is >90° and ≤135°, preferably 92° to 100°.
[0016] Preferably, the semiconductor bulk material is an intrinsically plastic semiconductor material, a plastic composite material prepared from an intrinsically plastic semiconductor material and an intrinsically non-plastic material, or a mud-like mixture based on an intrinsically non-plastic semiconductor material.
[0017] Furthermore, preferably, the composition of the semiconductor bulk material is selected from Ag-based semiconductor materials (Ag2S). x M 1-x M element is Se or Te, 0≤x≤1), Cu-based semiconductor materials (Cu) 2-y Ag y Se 1-z M z , 0≤y≤1, 0≤z≤1, M element is S or Te), Bi-Te based semiconductor materials, mud-like mixtures with Bi-Te based semiconductor materials as the main component.
[0018] Preferably, the embedding material is selected from photoresist (such as SU-8, AZ5214, UVN, etc.), PDMS, AB glue, hot and cold embedding materials (such as phenolic resins from brands such as Aipu, Sanling Metallographic, and Huake), and ethyl cyanoacrylate.
[0019] Preferably, the physical treatment and / or chemical treatment is at least one of mechanical polishing, chemical polishing, etching, and chemical corrosion.
[0020] Preferably, the morphology of the end face of the semiconductor material arm array is controlled after planarization and before deposition of the interface layer; more preferably, the morphology of the end face is controlled by sandblasting, chemical etching or chemical etching to increase the end face roughness.
[0021] Preferably, the interface layer is selected from at least one of Cu, Ni, Al, In, Te, Sb, Bi, Ge, Pb, Ga, Zn, Cd, Pd, Pt, V, Ta, Hf, Fe, Co, Mn, Ru, Rh, Ir, Mo, Nb, W, Ti, Cr, Zr, Sn, Ag, Au, Pt, TiN, doped ZrO2, ThO2, LaCrO2, LaNiO2, LaMnO3(sr), CoCrO4, LaCoO3(sr), InO2 / SnO2, SiC, and MoSi2; the number of layers in the interface layer is ≥1; and the thickness of the interface layer is 10 nm to 20 μm, preferably 1 to 10 μm.
[0022] Preferably, the inlay material and the interface layer attached to the inlay material are removed by at least one of heating, light irradiation, chemical dissolution, and ultrasonic treatment.
[0023] Beneficial effects:
[0024] (1) By embedding the semiconductor material arm array as a whole, the present invention can effectively strengthen the individual material arm and avoid mechanical damage to it in subsequent processing (such as grinding and sandblasting).
[0025] (2) By selecting a suitable insert material, the present invention can easily remove the insert material and the interface layer attached to the insert material after the interface layer on the end face of the semiconductor material arm is prepared, leaving only the interface layer on the end face of the semiconductor material arm.
[0026] (3) This method is low in cost, simple to operate, and suitable for large-scale fabrication. This is because it does not require the preparation of a mask that precisely matches the semiconductor material arm array, and does not involve photolithography processes and related precision equipment. Attached Figure Description
[0027] Figure 1 The Ag2S material arm array obtained by hot extrusion in Example 1;
[0028] Figure 2 (As shown in Example 1) is a material ratio array sample that is integrally inlaid;
[0029] Figure 3 The material arm array sample in Example 1 is a flattened rear end face of the overall inlay. As can be seen from the figure, the material arm is embedded in the inlay material, with only the flattened upper end face exposed.
[0030] Figure 4 The image shows the material arm array in Example 1 after depositing a Cu interface layer and removing the insert material and the Cu interface layer attached to the insert material. As can be seen from the figure, the Cu interface layer only covers the upper end face of the material arm, and the side face of the material arm is not affected.
[0031] Figure 5 The Cu2Se material arm array obtained by hot extrusion in Example 2;
[0032] Figure 6 The image shows a sample of a material arm array after UVN overall inlay back face planarization, sandblasting, metallization, and de-inlay. As can be seen from the image, the metal interface layer only covers the upper end face of the material arm, and the side face of the material arm is not affected. Detailed Implementation
[0033] The present invention will be further illustrated by the following embodiments. It should be understood that the following embodiments are for illustrative purposes only and are not intended to limit the present invention.
[0034] like Figure 1 As shown in this disclosure, the batch preparation process of the semiconductor material arm end face interface layer includes the following main steps: overall embedding of the material arm array, planarization of the material arm end face, end face morphology treatment, preparation of the end face interface layer, and de-embedding. The interface layer can be prepared on the end face of the material arm without affecting the side face of the material arm.
[0035] This disclosure enables high-quality, low-cost, and large-scale fabrication of semiconductor material arm array interface layers, strongly supporting the integrated manufacturing of semiconductor thermoelectric devices. The following exemplarily illustrates the batch fabrication process of semiconductor material arm end-face interface layers.
[0036] Semiconductor arm arrays are prepared by extrusion molding. The preparation process of the semiconductor arm array includes the following main steps: designing and preparing an extrusion die, using an extrusion process to integrally form the n(p)-type semiconductor arm array, and demolding. Using this method, the semiconductor arms and their arrays can be integrally formed, achieving high-quality, low-cost, and large-scale preparation of semiconductor arm arrays.
[0037] A suitable material is selected for preparing the extrusion die. The die material should possess sufficient compressive strength to prevent deformation during repeated heating, cooling, and extrusion processes, which could affect array accuracy. Depending on the extrusion process parameters of different semiconductor materials, the corresponding die material can be steel such as cemented carbide steel, high-speed steel, die steel, or stainless steel; it can also be metallic materials such as W, Mo, Nb, and Ti; ceramic materials such as ZrO2, Al2O3, AlN, and Si3N4; or other inorganic or organic materials with the required compressive strength and processing properties. In a preferred embodiment, the die material is die steel.
[0038] Based on the parameters of the semiconductor material arms and array, a corresponding array of holes is fabricated on the surface of the mold material. Specifically, based on the parameters of the semiconductor material arm array, such as the shape, spacing, and arrangement of the material arms, a corresponding array of holes is fabricated on the surface of the mold material using techniques such as mechanical drilling, laser drilling, or etching. The horizontal projection of the holes in the mold can be circular, rectangular, triangular, trapezoidal, fan-shaped, or other irregular shapes, and the vertical projection can be rectangular, trapezoidal, or other irregular shapes. To facilitate demolding, the inner walls of the holes should be as smooth as possible. The projection of the holes on a plane perpendicular to the mold surface can be rectangular or trapezoidal, with a base angle of 90°–135°, preferably 92°–100°. The size of the projection of the holes on a plane parallel to the surface of the hard substrate can be 1μm–20mm, preferably 1μm–3000μm, more preferably 20μm–500μm, and most preferably 50μm–200μm. The shortest distance between the centers of adjacent holes can be 3μm to 20mm, preferably 50 to 800μm. The depth of the holes can be 1μm to 50mm, preferably 10μm to 3mm. In a preferred embodiment, the hole array is prepared by mechanical drilling, with a bottom diameter of approximately 200μm, a hole depth of approximately 400μm, a projected trapezoidal base angle of approximately 92°, and a center-to-center distance between nearest neighbor holes of approximately 707μm. In another preferred embodiment, the hole array is prepared by laser drilling, with a bottom diameter of approximately 70μm, a hole depth of approximately 200μm, and a projected trapezoidal base angle of approximately 92°.
[0039] An n(p) type semiconductor bulk material is placed on an array of pores in an extrusion die. Extrusion causes the material to undergo plastic deformation and fill all the pores. Appropriate extrusion temperature, pressure, and holding time are set according to the specific properties of the semiconductor material to ensure proper extrusion (complete filling of pores), reduce costs (energy consumption and die wear), and minimize the impact of extrusion on material properties.
[0040] In an optional embodiment, the bulk semiconductor material is Ag-based semiconductor material Ag2S. x M 1-xThe element M is Se or Te, 0≤x≤1, and its extrusion temperature can be 5~170℃, extrusion pressure can be 100MPa~1GPa, and holding time can be 10~60 minutes. In a preferred embodiment, the extrusion temperature of Ag2S material is 20℃, the pressure is 1.5GPa, and the holding time is 10min. In another preferred embodiment, the extrusion temperature of Ag2S material is 80℃, the pressure is 500MPa, and the holding time is 40min.
[0041] In an optional implementation, the bulk semiconductor material may be a Cu-based semiconductor material. 2-y Ag y Se 1-z M z The extrusion temperature can be 180–300℃, the extrusion pressure can be 300 MPa–1.5 GPa, and the holding time can be 10–60 minutes. In a preferred embodiment, the extrusion temperature of Cu2Se material is 250℃, the pressure is 1 GPa, and the holding time is 40 minutes.
[0042] After extrusion, the semiconductor material arms are separated from the extrusion die, resulting in a semiconductor material arm array composed of n(p)-type semiconductor material arms with the same shape as the holes, and the arrangement of the material arms is consistent with the die hole array. For different semiconductor bulk materials, an appropriate demolding temperature needs to be set according to the properties of the semiconductor bulk material during this process. Preferably, the demolding temperature should be slightly higher than the material softening temperature, typically between 10 and 50°C above it. If the temperature is too low, the thermoelectric arms are prone to tensile breakage during demolding, leaving broken thermoelectric arms in the extrusion die holes, rendering the die unusable, and failing to obtain a complete thermoelectric arm array. If the temperature is too high, the material is too soft and easily deformed under tension, or even break.
[0043] In an optional embodiment, the bulk semiconductor material is Ag-based semiconductor material Ag2S. x M 1-x The element M is Se or Te, 0≤x≤1, and the demolding temperature after extrusion can be 10~80℃, preferably 20~40℃.
[0044] In an optional implementation, the bulk semiconductor material may be a Cu-based semiconductor material. 2-y Ag y Se 1-z M z 0≤y≤1, 0≤z≤1, M element is S or Te, and its demolding temperature after extrusion can be 130~220℃, preferably 150~170℃.
[0045] Inserting inserts between semiconductor material arm arrays obtained through extrusion molding integrates the array and the inserts into a single unit. This insert reinforcement protects the semiconductor material arms from mechanical damage during subsequent processing. The inserts can be various photoresists (such as SU-8, AZ5214, UVN, etc.), PDMS, AB adhesive, hot and cold inserts (such as phenolic resins from brands like Aipu, Sanling Metallographic, and Huake), and organic binders such as ethyl cyanoacrylate.
[0046] By appropriately treating the end faces, the height of the material arm can be precisely adjusted, and the desired end face morphology can be obtained, achieving reliable bonding between the material arm and the interface layer. After the inlay material has cured, the end faces of the semiconductor material arms are appropriately treated by methods such as mechanical grinding, chemical polishing, chemical etching, or chemical etching to obtain a flat end face with the required dimensions and perpendicular to the height direction of the material arm, while ensuring the required consistency in the height of each material arm. Preferably, if necessary, the flat end face can be further treated, such as by sandblasting, chemical etching, or chemical etching, to obtain the desired surface morphology, thereby improving the bonding between the interface layer and the end face.
[0047] An interface layer is prepared on the surface of the semiconductor material arm array décor sample after the above treatment. Preparation methods include physical vapor deposition, screen printing, electroplating, and electroless plating. The interface layer can be one or more metals selected from Cu, Ni, Al, In, Te, Sb, Bi, Ge, Pb, Ga, Zn, Cd, Pd, Pt, V, Ta, Hf, Fe, Co, Mn, Ru, Rh, Ir, Mo, Nb, W, Ti, Cr, Zr, Sn, Ag, Au, Pt, etc., or conductive ceramics such as TiN, doped ZrO2, ThO2, LaCrO2, LaNiO2, LaMnO3(sr), CoCrO4, LaCoO3(sr), InO2 / SnO2, SiC, MoSi2, etc. The interface layer can be a single-layer structure or a multi-layer structure. The thickness of the interface layer can be 10 nm to 20 μm, preferably 1 to 10 μm.
[0048] The embedded material is removed by means of heating, light irradiation, chemical dissolution, ultrasonic treatment, or a combination thereof, while the interface layer attached to the embedded material is also removed, resulting in a semiconductor material arm array with the interface layer only attached to the end face of the material arm and the material arm height uniformity meeting the requirements. Because the interface layer is very thin, it collapses during the removal of the embedded material and is removed along with it.
[0049] In optional embodiments, different removal methods can be used for different mounting materials. For example, acetone can be used to remove ethyl cyanoacrylate, certain AB adhesives, and hot / cold mounting materials. Various photoresists can be removed using appropriate developers. Dichloromethane can be used to remove PDMS.
[0050] The semiconductor material arm array with the deposited interface layer can then be bonded to the corresponding circuit using appropriate processes.
[0051] The following examples further illustrate the present invention in detail. It should also be understood that the following examples are only for further explanation of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-essential improvements and adjustments made by those skilled in the art based on the above description of the present invention are within the scope of protection of the present invention. The specific process parameters, etc., in the following examples are merely examples within a suitable range; that is, those skilled in the art can make appropriate selections within the appropriate range based on the description herein, and are not intended to be limited to the specific values in the examples below.
[0052] Example 1
[0053] like Figure 1 As shown, an array of Ag2S material arms was obtained through hot extrusion. The bottom of the material arms is connected to an Ag2S material substrate with uniform thickness. The preparation process of the Ag2S material arm array includes: preparing the required array of holes on the surface of die steel (HRC=60) using mechanical drilling. The bottom hole diameter is approximately 200μm, the hole depth is approximately 500μm, and the projection of the hole onto a plane perpendicular to the die surface is trapezoidal with a base angle of approximately 92°. The Ag2S material is processed into a block with a diameter of 9.9mm and a thickness of 1mm, and placed on the hole array of the extrusion die. The material and the extrusion die are then placed sequentially in a pressure-resistant sleeve with an inner diameter of 10mm. The pressure is increased to 1.5GPa at a rate of 0.2GPa / s at room temperature of 20℃, held for 10min, and then released. Finally, the material is demolded at 20℃.
[0054] Ethyl cyanoacrylate was dropped into the gaps between the semiconductor material arm arrays to fill the gaps, and then cured at room temperature (5℃~35℃) for 12 hours. Figure 2 As shown. The inlaid sample is fixed on the sample stage of the grinding machine, and its surface is ground with an alumina grinding wheel until the end face of the material arm is exposed. Grinding continues downward to remove the non-uniform area at the top of the material arm, resulting in an inlaid array of material arms with consistent end face shape and size, and the height of each material arm also reaches the required consistency, as shown. Figure 3 As shown.
[0055] The sample surface was then sandblasted (Al2O3 particles, 220 mesh, sandblasting pressure 0.05-0.2 MPa), the sandblasted surface was ultrasonically cleaned with alcohol, and after drying, Cu was deposited on the surface by magnetron sputtering (sputtering power 200 W, temperature 100 °C, pressure 0.5 Pa, sputtering time 2 h) to obtain a Cu interface layer with a thickness of about 5 μm.
[0056] The sample with a sputtered Cu layer was immersed in acetone, and the embedding material was dissolved by ultrasonication. Simultaneously, the Cu layer attached to the embedding material was removed, resulting in an Ag2S material arm array with satisfactory arm height, end-face shape, and size, and with the Cu layer only attached to the end faces of the material arms. Figure 4 As shown. Figure 1-4 These are photographs of the products obtained from each step of preparing the Cu interface on the Ag2S material arm array in Example 1.
[0057] Example 2
[0058] like Figure 5 As shown, a Cu2Se material arm array was obtained through hot extrusion. The bottom of the material arms is connected to a Cu2Se material substrate with uniform thickness. The fabrication process of the Cu2Se material arm array includes: preparing the required array of holes on the surface of die steel (HRC=60) using mechanical drilling. The bottom hole diameter is approximately 200 μm, the hole depth is approximately 500 μm, and the projection of the hole onto a plane perpendicular to the die surface is trapezoidal with a base angle of approximately 92°. The Cu2Se material is processed into a block with a diameter of 9.9 mm and a thickness of 1 mm, and placed on the hole array of the extrusion die. The material and the extrusion die are then placed sequentially in a pressure-resistant sleeve with an inner diameter of 10 mm. The pressure is increased to 1 GPa at a rate of 0.2 GPa / s at 250 °C, held for 40 min, and then released. Finally, the material is demolded at 160 °C.
[0059] UVN photoresist was dropwise added between the semiconductor material arm arrays and placed at 95°C until it cured. Then, photoresist was dropped in again and placed at 95°C until it cured again. This process was repeated until the photoresist cured and still covered the top of the Cu2Se material arm.
[0060] The inlaid sample is fixed on the sample stage of the grinding machine, and its surface is ground with an alumina grinding wheel until the end face of the material arm is exposed. Grinding continues downward to remove the non-uniform area at the top of the material arm, resulting in an array of inlaid material arms with consistent end face shape and size, while the height of each material arm also reaches the required consistency.
[0061] The surface of the above sample was then sandblasted (Al2O3 particles, particle size 220 mesh, sandblasting pressure 0.05-0.2MPa), the sandblasted surface was ultrasonically cleaned with alcohol, and after drying, W (sputtering power 100W, temperature 100℃, pressure 0.5Pa, sputtering time 30min) and Cu (sputtering power 200W, temperature 100℃, pressure 0.5Pa, sputtering time 30min) were sequentially deposited on its surface by magnetron sputtering.
[0062] The sample with sputtered W / Cu layers was immersed in UVN developer, and the photoresist was ultrasonically dissolved and cured. Simultaneously, the interface layer attached to the inlay material was removed, resulting in a Cu2Se material arm array with the required arm height, end-face shape, and size, and with the W / Cu layer only attached to the end faces of the material arms. Figure 6 As shown. Figures 5-6 These are photographs of the products obtained in each step of preparing the Cu interface layer on the Cu2Se material arm array in Example 2.
Claims
1. A method for batch fabrication of an interface layer for an arm array of semiconductor materials, characterized in that, include: (1) Semiconductor material arm arrays were prepared by extrusion. (2) An organic binder is selected as the embedding material and cast into the semiconductor material arm array to achieve the overall embedding of the organic binder. After the embedding material is cured, the end face of the semiconductor material arm array is flattened by physical treatment and / or chemical treatment to obtain a semiconductor material arm array containing the embedding material. (3) After depositing an interface layer on the surface of a semiconductor material arm array containing an inlay, the inlay and the interface layer attached to the surface of the inlay are removed, thereby realizing the batch preparation of the interface layer of the semiconductor material arm array. The extrusion method is as follows: a semiconductor block material is placed on the surface of an extrusion mold, and the semiconductor block material is plastically deformed by extrusion to fill the holes arranged in an array on the surface of the extrusion mold. After demolding, the semiconductor material arm array is obtained.
2. The method for mass production of the semiconductor material arm array interface layer according to claim 1, characterized in that, The relative deviation between the diameter of the semiconductor bulk material and the extrusion die and the inner diameter of the pressure-resistant sleeve is ≤5%.
3. The method for batch fabrication of the semiconductor material arm array interface layer according to claim 2, characterized in that, The absolute deviation between the diameter of the semiconductor bulk material and the extrusion die and the inner diameter of the pressure-resistant sleeve is ≤0.2mm.
4. The method for mass production of the semiconductor material arm array interface layer according to claim 1, characterized in that, The extrusion die includes: a rigid substrate and an array of holes distributed in the rigid substrate; the rigid substrate is a metal substrate or a ceramic substrate; The shape of the projection of the hole onto a plane parallel to the surface of the hard substrate is a circle, a rectangle, a triangle, a trapezoid, or a fan shape, and the shape of the projection onto the plane perpendicular to the surface of the hard substrate is a rectangle or a trapezoid.
5. The method for mass production of the semiconductor material arm array interface layer according to claim 4, characterized in that, When the shape of the projection of the hole in the direction perpendicular to the surface of the hard substrate is trapezoidal, the base angle of the trapezoid is >90° and ≤135°.
6. The method for mass production of the semiconductor material arm array interface layer according to claim 5, characterized in that, When the shape of the projection of the hole in the direction perpendicular to the surface of the hard substrate is trapezoidal, the base angle of the trapezoid is 92° to 100°.
7. The method for mass production of the semiconductor material arm array interface layer according to claim 1, characterized in that, The semiconductor bulk material is an intrinsically plastic semiconductor material, a plastic composite material prepared from an intrinsically plastic semiconductor material and an intrinsically non-plastic material, or a mud-like mixture based on an intrinsically non-plastic semiconductor material.
8. The method for batch fabrication of the semiconductor material arm array interface layer according to claim 7, characterized in that, The composition of the semiconductor bulk material is selected from Ag-based semiconductor materials, Cu-based semiconductor materials, and Bi-Te-based semiconductor materials; the Ag-based semiconductor material is Ag₂S. x M 1-x The element M is Se or Te, 0 ≤ x ≤ 1; the Cu-based semiconductor material is Cu. 2-y Ag y Se 1- z M z , 0≤y≤1, 0≤z≤1, M element is S or Te.
9. A method for batch fabrication of the semiconductor material arm array interface layer according to any one of claims 1-8, characterized in that, The insert is selected from one of photoresist, PDMS, AB adhesive, hot and cold inserts, and ethyl cyanoacrylate.
10. A method for mass production of the semiconductor material arm array interface layer according to any one of claims 1-8, characterized in that, The physical treatment and / or chemical treatment is at least one of mechanical polishing, chemical grinding, chemical etching, and chemical corrosion.
11. A method for mass production of the semiconductor material arm array interface layer according to any one of claims 1-8, characterized in that, Morphology control of the end face of the semiconductor material arm array after planarization and before deposition of the interface layer.
12. The method for mass production of the semiconductor material arm array interface layer according to claim 11, characterized in that, Sandblasting, chemical etching, or chemical etching are used to control the morphology of the end face in order to increase the surface roughness.
13. A method for mass production of the semiconductor material arm array interface layer according to any one of claims 1-8, characterized in that, The interface layer is selected from at least one of Cu, Ni, Al, In, Te, Sb, Bi, Ge, Pb, Ga, Zn, Cd, Pd, Pt, V, Ta, Hf, Fe, Co, Mn, Ru, Rh, Ir, Mo, Nb, W, Ti, Cr, Zr, Sn, Ag, Au, Pt, TiN, doped ZrO2, ThO2, LaCrO2, LaNiO2, LaMnO3(Sr), CoCrO4, LaCoO3(Sr), InO2 / SnO2, SiC, and MoSi2; the number of interface layers is ≥1; and the thickness of the interface layer is 10 nm to 20 μm.
14. The method for mass production of the semiconductor material arm array interface layer according to claim 13, characterized in that, The thickness of the interface layer is 1–10 μm.
15. A method for batch fabrication of the semiconductor material arm array interface layer according to any one of claims 1-8, characterized in that, The inlay material and the interface layer attached to the inlay material are removed by at least one of the following methods: heating, light exposure, chemical dissolution, and ultrasonic treatment.