Link reconstruction method and device

Abstract

The present application provides a link reconstruction method and device, which can solve the problem that when data reading and writing fail and the data link is abnormal, it takes a long time to re-establish the link, thereby avoiding data reading / writing jams. The link reconstruction method includes: when the adjustment of the first data transmission link between the main chip and the flash memory fails, the main chip receives a second level signal from the flash memory that is longer than the duration of the first level signal, and the second level signal is used to indicate that the first data transmission link is abnormal. After receiving the second level signal, the main chip immediately sends a link establishment command to the flash memory to establish a second data transmission link.

Description

Technical Field

[0001] The present application relates to the field of data reading and writing, and in particular to a link reconstruction method and device. Background Art

[0002] The electronic device may include a main chip and a flash memory. The main chip may be configured to receive data from an application program (such as ) to initiate data read and write operations to the flash memory, such as completing the read and write operations through the data transmission link between the main chip and the flash memory. However, environmental factors such as excessive temperature or voltage of the main chip or flash memory may cause the data transmission link to be abnormal, thereby causing the read and write operations to fail. Therefore, when the data transmission link is abnormal, the data transmission link needs to be restored as soon as possible to ensure that the read and write operations proceed normally.

[0003] At present, the main chip can adjust the working parameters of the data transmission link between the main chip and the flash memory according to the level signal from the flash memory. If the data transmission link is still abnormal, the main chip can also rebuild the data transmission link. Specifically, the main chip sends a read and write request to the flash memory. If the main chip does not receive a read and write response from the flash memory within a long period of time (such as 3 seconds, 5 seconds), the main chip can execute the data transmission link reconstruction process. However, since the reconstruction process of the data transmission link is time-consuming, it will cause data reading / writing jams, resulting in a poor user experience. Summary of the invention

[0004] The embodiments of the present application provide a link reconstruction method and device, which can solve the problem that when data reading and writing fail, the main chip takes a long time from issuing a data read / write request to re-establishing the link, thereby avoiding data reading / writing jams and improving user experience.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, the present application provides a link reconstruction method, which is applied to a flash memory of an electronic device, and the electronic device also includes a main chip. The method includes: when the flash memory detects that the first data transmission link is in an abnormal state, the flash memory adjusts a first parameter. Wherein, the first parameter is a working parameter of the flash memory for transmitting data in the first data transmission link, and the first data transmission link is a communication link between the flash memory and the main chip. The flash memory sends a first level signal to the main chip, and the first level signal is used to request the main chip to restore the first data transmission link. If the flash memory detects that the first data transmission link fails to recover, it sends a second level signal to the main chip. Wherein, the duration of the second level signal is greater than the duration of the first level signal. The flash memory receives a link establishment command from the main chip. The flash memory establishes a second data transmission link according to the link establishment command.

[0007] Based on the link reconstruction method provided in the first aspect, when the first data transmission link between the main chip and the flash memory fails to be adjusted, the main chip receives a second level signal from the flash memory that is greater than the duration of the first level signal, and the second level signal is used to indicate that the first data transmission link is abnormal. After receiving the second level signal, the main chip immediately sends a link establishment command to the flash memory to establish a second data transmission link without waiting for a longer time, which can greatly reduce the time required to rebuild the link when an abnormality occurs in the data link, so as to avoid data reading / writing jams, thereby improving the user experience. In addition, the second level signal of the flash memory requesting the main chip 101 to rebuild the second data transmission link is a stable signal (no jump), and even if the first data transmission link is abnormal, the main chip can accurately detect the second level signal, and the reliability is high.

[0008] In a possible design, the difference between the duration of the second level signal and the duration of the first level signal may be greater than or equal to the first threshold. Since the difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to the first threshold, the main chip can accurately distinguish the first level signal from the second level signal, so that the first data transmission link can be restored according to the first level signal, and the second data transmission link can be re-established according to the second level signal.

[0009] Furthermore, the duration of the second level signal may be greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal, so as to distinguish the first level signal from the second level signal.

[0010] In a possible design scheme, before the flash memory adjusts the first parameter, the method described in the first aspect may also include: when the first data transmission link is in a normal state, the flash memory sends the duration of the second level signal and the duration of the first level signal to the main chip. Thus, when the main chip subsequently detects the level signal, it can compare the duration of the detected level signal with the first threshold and the second threshold to determine whether the detected level signal is the first level signal or the second level signal, so that the first data transmission link can be restored according to the first level signal, and the second data transmission link can be reestablished according to the second level signal.

[0011] Furthermore, before the flash memory sends the duration of the second level signal and the duration of the first level signal to the master chip, the method described in the first aspect may further include: the flash memory receives a data read request from the master chip.

[0012] In a possible design, the flash memory sends a first level signal and a second high level signal based on the same differential line. The differential line may be a signal line connecting the flash memory and the main chip. Since the first level signal and the second high level signal are transmitted based on the same differential line, no additional hardware design is required to save costs.

[0013] In a second aspect, the present application also provides another link reconstruction method, which is applied to a main chip of an electronic device, and the electronic device also includes a flash memory. The method includes: the main chip receives a first level signal output by the flash memory, and the first level signal is used to request the main chip to restore the first data transmission link. The main chip restores the first data transmission link in an abnormal state, wherein the first data transmission link is a communication link between the flash memory and the main chip. If the first data transmission link fails to recover, the main chip receives a second high level signal transmitted by the flash memory. The duration of the second high level signal is greater than a set threshold, and the set threshold is greater than or equal to the duration of the first level signal. A second data transmission link is established according to the second level signal. Establishing the second data transmission link includes sending a link establishment command to the flash memory.

[0014] In a possible design solution, a difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

[0015] Further, the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

[0016] In a possible design scheme, before the main chip receives the first level signal output by the flash memory, the method provided in the second aspect may also include: when the first data transmission link is in a normal state, the main chip receives the duration of the second level signal sent by the flash memory and the duration of the first level signal.

[0017] Furthermore, before the main chip receives the duration of the second level signal and the duration of the first level signal sent by the flash memory, the method provided in the second aspect may further include: the main chip sends a data read request to the flash memory.

[0018] In a possible design solution, the main chip receives the first level signal and the second high level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.

[0019] In a third aspect, the present application also provides a link reconstruction device, which is applied to a flash memory of an electronic device, and the electronic device also includes a main chip. The device includes a processing unit and a transceiver unit. Among them, the processing unit is used to adjust the first parameter when it detects that the first data transmission link is in an abnormal state. Among them, the first parameter is the working parameter of the flash memory transmitting data in the first data transmission link, and the first data transmission link is the communication link between the flash memory and the main chip. The transceiver unit is used to send a first level signal to the main chip, and the first level signal is used to request the main chip to restore the first data transmission link. The processing unit is also used to control the sending unit to send a second level signal to the main chip if it is detected that the recovery of the first data transmission link fails, wherein the duration of the second level signal is greater than the duration of the first level signal. The transceiver unit is also used to receive a link establishment command from the main chip. The processing unit is also used to establish a second data transmission link according to the link establishment command.

[0020] In a possible design solution, a difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

[0021] In a possible design solution, the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

[0022] In a possible design scheme, the transceiver unit may also be configured to send the duration of the second level signal and the duration of the first level signal to the main chip when the first data transmission link is in a normal state.

[0023] The transceiver unit can also be used to receive data read requests from the main chip.

[0024] In a possible design, the transceiver unit may also be used to send a first level signal and a second high level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.

[0025] Optionally, the transceiver unit and the processing unit provided in the third aspect may be integrated into one module, such as a processing module, or may be separately and independently provided. For example, the transceiver unit includes a receiving module and a sending module. The sending module is used to perform the sending function of the link reconstruction device described in the third aspect, and the receiving module is used to perform the receiving function of the link reconstruction device described in the third aspect.

[0026] Optionally, the device provided in the third aspect may further include a storage module. The storage module stores a program or instruction. When the processing module executes the program or instruction, the device can execute the link reconstruction method provided in the third aspect.

[0027] It should be noted that the link reconstruction device described in the third aspect can be a terminal device or a network device, or it can be a chip (system) or other parts or components that can be set in the terminal device or the network device, or it can be a device that includes a terminal device or a network device, and this application does not limit this.

[0028] In a fourth aspect, the present application also provides a link reconstruction device, which is applied to a main chip of an electronic device, and the electronic device also includes a flash memory. The device includes a transceiver unit and a processing unit. Among them, the transceiver unit is used to receive a first level signal output by the flash memory, and the first level signal is used to request the main chip to restore the first data transmission link. The processing unit is used to restore the first data transmission link in an abnormal state. Among them, the first data transmission link is a communication link between the flash memory and the main chip. The transceiver unit is also used to receive a second high level signal transmitted by the flash memory if the first data transmission link fails to recover. Among them, the duration of the second high level signal is greater than a set threshold, and the set threshold is greater than or equal to the duration of the first level signal. The processing unit is also used to establish a second data transmission link according to the second level signal. Among them, establishing the second data transmission link includes sending a link establishment command to the flash memory.

[0029] In a possible design solution, a difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

[0030] In a possible design solution, the duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

[0031] In a possible design scheme, the transceiver unit may also be configured to receive the duration of the second level signal and the duration of the first level signal sent by the flash memory when the first data transmission link is in a normal state.

[0032] Furthermore, the transceiver unit can also be used for the main chip to send a data read request to the flash memory.

[0033] In a possible design solution, the transceiver unit can also be used to receive the first level signal and the second high level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.

[0034] Optionally, the transceiver unit and the processing unit provided in the fourth aspect may be integrated into one module, such as a processing module, or may be separately and independently provided. For example, the transceiver unit may include a receiving module and a sending module. The sending module is used to perform the sending function of the link reconstruction device described in the fourth aspect, and the receiving module is used to perform the receiving function of the link reconstruction device described in the fourth aspect.

[0035] Optionally, the device provided in the fourth aspect may further include a storage module. The storage module stores a program or instruction. When the processing module executes the program or instruction, the device can execute the link reconstruction method provided in the fourth aspect.

[0036] It should be noted that the link reconstruction device described in the fourth aspect can be a terminal device or a network device, or it can be a chip (system) or other parts or components that can be set in the terminal device or the network device, or it can be a device that includes a terminal device or a network device, and this application does not limit this.

[0037] In a fifth aspect, the present application also provides an electronic device, including a flash memory and a main chip, wherein the flash memory is communicatively connected to the main chip, wherein the flash memory is used to execute the link reconstruction method provided in the first aspect above, and the main chip is used to execute the link reconstruction method provided in the second aspect above.

[0038] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer executes a link reconstruction method as described in the first aspect or the second aspect of the embodiment of the present application.

[0039] In the seventh aspect, an embodiment of the present application provides a computer program product, which includes: a computer program or instructions, which, when the computer program or instructions are run on a computer, enable the computer to execute the link reconstruction method of the first aspect or the second aspect of the embodiment of the present application.

[0040] It can be understood that the link reconstruction method provided by the second aspect, the link reconstruction device provided by the third aspect, the link reconstruction device provided by the fourth aspect, the electronic device provided by the fifth aspect, the computer-readable storage medium provided by the sixth aspect, and the computer program product provided by the seventh aspect are all the same as or corresponding to the technical features of the link reconstruction method provided by the first aspect. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the method provided by the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the hardware structure of a mobile phone provided in an embodiment of the present application;

[0042] Figure 2 An interactive flow chart of a link reestablishment method provided in an embodiment of the present application;

[0043] Figure 3 An interactive flow chart of a flash memory provided in an embodiment of the present application determining that a first data transmission link is in an abnormal state;

[0044] Figure 4A block diagram of the connection between the main chip and the flash memory provided in the embodiment of the present application;

[0045] Figure 5 An interactive flow chart for restoring a first data transmission link provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the software structure of a link reconstruction device provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of the structural composition of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The following is an introduction to the technical terms involved in the embodiments of the present application.

[0049] Universal flash storage: Universal flash storage (UFS) is a memory based on serial data transmission technology that allows multiple erasing and writing during operation. Although there are only two data channels between the internal storage unit and the main chip, the actual data transmission rate is high. UFS supports full-duplex mode, all data channels can perform read and write operations at the same time, and the response speed of data reading and writing is also very high.

[0050] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0051] A link reconstruction method provided in an embodiment of the present application can be applied to an electronic device, which may be a mobile phone, a tablet computer, a laptop computer, an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, a personal digital assistant (PDA), a wearable electronic device, a virtual reality device, etc. The embodiment of the present application does not impose any limitation on this.

[0052] Figure 1 The hardware structure diagram of the mobile phone 100 provided in the embodiment of the present application is shown in FIG. Figure 1 As shown, the electronic device in the embodiment of the present application may be a mobile phone 100. The embodiment is described in detail below by taking the mobile phone 100 as an example. It should be understood that the mobile phone 100 shown in the figure is only an example of the above-mentioned electronic device, and the mobile phone 100 may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations.

[0053] like Figure 1As shown, the mobile phone 100 includes a main chip 101, an internal memory 121, an external memory interface 122, an antenna A, a mobile communication module 131, an antenna B, a wireless communication module 132, an audio module 140, a speaker 140A, a receiver 140B, a microphone 140C, an earphone interface 140D, a display screen 151, a subscriber identification module (SIM) card interface 152, a camera 153, a button 154, a sensor module 160, a universal serial bus (USB) interface 170, a charging management module 180, a power management module 181 and a battery 182. In other embodiments, the mobile phone 100 may also include a motor, an indicator, etc.

[0054] Among them, the main chip 101 may include one or more processing units. For example, the main chip 101 may include an application processor (AP), a modem, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. It should be noted that different processing units can be independent devices, or they can be integrated into one or more independent processors, and can be integrated into the same device with other modules in the mobile phone 100. Taking the modem as an example, the modem can be a processing unit independent of the main chip 101, or it can be integrated into the same device with other processing units (such as AP, ISP, GPU, etc.), and some or all functions can also be integrated into the same device with the mobile communication module 131.

[0055] The internal memory 121 can be used to store data and / or at least one computer program, and the at least one computer program includes instructions. Specifically, the internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area can store at least one computer program. Computer programs may include applications (such as gallery, contacts, etc.), operating systems (such as Android operating system, or IOS operating system, etc.), or other programs. The data storage area can store at least one of the data created during the use of the mobile phone 100, the data received from other devices (such as other mobile phones 100, network devices, servers, etc.), or the data pre-stored before leaving the factory. For example, the data stored in the internal memory 121 can be at least one of information such as images, files, or logos.

[0056] In some embodiments, the internal memory 121 may include a high-speed random access memory and / or a non-volatile memory. For example, the internal memory 121 includes one or more disk storage devices, flash memory, or universal flash storage (UFS).

[0057] The main chip 101 can call one or more computer programs and / or data stored in the internal memory 121, so that the mobile phone 100 can implement one or more functions to meet the needs of the user. For example, the main chip 101 can call the instructions and data stored in the internal memory 121 to enable the electronic device to perform the link reconstruction method provided in the embodiment of the present application.

[0058] The external memory interface 122 can be used to connect an external memory card (e.g., a micro SD card) to expand the storage capacity of the mobile phone 100. The external memory card communicates with the main chip 101 through the external memory interface 122 to implement a data storage function. For example, files such as images, music, and videos are stored in the external memory card.

[0059] In some embodiments, a cache area may be further provided in the master chip 101 to store instructions and / or data that the master chip 101 needs to use cyclically. If the master chip 101 needs to use the instruction or data again, it may be directly called from the cache area. This helps avoid repeated accesses, reduces the waiting time of the master chip 101, and thus helps improve the efficiency of the system. For example, the cache area may be implemented by a high-speed cache memory.

[0060] Antenna A and antenna B are used to transmit and receive electromagnetic wave signals. Each antenna in the mobile phone 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of the antennas. For example, antenna A can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0061] The mobile communication module 131 can be used to realize the communication between the mobile phone 100 and the network device according to the mobile communication technology (such as 2G, 3G, 4G or 5G, etc.) supported by the mobile phone 100. For example, the mobile communication technology supported by the mobile phone 100 may include at least one of GSM, GPRS, CDMA, WCDMA, TD-SCDMA, LTE, or NR, etc. For example, the mobile phone 100 supports GSM. After the mobile phone 100 accesses the network through the cell provided by the BTS in the GSM communication system, the mobile phone 100 can communicate with the BTS through the mobile communication module 131 when the network signal strength of the accessed cell is not less than the decision threshold, that is, when the mobile phone 100 is in the state of being stationed on the network. For example, the mobile communication module 131 can amplify the signal modulated by the modem and send it to the network device via the antenna A; the mobile communication module 131 can also receive the signal sent by the network device through the antenna A, amplify it, and then send it to the modem, and the modem demodulates the received signal into a low-frequency baseband signal, and then performs other corresponding processing. In some embodiments, the mobile communication module 131 may include a filter, a switch, a power amplifier, a low noise amplifier (LNA), and the like.

[0062] The wireless communication module 132 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) network), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication technology (NFC), infrared technology (IR), etc., which are applied to the mobile phone 100. The GNSS may include at least one of the global positioning system (GPS), the global navigation satellite system (GLONASS), the Beidou navigation satellite system (BDS), the quasi-zenith satellite system (QZSS) and / or the satellite based augmentation system (SBAS). For example, the wireless communication module 132 can be one or more devices integrating at least one communication processing module. The wireless communication module 132 can communicate with the corresponding device through the antenna B according to the wireless communication technology supported by itself (such as Wi-Fi, Bluetooth, FM or NFC, etc.).

[0063] The mobile phone 100 can implement audio functions such as music playing and recording through the audio module 140, the speaker 140A, the receiver 140B, the microphone 140C, the earphone interface 140D and the AP.

[0064] The mobile phone 100 can realize the display function through the GPU, the display screen 151, and the AP. The display screen 151 can be used to display images, videos, etc. The display screen 151 may include a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the mobile phone 100 may include 1 or N display screens 151, where N is a positive integer greater than 1.

[0065] The key 154 may include a power key, a volume key, etc. The key 154 may be a mechanical key, or a virtual button or a virtual option, etc. The mobile phone 100 may receive key inputs and generate key signal inputs related to user settings and function control of the mobile phone 100. For example, in response to selecting a virtual option for indicating consent to participate in the "User Experience Improvement Program", the mobile phone 100 may count or collect some information about the user's use of the mobile phone 100, so as to provide the user with more personalized services, thereby improving the user experience.

[0066] The sensor module 160 may include one or more sensors. For example, the sensor module 160 includes an acceleration sensor 160A, a touch sensor 160B, a fingerprint sensor 160C, etc. In some embodiments, the sensor module 160 may also include a pressure sensor, a gyroscope sensor, an environmental sensor, a distance sensor, a proximity light sensor, a bone conduction sensor, etc.

[0067] The acceleration sensor (ACC sensor) 160A can collect the magnitude of the acceleration of the mobile phone 100 in all directions (generally three axes). When the mobile phone 100 is stationary, the magnitude and direction of gravity can be detected. In addition, the acceleration sensor 160A can also be used to identify the posture of the mobile phone 100, and is applied to applications such as horizontal and vertical screen switching and pedometers. In some embodiments, the acceleration sensor 160A can be connected to the main chip 101 through a micro controller unit (MCU), thereby helping to save power consumption of the mobile phone 100. For example, the acceleration sensor 160A can be connected to an AP and a modem through an MCU. In some embodiments, the MCU can be a universal intelligent sensor hub.

[0068] The touch sensor 160B may also be referred to as a "touch panel". The touch sensor 160B may be disposed on the display screen 151, and the touch sensor 160B and the display screen 151 form a touch screen, also referred to as a "touch screen". The touch sensor 160B is used to detect touch operations acting on or near it. The touch sensor 160B may transmit the detected touch operation to the AP to determine the type of touch event. Then, the mobile phone 100 provides visual output related to the touch operation through the display screen 151 according to the determined type of touch event. In other embodiments, the touch sensor 160B may also be disposed on the surface of the mobile phone 100, at a position different from that of the display screen 151.

[0069] The fingerprint sensor 160C is used to collect fingerprints. The mobile phone 100 can use the collected fingerprint characteristics to realize fingerprint unlocking, access application locks, fingerprint photography, fingerprint answering calls, etc.

[0070] In other embodiments, the main chip 101 may also include one or more interfaces. For example, the interface may be a SIM card interface 152. For another example, the interface may also be a USB interface 170. For another example, the interface may also be an inter-integrated circuit (12C) interface, an inter-integrated circuit sound (12S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, etc. It is understandable that the main chip 101 provided in the embodiment of the present application can be connected to different modules of the mobile phone 100 through an interface, so that the mobile phone 100 can realize different functions. For example, sending and receiving information, etc. It should be noted that the embodiment of the present application does not limit the connection method of the interface in the mobile phone 100.

[0071] The SIM card interface 152 is used to connect a SIM card. The SIM card can be connected to and separated from the mobile phone 100 by inserting it into the SIM card interface 152 or pulling it out from the SIM card interface 152. The mobile phone 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 152 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 152 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 152 can also be compatible with different types of SIM cards. In some embodiments, the SIM card interface 152 can also be compatible with external memory cards. The mobile phone 100 uses a SIM card to implement functions such as calls and data communications. In some embodiments, the mobile phone 100 can also use an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the mobile phone 100 and cannot be separated from the mobile phone 100.

[0072] The USB interface 170 is an interface that complies with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 170 can be used to connect a charger to charge the mobile phone 100, and can also be used to transfer data between the mobile phone 100 and peripheral devices. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.

[0073] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration and does not constitute a structural limitation on the mobile phone 100. In other embodiments of the present application, the mobile phone 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0074] The charging management module 180 is used to receive charging input from a charger. The charger can be a wireless charger or a wired charger. The power management module 181 is used to connect the battery 182, the charging management module 180 and the main chip 101. The power management module 181 receives input from the battery 182 and / or the charging management module 180 to power the main chip 101 and other modules. In some embodiments, the power management module 181 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc.

[0075] It should be understood that Figure 1 The structure of the mobile phone 100 shown is only an example. The mobile phone 100 of the embodiment of the present application may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. The various components shown in the figure may be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application specific integrated circuits.

[0076] For example, Figure 2 The flowchart of the link reconstruction method provided in the embodiment of the present application is shown in FIG. The link reconstruction method can be applied to the flash memory 103 and the main chip 101 in the mobile phone 100. The method includes:

[0077] S201 , the master chip 101 sends a data read / write request to the flash memory 103 , and the flash memory 103 receives the data read / write request from the master chip 101 .

[0078] Exemplarily, the main chip 101 may include a software layer and a physical layer. The software layer may include at least one application program of e-mail, instant messaging application, shopping application, game application, etc., which is not limited here. Specifically, the user can open the instant messaging application through the main page of the mobile phone 100. If the instant messaging application receives a picture message, the software layer of the main chip 101 can write the picture information into the double data rate synchronous dynamic random access memory (DDR), and notify the physical layer of the main chip 101 to send a data write request to the flash memory 103, and the data write request is used to indicate the writing of the picture information. The flash memory 103 receives the data write request from the physical layer of the main chip 101.

[0079] It should be noted that the picture information is only an example, and the data read / written between the main chip 101 and the flash memory 103 may also be other types of data, such as video information, text information, etc., and the embodiments of the present application do not specifically limit this.

[0080] S202: The flash memory 103 detects that the first data transmission link is abnormal.

[0081] The first data transmission link may be a communication link between the flash memory 103 and the main chip 101. The first data transmission link includes a first transmission channel and a second transmission channel, wherein the first transmission channel is a transmission channel for the flash memory 103 to send data to the main chip 101, and the second transmission channel is a transmission channel for the main chip 101 to send data to the flash memory 103.

[0082] Exemplarily, the first data transmission link abnormality means that: the first transmission channel cannot complete data transmission and / or the second transmission channel cannot complete data transmission, or the data transmission rate of the first transmission channel and / or the second transmission channel cannot meet business requirements.

[0083] Specifically, after receiving the data write request, the flash memory 103 may detect whether the first data transmission link is abnormal. Figure 3 The interactive flow chart of the flash memory provided in the embodiment of the present application determining that the first data transmission link is in an abnormal state. For example, please refer to Figure 3 , the main chip 101 sends a data read request to the flash memory 103, and the flash memory 103 feeds back a confirmation packet of receiving the data read request to the main chip, and then the flash memory 103 sends a data packet to the main chip 101. If the flash memory 103 does not receive a confirmation packet of receiving the data packet from the main chip 101, the flash memory 103 can determine that the first data transmission link is abnormal. The data packet may include the above-mentioned picture information.

[0084] It should be noted that if the flash memory 103 detects that the first data transmission link is normal, it only needs to perform normal read and write operations, and there is no need to execute the following S203-S208. The specific implementation can refer to the existing implementation method, and the embodiments of this application will not be repeated.

[0085] S203, the flash memory 103 adjusts the first parameter.

[0086] The first parameter is a working parameter of the flash memory 103 transmitting data in the first data transmission link, for example, adjusting the high data transmission rate of the flash memory 103 in the first transmission channel to a low data transmission rate. The first data transmission link is a communication link between the flash memory 103 and the main chip 101.

[0087] S204 , the flash memory 103 sends a first level signal to the master chip 101 , and the master chip 101 receives the first level signal from the flash memory 103 .

[0088] The first level signal is used to request the main chip 101 to restore the first data transmission link. The duration of the first level signal is specified by the communication protocol between the main chip 101 and the flash memory 103, such as 2ms, 1.5ms, etc., which is not limited here. The first level signal can be a high level signal or a low level signal, which is not limited here.

[0089] Figure 4 This is a block diagram of the connection between the main chip 101 and the flash memory 103 provided in the embodiment of the present application. Figure 4 As shown, a differential line 401 is connected between the flash memory 103 and the main chip 101, and the flash memory 103 can send a first level signal to the main chip 101 through the differential line 401. The above S204, the flash memory 103 sends the first level signal to the main chip 101, and the main chip 101 receives the first level signal from the flash memory 103, can be specifically implemented as follows: assuming that the first level signal is a high level signal, the flash memory 103 can drive the two connecting lines of the differential line 401 to output a high level signal, and the duration of the high level signal is the preset duration of the first level signal; accordingly, if the main chip 101 detects that the signal on the differential line 401 is a high level signal, and the duration of the high level signal reaches the duration of the first level signal, the main chip 101 can confirm that the high level signal is the first level signal, that is, the main chip 101 receives the first level signal. Since the anti-interference capability of the level signal output in a differential manner is stronger than that of the level signal output in a non-differential manner (such as a single-line manner), transmitting the first level signal through the differential line 401 can improve the reliability of the first level signal.

[0090] S205 , the master chip 101 restores the first data transmission link that is in an abnormal state.

[0091] S206, the flash memory 103 detects that the first data transmission link has not been successfully restored.

[0092] Figure 5 The interactive flow chart of restoring the first data transmission link provided in the embodiment of the present application is as follows. Figure 5As shown, the process of restoring the first data transmission link may include: the main chip 101 adjusts the second parameter. The second parameter is a working parameter for the main chip 101 to transmit data in the first data transmission link. For example, the high data transmission rate of the main chip 101 in the first transmission channel is adjusted to a low data transmission rate. The first parameter and the second parameter are equal. The main chip 101 receives a first data packet from the flash memory 103, and the first data packet carries a recovery request. If the main chip 101 receives the first data packet, the first data packet is parsed and the recovery request is identified, then the main chip 101 adjusts the third parameter, and the third parameter can be a working parameter of the main chip 101 in the second transmission channel. For example, the high data transmission rate of the main chip 101 in the second transmission channel is adjusted to a low data transmission rate. The main chip 101 sends a third level signal to the flash memory 103. After the flash memory 103 receives the third level signal from the main chip 101, it is considered that the first data packet is sent successfully to the main chip 101, that is, the first transmission channel is successfully restored. On the contrary, if the flash memory 103 does not receive the first level signal from the master chip 101 after sending the first data packet, it is considered that the first data packet fails to be sent to the master chip 101, that is, the first transmission channel fails to recover.

[0093] Please continue reading Figure 5 , after receiving the first level signal from the main chip 101, the flash memory 103 adjusts the fourth parameter. The fourth parameter can be adjusted by adjusting the high data transmission rate of the flash memory 103 in the second transmission channel to a low data transmission rate. The third parameter is equal to the fourth parameter. The main chip 101 sends a second data packet to the flash memory 103. If the flash memory 103 receives the second data packet from the main chip 101, it is considered that the second transmission channel has been successfully restored; conversely, if the flash memory 103 does not receive the second data packet from the main chip 101, it is considered that the second transmission channel has failed to be restored.

[0094] It should be noted that when any one of the first transmission channel and the second transmission channel fails to recover, the flash memory 103 determines that the first data transmission link has not been successfully recovered. In addition, if the flash memory 103 detects that the first data transmission link has been successfully recovered, it only needs to perform normal read and write operations, and does not need to perform the following S208-S212. The specific implementation can refer to the existing implementation method, and the embodiment of this application will not be repeated.

[0095] S207 , the flash memory 103 sends a second level signal to the master chip 101 , and the master chip 101 receives the second level signal from the flash memory 103 .

[0096] In order to distinguish the first level signal requesting the master chip 101 to restore the first data transmission link from the second level signal requesting the master chip 101 to re-establish the link, the duration of the second level signal can be set to be greater than the duration of the first level signal. For example, when the duration of the first level signal is 2ms, the duration of the second level signal can be 5ms, 6ms, 7ms, etc., which is not limited here.

[0097] It should be noted that when the first data transmission link is in a normal state, the main chip 101 can receive the duration of the second level signal and the duration of the first level signal from the flash memory 103, so that the main chip 101 can identify the second level signal and the first level signal.

[0098] Exemplarily, the duration of the second level signal and the duration of the first level signal can be actively sent by the flash memory 103 to the main chip 101, or can be sent by the flash memory 103 after the main chip 101 sends a data read request to the flash memory 103; it can also be pre-configured in the main chip 101, which is not limited here.

[0099] In a possible implementation, the difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to the first threshold. The first threshold may be 3ms, 5ms, 7ms, etc., which is not limited here. For example, the duration of the first level signal is 3ms, and the duration of the second level signal is 6ms; or, the duration of the second level signal is 3ms, and the duration of the second level signal is 8ms. Since the difference between the duration of the second level signal and the duration of the first level signal is greater than or equal to the first threshold, the main chip 101 can accurately distinguish between the first level signal and the second level signal.

[0100] In another implementation, the duration of the second level signal is greater than or equal to the second threshold, and the second threshold is greater than the duration of the first level signal. The second threshold can be stored in a register set by the main chip 101, and the main chip 101 can access the register at any time to obtain the second threshold.

[0101] For example, the second threshold value can be obtained by taking a value greater than the duration of the first level signal and less than the duration of the second level signal after the main chip 101 obtains the duration of the first level signal and the duration of the second level signal. For example, if the duration of the first level signal is 2ms and the duration of the second level signal is 10ms, the main chip 101 can determine that the second threshold value is 6ms. It can be understood that when the duration of the second level signal is greater than the second threshold value, the difference between the duration of the first level signal and the duration of the first level signal is large, so that the main chip 101 can accurately distinguish the first level signal from the second level signal.

[0102] It should be understood that Figure 4 As shown, in order to save hardware resources, the flash memory 103 can send a first level signal and a second high level signal to the main chip 101 based on the same differential line 401. The differential lines 401 are signal lines connecting the flash memory 103 and the main chip 101. Since the first level signal and the second high level signal are transmitted based on the same differential line, there is no need to add additional hardware resources, thereby saving costs.

[0103] In addition, two groups of differential lines 401 may be provided between the flash memory 103 and the main chip 101, wherein one group of differential lines 401 is used to transmit a first level signal, and the other group of differential lines 401 is used to transmit a second level signal. It can be understood that the pin identifiers of the two groups of differential lines are different, and the main chip 101 can determine whether the received level signal is a first level signal or a second level signal according to the pin identifiers of the differential lines.

[0104] It should be noted that, when there are two groups of differential lines, the duration of the first level signal and the duration of the second level signal may have no magnitude relationship.

[0105] S208 , the master chip 101 establishes a second data transmission link, and the flash memory 103 establishes a second data transmission link.

[0106] The master chip 101 establishes the second data transmission link by sending a link establishment command to the flash memory 103 ; and the flash memory 103 establishes the second data transmission link by receiving a link establishment command from the master chip 101 .

[0107] like Figure 4 As shown, a reset line 402 is also connected between the flash memory 103 and the main chip 101. The link establishment command may include a reset command. The specific process of S208 includes: the main chip 101 restarts by controlling its own reset pin to reset, and then the main chip 101 sends a reset command to the flash memory 103 through the reset line 402 to enable the reset pin of the flash memory 103 to reset, thereby controlling the flash memory 103 to restart. Then the main chip 101 shakes hands with the flash memory 103 again and cooperates with each other to establish a second data transmission link. As a result, the main chip 101 can immediately read and write data to the flash memory 103 normally through the second data transmission link. For example, the main chip 101 writes the above-mentioned picture information to the flash memory 103 through the second data transmission link.

[0108] According to the inventor's experiment, in the prior art, the main chip 101 needs to wait for 3 seconds to 5 seconds from issuing a data read and write request to start establishing the second data transmission link, while the embodiment of the present application only needs to wait for 5 milliseconds to 10 milliseconds from issuing a data read and write request to start establishing the second data transmission link, which can greatly reduce the time required to rebuild the link when an abnormality occurs in the data link to avoid data read / write jams, thereby improving the user experience. In addition, the second level signal of the flash memory requesting the main chip 101 to rebuild the second data transmission link is a stable signal (no jump), and even if the first data transmission link is abnormal, the main chip 101 can accurately detect the second level signal, with high reliability.

[0109] Figure 6 A schematic diagram of the software structure of the link reconstruction device provided in the embodiment of the present application. Figure 6 The link reconstruction device 600 can be applied to a flash memory of an electronic device, and the electronic device also includes a main chip 101. Figure 4 As shown, a differential line 401 and a reset line 402 are connected between the flash memory 103 and the main chip 101. The differential line 401 in the embodiment of the present application has the same function as the differential line 401 in the above embodiment; the reset line 402 in the present embodiment has the same function as the reset line 402 in the above embodiment, which will not be described in detail. Figure 6 As shown, the link reconstruction device 600 includes a processing unit 601 and a transceiver unit 602. The transceiver unit 602 is used to execute S201, S204, and S207 in the above embodiment; the processing unit 601 is used to execute S202, S203, S206, and S208 in the above embodiment.

[0110] In addition, the link reconstruction device 600 can also be applied to the main chip 101. When the link reconstruction device 600 is applied to the main chip 101, the transceiver unit 602 is used to execute S201, S204, S207 in the above embodiment, and the processing unit 601 is used to execute S205, S208 in the above embodiment.

[0111] Optionally, the link reconstruction device 600 may further include a storage unit ( Figure 6 (not shown in the figure). The storage unit stores a program or instruction. When the processing unit executes the program or instruction, the link reconstruction device 600 can execute Figure 2 or Figure 4 Link reconstruction method in .

[0112] Optionally, the transceiver unit may be integrated into one unit, or may be divided into a receiving unit and a sending unit, wherein the sending unit is used to perform the sending function of the link reconstruction device 600 , and the receiving unit is used to perform the receiving function of the link reconstruction device 600 .

[0113] It should be noted that the basic principle and technical effect of the link reconstruction device 600 provided in the embodiment of the present application are the same as those of the above-mentioned method embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above-mentioned method embodiment.

[0114] For example, Figure 7 This is a schematic diagram of the structure of the electronic device 700 provided in the embodiment of the present application. Figure 7 The components of the electronic device 700 are described in detail:

[0115] Among them, the main chip 701 is the control center of the electronic device 700, and the main chip 701 may include a processor 7011 and a processor 7022. For example, the processor 7011 and the processor 7022 may include one or more central processing units (CPUs), or may include application specific integrated circuits (ASICs), or may include one or more integrated circuits configured to implement the embodiments of the present application, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (field programmable gate arrays, FPGAs).

[0116] Optionally, the main chip 701 can execute various functions of the electronic device 700 by running or executing the software program stored in the read-only memory 702, and calling the data stored in the read-only memory 702. For example, the main chip 701 can execute S201, S204, S205, S207, and S208 in the above embodiments of the present application, which are not limited here.

[0117] In a specific implementation, as an embodiment, the main chip 701 may include one or more CPUs, such as Figure 7 CPU0 and CPU1 are shown in FIG.

[0118] Among them, the read-only memory 702 is used to store the software program for executing the solution of the present application, and the main chip 701 controls the execution. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0119] Optionally, the read-only memory 702 may be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The read-only memory 702 may be integrated with the main chip 701, or may exist independently and access the main chip 701 through the interface circuit ( Figure 7 (not shown) is coupled to the main chip 701, which is not specifically limited in the embodiment of the present application.

[0120] The transceiver 703 is used for communication with other electronic devices. For example, if the electronic device 700 is an electronic device, the transceiver 703 can be used to communicate with a network device or another electronic device. For another example, if the electronic device 700 is a network device, the transceiver 703 can be used to communicate with an electronic device or another network device.

[0121] Optionally, the transceiver 703 may include a receiver and a transmitter ( Figure 7 The receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0122] Optionally, the transceiver 703 may be integrated with the main chip 701, or may exist independently and communicate with the electronic device 700 through an interface circuit ( Figure 7 (not shown) is coupled to the main chip 701, which is not specifically limited in the embodiment of the present application.

[0123] Flash memory 704 is a memory built based on serial data transmission technology that allows it to be erased or written multiple times during operation. Although there are only two data channels between its internal storage unit and the main chip, due to the use of serial data transmission, its actual data transmission speed is very high. UFS supports full-duplex mode, all data channels can perform read and write operations at the same time, and the response speed of data reading and writing is also very high. Flash memory 704 can execute S201, S202, S203, S204, S206, S207, and S208 in the above embodiments of this application.

[0124] It should be noted that Figure 7The structure of the electronic device 700 shown in the figure does not constitute a limitation on the link reconstruction device. The actual link reconstruction device may include more or fewer components than those shown in the figure, or combine certain components, or arrange the components differently.

[0125] In addition, the technical effects of the electronic device 700 can refer to the technical effects of the link reconstruction method described in the above method embodiment, which will not be repeated here.

[0126] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program code is stored. When a processor executes the computer program code, the electronic device executes the method in the above embodiment.

[0127] The embodiments of the present application also provide a computer program product. When the computer program product is run on an electronic device, the electronic device executes the method in the above embodiments.

[0128] Through the description of the above implementation methods, technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0129] Each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0130] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as flash memory, mobile hard disk, read-only memory, random access memory, disk or optical disk.

[0131] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.

Claims

1. A link reestablishment method, characterized in that: A flash memory applied to an electronic device, wherein the electronic device further comprises a main chip, and the method comprises: When the flash memory detects that the first data transmission link is in an abnormal state, the flash memory adjusts a first parameter, wherein the first parameter is a working parameter of the flash memory transmitting data in the first data transmission link, and the first data transmission link is a communication link between the flash memory and the main chip; The flash memory sends a first level signal to the master chip, where the first level signal is used to request the master chip to restore the first data transmission link; If the flash memory detects that the first data transmission link fails to recover, it sends a second level signal to the main chip, wherein the duration of the second level signal is greater than the duration of the first level signal; The flash memory receives a link establishment command from the main chip; The flash memory establishes a second data transmission link according to the link establishment command.

2. The method according to claim 1, characterized in that A difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

3. The method according to claim 1 or 2, characterized in that: The duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

4. The method according to claim 1, characterized in that Before the flash memory adjusts the first parameter, the method further includes: When the first data transmission link is in a normal state, the flash memory sends the duration of the second level signal and the duration of the first level signal to the main chip.

5. The method according to claim 4, characterized in that Before the flash memory sends the duration of the second level signal and the duration of the first level signal to the main chip, the method further includes: The flash memory receives a data read request from the master chip.

6. The method according to claim 1, characterized in that The flash memory sends the first level signal and the second level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.

7. A link reestablishment method, characterized in that: A main chip applied to an electronic device, wherein the electronic device further includes a flash memory, and the method includes: The master chip receives a first level signal output by the flash memory, where the first level signal is used to request the master chip to restore a first data transmission link; The master chip restores the first data transmission link in an abnormal state, wherein the first data transmission link is a communication link between the flash memory and the master chip; If the first data transmission link fails to recover, the main chip receives a second level signal transmitted by the flash memory, wherein the duration of the second level signal is greater than a set threshold, and the set threshold is greater than or equal to the duration of the first level signal; A second data transmission link is established according to the second level signal, wherein the establishing the second data transmission link comprises sending a link establishment command to the flash memory.

8. The method according to claim 7, characterized in that A difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

9. The method according to claim 7 or 8, characterized in that: The duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

10. The method according to claim 7, characterized in that Before the main chip receives the first level signal output by the flash memory, the method further includes: When the first data transmission link is in a normal state, the main chip receives a duration of the second level signal and a duration of the first level signal sent by the flash memory.

11. The method according to claim 10, characterized in that Before the main chip receives the duration of the second level signal and the duration of the first level signal sent by the flash memory, the method further includes: The master chip sends a data read request to the flash memory.

12. The method according to claim 7, characterized in that The master chip receives the first level signal and the second level signal based on a same differential line, wherein the differential line is a signal line connecting the flash memory and the master chip.

13. A link reconstruction device, characterized in that: A flash memory applied to an electronic device, wherein the electronic device further comprises a main chip, and the device comprises a processing unit and a transceiver unit; wherein, The processing unit is configured to adjust a first parameter when detecting that the first data transmission link is in an abnormal state, wherein the first parameter is a working parameter of the flash memory in transmitting data in the first data transmission link, and the first data transmission link is a communication link between the flash memory and the main chip; The transceiver unit is used to send a first level signal to the master chip, where the first level signal is used to request the master chip to restore the first data transmission link; The processing unit is further configured to control the transceiver unit to send a second level signal to the main chip if it is detected that the first data transmission link fails to recover, wherein the duration of the second level signal is greater than the duration of the first level signal; The transceiver unit is further used to receive a link establishment command from the master chip; The processing unit is further configured to establish a second data transmission link according to the link establishment command.

14. The device according to claim 13, characterized in that A difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

15. The device according to claim 13 or 14, characterized in that The duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

16. The device according to claim 13, characterized in that The transceiver unit is further configured to send the duration of the second level signal and the duration of the first level signal to the main chip when the first data transmission link is in a normal state.

17. The device according to claim 16, characterized in that The transceiver unit is also used to receive a data read request from the master chip.

18. The device according to claim 13, characterized in that The transceiver unit is further configured to send the first level signal and the second level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.

19. A link reconstruction device, characterized in that: A main chip applied to an electronic device, wherein the electronic device further comprises a flash memory, and the device comprises a transceiver unit and a processing unit; wherein, The transceiver unit is used to receive a first level signal output by the flash memory, where the first level signal is used to request the master chip to restore the first data transmission link; The processing unit is used to restore a first data transmission link in an abnormal state, wherein the first data transmission link is a communication link between the flash memory and the main chip; The transceiver unit is further configured to receive a second level signal transmitted by the flash memory if the first data transmission link fails to recover, wherein the duration of the second level signal is greater than a set threshold, and the set threshold is greater than or equal to the duration of the first level signal; The processing unit is further configured to establish a second data transmission link according to the second level signal, wherein establishing the second data transmission link includes sending a link establishment command to the flash memory.

20. The device according to claim 19, characterized in that A difference between a duration of the second level signal and a duration of the first level signal is greater than or equal to a first threshold.

21. The device according to claim 19 or 20, characterized in that The duration of the second level signal is greater than or equal to a second threshold, wherein the second threshold is greater than the duration of the first level signal.

22. The device according to claim 19, characterized in that The transceiver unit is further configured to receive the duration of the second level signal and the duration of the first level signal sent by the flash memory when the first data transmission link is in a normal state.

23. The device according to claim 22, characterized in that The transceiver unit is also used for the main chip to send a data read request to the flash memory.

24. The device according to claim 19, characterized in that The transceiver unit is further configured to receive the first level signal and the second level signal based on the same differential line, wherein the differential line is a signal line connecting the flash memory and the main chip.

25. An electronic device, characterized in that: It comprises a flash memory and a main chip, wherein the flash memory is communicatively connected to the main chip, wherein the flash memory is used to execute the link reconstruction method according to any one of claims 1 to 6, and the main chip is used to execute the link reconstruction method according to any one of claims 7 to 12.

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