Inverted-t negative capacitance tunneling field effect transistor based biosensor and method of fabrication

Abstract

The application discloses a biosensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, and mainly solves the problems of low sensitivity and complex manufacturing process in the prior art. The biosensor comprises, from bottom to top, a substrate (1), a channel region (4), a gate insulating dielectric layer (5), a gate ferroelectric layer (7), a gate titanium nitride layer (8), a gate metal layer (9), a source region (3) and a conductive layer (11). The channel region is provided with drain regions (6) on both sides, the drain regions are provided with isolation grooves (2) on both sides, the gate insulating dielectric layer is provided with biological filling layers (10) on both sides of a vertical part, the channel region adopts an inverted T-shaped structure, the gate insulating dielectric layer adopts a symmetrical L-shaped structure, and the gate metal layer is composed of a lower metal hafnium and an upper metal aluminum. The biosensor has high sensitivity and on-state current, can effectively inhibit short channel effect and bipolar effect, has simple manufacturing process and low manufacturing cost, and can be used for label-free detection of biomolecules.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a negative capacitance tunneling field effect transistor which can be used for label-free detection of biomolecules. BACKGROUND

[0002] With the development and progress of science and technology, the performance requirements of biological sensing technology for rapid detection and analysis are increasingly high in the fields of medical testing technology, environmental monitoring and agricultural industry. In particular, in the field of medical testing, due to the increasing demand for instant detection tools, there is an urgent need for a biological sensor with high sensitivity, high reliability, low cost and low response time.

[0003] The dielectric modulation biosensor based on field effect transistor is currently a relatively optimal solution, which not only overcomes the shortcomings of ion-sensitive biosensors that can only detect charged biomolecules and cannot detect electrically neutral biomolecules, but also has the characteristics of small size, high sensitivity, low power consumption, compatibility with existing CMOS process and the advantage of rapid screening of biomolecules.

[0004] However, with the continuous reduction of the size of semiconductor devices, biosensors based on traditional MOS field effect transistors face problems such as rising power consumption due to short channel effect and inability to break through the limit of sub-threshold swing at room temperature, while biosensors based on tunneling field effect transistors (TFET) can break through the limit of sub-threshold swing, but have the disadvantages of small on-state current, large leakage power consumption and bipolar characteristics, which seriously affect the sensitivity and performance of the sensor.

[0005] At present, researchers have proposed various improvement schemes for the above problems:

[0006] The patent document with application number CN202011516842.4 discloses a "biological sensor based on nanosheet stacked field effect transistor and preparation method" scheme, which includes a substrate, a source region, a nanosheet stacking region, an isolation region and a drain region. The nanosheet stacking region includes a plurality of nanosheet conductive channel layers arranged in parallel. The nanosheet conductive channel layer and the gate metal layer form a biomolecule detection cavity, and the nanosheet conductive channel layers adjacent to each other form a biomolecule detection cavity. This structure can well suppress the short channel effect, the preparation method is compatible with the existing FinFET process, and the manufacturing cost is low, but it also has the problem of low sensitivity.

[0007] The journal "IEEE Sensors Journal" published a "Simulation Study of Dual Metal-Gate Inverted T-Shaped TFET for Label-Free Biosensing" scheme, which includes a substrate, a source region, a drain region, a channel region, a gate and a biomolecule detection cavity; the channel region adopts a vertical structure; the gate is stacked by two metals with different work functions; the biomolecule detection cavity is arranged on both sides of the channel. The device has a simple preparation process, but its sensitivity is low.

[0008] The journal "IEEE Sensors Journal" published a "Design and Performance Assessment of Dielectrically Modulated Nanotube TFET Biosensor" scheme, which adopts a nanotube structure, including: a source region, a drain region, a channel region, a gate region and a biomolecule detection cavity; the source region and the drain region use charge plasma technology to generate carriers; the gate metal is stacked by two metals of chromium and silver; the biomolecule detection cavity is composed of an inner cavity arranged in the source region and an outer cavity arranged on the upper part of the gate dielectric layer. Although this device can avoid the influence of doping fluctuation, its manufacturing process is complex, the manufacturing cost is high, and the sensitivity is low.

[0009] The patent document with application number CN201910224882.2 discloses a "semiconductor biosensor based on tunneling field effect transistor and its preparation method", as shown in Figure 1 It includes: SOI substrate and interconnection metal, isolation groove, source region, channel region and drain region; the surface of the channel region is provided with a gate dielectric layer; the upper surface of the gate dielectric layer is provided with a gate metal; the left side of the gate dielectric layer is provided with a biological filling layer. Based on the tunneling field effect transistor, an L-shaped structure is adopted in the channel region and the gate dielectric layer. Although this device can overcome the limitation of subthreshold swing at room temperature, the process is relatively simple, but its sensitivity is low. SUMMARY

[0010] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a negative capacitance tunneling field effect transistor biosensor based on inverted T-shaped and its preparation method, in order to improve the sensitivity of the sensor and simplify the manufacturing process of the device.

[0011] To achieve the above purpose, the technical scheme of the present application is as follows:

[0012] 1.A biosensor based on inverted T-shaped negative capacitance tunneling field effect transistor, comprising: a substrate, an isolation groove, a source region, a channel region, a gate insulating layer, a drain region, a gate ferroelectric layer, a gate titanium nitride layer, a gate metal layer, a biological filling layer, and a conductive layer; the channel region and the drain region are located on the upper surface of the substrate; the isolation groove is located on both sides of the drain region; the source region is located on the upper part of the channel region; the gate insulating layer, the gate ferroelectric layer, the gate titanium nitride layer, and the gate metal layer are sequentially stacked on the upper side of the channel region; the biological filling layer is located on both sides of the vertical part of the gate insulating layer, characterized in that:

[0013] The channel region adopts an inverted T-shaped structure to increase the filling area of biological molecules and improve sensitivity.

[0014] The gate insulating layer adopts a symmetric L-shaped structure and is located on both sides of the channel region.

[0015] The gate ferroelectric layer is stacked on the horizontal part of the gate insulating layer.

[0016] The gate metal layer is provided as two layers, and the upper layer adopts metal aluminum and the lower layer adopts metal hafnium.

[0017] Further, the horizontal part length and the vertical part length of the inverted T-shaped channel region are in a ratio of 1.8:1 to 2:1.

[0018] Further, the gate insulating layer adopts a symmetric L-shaped structure, and the ratio of the length of the horizontal part to the length of the vertical part is 0.7:1 to 1:1.

[0019] Further, the gate ferroelectric layer adopts a zirconium oxide ferroelectric material, and the thickness is 5.5 nm to 10.5 nm.

[0020] Further, the upper and lower gate metal layers have a ratio of the thickness of the upper layer to the thickness of the lower layer of 1:0.6 to 1:1.

[0021] Further, the substrate adopts a three-layer structure of a bottom layer of silicon, an oxide buried layer, and a top layer of silicon.

[0022] Further, the source region adopts germanium semiconductor material.

[0023] Further, the channel region and the drain region both adopt silicon semiconductor material.

[0024] 2.A biosensor preparation method based on an inverted T-shaped negative capacitance tunneling field effect transistor, characterized in that it comprises the following steps:

[0025] 1) Selecting an intrinsic bottom layer of silicon substrate, and sequentially depositing an oxide buried layer and a top layer of silicon on the surface to form an SOI substrate;

[0026] 2) Photoetching and etching are carried out on both sides of the top silicon, and etching is stopped at the oxide buried layer to form a shallow trench isolation region, oxide deposition is carried out to form an isolation trench, and the surface is polished flat;

[0027] 3) Photoetching and etching are carried out at the middle position of the top silicon surface to form a groove of the source region, germanium is deposited in the groove by using a chemical vapor phase epitaxy deposition process, boron doping gas is introduced into the germanium for in-situ doping to form a P-type source region;

[0028] 4) Photoetching and etching are carried out on both sides of the source region to form two symmetrical L-shaped groove structures, and a silicon dioxide layer is deposited on the surface of the L-shaped groove by using a chemical vapor phase epitaxy deposition process to form a gate insulating medium layer;

[0029] 5) Part of the silicon dioxide on the surface of the gate insulating medium layer close to the isolation trench is etched away by using a reactive ion etching process to expose the silicon surface to form a symmetrical drain region pattern, arsenic ions are implanted in the drain region by using an ion implantation process, and the impurities are activated by annealing to form an N-type drain region;

[0030] 6) A polysilicon dummy gate is deposited on the gate insulating medium layer by using a chemical vapor phase epitaxy deposition process;

[0031] 7) The polysilicon dummy gate on the horizontal part of the L-shaped gate medium layer is etched by using an ion etching process, the polysilicon dummy gate on the vertical part of the L-shaped gate medium layer is reserved, zirconium oxide is deposited on the surface of the horizontal part of the L-shaped gate medium layer by using an atomic layer deposition method ALD, and the ferroelectric layer is processed by using a rapid thermal treatment RTA method to form a gate ferroelectric layer;

[0032] 8) A conductive material titanium nitride is deposited on the gate ferroelectric layer by using a chemical vapor phase epitaxy deposition process to form a gate titanium nitride layer;

[0033] 9) Metal hafnium is first deposited on the titanium nitride conductive layer by using a reactive sputtering process, and then metal aluminum is deposited on the surface of the metal hafnium to form a gate metal layer;

[0034] 10) The remaining polysilicon dummy gate is etched away by using a reactive ion etching process to expose the gap between the gate metal layer, the gate ferroelectric layer and the gate insulating medium layer to form a biological filling layer;

[0035] 11) Lead windows are photoetched on the source region, the drain region and the gate metal layer respectively to form lead holes, metal is deposited as an interconnection line to form a conductive layer, and finally the preparation of the biological sensor of the inverted T-shaped negative capacitance tunneling field effect transistor is completed.

[0036] Compared with the prior art, the present application has the following advantages:

[0037] First, the application can increase the biological filling layer area and improve the sensor sensitivity by using symmetrical L-shaped gate dielectric layers on both sides of the source region to form an inverted T-shaped channel region.

[0038] Second, the application can effectively suppress short channel effect and bipolar effect by using two kinds of gate metal stacking methods.

[0039] Third, the application can improve the on-state current of the device by using germanium material with narrow band gap in the source region.

[0040] Fourth, the application can improve the switching characteristics and sensitivity of the biosensor by introducing negative capacitance effect by stacking the gate ferroelectric layer on the horizontal part of the gate insulating dielectric layer.

[0041] Fifth, the manufacturing process of the application is simple and easy to implement, compatible with the current CMOS semiconductor manufacturing process, and reduces the manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is a structural schematic diagram of the existing biosensor based on L-shaped tunneling field effect transistor;

[0043] Figure 2 It is a structural schematic diagram of the device of the application;

[0044] Figure 3 It is a preparation flowchart of the device of the application;

[0045] Figure 4 It is a transfer characteristic curve diagram of the embodiment 1 of the application simulated by computer aided design software;

[0046] Figure 5 It is a sensitivity comparison diagram of the embodiment 1 of the application and the biosensor based on the traditional TFET in different dielectric constant biological molecules simulated by computer aided design software.

[0047] Figure 6 It is a transfer characteristic curve diagram of the embodiment 2 of the application simulated by computer aided design software;

[0048] Figure 7 It is a sensitivity comparison diagram of the embodiment 2 of the application and the biosensor based on the traditional TFET in different dielectric constant biological molecules simulated by computer aided design software.

[0049] Figure 8 It is a transfer characteristic curve diagram of the embodiment 3 of the application simulated by computer aided design software;

[0050] Figure 9is a comparison chart of the sensitivity of the embodiment 3 of the application and the biosensor based on the conventional TFET to the biological molecules with different dielectric constants simulated by computer-aided design software. DETAILED DESCRIPTION

[0051] The embodiments and effects of the application will be described in detail below with reference to the drawings:

[0052] Referring to Figure 2 , the biosensor based on the T-shaped negative capacitance tunneling field effect transistor includes a substrate 1, an isolation groove 2, a source region 3, a channel region 4, a gate insulating dielectric layer 5, a drain region 6, a gate ferroelectric layer 7, a gate titanium nitride layer 8, a gate metal layer 9, a biological filling layer 10, and a conductive layer 11, wherein:

[0053] The substrate 1 is composed of a bottom layer of a silicon wafer 1A, an intermediate oxide buried layer 1B, and a top layer of silicon 1C;

[0054] The isolation groove 2 is located on both sides of the top layer of silicon 1C;

[0055] The source region 3 is located on the upper part of the channel region 4 and adopts germanium semiconductor material;

[0056] The channel region 4 is located on the upper surface of the intermediate oxide buried layer 1B and adopts an inverted T-shaped structure composed of silicon semiconductor, and the ratio of the length of the horizontal part to the length of the vertical part is 1.8:1 to 2:1;

[0057] The gate insulating dielectric layer 5 is located on both sides of the source region 3 and adopts a symmetrical L-shaped structure, and the ratio of the length of the horizontal part to the length of the vertical part is 0.7:1 to 1:1;

[0058] The drain region 6 is located on both sides of the horizontal part of the channel region 4 and adopts silicon semiconductor material;

[0059] The gate ferroelectric layer 7 is stacked on the horizontal part of the gate insulating dielectric layer 5 and adopts HZO ferroelectric material with a thickness of 5.5 nm to 10.5 nm;

[0060] The gate titanium nitride layer 8 is stacked on the gate ferroelectric layer 7 and has a thickness of 2 nm;

[0061] The gate metal layer 9 is stacked on the gate titanium nitride layer and adopts a two-layer metal structure, the upper layer 92 adopts aluminum, the lower layer 91 adopts hafnium, and the ratio of the thickness of the aluminum to the thickness of the hafnium is 1:0.6 to 1:1;

[0062] The biological filling layer 10 is located on both sides of the vertical part of the gate insulating dielectric layer 5 and has a width of 5.5 nm;

[0063] The conductive layer 11 is composed of a source lead 111, a drain lead 112 and a gate lead 113, which are respectively located on the source region, the drain region and the upper part of the gate metal layer.

[0064] Referring to Figure 5 , the application prepares a biosensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, and gives the following three embodiments:

[0065] Embodiment 1: A biosensor of an inverted T-shaped negative capacitance tunneling field effect transistor is prepared, in which the horizontal and vertical length ratio of the inverted T-shaped channel region is 1.8:1, the horizontal and vertical length ratio of the L-shaped gate insulating layer is 0.7:1, the thickness ratio of the gate metal aluminum and hafnium is 1:0.6, and the thickness of the gate ferroelectric layer is 5.5 nm.

[0066] Step 1: Making a substrate, such as Figure 3 (a).

[0067] 1a) At a temperature of 900℃, a dry oxygen oxidation process is used to generate a 10nm-thick silicon dioxide oxide buried layer on the initial silicon substrate of the bottom layer;

[0068] 1b) The process conditions of setting the temperature to 800℃, the pressure in the reaction cavity to 760mT, and inputting the reaction source gas SiH4 and the protective gas He are used to grow a 100nm-thick top layer silicon on the oxide buried layer by chemical vapor deposition method, so as to form the substrate.

[0069] Step 2: Forming isolation grooves on both sides of the top layer silicon, such as Figure 3 (b).

[0070] 2a) SiO2 is first deposited on the surface of the top layer silicon as a base oxide layer, and then Si3N4 is deposited on the surface of the layer as a protective layer;

[0071] 2b) A photolithography machine is used to form a shallow trench isolation pattern on the Si3N4 protective layer by using a photolithography process;

[0072] 2c) An etching cavity is manually set to have a pressure of 10mT and a power of 20W by using a plasma etching machine, and 50sccm of Cl2 and 20sccm of O2 are input into the etching cavity through a gas supply system to etch at the shallow trench isolation pattern to the oxide buried layer, so as to form a shallow trench isolation region;

[0073] 2d) A chemical vapor deposition device is used to deposit silicon dioxide material in the shallow trench isolation region by chemical vapor deposition process under the process conditions of setting the temperature to 700℃, the pressure in the reaction cavity to 760mT, inputting the reaction source gas Si3H4 and N2O, and the protective gas He being He, and the thickness of the deposited silicon dioxide is the same as that of the top layer silicon;

[0074] 2e) using a polishing machine, mechanically polishing the top silicon surface after the silicon dioxide is deposited, removing the excess SiO2 and Si3N4 on the top silicon surface, making the top silicon surface flat, and forming the isolation groove.

[0075] Step 3, preparing a source region with a doping concentration of 5 x 1019 cm-3, as shown in 19 cm -3 -3. Figure 3 (c).

[0076] 3a) first depositing SiO2 on the top silicon surface as a base oxide layer, and then depositing Si3N4 on the surface of the layer as a protective layer;

[0077] 3b) using a photoetching machine, performing photoetching on the Si3N4 protective layer using a photoetching process to form a source region pattern;

[0078] 3c) using a plasma etching machine, manually setting the pressure of the etching cavity to 10 mT and the power to 20 W as the process parameters, and simultaneously inputting 50 sccm of Cl2 and 20 sccm of O2 into the etching cavity through the gas supply system to etch at the source region pattern to form a source region groove;

[0079] 3d) setting the temperature to 750°C, the pressure in the reaction cavity to 760 mT, and the process conditions of the reaction source gas GeH4 and the protective gas He to deposit germanium material in the source region groove to completely fill the groove;

[0080] 3e) inputting boron doping gas to in-situ dope the source region, and then annealing to achieve in-situ activation of the doping elements to form a highly doped P-type source region with a doping concentration of 5 x 1019 cm-3. 19 cm -3 -3.

[0081] Step 4, forming symmetrical L-shaped gate dielectric layers on both sides of the source region, as shown in Figure 3 (d).

[0082] 4a) first depositing SiO2 on the top silicon surface as a base oxide layer, and then depositing Si3N4 on the surface of the layer as a protective layer;

[0083] 4b) performing photoetching on the Si3N4 protective layer to form symmetrical L-shaped groove area patterns on both sides of the source region, and forming an inverted T-shaped channel region on the top silicon, wherein the horizontal length of the L-shaped is 30 nm and the vertical length is 46 nm; the horizontal length of the inverted T-shaped is 82 nm and the vertical length is 46 nm;

[0084] 4c) removing the excess SiO2 and Si3N4 on the silicon surface using chemical mechanical polishing to make the silicon surface flat;

[0085] 4d) Set the temperature at 800℃, the pressure in the reaction cavity at 760mT, and the process conditions of the input reaction source gas Si3H4 and N2O and the protective gas He, and use the chemical vapor deposition process to deposit a 0.5nm-thick silicon dioxide gate dielectric layer on the L-shaped groove area on both sides of the source region.

[0086] Step 5, preparation of a doped concentration of 5x1019cm-3 18 cm-3 -3 for the drain region, such as Figure 3 (e).

[0087] 5a) Deposit Si3N4 as a protective layer on the surface of the gate dielectric layer;

[0088] 5b) Use a photoetching machine to photoetch the Si3N4 protective layer on both sides of the isolation groove to form a drain region pattern, and then use a plasma etching machine to set the pressure in the etching cavity at 10mT and the power at 20W, and through the gas supply system, input 50sccm of Cl2 and 20sccm of O2 into the etching cavity at the same time, to etch the silicon dioxide at the drain region pattern to expose the drain region;

[0089] 5c) Use an ion implantation process to implant arsenic ions into the exposed drain region at a dose of 1e14 and an implantation energy of 40keV to form a doped concentration of 5x1019cm-3 18 cm-3 -3 N-type doped drain region;

[0090] 5d) Set the annealing temperature at 1000℃, and use a rapid thermal annealing process to activate the doped arsenic ion impurities;

[0091] 5e) Use a polishing machine to mechanically polish the surface of the drain region silicon and the surface of the gate dielectric layer to remove excess Si3N4 and make the surfaces flat.

[0092] Step 6, deposit polycrystalline silicon on the surface of the gate dielectric layer, such as Figure 3 (f).

[0093] 6a) Set the temperature at 580℃, the pressure in the reaction cavity at 800mT, and the process conditions of the reaction source gas SiH4 and the protective gas He, and deposit 46nm-thick polycrystalline silicon on the surface of the gate dielectric layer;

[0094] 6b) Use a plasma etching machine to manually set the pressure in the etching cavity at 10mT and the power at 20W, and through the gas supply system, input 50sccm of Cl2 and 20sccm of O2 into the etching cavity to perform reactive ion etching, selectively etch the polycrystalline silicon on the horizontal part of the gate dielectric layer, and retain the polycrystalline silicon near the vertical sides of the gate dielectric layer;

[0095] 6c) using a polishing machine to mechanically polish the surface of the gate dielectric layer to remove the excess polysilicon.

[0096] Step 7, depositing a gate ferroelectric layer on the surface of the gate dielectric layer, such as Figure 3 (g).

[0097] 7a) setting the reaction cavity temperature to 350°C, the reaction source gas to TEMAHf, TEMAZr, O3, and N2 as the purge gas, using atomic layer deposition ALD to deposit a 5.5 nm thick ferroelectric material HZO on the horizontal surface of the gate insulating dielectric layer;

[0098] 7b) using a rapid annealing furnace, setting the annealing temperature to 500°C, and using rapid thermal annealing RTA to process the ferroelectric layer;

[0099] 7c) using chemical mechanical polishing to polish the surface of the ferroelectric layer flat.

[0100] Step 8, depositing a titanium nitride layer on the surface of the ferroelectric layer, such as Figure 3 (h).

[0101] 8a) setting the temperature to 600°C, introducing 99.99% pure Ar as the carrier gas, 98% pure TiCl4 as the reaction source gas, and 99.99% pure NH3 as the reaction source gas, using chemical vapor deposition to deposit a 2 nm thick titanium nitride layer on the surface of the ferroelectric layer;

[0102] 8b) using chemical mechanical polishing to polish the surface of the titanium nitride layer flat.

[0103] Step 9, depositing a multi-metal layer on the surface of the titanium nitride layer, such as Figure 3 (i).

[0104] 9a) setting the reaction cavity vacuum pressure to 8E-6 Torr, the power to 350W, and the Ar pressure to 5mTorr, using reactive sputtering to deposit a 13.8 nm thick hafnium metal layer on the surface of the titanium nitride layer;

[0105] 9b) under the same conditions, using reactive sputtering to deposit a 24.8 nm thick aluminum metal layer on the surface of the hafnium metal layer, and using chemical mechanical polishing to polish the metal surface flat.

[0106] Step 10, making a bio-filling layer, such as Figure 3 (j).

[0107] 10a) using a plasma etching machine, setting the pressure of the etching chamber to 10 mT, the power to 20 W, and inputting 50 sccm of Cl2 and 20 sccm of O2 into the etching chamber through the gas supply system, etching away the polysilicon near the vertical two sides of the gate dielectric layer, leaking out the gap between the gate metal layer, the gate ferroelectric layer, the gate titanium nitride layer and the gate insulating dielectric layer, and forming a biological filling layer.

[0108] Step 11, making a conductive layer, such as Figure 3 (k).

[0109] 11a) depositing a thickness of Si3N4 insulating layer in the recess on the top side of the drain region;

[0110] 11b) using a polishing machine to mechanically polish the surface of the Si3N4 insulating layer to make it smooth and flat;

[0111] 11c) using a photolithography process to expose the recess of the source, drain and gate metal layer contact hole, forming a lead hole;

[0112] 11d) sputtering metal in the recess of the source, drain and gate metal layer contact hole until the lead hole is filled, and mechanically polishing the surface of the metal to make it flat, forming the source electrode, gate electrode and drain electrode lead, and completing the fabrication of the inverted T-shaped negative capacitance tunneling field effect transistor biosensor.

[0113] Example 2, preparing a negative capacitance tunneling field effect transistor biosensor with an inverted T-shaped channel region horizontal and vertical length ratio of 1.9:1, an L-shaped gate insulating layer horizontal and vertical length ratio of 0.8:1, a gate metal aluminum and metal hafnium thickness ratio of 1:0.8, and a gate ferroelectric layer thickness of 6.5 nm.

[0114] Step one, making a substrate, such as Figure 3 (a).

[0115] The specific implementation of this step is the same as step 1 of example 1.

[0116] Step two, forming an isolation groove on both sides of the top layer of silicon, such as Figure 3 (b).

[0117] The specific implementation of this step is the same as step 2 of example 1.

[0118] Step three, preparing a source region with a doping concentration of 5x10 19 cm -3 , such as Figure 3 (c).

[0119] The specific implementation of this step is the same as step 3 of example 1.

[0120] Step four, forming symmetrical L-shaped gate dielectric layer on both sides of source region, as shown in Figure 3 (d).

[0121] 4.1) First, depositing SiO2 as a base oxide layer on the top surface of silicon, and then depositing Si3N4 as a protective layer on the surface of the layer;

[0122] 4.2) Photolithography is performed on the Si3N4 protective layer to form symmetrical L-shaped groove area patterns on both sides of the source region, and an inverted T-shaped channel region is formed on the top surface of silicon, wherein the horizontal length of the L-shaped is 34 nm, and the vertical length is 43 nm; the horizontal length of the inverted T-shaped is 82 nm, and the vertical length is 43 nm;

[0123] 4.3) Excess SiO2 and Si3N4 on the surface of silicon are removed by chemical mechanical polishing to make the surface of silicon flat;

[0124] 4.4) Using chemical vapor deposition process, under the process conditions of temperature 800℃, pressure 760mT in the reaction cavity, and inputting reaction source gas Si3H4 and N2O as well as protective gas He, depositing a gate dielectric layer with a thickness of 0.5nm on the symmetrical L-shaped groove area on both sides of the source region.

[0125] Step five, preparing a drain region with a doping concentration of 5×10 18 cm -3 , as shown in Figure 3 (e).

[0126] The specific implementation of this step is the same as step 5 of embodiment 1.

[0127] Step six, depositing polysilicon on the surface of the gate dielectric layer, as shown in Figure 3 (f)

[0128] 6.1) Using chemical vapor deposition process, under the process conditions of temperature 580℃, pressure 700mT in the reaction cavity, and inputting reaction source gas SiH4 and protective gas He, depositing polysilicon with a thickness of 43nm on the surface of the gate dielectric layer;

[0129] 6.2) Using a plasma etching machine, and adopting a reactive ion etching process to selectively etch the polysilicon on the horizontal part of the gate dielectric layer, and retaining the polysilicon close to the vertical two sides of the gate dielectric layer. The process conditions of the reactive ion etching are: pressure 10mT in the etching cavity, power 20W, and inputting 50sccm of Cl2 and 20sccm of O2 into the etching cavity through the gas supply system;

[0130] 6.3) Using a polishing machine, mechanically polishing the surface of the gate dielectric layer to remove excess polysilicon.

[0131] Step seven, depositing and forming a gate ferroelectric layer on the surface of the gate dielectric layer, as shown inFigure 3 (g).

[0132] 7.1) Atomic layer deposition (ALD) is used to deposit a ferroelectric material HZO on the horizontal surface of the gate insulating layer to form a gate ferroelectric layer, with a thickness of 6.5 nm, under the following process conditions: a temperature of 250°C, source gas of TEMAHf and TEMAZr, and purging gas of N2.

[0133] 7.2) Rapid thermal annealing (RTA) is used to anneal the ferroelectric layer, with an annealing temperature of 600°C.

[0134] 7.3) Chemical mechanical polishing (CMP) is used to polish the surface of the gate ferroelectric layer.

[0135] Step eight, a titanium nitride layer is deposited on the surface of the gate ferroelectric layer, such as Figure 2 (h).

[0136] The specific implementation of this step is the same as step eight of embodiment 1.

[0137] Step nine, a multi-metal layer is deposited on the surface of the titanium nitride layer, such as Figure 2 (i).

[0138] 9.1) A hafnium metal layer with a thickness of 15 nm is deposited on the surface of the titanium nitride layer using a reactive sputtering process under the following conditions: a reaction chamber vacuum pressure of 8E-6 Torr, a power of 350 W, and an Ar pressure of 5 mTorr.

[0139] 9.2) A 19-nm-thick aluminum metal layer is deposited on the surface of the hafnium metal layer using a reactive sputtering process under the same conditions, and the metal surface is polished flat using chemical mechanical polishing.

[0140] Step ten, a bio-filling layer is made, such as Figure 3 (j).

[0141] The specific implementation of this step is the same as step ten of embodiment 1.

[0142] Step eleven, a conductive layer is made, such as Figure 3 (k).

[0143] The specific implementation of this step is the same as step eleven of embodiment 1.

[0144] Example 3, a negative capacitance tunneling field effect transistor biosensor is prepared, with a horizontal-to-vertical length ratio of the inverted T-shaped channel region of 2:1, a horizontal-to-vertical length ratio of the L-shaped gate insulating layer of 1:1, a gate aluminum metal-to-hafnium metal thickness ratio of 1:1, and a gate ferroelectric layer thickness of 10.5 nm.

[0145] First step, a substrate is made, such asFigure 3 (a).

[0146] The implementation of this step is the same as step 1 of Example 1.

[0147] In the second step, isolation grooves are formed on both sides of the top layer of silicon, as shown in Figure 3 (b).

[0148] The implementation of this step is the same as step 2 of Example 1.

[0149] In the third step, a source region with a doping concentration of 5 x 1019cm-3 is prepared, as shown in 19 cm-3 -3 Figure 3 (c).

[0150] The implementation of this step is the same as step 3 of Example 1.

[0151] In the fourth step, symmetric L-shaped gate dielectric layers are formed on both sides of the source region, as shown in Figure 3 (d).

[0152] First, SiO2 is deposited on the surface of the top layer of silicon, and then Si3N4 is deposited on the surface of the SiO2 as a protective layer;

[0153] Then, the Si3N4 protective layer is subjected to photolithography to form symmetric L-shaped groove area patterns on both sides of the source region, and an inverted T-shaped channel region is formed on the top layer of silicon, wherein the horizontal length of the L-shaped groove is 40 nm, the vertical length is 40 nm, the horizontal length of the inverted T-shaped groove is 82 nm, and the vertical length is 40 nm;

[0154] Next, the excess SiO2 and Si3N4 on the surface of the silicon are removed by chemical mechanical polishing to make the surface of the silicon flat, and then a gate dielectric layer with a thickness of 0.5 nm is deposited on the symmetric L-shaped groove area on both sides of the source region using chemical vapor deposition, wherein the process conditions of the chemical vapor deposition are: temperature 800°C, pressure in the reaction chamber 760mT, and reaction source gas Si3H4 and N2O.

[0155] In the fifth step, a drain region with a doping concentration of 5 x 1019cm-3 is prepared, as shown in 18 cm-3 -3 Figure 3 (e).

[0156] The implementation of this step is the same as step 5 of Example 1.

[0157] In the sixth step, polycrystalline silicon is deposited on the surface of the gate dielectric layer, as shown in Figure 3 (f).

[0158] ​​First, a chemical vapor deposition process is used to deposit 40 nm of polysilicon on the surface of the gate dielectric layer. Then, a reactive ion etching process is used to selectively etch the polysilicon on the horizontal part of the gate dielectric layer, leaving the polysilicon near the vertical sides of the gate dielectric layer. Finally, a polishing machine is used to mechanically polish the surface of the gate dielectric layer to remove the excess polysilicon.

[0159] The chemical vapor deposition process conditions are: temperature 580℃, pressure in the reaction chamber 800mT, reaction source gas SiH4, and protective gas He.

[0160] The reactive ion etching process conditions are: etching chamber pressure 10mT, power 20W, and 50sccm of Cl2 and 20sccm of O2 are input into the etching chamber through the gas supply system.

[0161] In the seventh step, a gate ferroelectric layer is deposited on the surface of the gate dielectric layer, as shown in Figure 3 (g)。

[0162] An atomic layer deposition method ALD is used to deposit a thickness of 10.5 nm of ferroelectric material HZO on the surface of the horizontal part of the gate insulating dielectric layer to form a ferroelectric layer. Then, a rapid thermal annealing RTA method is used to anneal the ferroelectric layer at an annealing temperature of 600℃. Finally, a chemical mechanical polishing is used to polish the surface of the ferroelectric layer to be flat.

[0163] The process conditions of the atomic layer deposition method are: temperature 350℃, reaction source gas: TEMAHf, TEMAZr, H2O, and purge gas N2.

[0164] In the eighth step, a titanium nitride layer is deposited on the surface of the ferroelectric layer, as shown in Figure 3 (h)。

[0165] The specific implementation of this step is the same as step 8 of embodiment 1.

[0166] In the ninth step, a multi-metal layer is deposited on the surface of the titanium nitride layer, as shown in Figure 4 (i)。

[0167] A hafnium metal layer with a thickness of 13 nm is deposited on the surface of the titanium nitride layer using a reactive sputtering process. Then, a aluminum metal layer with a thickness of 13 nm is deposited on the surface of the hafnium metal layer under the same conditions using a reactive sputtering process. Finally, a chemical mechanical polishing is used to polish the surface to be flat.

[0168] The process conditions of the reactive sputtering are: reaction chamber vacuum pressure 8E-6Torr, power 350W, and Ar pressure 5mTorr.

[0169] In the tenth step, a biological filling layer is made, as shown in Figure 5(j).

[0170] The specific implementation of this step is the same as step 10 in Example 1.

[0171] Step 11: Create a conductive layer, such as... Figure 6 (k).

[0172] The specific implementation of this step is the same as step 11 in Example 1.

[0173] The effects of this invention can be further illustrated by the following simulation experiments.

[0174] Simulation Experiment 1:

[0175] The transfer characteristics of the biosensor of Embodiment 1 of the present invention were simulated using computer-aided design software under conditions where biomolecules with different dielectric constants were completely filled with a biological filling layer. The results are as follows: Figure 7 As shown, the sensitivity of the biosensor in Example 1 is calculated from the simulated transfer characteristics and compared with that of a conventional TFET-based biosensor. The results are as follows. Figure 8 As shown.

[0176] Simulation Experiment 2:

[0177] The biosensor of Embodiment 2 of the present invention was simulated using computer-aided design software to demonstrate its transfer characteristics under conditions where biomolecules with different dielectric constants were completely filled with a biological filling layer. The results are as follows: Figure 9 As shown, the sensitivity of the biosensor in Embodiment 2 of the present invention is calculated from the results of the simulated transfer characteristics, and compared with that of a conventional TFET-based biosensor. The results are as follows. Figures 4 to 9 As shown.

[0178] Simulation Experiment 3:

[0179] The transfer characteristics of the biosensor of Embodiment 3 of the present invention were simulated using computer-aided design software under conditions where biomolecules with different dielectric constants were completely filled with a biological filling layer. The results are as follows: ​ As shown, the sensitivity of the biosensor in Example 3 is calculated from the simulated transfer characteristics and compared with that of a conventional TFET-based biosensor. The results are as follows. ​ As shown.

[0180] from ​The comparison results can be seen that compared with the biosensor based on the conventional TFET, the biosensor based on the inverted T-shaped negative capacitance tunneling field effect transistor has significantly improved sensitivity, and can effectively suppress the short channel effect and bipolar effect of the device. When the structure parameters of the device and the thickness of the ferroelectric layer change, the transfer characteristics of the device change. With the increase of the structure parameters of the device and the thickness of the ferroelectric layer, the sensitivity of the device increases.

[0181] The above description is only three specific examples of the present application, and does not constitute any limitation on the present application. Obviously, for those skilled in the art, after understanding the content and principles of the present application, various modifications and changes in form and details can be made without departing from the principles and structures of the present application, for example, the substrate material can be one of sapphire, SiC, diamond substrate material in addition to the SOI substrate given in the embodiment; the gate dielectric layer can be hafnium oxide gate dielectric material in addition to the silicon dioxide given in the embodiment, but these modifications and changes based on the idea of the present application are still within the protection scope of the claims of the present application.

Claims

1. An inverted-T-shaped negative capacitance tunneling field effect transistor based biosensor, comprising: The substrate (1), the isolation groove (2), the source area (3), the channel area (4), the gate insulating medium layer (5), the drain area (6), the gate ferroelectric layer (7), the gate titanium nitride layer (8), the gate metal layer (9), the biological filling layer (10), and the conductive layer (11); the channel area (4) and the drain area (6) are located on the upper surface of the substrate (1); the isolation groove (2) is located on both sides of the drain area (6); the source area (3) is located on the upper part of the channel area (4); the gate insulating medium layer (5), the gate ferroelectric layer (7), the gate titanium nitride layer (8), and the gate metal layer (9) are sequentially stacked on the upper side of the channel area (4); the biological filling layer (10) is located on the left and right sides of the vertical part of the gate insulating medium layer (5), characterized in that: The channel area (4) adopts an inverted T-shaped structure to increase the filling area of biological molecules and improve sensitivity. The gate insulating medium layer (5) adopts a symmetrical L-shaped structure and is located on both sides of the channel area (4). The gate ferroelectric layer (7) is stacked on the horizontal part of the gate insulating medium layer (5). The gate metal layer (9) is provided in two layers, and the upper layer adopts metal aluminum and the lower layer adopts metal hafnium.

2. The biosensor of claim 1, wherein, The horizontal part length and the vertical part length of the inverted T-shaped channel area are in a ratio of 1.8:1~2:

1.

3. The biosensor of claim 1, wherein, The gate insulating medium layer adopts a symmetrical L-shaped structure, and the ratio of the horizontal part length to the vertical part length is 0.7:1~1:

1.

4. The biosensor of claim 1, wherein, The gate ferroelectric layer adopts HZO ferroelectric material, and the thickness is 5.5nm~10.5nm.

5. The biosensor of claim 1, wherein, The upper and lower gate metal layers have a ratio of the upper layer metal thickness to the lower layer metal thickness of 1:0.6~1:

1.

6. The biological sensor of claim 1, characterized in that: The substrate adopts a three-layer structure of a bottom layer of silicon, an oxide buried layer, and a top layer of silicon. The source area adopts germanium semiconductor material. The channel area and the drain area both adopt silicon semiconductor material.

7. A preparation method of a biological sensor based on an inverted T-shaped negative capacitance tunneling field effect transistor, characterized in that, The method comprises the following steps: 1) An intrinsic bottom layer of silicon substrate is selected, an oxide buried layer and a top layer of silicon are sequentially deposited on the surface of the substrate to form an SOI substrate (1); 2) Photolithography and etching are performed on both sides of the top layer of silicon to stop etching at the oxide buried layer to form a shallow trench isolation region, oxide deposition is performed, an isolation groove (2) is formed, and the surface is polished flat; 3) Photolithography and etching are performed on the middle position of the top layer of silicon to form a source area recess, germanium is deposited in the recess using chemical vapor deposition, boron doping gas is introduced into the germanium for in-situ doping to form a P-type source area (3); 4) Photolithography and etching are performed on both sides of the source area (3) to form two symmetrical L-shaped recess structures, silicon dioxide is deposited on the surface of the L-shaped recess using chemical vapor deposition to form a gate insulating medium layer (5); 5) Etching away part of the silicon dioxide near the surface of the gate insulating medium layer close to the isolation groove (2) to expose the silicon surface by using a reactive ion etching process to form a symmetric drain region pattern, implanting arsenic ions in the drain region by using an ion implantation process, and then annealing to activate the impurities to form an N-type drain region (6); 6) Depositing a polysilicon dummy gate on the gate insulating medium layer by using a chemical vapor phase epitaxy deposition process; etching the polysilicon dummy gate on the horizontal part of the L-shaped gate dielectric layer by using a reactive ion etching process, and retaining the polysilicon dummy gate on the vertical part of the L-shaped gate dielectric layer; 7) Depositing HZO on the surface of the horizontal part of the L-shaped gate dielectric layer by using an atomic layer deposition method ALD, and processing the ferroelectric layer by using a rapid thermal treatment RTA method to form a gate ferroelectric layer (7); 8) Depositing a conductive material titanium nitride on the gate ferroelectric layer (7) by using a chemical vapor phase epitaxy deposition process to form a gate titanium nitride layer (8); 9) Depositing hafnium metal on the gate titanium nitride layer (8) by using a reactive sputtering process, and then depositing aluminum metal on the surface of the hafnium metal to form a gate metal layer (9); 10) Etching away the remaining polysilicon dummy gate by using a reactive ion etching process to expose the gap between the gate metal layer (9), the gate ferroelectric layer (7), and the gate titanium nitride layer (8) and the gate insulating medium layer (5) to form a biological filling layer; 11) Forming a lead hole by etching a lead window on the source region (3), the drain region (6), and the gate metal layer (9) respectively, depositing a metal as an interconnection line to form a conductive layer (11), and finally completing the preparation of the biological sensor of the inverted T-shaped negative capacitance tunneling field effect transistor.

8. The method of claim 7, wherein, In step 3), the germanium is deposited in the groove by using a vapor phase epitaxy deposition process, and the process conditions are as follows: The growth temperature is 750-800℃; The reaction source gas is GeH4; The protective gas is He; The pressure in the reaction cavity is 760mT. In steps 1), 2), and 4), the silicon dioxide is deposited by using a vapor phase epitaxy deposition process, and the process conditions are as follows:

9. The method of claim 7, wherein, The growth temperature is 600-800℃; The reaction source gas is Si3H4 and N2O; The protective gas is He; The pressure in the reaction cavity is 760mT. In step 5), the arsenic ions are implanted in the drain region by using an ion implantation process, and the process conditions are as follows:

10. The method of claim 7, wherein, The arsenic ion implantation dose is 1e14; The implantation energy is 40keV; The rapid thermal annealing temperature condition is 1000℃-1200℃. In step 7), the gate ferroelectric layer is formed by using an atomic layer deposition method, and the process conditions are as follows:

11. The method of claim 7, wherein, The growth temperature is 250-500℃; The reaction source gas is TEMAHf, TEMAZr, H2O, or O3; The purge gas is N2; The rapid thermal treatment RTA temperature is 500℃-600℃. In the etching processes in steps 2), 5), 7), and 10), the etching process conditions are as follows:

12. The method of claim 7, wherein, The reaction gas is Cl2 and O2; The pressure in the reaction cavity is 10mTorr; The power is 20W. ​

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