Method and apparatus for implementing TLB invalidation operation in multi-copy non-atomic write

Abstract

This invention discloses a method and apparatus for implementing TLB obsolescence operations for multi-replica non-atomic writes. It provides a TLB obsolescence processing module comprising three request queues, a TLB obsolescence response counter, and a response channel filter. Through a unique protocol flow, processing method, and counting mechanism, it ensures that all preceding write operations have been truly completed by the time the TLB obsolescence instruction is executed, thus solving the implementation problem of TLB obsolescence operations in Non-MCAW. The completion of preceding write operations is marked by the arrival of the storage consistency point. Furthermore, the problem of determining the completion mark of write operations is solved by adding a two-level broadcast protocol flow and a TLB obsolescence response counter. This approach offers advantages such as reliable judgment results and low hardware implementation overhead.

Description

Technical Field

[0001] This invention belongs to the field of non-atomic write TLB obsolescence operation technology, and in particular relates to a method and apparatus for implementing multi-copy non-atomic write TLB obsolescence operation. Background Technology

[0002] Modern microprocessors typically employ a multi-core, multi-threaded shared memory architecture, and memory consistency is fundamental to the correct execution of parallel programs within this architecture. Memory consistency defines the ordering rules for memory access operations at different addresses. Depending on the allowed ordering rules, there are various memory consistency implementation models, such as sequential consistency, Total Store Order (TSO), and relaxed consistency. Because different memory consistency models define different valid memory orders, software programmers must understand the memory consistency model used by the multi-core, multi-threaded shared memory architecture in order to write correct parallel programs on that architecture.

[0003] To improve memory access performance, modern multi-core, multi-threaded microprocessors typically implement multi-level caches. The introduction of caches can lead to inconsistencies between multiple data copies at the same address. To address this, multi-core, multi-threaded microprocessors generally employ cache coherence protocols to ensure the consistency of data copies across different caches. The implementation of a cache coherence protocol typically requires a Cache Agent (CA), a Home Agent (HA; most modern multi-core, multi-threaded microprocessors use directory-based cache coherence protocols), and an I / O Agent (IA). The CA caches data copies, issues access requests, receives data responses, and listens for requests (used to invalidate data copies or retrieve the latest data). The HA records the status of data copies and receives access requests, issues data responses, and listens for requests. The IA does not cache data copies but issues access requests and data responses, receives access requests, data responses, and listens for requests (used to retrieve the latest data). As can be seen, to avoid protocol deadlock, the implementation of a coherence protocol requires at least three message channels: a request channel, a response channel, and a listener channel, used to transmit access requests, data responses, and listener requests, respectively. CA, HA, and IA are connected through an on-chip interconnect network, which is generally a sequential network (i.e., messages sent from the same source agent will arrive at the same destination agent in sequence).

[0004] In multi-core, multi-threaded microprocessors, there may be multiple levels of cache between the processor core and memory. The latest write data issued by the processor core hardware thread needs to pass through multiple caches before finally reaching memory. This results in some caches containing the latest data copy, while others contain older data copies, introducing atomicity issues for write operations. Besides defining valid storage order rules, storage consistency also requires defining atomic properties of write operations to describe this atomicity problem. Based on the different times when different hardware threads can observe the new value of the written data, the atomicity properties of write operations can be divided into two categories: multi-copy atomic write (MCAW) and non-multi-copy atomic write (Non-MCAW). MCAW guarantees that when a hardware thread observes a write operation, and that hardware thread is not the initiator of the write operation, all other threads can observe that write operation. MCAW ensures that the write data of a hardware thread can either be observed simultaneously by other hardware threads (i.e., all can read the new value) or none can be observed (i.e., all can only read the old value), indicating that the write operation has atomic characteristics. Non-MCAW cannot guarantee the atomicity of write operations. When a hardware thread observes a write operation, other threads may not be able to observe the write operation. That is, some hardware threads can read the new value of the write operation, while others can only read the old value of the write operation.

[0005] Microprocessor architectures using the MCAW (Write-Back-Away) implementation include x86 and ARMv8. These architectures typically employ a write-back cache, and in the cache coherence protocol, a new value can only be written to the cache after write access has been granted (i.e., all other cached data copies have been invalidated). Because MCAW allows software engineers to see a view of write operations with atomic characteristics, it simplifies parallel programming. However, these architectures incur significant hardware costs to support atomic writes. Microprocessor architectures using the non-MCAW implementation are primarily the POWER series processors. These architectures typically use a write-through cache, and in the cache coherence protocol, new values ​​can be directly written to the cache without needing to acquire write access or wait for the invalidation of all other cached data copies. Non-MCAW simplifies hardware design but increases the difficulty of parallel programming because software engineers now see a view of write operations with non-atomic characteristics.

[0006] Modern microprocessor cores typically implement a Translation Lookaside Buffer (TLB) to cache frequently used virtual address-to-physical address mappings, accelerating the execution speed of the operating system's virtual memory management operations. The operating system generally maintains the virtual address-to-physical address mapping for each allocated page in the page table, on a page-by-page basis. When a page is freed or its mapping changes, the entry in the TLB used to cache that mapping needs to be invalidated. Since each processor core's TLB may cache the virtual address-to-physical address mapping for the same page, when that page is freed or its mapping changes, all TLB entries caching that mapping in all processor cores need to be invalidated (i.e., TLB Shootdown) to ensure that the page address mappings cached in all TLBs remain consistent with the page tables maintained by the operating system. To shorten the execution time of TLB invalidation operations, modern high-performance microprocessors generally support TLB Shootdown operations in hardware: the processor core executing the TLB Shootdown instruction broadcasts a TLB invalidation request to all other processor cores; when a processor core receives a TLB invalidation request, it invalidates the corresponding entry in its local TLB and then returns a TLB invalidation response to the processor core that initiated the TLB Shootdown; once the processor core executing the TLB Shootdown instruction has collected all the TLB invalidation responses and completed its own TLB invalidation operation, the TLB Shootdown instruction is executed.

[0007] When the mapping between the virtual address and physical address of a page changes, it is essential to ensure that the new write operation data after the change overwrites the old write operation data before the change, so that subsequent new read operations can obtain the latest data. Therefore, when the processor core receives a TLB invalidation request, in addition to invalidating the corresponding TLB entry, it must wait until all preceding write operations have been completed before returning a TLB invalidation response. In modern microprocessors, HA and IA are generally memory consistency points for write operations, meaning that write operation data arriving at HA or IA first will be overwritten by later write operation data. Therefore, the completion of preceding write operations issued by the processor core is marked by all these write operations having reached the microprocessor's memory consistency point HA or IA.

[0008] Microprocessor architectures using the MCAW (Multi-Consistency Execution) approach can relatively easily determine the write operation completion flag because, in this architecture, a write operation can only be executed after write privileges have been granted. Since write privileges are issued by the memory consistency point (HA) or IA (Integration Aspect), when the processor core completes the write operation, the write operation has definitely reached the memory consistency point. Therefore, processor cores based on the MCAW implementation can easily determine the write operation completion flag, thus easily implementing TLB (Telematics Block) invalidation instructions. However, for microprocessor architectures using the Non-MCAW implementation, determining the write operation completion flag is more difficult because, in this architecture, the execution of a write operation does not require obtaining write privileges. As long as the processor core issues a write operation, it means that the write operation has been completed, but at this time, the write operation may not have reached the memory consistency point (HA) or IA.

[0009] Prior to this application, the applicant had proposed a solution specifically for addressing the strong synchronization semantics implementation problem in Non-MCAW microprocessor architectures—a method and apparatus for implementing memory order synchronization operations for multi-copy non-atomic writes [Publication No.: CN113900968A]. This solution considered that for Non-MCAW microprocessor architectures, when the processor core's cache has processed all memory access requests, it can only guarantee that all read access responses have returned, but cannot guarantee global write visibility. Therefore, it proposed a solution to address the strong synchronization semantics implementation problem. However, this solution only solves the strong synchronization semantics implementation problem and cannot solve the implementation problem of TLB invalidation operations in Non-MCAW scenarios, nor can it solve the TLB invalidation operation implementation problem in Non-MCAW scenarios by using the processing method of the synchronization processing module. Furthermore, no existing technology has published a method for implementing TLB invalidation operations in Non-MCAW scenarios. Summary of the Invention

[0010] The purpose of this invention is to address the above-mentioned problems by providing a method and apparatus for implementing TLB invalidation operations for multiple copies of non-atomic writes.

[0011] To achieve the above objectives, the present invention adopts the following technical solutions:

[0012] A device for implementing TLB obsolescence operations with multiple copies and non-atomic writes includes a microprocessor architecture that adopts a non-atomic write implementation method. The microprocessor architecture includes several CAs, several HAs, and several IAs. The several CAs are connected to the several HAs and several IAs through an on-chip interconnect network. Each CA corresponds to a TLB obsolescence processing module. Each TLB obsolescence processing module is connected between its corresponding CA and the on-chip interconnect network.

[0013] The on-chip interconnect network described above has at least three message channels: a request channel, a response channel, and a listening channel.

[0014] The TLB obsolescence processing module includes a processor core request queue, a TLB obsolescence listening request queue, a non-TLB obsolescence listening request queue, a TLB obsolescence response counter, and a response channel filter.

[0015] The processor core request queue is used to store access requests from the local CA connected to this TLB obsolescence processing module.

[0016] The TLB obsolescence listener request queue is used to store TLB obsolescence listener requests converted from TLB obsolescence requests from the on-chip interconnect network. That is, when the TLB obsolescence processing module is not the source TLB obsolescence processing module, it is used to store TLB obsolescence listener requests in this case. It also stores TLB obsolescence listener requests converted from TLB obsolescence requests from the processor core request queue. When the TLB obsolescence processing module is the source TLB obsolescence processing module, it is used to store TLB obsolescence listener requests in this case.

[0017] Non-TLB invalidated listener request queue, used to store listener requests from on-chip interconnect network;

[0018] The TLB invalidation response counter is used to record the number of TLB invalidation responses that the local CA has not yet received after executing the TLB invalidation instruction. When the TLB invalidation response counter reaches zero, a TLB invalidation completion response is generated and sent to the local CA.

[0019] The response channel filter is used to identify TLB invalidation rejection response messages and TLB invalidation completion response messages from the response messages sent from the on-chip interconnect network to the local CA, and to perform corresponding decrement operations on the TLB invalidation response counter. The remaining response messages are sent directly to the local CA. It receives TLB invalidation rejection requests from the processor core request queue, generates TLB invalidation rejection response messages to be sent to the source TLB invalidation processing module, and sends them to the on-chip interconnect network through the response channel.

[0020] In the above-mentioned TLB invalidation operation implementation device with multiple copies and non-atomic write, a listening request is scheduled from the TLB invalidation listening request queue and the non-TLB invalidation listening request queue and sent to the local CA using a fair round-robin scheduling method.

[0021] In the aforementioned implementation device for TLB obsolescence operations involving multiple copies and non-atomic writes, the TLB obsolescence response counter is initialized by TLB obsolescence requests from the processor core request queue. When the TLB obsolescence processing module receives a TLB obsolescence request from a local CA, it initializes the TLB obsolescence response counter to m*(n+k), where m is the number of CAs, n is the number of HAs, and k is the number of IAs.

[0022] When a TLB invalidation rejection request is received from the processor core request queue, the TLB invalidation response counter is decremented by n+k;

[0023] When a TLB invalidation rejection response message is received from the response channel filter, the TLB invalidation response counter is decremented by n+k;

[0024] When a TLB invalidation completion response message is received from the response channel filter, the TLB invalidation response counter is decremented by 1.

[0025] A method for implementing TLB invalidation operations for multi-copy non-atomic writes includes the following steps:

[0026] When the S1.TLB obsolescence processing module receives a TLB obsolescence request from the local CA,

[0027] Initialize the TLB invalidation response counter.

[0028] The TLB obsolescence request message is broadcast to all other TLB obsolescence processing modules via the request channel.

[0029] Send a TLB cancellation request to the local CA;

[0030] S2. After receiving the TLB obsolescence request message from the on-chip interconnect network, each TLB obsolescence processing module sends a TLB obsolescence listening request to its local CA.

[0031] S3. When each CA receives a TLB invalidation listening request, it invalidates the relevant TLB entries and waits for the preceding write access requests to be sent. Then, it broadcasts the TLB invalidation completion request message to all storage consistency points HA and IA through the request channel.

[0032] After receiving the TLB cancellation completion request message, S4.HA and IA return a TLB cancellation completion response to the source TLB cancellation processing module that initiated the TLB cancellation request.

[0033] S5. Each time a TLB obsolescence completion response is received, the TLB obsolescence response counter of the source TLB obsolescence processing module counts once, until all TLB obsolescence completion responses are received, and then a TLB obsolescence completion response is returned to the local CA.

[0034] In the above implementation method of TLB invalidation operation for multiple copies of non-atomic write, in step S1, the value of the TLB invalidation response counter is initialized to m*(n+k), where m is the number of CAs, n is the number of HAs, and k is the number of IAs.

[0035] In step S5, for each TLB obsolescence completion response received, the TLB obsolescence response counter of the source TLB obsolescence processing module is decremented by 1. If the TLB obsolescence response counter is zero after the decrement operation is completed, it is considered that all TLB obsolescence completion responses have been received.

[0036] In the above-described method for implementing TLB invalidation operations for multiple replicas and non-atomic writes, in step S2, when the CA receives a TLB invalidation listening request, if the CA determines that the virtual address to physical address mapping relationship corresponding to the TLB invalidation listening request has never been used, then the CA will not perform the TLB-related entry invalidation operation, but will directly return a TLB invalidation rejection response to the source TLB invalidation processing module through the response channel.

[0037] In the above implementation method for TLB invalidation operation of multiple copies non-atomic write, in step S3, when CA receives a listening request sent by the corresponding TLB invalidation processing module, it checks whether the request is a TLB invalidation listening request.

[0038] If yes, continue to determine whether the mapping relationship between the virtual address and the physical address corresponding to the TLB listening request is used. If yes, then invalidate the corresponding TLB entry, wait for all preceding write access requests to be sent, and then send a TLB invalidation completion request to the TLB invalidation processing module. If no, then send a TLB invalidation rejection request to the TLB invalidation processing module.

[0039] If the request is not a TLB invalidation listening request, then the request will be processed according to the original cache consistency protocol.

[0040] In the above implementation method of TLB invalidation operation for multi-copy non-atomic write, when the TLB invalidation processing module receives an access request from the local CA connected to it, it detects the request type.

[0041] If the request is a TLB invalidation request, the TLB invalidation response counter is initialized; a TLB invalidation listening request to be sent to the local CA is generated and stored in the TLB invalidation listening request queue, and the listening request is sent to the local CA after the scheduling is successful; a TLB invalidation request message to be sent to all other TLB invalidation processing modules is generated, and the TLB invalidation request message is sent to the on-chip interconnection network through the request channel.

[0042] If the request is a TLB cancellation completion request, a TLB cancellation completion request message is generated and sent to all HAs and IAs, and the TLB cancellation completion request message is sent to the on-chip interconnect network through the on-chip interconnect network.

[0043] If the request is a TLB cancellation rejection request and the initiator of the TLB cancellation request is the local CA, then the TLB cancellation response counter is decremented by n+k. If the TLB cancellation response counter is zero after the decrement operation is completed, then a TLB cancellation completion response is sent to the local CA.

[0044] If the request is a TLB invalidation rejection request and the initiator of the TLB invalidation request is not the local CA, a TLB invalidation rejection response message is generated and sent to the source TLB invalidation processing module, and the TLB invalidation rejection response message is sent to the on-chip interconnection network through the response channel.

[0045] If it is another type of request, the request message is sent to the on-chip interconnect network through the request channel.

[0046] In the above implementation method of TLB obsolescence operation for multiple copies of non-atomic write, when the TLB obsolescence processing module receives a response message from the on-chip interconnect network, it detects the response type.

[0047] If the response is a TLB invalidation rejection response message, the TLB invalidation response counter is decremented by n+k. If the response is a TLB invalidation completion response message, the TLB invalidation response counter is decremented by 1. If the TLB invalidation response counter is zero after the decrement operation is completed, a TLB invalidation completion response is sent to the local CA.

[0048] If it is another response type, the response is sent to the local CA.

[0049] In the above implementation method of TLB invalidation operation for multi-replica non-atomic write, when the TLB invalidation processing module receives a listening message, it stores the message in the non-TLB invalidation listening request queue. When it receives a TLB invalidation request message, it stores the message in the TLB invalidation listening request queue. It selects one of the two queues using a fair round-robin scheduling method and sends the listening request at the head of the queue to the local CA.

[0050] When HA or IA receives a request message from the on-chip interconnect network, if the message is a TLB obsolescence completion request message, it returns a TLB obsolescence completion response to the source TLB obsolescence processing module; otherwise, it processes the request message according to the original cache coherence protocol.

[0051] The advantages of this invention are as follows: It provides a TLB obsolescence processing module including three request queues, a TLB obsolescence response counter, and a response channel filter. Through a unique protocol flow, processing method, and counting method, it ensures that all preceding write operations have been truly completed when the TLB obsolescence instruction is executed, thus solving the implementation problem of TLB obsolescence operations in Non-MCAW. It uses the arrival of the storage consistency point of the write operation as the completion mark of the preceding write operation. Furthermore, by adding a two-level broadcast protocol flow and a TLB obsolescence response counter, it solves the problem of determining the write operation completion mark, which has the advantages of reliable judgment results and low hardware implementation overhead. Attached Figure Description

[0052] Figure 1 A schematic diagram of a multi-core, multi-threaded microprocessor architecture without a TLB obsolescence handling module;

[0053] Figure 2 This is a schematic diagram of the multi-core, multi-threaded microprocessor architecture with a TLB obsolescence processing module of the present invention.

[0054] Figure 3 This is a flowchart illustrating the CA's handling of listening requests in this invention.

[0055] Figure 4 This is a flowchart of the access request processing of the TLB invalidation processing module in this invention;

[0056] Figure 5 This is a flowchart of the response message processing of the TLB obsolescence processing module in this invention;

[0057] Figure 6 This is a flowchart of the TLB obsolescence processing module's listening message and TLB obsolescence request message processing in this invention.

[0058] Figure 7 This is a flowchart of the request message processing for HA and IA in this invention;

[0059] Figure 8 This is a schematic diagram of the implementation device of the TLB obsolescence processing module in this invention;

[0060] Figure 9 This is an example of a TLB obsolescence processing protocol message flow diagram in this invention.

[0061] Cache Proxy - CA; Directory Proxy - HA; IO Proxy - IA. Detailed Implementation

[0062] The following is a further explanation of this scheme with reference to the accompanying drawings:

[0063] like Figure 1-9As shown, this invention addresses the implementation problem of TLB invalidation instructions for Non-MCAW by providing a method and apparatus for implementing TLB invalidation operations for multi-copy non-atomic writes.

[0064] Figure 1 The diagram illustrates a multi-core, multi-threaded microprocessor architecture to which this invention is applicable. The multi-core, multi-threaded microprocessor architecture consists of m CAs, n HAs, and k IAs, connected via an on-chip interconnect network. The CAs, HAs, IAs, and the on-chip interconnect network jointly implement the cache coherence protocol, ensuring the consistency of cached data copies. A CA (Cache Agent) typically consists of a processor core, a Level 1 instruction cache, and a Level 1 data cache (write-through cache). A HA (Directory Agent) typically consists of a Level 2 cache, a directory controller, and a storage controller. An IA (I / O Agent) typically consists of an I / O controller and I / O devices. The on-chip interconnect network must provide at least three message channels for the cache coherence protocol: a request channel, a response channel, and a listener channel, capable of transmitting request messages, response messages, and listener messages respectively, to resolve protocol deadlock issues. To improve protocol performance, the on-chip interconnect network can also provide more message channels for the cache coherence protocol; however, for implementing TLB invalidation operations, this invention only needs to use the request channel, response channel, and listener channel. The on-chip interconnect network is a sequential network, where messages sent from the same source node (CA, HA, or IA) will arrive at the same destination node (CA, HA, or IA) in sequence.

[0065] In the Non-MCAW scenario, when the CA receives a TLB invalidation request and returns a TLB invalidation response, the CA can only guarantee that all previously issued write access requests have been sent to the on-chip interconnect network, but cannot guarantee that these write access requests have reached the storage consistency point HA or IA, thus failing to guarantee the actual completion of the write operation. Therefore, the TLB invalidation implementation method in the MCAW scenario cannot be directly applied to the Non-MCAW scenario.

[0066] like Figure 2 As shown in the figure, this diagram illustrates a multi-core, multi-threaded processor architecture with a TLB obsolescence module. To implement TLB obsolescence operations with minimal hardware overhead and reduce modifications to the CA (Computer Access Controller), Figure 2A TLB obsolescence processing module was added between the CA and the on-chip interconnect network to implement the TLB obsolescence function. The key to implementing the TLB obsolescence function lies in ensuring that when the CA executing the TLB obsolescence instruction receives all TLB obsolescence responses, all write access requests issued prior to the CA have reached the corresponding memory consistency point HA or IA. The TLB obsolescence processing module can leverage the existing cache consistency protocol, using two-level broadcasting and TLB obsolescence response counting to achieve this function.

[0067] The TLB obsolescence handling module implements a TLB obsolescence response counter to record the number of TLB obsolescence responses that have not yet been received after the local CA has executed a TLB obsolescence instruction. Generally, a processor core cannot execute a new TLB obsolescence instruction until the preceding TLB obsolescence instruction has been completed; therefore, only one TLB obsolescence response counter is needed. When the TLB obsolescence handling module receives a TLB obsolescence request from the local CA, it initializes the TLB obsolescence response counter and broadcasts the TLB obsolescence request message to all other TLB obsolescence handling modules via the request channel. It also sends a TLB obsolescence listening request to the local CA. Upon receiving a TLB obsolescence request message from the on-chip interconnect network, the TLB obsolescence handling module sends a TLB obsolescence listening request to the local CA. Each CA (including the local CA connected to the source TLB obsolescence handling module), upon receiving the TLB obsolescence listening request, obsolescences the relevant TLB entries, waits for the preceding write access request to be completed, and then broadcasts a TLB obsolescence completion request message to all memory consistency points (HA and IA) via the request channel. After receiving the TLB obsolescence completion request message, HA and IA return a TLB obsolescence completion response to the source TLB obsolescence processing module that initiated the TLB obsolescence request. The source TLB obsolescence processing module is the TLB obsolescence processing module that received the TLB obsolescence request from the local CA. After collecting all TLB obsolescence completion responses, the source TLB obsolescence processing module returns a TLB obsolescence completion response to the local CA. The broadcast operation of the second-level TLB obsolescence completion message ensures that before HA or IA returns the TLB obsolescence completion response, the preceding write access request of each CA has reached the corresponding storage consistency point HA or IA (because the on-chip interconnect network is a sequential network, when a TLB obsolescence completion message sent by a CA reaches a certain HA or IA, the preceding write access request sent by that CA destined for that HA or IA must also have reached it). This ensures that when the source TLB obsolescence processing module collects all TLB obsolescence completion responses, the preceding write access requests of all CAs have truly been completed. This demonstrates that the TLB obsolescence process in the Non-MCAW scenario is achieved through two-level broadcasting and by moving the determination of the write access request completion flag from the CA to the storage consistency points HA and IA. Since there are m CAs, n HAs, and k IAs in the system, the source TLB obsolescence processing module needs to collect m*(n+k) TLB obsolescence responses.

[0068] When a CA receives a TLB invalidation listener request, if the CA can determine that it has never used the virtual address-to-physical address mapping corresponding to the TLB invalidation listener request, then the CA does not need to perform TLB entry invalidation and the second-level broadcast operation, because the preceding write access request never performed a write access to the relevant physical address. For example, a multi-core, multi-threaded microprocessor may operate in logical partition mode, and different CAs may belong to different logical partitions. CAs belonging to different logical partitions will not use the same virtual address-to-physical address mapping. Therefore, when a CA receives a TLB invalidation listener request initiated by a CA from a different logical partition, it can skip the TLB invalidation-related operations and the second-level broadcast operation, and directly return a TLB invalidation rejection response, thereby accelerating the TLB invalidation process.

[0069] like Figure 3 As shown in the diagram, this illustrates the processing flow of the CA handling the listening request. When the CA receives a listening request from the connected TLB obsolescence processing module, it checks whether the request is a TLB obsolescence listening request.

[0070] If the request is a TLB invalidation listener request, it is determined whether the virtual address to physical address mapping corresponding to the TLB listener request is used. If it is used, the corresponding TLB entry is invalidated, and after all preceding write access requests have been sent, a TLB invalidation completion request is sent to the TLB invalidation processing module. The TLB invalidation processing module broadcasts the TLB invalidation completion request message to all storage consistency points (HAs) and IAs through the request channel. If it is not used, a TLB invalidation rejection request is sent to the TLB invalidation processing module, which directly returns a TLB invalidation rejection response to the source TLB invalidation processing module through the response channel. Communication between each CA and the on-chip interconnect network is forwarded through the corresponding TLB invalidation processing module.

[0071] If the request is not a TLB invalidation listener request, then the request is processed according to the original cache consistency protocol.

[0072] like Figure 4 As shown in the diagram, this illustrates the processing flow of the TLB deregistration module in handling access requests from the local CA. When the TLB deregistration module receives an access request from the local CA it is connected to, it checks the request type.

[0073] If the request is a TLB obsolescence request, the TLB obsolescence response counter is initialized and set to m*(n+k) (where m is the number of CAs, n is the number of HAs, and k is the number of IAs). A TLB obsolescence listening request is generated for the local CA, and the request is stored in the TLB obsolescence listening request queue. After successful scheduling, the listening request is sent to the local CA. A TLB obsolescence request message is generated for all other TLB obsolescence processing modules, and the TLB obsolescence request message is sent to the on-chip interconnect network through the request channel.

[0074] If the request is a TLB obsolescence completion request, a TLB obsolescence completion request message is generated and sent to all HAs and IAs, and then sent to the on-chip interconnect network through the request channel.

[0075] If the request is a TLB cancellation rejection request and the initiator of the TLB cancellation request is the local CA, then the TLB cancellation response counter is decremented by n+k. If the TLB cancellation response counter is zero after the decrement operation is completed, then a TLB cancellation completion response is sent to the local CA.

[0076] If the request is a TLB invalidation rejection request and the initiator of the TLB invalidation request is not the local CA, a TLB invalidation rejection response message is generated and sent to the source TLB invalidation processing module, and the TLB invalidation rejection response message is sent to the on-chip interconnect network through the response channel.

[0077] If it is another type of request, the request message is sent to the on-chip interconnect network through the request channel.

[0078] like Figure 5 As shown in the figure, this diagram illustrates the processing flow of the TLB obsolescence module when handling response messages from the on-chip interconnect network. When the TLB obsolescence module receives a response message from the on-chip interconnect network, it detects the response type.

[0079] If the response is a TLB invalidation rejection response message, then the TLB invalidation response counter is decremented by n+k. If the TLB invalidation response counter is zero after the decrement operation is completed, then a TLB invalidation completion response is sent to the local CA.

[0080] If the response is a TLB cancellation completion response message, the TLB cancellation response counter is decremented by 1. If the TLB cancellation response counter is zero after the decrement operation is completed, a TLB cancellation completion response is sent to the local CA.

[0081] If it is another response type, the response will be sent to the local CA.

[0082] like Figure 6As shown in the diagram, this illustrates the processing flow of the TLB obsolescence module in handling listener messages and TLB obsolescence request messages from the on-chip interconnect network. When a listener message is received, it is stored in the non-TLB obsolescence listener request queue; when a TLB obsolescence request message is received, it is stored in the TLB obsolescence listener request queue. A fair round-robin scheduling method is used to select one of the two queues, and the listener request at the head of that queue is sent to the local CA.

[0083] As can be seen above, TLB invalidation request messages from the request channel are converted into TLB invalidation listening requests and sent to the local CA, causing the request channel to depend on the listening channel. Conversely, TLB invalidation listening requests may generate TLB invalidation completion request messages, causing the listening channel to depend on the request channel. This interdependence between the request and listening channels can lead to protocol deadlock. To prevent this deadlock, the TLB invalidation processing module is designed to store all possible input TLB invalidation request messages. Since each CA can only send one TLB invalidation request at a time, setting the depth of the TLB invalidation listening request queue to m (i.e., the number of all CAs) is sufficient to store all TLB invalidation request messages.

[0084] like Figure 7 As shown in the diagram, this illustrates the processing flow of request messages from the on-chip interconnect network (HCB) by the HA and IA. When the HA or IA receives a request message from the HCB, if the message is a TLB obsolescence completion request message, it returns a TLB obsolescence completion response to the source TLB obsolescence processing module that initiated the TLB obsolescence request; otherwise, it processes the request message according to the original cache coherence protocol.

[0085] like Figure 8 As shown in the figure, this diagram illustrates the device of the TLB obsolescence processing module, which implements the aforementioned TLB obsolescence operation method for multi-copy non-atomic writes. Specifically, the TLB obsolescence processing module includes a processor core request queue, a TLB obsolescence listening request queue, a non-TLB obsolescence listening request queue, a TLB obsolescence response counter, and a response channel filter.

[0086] The processor core request queue stores access requests from the connected local CA; the TLB invalidation listener request queue stores TLB invalidation listener requests converted from TLB invalidation request messages from the on-chip interconnect network, and also stores TLB invalidation listener requests converted from TLB invalidation requests from the processor core request queue; the non-TLB invalidation listener request queue stores listener requests from the on-chip interconnect network. A listener request is scheduled from the TLB invalidation listener request queue and the non-TLB invalidation listener request queue using a fair round-robin scheduling method and sent to the local CA.

[0087] The TLB invalidation response counter records the number of TLB invalidation responses that the local CA has not yet received after executing a TLB invalidation instruction. It is initialized by TLB invalidation requests from the processor core request queue. A TLB invalidation rejection request from the processor core request queue may decrement the TLB invalidation response counter by n+k. If the TLB invalidation command was not initiated by the local CA, the rejection request generates a TLB invalidation rejection response and sends it to the source TLB invalidation processing module via the response channel filter; in this case, the TLB invalidation response counter remains unchanged. If the TLB invalidation command was initiated by the local CA, the rejection request decrements the counter by n+k. A TLB invalidation rejection response message from the response channel filter decrements the counter by n+k, and a TLB invalidation completion response message from the response channel filter decrements the counter by 1. When the TLB invalidation response counter reaches zero, a TLB invalidation completion response is generated and sent to the local CA.

[0088] The response channel filter identifies TLB invalidation rejection and TLB invalidation completion response messages from the response messages sent from the on-chip interconnect network to the local CA, and decrements the TLB invalidation response counter accordingly. The remaining response messages are sent directly to the local CA. The response channel filter also receives TLB invalidation rejection requests from the processor core request queue, generates TLB invalidation rejection response messages for the source TLB invalidation processing module, and sends them to the on-chip interconnect network via the response channel.

[0089] like Figure 9 As shown in the figure, this provides an example of a TLB obsolescence protocol message flow diagram. Assume a multi-core, multi-threaded microprocessor consists of three CAs (CA0, CA1, CA2), two HAs (HA0, HA1), one IA, and an on-chip interconnect network. Each CA is connected to the on-chip interconnect network through a corresponding TLB obsolescence processing module. Specifically, CA0 is connected to TLB obsolescence processing module 0, CA1 is connected to TLB obsolescence processing module 1, and CA2 is connected to TLB obsolescence processing module 2.

[0090] CA0 executed the TLB obliteration instruction and sent a TLB obliteration request TLBIBN_REQ to the TLB obliteration processing module 0.

[0091] After receiving TLBINV_REQ, TLB obsolescence processing module 0 sets the TLB obsolescence response counter CNT to 9, sends a TLB obsolescence listening request TLBINV_SNP to CA0, and sends a TLB obsolescence request message TLBINV_REQ to TLB obsolescence processing module 1 and TLB obsolescence processing module 2.

[0092] After receiving TLBINV_REQ, TLB obsolescence processing module 1 and TLB obsolescence processing module 2 send TLB obsolescence listening requests TLBINV_SNP to CA1 and CA2 respectively.

[0093] After receiving TLB BINV_SNP, CA0 sends a TLB cancellation completion request CPLT_REQ to TLB cancellation processing module 0; after receiving TLB BINV_SNP, CA1 sends a TLB cancellation rejection request REJECT_REQ to TLB cancellation processing module 1; after receiving TLB BINV_SNP, CA2 sends a TLB cancellation completion request CPLT_REQ to TLB cancellation processing module 2.

[0094] After receiving CPLT_REQ, TLB cancellation processing module 0 sends TLB cancellation completion request messages CPLT_REQ to HA0, HA1, and IA respectively; after receiving REJECT_REQ, TLB cancellation processing module 1 sends TLB cancellation rejection response messages REJECT_RSP to TLB cancellation processing module 0; after receiving CPLT_REQ, TLB cancellation processing module 2 sends TLB cancellation completion request messages CPLT_REQ to HA0, HA1, and IA respectively.

[0095] Each time HA0, HA1, and IA receive a CPLT_REQ, they send a TLB obsolescence completion response message CPLT_RSP to TLB obsolescence processing module 0.

[0096] After receiving a REJECT_RSP, the TLB obsolescence processing module 0 decrements the TLB obsolescence response counter CNT by 3, and decrements CNT by 1 for each received CPLT_RSP. When CNT reaches 0, the TLB obsolescence processing module 0 returns a TLB obsolescence completion response TLBINV_RSP to CA0.

[0097] Note that in this article, "local" means "corresponding to" or "connected to". For example, the local CA of a TLB obsolescence processing module X refers to the CA corresponding to the TLB obsolescence processing module X.

[0098] The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

Claims

1. A device for implementing TLB invalidation operation of multi-copy non-atomic write, comprising a microprocessor architecture using non-atomic write implementation mode, the microprocessor architecture comprising a plurality of CAs, a plurality of HAs and a plurality of IAs, the plurality of CAs being connected to the plurality of HAs and the plurality of IAs through an on-chip interconnection network, characterized in that, the device comprises: a TLB invalidation operation implementation unit, configured to implement the TLB invalidation operation of multi-copy non-atomic write by using the non-atomic write implementation mode. Each CA corresponds to a TLB invalidation processing module, and each TLB invalidation processing module is connected between the corresponding CA and an on-chip interconnection network; The on-chip interconnection network has at least three message channels, i.e., a request channel, a response channel and a monitoring channel; The TLB invalidation processing module comprises a processor core request queue, a TLB invalidation monitoring request queue, a non-TLB invalidation monitoring request queue, a TLB invalidation response counter and a response channel filter; The processor core request queue is used for storing access requests sent by the local CA connected to the TLB invalidation processing module; The TLB invalidation monitoring request queue is used for storing TLB invalidation monitoring requests converted from TLB invalidation requests from the on-chip interconnection network and TLB invalidation monitoring requests converted from TLB invalidation requests from the processor core request queue; The non-TLB invalidation monitoring request queue is used for storing monitoring requests from the on-chip interconnection network; The TLB invalidation response counter is used for recording the number of TLB invalidation responses not received by the local CA after the execution of a TLB invalidation instruction, and when the TLB invalidation response counter is zero, a TLB invalidation completion response is generated and sent to the local CA; The response channel filter is used for identifying TLB invalidation rejection response messages and TLB invalidation completion response messages from response messages sent by the on-chip interconnection network to the local CA, and performing corresponding subtraction operations on the TLB invalidation response counter, wherein if the message is a TLB invalidation rejection response message, the TLB invalidation response counter is subtracted by n+k, and if the message is a TLB invalidation completion response message, the TLB invalidation response counter is subtracted by 1, n is the number of HAs, and k is the number of IAs; The rest of the response messages are directly sent to the local CA; the TLB invalidation rejection request from the processor core request queue is received, a TLB invalidation rejection response message is generated and sent to the source TLB invalidation processing module, and the message is sent to the on-chip interconnection network through the response channel.

2. The apparatus of claim 1, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. A monitoring request is dispatched from the TLB invalidation monitoring request queue and the non-TLB invalidation monitoring request queue to the local CA in a fair round-robin scheduling manner.

3. The apparatus of claim 1, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. The TLB invalidation response counter is initialized by a TLB invalidation request from the processor core request queue, and when the TLB invalidation processing module receives a TLB invalidation request sent by the local CA, the TLB invalidation response counter is initialized as m*(n+k), m is the number of CAs, n is the number of HAs, and k is the number of IAs, and When a TLB invalidation rejection request from the processor core request queue is received, the TLB invalidation response counter is subtracted by n+k; When a TLB invalidation rejection response message from the response channel filter is received, the TLB invalidation response counter is subtracted by n+k; When a TLB invalidation completion response message from the response channel filter is received, the TLB invalidation response counter is subtracted by 1.

4. A method for implementing a TLB invalidation operation for multi-copy non-atomic write, characterized in that, The method comprises the following steps: S1. When the TLB invalidation processing module receives a TLB invalidation request sent by the local CA, initializes the TLB invalidation response counter, broadcasts a TLB invalidation request message to all other TLB invalidation processing modules through the request channel, sending a TLB invalidation monitoring request to the local CA; S2. After each TLB invalidation processing module receives a TLB invalidation request message from the on-chip interconnection network, it sends a TLB invalidation monitoring request to the local CA; S3. When each CA receives a TLB invalidation monitoring request, it invalidates the TLB related table entries, waits for the previous write access request to be sent, and then broadcasts a TLB invalidation completion request message to all storage consistency points HA and IA through the request channel; S4. After the HA and IA receive the invalidation completion request message, they return a TLB invalidation completion response to the source TLB invalidation processing module that initiated the TLB invalidation request; S5. After receiving one TLB invalidation completion response, the TLB invalidation response counter of the source TLB invalidation processing module is decremented by 1. If the TLB invalidation response counter is zero after the decrement operation is completed, it is considered that all TLB invalidation completion responses have been received, and a TLB invalidation completion response is returned to the local CA.

5. The method of claim 4, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. In step S1, the value of the TLB invalidation response counter is initialized to m*(n+k), where m is the number of CAs, n is the number of HAs, and k is the number of IAs.

6. The method of claim 5, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. In step S2, when the CA receives a TLB invalidation monitoring request, if the CA determines that the virtual address to physical address mapping corresponding to the TLB invalidation monitoring request has never been used, it does not perform the TLB related table invalidation operation, and directly returns a TLB invalidation rejection response to the source TLB invalidation processing module through the response channel.

7. The method of claim 6, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. In step S3, when the CA receives the monitoring request sent by the corresponding TLB invalidation processing module, it detects whether the request is a TLB invalidation monitoring request; If it is, it continues to determine whether the virtual address to physical address mapping corresponding to the TLB invalidation monitoring request has been used. If it has, it invalidates the corresponding TLB table entries, waits for all previous write access requests to be sent, and then sends a TLB invalidation completion request to the TLB invalidation processing module. If it has not, it sends a TLB invalidation rejection request to the TLB invalidation processing module. If the request is not a TLB invalidation monitoring request, it processes the request according to the original Cache coherence protocol.

8. The method of claim 7, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. When the TLB invalidation processing module receives an access request from the local CA connected to it, it detects the request type; If the request is a TLB invalidation request, it initializes the TLB invalidation response counter, generates a TLB invalidation monitoring request to the local CA and stores it in the TLB invalidation monitoring request queue, waits for the monitoring request to be successfully dispatched and then sends it to the local CA, generates a TLB invalidation request message to all other TLB invalidation processing modules, and sends the TLB invalidation request message to the on-chip interconnection network through the request channel; If the request is a TLB invalidation completion request, it generates a TLB invalidation completion request message to all HAs and IAs, and sends the TLB invalidation completion request message to the on-chip interconnection network through the request channel; If the request is TLB invalidation rejection request and the initiator of the TLB invalidation request is the local CA, the TLB invalidation response counter is decreased by n+k, and if the TLB invalidation response counter is zero after the decrease operation is performed, a TLB invalidation completion response is sent to the local CA; If the request is TLB invalidation rejection request and the initiator of the TLB invalidation request is not the local CA, a TLB invalidation rejection response message is generated and sent to the on-chip interconnection network through the response channel; If it is other request type, the request message is sent to the on-chip interconnection network through the request channel.

9. The method of claim 8, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. When the TLB invalidation processing module receives a response message from the on-chip interconnection network, the type of the response is detected; If the response is TLB invalidation rejection response message, the TLB invalidation response counter is decreased by n+k, and if the response is TLB invalidation completion response message, the TLB invalidation response counter is decreased by 1, and if the TLB invalidation response counter is zero after the decrease operation is performed, a TLB invalidation completion response is sent to the local CA; If it is other response type, the response is sent to the local CA.

10. The method of claim 9, wherein the TLB invalidation operation is a multi-copy non-atomic write operation. When the TLB invalidation processing module receives a monitoring message, the message is stored in the non-TLB invalidation monitoring request queue, and when a TLB invalidation request message is received, the message is stored in the TLB invalidation monitoring request queue, a fair round-robin scheduling method is used to select one of the two request queues, and the monitoring request at the head of the queue is sent to the local CA; When the HA or IA receives a request message from the on-chip interconnection network, if the message is TLB invalidation completion request message, a TLB invalidation completion response is returned to the source TLB invalidation processing module, otherwise the request message is processed according to the original Cache coherence protocol.

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