Semiconductor test structure and method of making the same

Abstract

The present disclosure provides a semiconductor test structure and a preparation method thereof. The semiconductor test structure comprises a substrate, the substrate comprises a first doped region and a second doped region, a transistor is arranged on the substrate of the first doped region, and a first conductive layer, a dielectric layer and a second conductive layer are sequentially arranged on the substrate of the second doped region. The material of the first conductive layer comprises a metal material, the material of the substrate comprises a semiconductor material, the first conductive layer is electrically connected with a gate of the transistor, the first conductive layer forms a Schottky contact with the substrate, and the first conductive layer and the second conductive layer are electrically isolated by the dielectric layer. The charge on the gate can be discharged through the first conductive layer and the substrate. The first conductive layer, the dielectric layer and the second conductive layer can jointly form a capacitor structure, and the capacitor structure can share the charge on the gate. Therefore, the semiconductor test structure and the preparation method thereof provided by the present disclosure can more comprehensively reduce or avoid the damage of the antenna effect to the transistor, thereby improving the protection effect of the transistor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor test structure and its fabrication method. Background Technology

[0002] In semiconductor chip manufacturing, certain processes generate free charges. For example, during plasma etching, conductive components exposed to the plasma environment accumulate charge (like an antenna collecting charge), creating a potential. The accumulated charge is proportional to the area of ​​the conductive component exposed to the plasma. If a conductive component with sufficient accumulated charge directly connects to the gate of a transistor, the gate oxide layer of the transistor will be broken down, leading to reduced reliability and lifespan, or even failure. This condition is known as Plasma Induced Damage (PID), also called the Process Antenna Effect (PAE).

[0003] In related technologies, in order to alleviate the antenna effect and protect the transistor, a reverse-biased diode can be added to the conductor where the antenna effect exists. The diode is electrically connected between the gate terminal and the base terminal of the transistor, providing a discharge path for the accumulated charge.

[0004] However, the aforementioned diodes offer poor protection for transistors. Summary of the Invention

[0005] This disclosure provides a semiconductor test structure and its fabrication method, which can more comprehensively reduce or avoid damage to transistors caused by antenna effects, thereby improving the protection effect on transistors.

[0006] The embodiments disclosed herein provide the following technical solutions:

[0007] A first aspect of this disclosure provides a semiconductor test structure, comprising: a substrate, the substrate including a first doped region and a second doped region, a transistor disposed on the substrate in the first doped region, and a first conductive layer, a dielectric layer and a second conductive layer sequentially stacked on the substrate in the second doped region; the material of the first conductive layer includes a metallic material, the material of the substrate includes a semiconductor material, the first conductive layer is electrically connected to the gate of the transistor, the first conductive layer forms a Schottky contact with the substrate, and the first conductive layer and the second conductive layer are electrically isolated through the dielectric layer.

[0008] The semiconductor test structure provided in this disclosure includes a substrate comprising a first doped region and a second doped region. A transistor is disposed on the substrate in the first doped region, and a first conductive layer, a dielectric layer, and a second conductive layer are sequentially stacked on the substrate in the second doped region. The first conductive layer is electrically connected to the gate of the transistor. The material of the first conductive layer includes a metallic material, and the material of the substrate includes a semiconductor material. The first conductive layer and the substrate form a Schottky contact (i.e., a Schottky junction), and the Schottky contact has a low forward voltage. If the transistor is a PMOS transistor, when positive charge accumulates on the gate, the positive charge can cross the Schottky barrier and be discharged from the first conductive layer to the substrate, thereby reducing or avoiding damage to the transistor caused by the antenna effect of positive charge. If the transistor is an NMOS transistor, when negative charge accumulates on the gate, the negative charge can cross the Schottky barrier and be discharged from the first conductive layer to the substrate, thereby reducing or avoiding damage to the transistor caused by the antenna effect of negative charge. In addition, the first conductive layer and the second conductive layer are electrically isolated by the dielectric layer, and the first conductive layer, the dielectric layer, and the second conductive layer can together form a capacitor structure. When charge accumulates on the gate, the capacitor structure can distribute the charge, thereby reducing the amount of charge on the gate and mitigating or preventing damage to the transistor from the antenna effect. Since the capacitor structure can distribute both positive and negative charges, it can more comprehensively reduce or prevent damage to the transistor from the antenna effect, thus improving the protection of the transistor.

[0009] In one possible implementation, the second doped region has a groove in which at least a portion of the first conductive layer, the dielectric layer, and the second conductive layer are located.

[0010] This can increase the facing area of ​​the first conductive layer and the second conductive layer, thereby increasing the capacitance of the capacitor structure. This allows the capacitor structure to distribute more charge, thus better protecting the transistor. In addition, it can also reduce the influence of the first conductive layer, the dielectric layer and the second conductive layer on the thickness of the semiconductor test structure.

[0011] In one possible implementation, the gate includes a gate metal layer, which is disposed in the same layer and with the same material as the first conductive layer.

[0012] And / or, the gate includes a doped semiconductor layer, which is disposed in the same layer and of the same material as the second conductive layer.

[0013] It can simplify the fabrication process of semiconductor test structures.

[0014] In one possible implementation, both the first doped region and the second doped region are N-type doped regions.

[0015] In one possible implementation, the material of the first conductive layer includes a metal nitride;

[0016] And / or, the material of the second conductive layer includes polycrystalline silicon.

[0017] In one possible implementation, the semiconductor test structure further includes a source test pad, a drain test pad, a substrate test pad, and a gate test pad. The source test pad is electrically connected to the source of the transistor, the drain test pad is electrically connected to the drain of the transistor, the substrate test pad is electrically connected to the first doped region, and the gate test pad is electrically connected to the gate and the first conductive layer.

[0018] Source test pads, drain test pads, substrate test pads, and gate test pads are used for electrical connections to external test devices to measure the electrical performance of transistors.

[0019] A second aspect of this disclosure provides a method for fabricating a semiconductor test structure, comprising:

[0020] A substrate is provided, the substrate including a first doped region and a second doped region;

[0021] A transistor, a first conductive layer, a dielectric layer, and a second conductive layer are formed. The transistor is located on a substrate in a first doped region, and the first conductive layer, the dielectric layer, and the second conductive layer are sequentially stacked on a substrate in a second doped region.

[0022] The first conductive layer is made of a metallic material, the substrate is made of a semiconductor material, the first conductive layer is electrically connected to the gate of the transistor, the first conductive layer forms a Schottky contact with the substrate, and the first conductive layer and the second conductive layer are electrically isolated through a dielectric layer.

[0023] The method for fabricating a semiconductor test structure provided in this disclosure can be used to fabricate a semiconductor test structure. The semiconductor test structure may include a substrate, which includes a first doped region and a second doped region. A transistor is disposed on the substrate in the first doped region, and a first conductive layer, a dielectric layer, and a second conductive layer are sequentially stacked on the substrate in the second doped region. The first conductive layer is electrically connected to the gate of the transistor. The material of the first conductive layer includes a metallic material, and the material of the substrate includes a semiconductor material. The first conductive layer and the substrate form a Schottky contact. The Schottky contact has a low forward voltage. If the transistor is a PMOS transistor, when positive charge accumulates on the gate, the positive charge can overcome the Schottky barrier and be discharged from the first conductive layer to the substrate, thereby reducing or avoiding damage to the transistor caused by the antenna effect of positive charge. If the transistor is an NMOS transistor, when negative charge accumulates on the gate, the negative charge can overcome the Schottky barrier and be discharged from the first conductive layer to the substrate, thereby reducing or avoiding damage to the transistor caused by the antenna effect of negative charge. Furthermore, the first conductive layer and the second conductive layer are electrically isolated by the dielectric layer, and the first conductive layer, the dielectric layer, and the second conductive layer can together form a capacitor structure. When charge accumulates on the gate, the capacitor structure can distribute the charge, thereby reducing the amount of charge on the gate and mitigating or preventing damage to the transistor from the antenna effect. Since the capacitor structure can distribute both positive and negative charges, it can more comprehensively reduce or prevent damage to the transistor from the antenna effect, thus improving the protection of the transistor.

[0024] In one possible implementation, forming a transistor, a first conductive layer, a dielectric layer, and a second conductive layer includes:

[0025] A groove is formed in the second doped region, and at least a portion of the first conductive layer, the dielectric layer, and the second conductive layer are located in the groove.

[0026] This can increase the facing area of ​​the first conductive layer and the second conductive layer, thereby increasing the capacitance of the capacitor structure. This allows the capacitor structure to distribute more charge, thus better protecting the transistor. In addition, it can also reduce the influence of the first conductive layer, the dielectric layer and the second conductive layer on the thickness of the semiconductor test structure.

[0027] In one possible implementation, after forming the groove, the process includes:

[0028] A metal material layer, a dielectric material layer, and a semiconductor material layer are sequentially formed, with the metal material layer, dielectric material layer, and semiconductor material layer located in the groove and on the top surface of the substrate;

[0029] Partial removal of the metal material layer, dielectric material layer, and semiconductor material layer leaves the remaining metal material layer and semiconductor material layer corresponding to the first doped region and the second doped region. The metal material layer corresponding to the first doped region forms the gate metal layer of the gate, the metal material layer corresponding to the second doped region forms the first conductive layer, the semiconductor material layer corresponding to the first doped region forms the doped semiconductor layer of the gate, and the semiconductor layer corresponding to the second doped region forms the second conductive layer. The remaining dielectric material layer corresponds to the second doped region and forms the dielectric layer.

[0030] It can simplify the fabrication process of the gate, the first conductive layer and the second conductive layer, thereby simplifying the fabrication process of semiconductor test structures.

[0031] In one possible implementation, the method for fabricating the semiconductor test structure further includes:

[0032] Form source test pads, drain test pads, substrate test pads and gate test pads;

[0033] Among them, the source test pad is electrically connected to the source of the transistor, the drain test pad is electrically connected to the drain of the transistor, the substrate test pad is electrically connected to the first doped region, and the gate test pad is electrically connected to the gate and the first conductive layer.

[0034] Source test pads, drain test pads, substrate test pads, and gate test pads are used for electrical connections to external test devices to measure the electrical performance of transistors.

[0035] The structure of this disclosure, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the semiconductor test structure provided in an embodiment of the present disclosure;

[0038] Figure 2 This is a schematic diagram of a structure in which a transistor is disposed on a substrate according to an embodiment of the present disclosure;

[0039] Figure 3 Another schematic diagram of a structure in which a transistor is disposed on a substrate according to an embodiment of this disclosure;

[0040] Figure 4 A schematic diagram of a substrate having a first conductive layer, a dielectric layer, a second conductive layer, and a conductive element provided in an embodiment of this disclosure;

[0041] Figure 5 Another schematic diagram of a substrate having a first conductive layer, a dielectric layer, a second conductive layer, and a conductive element provided in an embodiment of this disclosure;

[0042] Figure 6 A top view of a substrate having a first conductive layer, a dielectric layer, and a second conductive layer provided in an embodiment of this disclosure;

[0043] Figure 7 This is a schematic diagram of the structure of the second conductive layer inducing negative charge according to an embodiment of the present disclosure;

[0044] Figure 8 A schematic flowchart illustrating the method for fabricating a semiconductor test structure according to an embodiment of this disclosure;

[0045] Figure 9 This is a schematic diagram of the structure after providing a substrate, as provided in an embodiment of this disclosure;

[0046] Figure 10 This is a schematic diagram of a structure in which a first groove is formed in the second doped region, as provided in an embodiment of this disclosure.

[0047] Figure 11 This is a schematic diagram of the structure after forming the gate insulating material layer according to an embodiment of the present disclosure;

[0048] Figure 12 This is a schematic diagram of the structure after adjusting the material layer by forming a power function according to an embodiment of the present disclosure;

[0049] Figure 13 This is a schematic diagram of the structure after the formation of the metal material layer provided in an embodiment of this disclosure;

[0050] Figure 14 This is a schematic diagram of the structure after a metal material layer is formed in the first groove according to an embodiment of the present disclosure;

[0051] Figure 15 This is a schematic diagram of the structure after forming the dielectric material layer according to an embodiment of the present disclosure;

[0052] Figure 16 This is a schematic diagram of the structure after a dielectric material layer is formed in the second groove according to an embodiment of the present disclosure;

[0053] Figure 17 A schematic diagram of the structure after removing the dielectric material layer on the substrate located in the first doped region, provided in an embodiment of this disclosure;

[0054] Figure 18This is a schematic diagram of the structure after forming a semiconductor material layer according to an embodiment of the present disclosure;

[0055] Figure 19 This is a schematic diagram of the structure after forming a gate insulating layer, a first gate layer, a second gate layer, a first conductive layer, a dielectric layer, and a second conductive layer, according to an embodiment of this disclosure.

[0056] Figure 20 This is a schematic diagram of the structure after forming a first conductive layer, a dielectric layer, and a second conductive layer on a substrate in the second doped region, as provided in an embodiment of this disclosure.

[0057] Explanation of reference numerals in the attached figures:

[0058] 100: Semiconductor test structure; 110: Substrate;

[0059] 111: First doped region; 112: Second doped region;

[0060] 113: Base; 120: Transistor;

[0061] 121: Active layer; 1211: Source layer;

[0062] 1212: Drain; 1213: Channel;

[0063] 122a: Interface material layer; 122: Interface layer;

[0064] 123a: Gate insulating material layer; 123: Gate insulating layer;

[0065] 124a: Work function adjustment material layer; 124: Work function adjustment layer;

[0066] 1241a: Work function material layer; 1241: Work function layer;

[0067] 1242a: Barrier material layer; 1242: Barrier layer;

[0068] 125: Gate; 1251: First gate layer;

[0069] 1252: Second gate layer; 130: Capacitor structure;

[0070] 131: First conductive layer; 132: Second conductive layer;

[0071] 133a: Dielectric material layer; 133: Dielectric layer;

[0072] 141: First groove; 142: Second groove;

[0073] 143: Third groove; 150: Test pad assembly;

[0074] 151: Source test pad; 152: Drain test pad;

[0075] 153: Substrate test pad; 154: Gate test pad;

[0076] 160: Conductive component; 171a: Metallic material layer;

[0077] 172a: Semiconductor material layer. Detailed Implementation

[0078] In related technologies, semiconductor test structures may include transistors and protection diodes. A transistor may include a semiconductor substrate, a gate insulating layer, and a gate, which are sequentially stacked. During the fabrication of the gate, for example, in a plasma processing process, a large amount of charge (positive or negative) accumulates on the gate, causing a voltage to be generated between the gate and the semiconductor substrate. When the voltage is high, it may break down the gate insulating layer and damage the transistor. A protection diode can be electrically connected between the gate and the semiconductor substrate to discharge the charge accumulated on the gate, thereby protecting the transistor.

[0079] However, because it's necessary to measure the electrical performance of the transistor in the on-state, such as the threshold voltage, the protection diode must not conduct when the transistor is on to avoid affecting its conduction. This means the protection diode must be reverse-biased, allowing it to discharge only one type of charge: positive or negative. For example, when the transistor is an NMOS (N-Metal Oxide Semiconductor Field Effect Transistor), the protection diode can only discharge electrons. If positive charge accumulates on the gate, the protection diode cannot discharge it, making it susceptible to damage. Similarly, when the transistor is a PMOS (Pure Metal Oxide Semiconductor Field Effect Transistor), the protection diode can only discharge positive charge. If negative charge accumulates on the gate, the protection diode cannot discharge it, making it susceptible to damage. Therefore, the protection diode provides relatively poor protection for the transistor.

[0080] This disclosure provides a semiconductor test structure and its fabrication method. The semiconductor test structure may include a substrate, which includes a first doped region and a second doped region. A transistor is disposed on the substrate in the first doped region, and a first conductive layer, a dielectric layer, and a second conductive layer are sequentially stacked on the substrate in the second doped region. The first conductive layer is electrically connected to the gate of the transistor. The material of the first conductive layer includes a metallic material, and the material of the substrate includes a semiconductor material. The first conductive layer and the substrate form a Schottky contact. The Schottky contact has a low forward voltage. If the transistor is a PMOS transistor, when positive charge accumulates on the gate, the positive charge can cross the Schottky barrier and be discharged from the first conductive layer to the substrate, thereby reducing or avoiding damage to the transistor caused by the antenna effect of positive charge. If the transistor is an NMOS transistor, when negative charge accumulates on the gate, the negative charge can cross the Schottky barrier and be discharged from the first conductive layer to the substrate, thereby reducing or avoiding damage to the transistor caused by the antenna effect of negative charge. In addition, the first conductive layer and the second conductive layer are electrically isolated by the dielectric layer, and the first conductive layer, the dielectric layer, and the second conductive layer can together form a capacitor structure. When charge accumulates on the gate, the capacitor structure can distribute the charge, thereby reducing the amount of charge on the gate and mitigating or preventing damage to the transistor from the antenna effect. Since the capacitor structure can distribute both positive and negative charges, it can more comprehensively reduce or prevent damage to the transistor from the antenna effect, thus improving the protection of the transistor.

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0082] The following will combine Figures 1-20 The semiconductor test structure 100 provided in the embodiments of this disclosure will be described.

[0083] The semiconductor test structure 100 provided in this disclosure can be applied to semiconductor structures. Semiconductor structures may include wafers. A wafer can refer to a silicon wafer used in the fabrication of silicon semiconductor integrated circuits; because its shape is usually circular, it is called a wafer.

[0084] In some embodiments, the semiconductor structure may include multiple chip regions, with a dicing channel between each pair of adjacent chip regions. For example, the multiple chip regions may be arranged in an array. Various circuit elements, such as diodes, transistors, field-effect transistors, low-power resistors, inductors, and capacitors, can be formed within the chip regions. After the circuit elements within the chip regions are fabricated, they are diced along the dicing channel to obtain multiple independent chips.

[0085] In some embodiments, the semiconductor test structure 100 can be located in the dicing area, thereby avoiding the impact of the semiconductor test structure 100 on the layout of various circuit elements in the chip area and improving the chip integration. The performance of the circuit elements in the chip area can be reflected by testing the semiconductor test structure 100.

[0086] It is understood that the semiconductor test structure 100 may also be located in the chip area, and the present disclosure does not limit the location of the semiconductor test structure 100.

[0087] See Figure 1 The semiconductor test structure 100 may include a substrate 110, and the material of the substrate 110 may include semiconductor materials. The material of the substrate 110 may include, but is not limited to, any one or more of single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compounds, gallium arsenide compounds, gallium phosphide compounds, gallium sulfide compounds, etc., or other materials known to those skilled in the art. The substrate 110 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 110 may provide a supporting foundation for other structural layers on the substrate 110. This disclosure describes embodiments using silicon as the material of the substrate 110.

[0088] See Figure 1 The substrate 110 may include a first doped region 111 (e.g., a well region), and a transistor 120 may be disposed on the substrate 110 of the first doped region 111. The first doped region 111 may be an N-type doped region, and the transistor 120 may be a PMOS transistor. Applying a suitable negative voltage to the gate 125 of the PMOS transistor will turn it on. Alternatively, the first doped region 111 may be a P-type doped region, and the transistor 120 may be an NMOS transistor. Applying a suitable positive voltage to the gate 125 of the NMOS transistor will turn it on.

[0089] The transistor 120 provided in the embodiments of this disclosure will be described below.

[0090] See Figure 1The transistor 120 may include an active layer 121, a gate insulating layer 123, and a gate 125 stacked sequentially. The active layer 121 may include a source 1211, a drain 1212, and a channel 1213, with the source 1211 and drain 1212 connected through the channel 1213. The gate insulating layer 123 and the gate 125 are sequentially located on the channel 1213.

[0091] The active layer 121 can be made of the same material as the substrate 110, which simplifies the fabrication process of the active layer 121. For example, both the active layer 121 and the substrate 110 can be made of silicon. Alternatively, the active layer 121 and the substrate 110 can be made of different materials. For example, the active layer 121 can be made of silicon germanium (SiGe), where the bandgap of germanium is smaller than that of silicon, resulting in a smaller bandgap in the channel 1213 and thus a higher carrier mobility in the channel 1213.

[0092] See some examples. Figure 2 The active layer 121 can be located within the substrate 110 of the first doped region 111, and the top surface of the active layer 121 can be flush with the top surface of the substrate 110. See also other examples. Figure 3 The active layer 121 can be located on the top surface of the substrate 110 of the first doped region 111, and the active layer 121 can be disposed protruding from the top surface of the substrate 110 of the first doped region 111.

[0093] For example, the gate insulating layer 123 may include a material with a high dielectric constant. The high dielectric constant material has a thinner equivalent oxide thickness (EOT), which effectively reduces the gate capacitance 125; additionally, the high dielectric constant material can also reduce leakage current at the gate 125. For example, the high dielectric constant material may include any one or more of tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium oxide (HfO), silicon titanium oxide (SiTiO3), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), and zirconium silicon oxynitride (ZrSiON).

[0094] See Figure 1The gate 125 may be located above the gate insulating layer 123. The gate 125 may be a single-layer structure or a multi-layer stacked structure. The material of the gate 125 may include any one or more of polysilicon, metal, metal silicide, and metal nitride. For example, the metal may include any one or more of aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), tantalum (Ta), and hafnium (Hf); the metal silicide may include any one or more of nickel silicide (NiSi), molybdenum silicide (MoSi), and hafnium silicide (HfSi); and the metal nitride may include any one or more of titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), aluminum hafnium nitride (HfAlN), molybdenum nitride (MoN), and aluminum nickel nitride (NiAlN).

[0095] For example, see Figure 1 The gate 125 may include at least a first gate layer 1251 and a second gate layer 1252, and the materials of the first gate layer 1251 and the second gate layer 1252 may be different. The second gate layer 1252 may be located on the first gate layer 1251. The materials of the first gate layer 1251 and the second gate layer 1252 may include polysilicon, metal, metal silicide, or metal nitride. For example, the first gate layer 1251 may be a gate metal layer, and the second gate layer 1252 may be a doped semiconductor layer located on the gate metal layer. The material of the gate metal layer may include metal, metal silicide, or metal nitride, and the material of the doped semiconductor layer may include polysilicon.

[0096] See Figure 2 The transistor 120 may include an interface layer 122, which may be located above the channel 1213 and between the channel 1213 and the gate insulating layer 123. The material of the interface layer 122 may include SiO2. The interface formed between the channel 1213 and the interface layer 122 has high stability, which can ensure the stable setting of other subsequent structural layers.

[0097] See Figure 2 and Figure 3 The transistor 120 may include a work function adjustment layer 124, which can be used to adjust the work function. The work function adjustment layer 124 may include a work function layer 1241, and the material of the work function layer 1241 may include aluminum oxide or lanthanum oxide, etc.

[0098] See Figure 3The work function adjustment layer 124 may include a barrier layer 1242 and at least one work function layer 1241. The barrier layer 1242 can be used to block the diffusion of metal atoms in the work function layer 1241. The material of the barrier layer 1242 may include a metal nitride. Exemplarily, the barrier layer 1242 and the work function layer 1241 may be alternately arranged. The bottom structural layer and / or the top structural layer of the work function adjustment layer 124 may be the barrier layer 1242. The barrier layer 1242 can prevent the work function layer 1241 from directly contacting the gate insulating layer 123, reduce the influence of the gate insulating layer 123 on the work function layer 1241, and ensure the stability of the structure of the work function layer 1241. In the embodiment where the material of the first gate layer 1251 is a metal nitride, the top structural layer of the work function adjustment layer 124 may be the work function layer 1241, without having to set the top structural layer as the barrier layer 1242, which is beneficial to simplify the fabrication process of the transistor 120.

[0099] The test pad assembly 150 provided in the embodiments of this disclosure will be described below.

[0100] See Figure 1 The semiconductor test structure 100 may include a test pad assembly 150. The test pad assembly 150 is used for electrical connection to an external test device to measure the electrical performance of the transistor 120, and can also apply a voltage to the transistor 120. The test pad assembly 150 may include at least one of a source test pad 151, a drain test pad 152, a substrate test pad 153, and a gate test pad 154. The source test pad 151 is electrically connected to the source 1211 of the transistor 120, the drain test pad 152 is electrically connected to the drain 1212 of the transistor 120, the substrate test pad 153 is electrically connected to the substrate 110 of the first doped region 111, and the gate test pad 154 is electrically connected to the gate 125 and the first conductive layer 131. The test pad assembly 150 can be electrically connected to the transistor 120 and the first conductive layer 131 via a conductive element 160. For example, the first doped region 111 may include a base 113, and the substrate test pad 153 can be electrically connected to the substrate 110 of the first doped region 111 via the base 113.

[0101] The protection of transistor 120 by the first conductive layer 131, dielectric layer 133 and second conductive layer 132 provided in the embodiments of this disclosure will be described below.

[0102] See Figure 4 and Figure 5 The substrate 110 may include a second doped region 112 (e.g., a well region), and a first conductive layer 131, a dielectric layer 133, and a second conductive layer 132 may be sequentially stacked on the substrate 110 of the second doped region 112.

[0103] For example, the material of the first conductive layer 131 includes a metallic material. For instance, the material of the first conductive layer 131 may include any one or more of metals, metal silicides, and metal nitrides. The second conductive material may include any one or more of polysilicon, metals, metal silicides, and metal nitrides.

[0104] In some embodiments, the material of the first conductive layer 131 may include a metallic material, and the material of the substrate 110 may include a semiconductor material. The first conductive layer 131 and the substrate 110 may form a Schottky contact (i.e., a Schottky junction). The first conductive layer 131 may be electrically connected to the gate 125 of the transistor 120, for example, the first conductive layer 131 and the gate 125 may be electrically connected through a conductive element 160. Charge on the gate 125 may be conducted to the first conductive layer 131. A surface barrier, i.e., a Schottky barrier, is formed at the interface of the Schottky contact. The Schottky barrier is low, therefore the forward voltage of the first conductive layer 131 and the substrate 110 is low, which can discharge one of the positive and negative charges accumulated on the gate 125, thereby mitigating the damage of the antenna effect to the transistor 120 and extending the lifespan of the transistor 120. The first conductive layer 131 and substrate 110 have a lower on-state voltage (e.g., 0.3V) compared to the on-state voltage of a protection diode in the related art (e.g., 0.7V). This results in a lower on-state voltage, a larger on-state current, and a faster discharge speed, making it easier to discharge either the positive or negative charge accumulated on the gate 125. The reverse leakage current of the first conductive layer 131 and substrate 110 in the Schottky contact is also greater than that of the protection diode in the related art. Therefore, the charge distributed on the capacitor structure 130 is more easily discharged over time, thus better mitigating the damage to the transistor 120 caused by the antenna effect.

[0105] Furthermore, the first conductive layer 131 and the second conductive layer 132 are electrically isolated by the dielectric layer 133. The first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 can together form a capacitor structure 130. When charge accumulates on the gate 125, the capacitor structure 130 can share the charge on the gate 125, thereby reducing the amount of charge on the gate 125 and reducing or avoiding damage to the transistor 120 caused by the antenna effect. Since the capacitor structure 130 can share both positive and negative charges, it can protect the transistor 120 regardless of whether the charge accumulated on the gate 125 is positive or negative. This can more comprehensively reduce or avoid damage to the transistor 120 caused by the antenna effect, thereby improving the protection effect of the transistor 120. For example, see... Figure 6 and Figure 7When positive charge accumulates in the gate 125, the positive charge is conducted to the first conductive layer 131 of the capacitor structure 130, so that a negative charge E is induced on the side of the second conductive layer 132 of the capacitor structure 130 near the first conductive layer 131.

[0106] Understandably, Schottky contacts arise because the work functions of the metal and semiconductor materials differ. Charge migrates across the metal / semiconductor interface, generating an interfacial electric field. This causes the energy bands on the semiconductor surface to bend, thus forming a Schottky barrier. The rectifying characteristics formed by the contact between a metal and a semiconductor material can take two forms: one is when the metal is in contact with an N-type semiconductor, where the work function of the N-type semiconductor is less than that of the metal; the other is when the metal is in contact with a P-type semiconductor, where the work function of the P-type semiconductor is greater than that of the metal.

[0107] In the embodiment where transistor 120 is a PMOS transistor, both the first doped region 111 and the second doped region 112 can be N-type doped regions. The work function of the material of the first conductive layer 131 is greater than the work function of the material of the substrate 110 of the second doped region 112 (considering doping). During the fabrication of the gate 125, when positive charge accumulates on the gate 125, the positive charge is conducted to the first conductive layer 131, the Schottky barrier decreases, and the positive charge can cross the Schottky barrier. The positive charge is then discharged from the first conductive layer 131 to the substrate 110, thereby reducing or avoiding damage to the transistor 120 caused by the antenna effect of positive charge. When it is necessary to turn on the PMOS transistor, a negative voltage is applied to the gate 125. The gate 125 accumulates negative charge, the Schottky barrier increases, and the negative charge cannot cross the Schottky barrier, thus allowing the PMOS transistor to conduct normally. The Schottky contact between the first conductive layer 131 and the substrate 110 will not affect the conduction test of the PMOS transistor.

[0108] In the embodiment where transistor 120 is an NMOS transistor, both the first doped region 111 and the second doped region 112 can be P-type doped regions. The work function of the material of the first conductive layer 131 is less than the work function of the material of the substrate 110 of the second doped region 112 (considering doping). During the fabrication of the gate 125, when negative charge accumulates in the gate 125, the negative charge is conducted to the first conductive layer 131, the Schottky barrier decreases, and the negative charge can cross the Schottky barrier. The negative charge is then discharged from the first conductive layer 131 to the substrate 110, thereby reducing or avoiding damage to the transistor 120 caused by the antenna effect of negative charge. When it is necessary to turn on the NMOS transistor, a positive voltage is applied to the gate 125. Positive charge accumulates in the gate 125, the Schottky barrier increases, and the positive charge cannot cross the Schottky barrier, thus allowing the NMOS transistor to conduct normally. The Schottky contact between the first conductive layer 131 and the substrate 110 will not affect the conduction test of the NMOS transistor.

[0109] It is understandable that the doping types of the first doped region 111 and the second doped region 112 can be the same.

[0110] In some embodiments, at least one of the first conductive layer 131 and the second conductive layer 132 can be disposed in the same layer and with the same material as the gate 125, thereby simplifying the fabrication process of the semiconductor test structure 100. For example, both the first conductive layer 131 and the second conductive layer 132 can be disposed in the same layer and with the same material as the gate 125. The first conductive layer 131 can be disposed in the same layer and with the same material as the first gate layer 1251, and the second conductive layer 132 can be disposed in the same layer and with the same material as the second gate layer 1252. In embodiments where the first gate layer 1251 is a gate metal layer and the second gate layer 1252 is a doped semiconductor layer, the materials of the first conductive layer 131 and the gate metal layer can include metal, metal silicide, or metal nitride, etc., and the materials of the second conductive layer 132 and the doped semiconductor layer can include polysilicon.

[0111] "Same layer, same material" refers to a base membrane layer formed from the same material. After patterning and / or other processing of the base membrane layer, different parts of the base membrane layer are formed into various structural membrane layers. The processing techniques for the different structural membrane layers can be the same or different, and the different structural membrane layers can have the same or different thicknesses, and can be located on the same horizontal plane or different horizontal planes.

[0112] In some embodiments, the gate 125 and at least one of the first conductive layer 131 and the second conductive layer 132 may be made of different materials and prepared separately. For example, in an embodiment where the first conductive layer 131 is a metal nitride and the second conductive layer 132 is polysilicon, the metal nitride of the first conductive layer 131 may be rich in titanium. A high titanium content allows the metal nitride to absorb oxygen from other oxygen-containing structural layers or oxygen-containing processing environments, forming titanium oxide at the interface between the metal nitride and the polysilicon. This titanium oxide, the first conductive layer 131, and the second conductive layer 132 together form the capacitor structure 130. This configuration eliminates the need for a separate dielectric layer 133, simplifying the fabrication process of the semiconductor test structure 100 and reducing costs. It is understood that the interface between the first gate layer 1251 and the second gate layer 1252 of the transistor 120 cannot form the aforementioned titanium oxide, otherwise it may affect the electrical connection between the first gate layer 1251 and the second gate layer 1252.

[0113] In some embodiments, see Figure 1 and Figure 4The substrate 110 of the second doped region 112 may have a groove, which may be a first groove 141. At least a portion of the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 may be located in the first groove 141. Since the inner wall area of ​​the first groove 141 is relatively large, when the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 are covered on the inner wall of the first groove 141, the facing area of ​​the first conductive layer 131 and the second conductive layer 132 can be increased, thereby increasing the capacitance of the capacitor structure 130. This allows the capacitor structure 130 to distribute more charge, thus better protecting the transistor 120. In addition, it can also reduce the influence of the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 on the thickness of the semiconductor test structure 100.

[0114] For example, the first conductive layer 131 may be at least partially located in the first recess 141. For instance, a portion of the first conductive layer 131 may be located in the first recess 141, while another portion of the first conductive layer 131 may extend to the top surface of the substrate 110. Alternatively, all of the first conductive layer 131 may be located in the first recess 141. See also... Figure 14 , Figure 16 , Figure 17 and Figure 18 The first conductive layer 131 (i.e., the metal material layer 171a) located in the first groove 141 has a second groove 142, and the dielectric layer 133 (i.e., the dielectric material layer 133a) can be at least partially located in the second groove 142. The dielectric layer 133 located in the second groove 142 has a third groove 143, and the second conductive layer 132 (i.e., the semiconductor material layer 172a) can be at least partially located in the third groove 143. The principle is similar to that of the first conductive layer 131 and the first groove 141, and will not be described again. See also... Figure 19 In an embodiment where the second conductive layer 132 is completely located in the third groove 143, the top surface of the second conductive layer 132 may be flush with the top surface of the dielectric layer 133.

[0115] In some embodiments, the first groove 141 may not be provided in the substrate 110 of the second doped region 112, and the first conductive layer 131, the dielectric layer 133 and the second conductive layer 132 may be directly disposed on the top surface of the substrate 110, thereby simplifying the fabrication process of the semiconductor test structure 100.

[0116] The following describes the fabrication method of the semiconductor test structure 100 provided in the embodiments of this disclosure.

[0117] This disclosure provides a method for fabricating the semiconductor test structure 100, which can be used to fabricate the semiconductor test structure 100 in the above embodiments. See also... Figure 8 The preparation method may include:

[0118] S100: Provides a substrate, which includes a first doped region and a second doped region.

[0119] See Figure 9 A substrate 110 is provided, which can provide support for other structural layers fabricated on the substrate 110. The substrate 110 is doped to form a first doped region 111 and a second doped region 112.

[0120] For example, doping treatment may include ion implantation, plasma doping, etc.

[0121] S200: A transistor, a first conductive layer, a dielectric layer, and a second conductive layer are formed. The transistor is located on a substrate in a first doped region, and the first conductive layer, the dielectric layer, and the second conductive layer are sequentially stacked on a substrate in a second doped region.

[0122] See Figure 1 A transistor 120 is formed on a substrate 110 in the first doped region 111, and a first conductive layer 131, a dielectric layer 133, and a second conductive layer 132 are sequentially formed on a substrate 110 in the second doped region 112.

[0123] The material of the first conductive layer 131 may include a metallic material, and the material of the substrate 110 may include a semiconductor material. The first conductive layer 131 and the substrate 110 may form a Schottky contact. The first conductive layer 131 may be electrically connected to the gate 125 of the transistor 120. The charge on the gate 125 may be conducted to the first conductive layer 131, and either the positive or negative charge accumulated on the gate 125 may be discharged through the first conductive layer 131 and the substrate 110, thereby mitigating the damage of the antenna effect to the transistor 120 and extending the lifespan of the transistor 120. In addition, the first conductive layer 131 and the second conductive layer 132 are electrically isolated by the dielectric layer 133, and the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 may together form a capacitor structure 130. When charge accumulates on the gate 125, the capacitor structure 130 can share the charge on the gate 125 (which can be positive or negative), thereby reducing the amount of charge on the gate 125 and more comprehensively reducing or avoiding the damage of the antenna effect to the transistor 120, thus improving the protection effect on the transistor 120. The principle has been explained and will not be repeated here.

[0124] Forming transistor 120, first conductive layer 131, dielectric layer 133, and second conductive layer 132 may include: see [link / reference] Figure 10A first groove 141 is formed in the substrate 110 of the second doped region 112. At least a portion of the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 can be located in the first groove 141, which can be formed before the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132. This configuration can increase the capacitance of the capacitor structure 130, allowing it to distribute more charge and thus better protect the transistor 120. Furthermore, it can reduce the impact of the first conductive layer 131, the dielectric layer 133, and the second conductive layer 132 on the thickness of the semiconductor test structure 100. The principle has been explained and will not be repeated here.

[0125] Forming transistor 120 may include: see Figure 11 A gate insulating material layer 123a is deposited on substrate 110, exposing the substrate 110 of the second doped region 112. In some examples, the gate insulating material layer 123a may be formed on the top surface of substrate 110 before the first groove 141, and then the gate insulating material layer 123a located on the top surface of substrate 110 of the second doped region 112 is removed, exposing the top surface of substrate 110 of the second doped region 112, and then the first groove 141 is formed in substrate 110 of the second doped region 112. In other examples, the gate insulating material layer 123a may be formed after the first groove 141, and then the first groove 141 is formed on substrate 110 of the second doped region 112, and then the substrate 110 of the second doped region 112 may be covered with a mask layer, exposing the remaining portion (including the first doped region 111) of substrate 110, so that the gate insulating material layer 123a is formed on the remaining portion of substrate 110. In other examples, the gate insulating material layer 123a may be formed after the first groove 141. The first groove 141 is formed on the substrate 110 of the second doped region 112, and the gate insulating material layer 123a is formed on the top surface of the substrate 110 and in the first groove 141. Then, the gate insulating material layer 123a located in the first groove 141 and at least part of the top surface of the substrate 110 of the second doped region 112 is removed, and the gate insulating material layer 123a on the remaining part of the top surface of the substrate 110 is retained.

[0126] For example, deposition may include atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0127] See Figure 12Before forming the gate insulating material layer 123a, an interface material layer 122a can be deposited on the substrate 110, exposing the substrate 110 of the second doped region 112. The interface material layer 122a can be formed before the first groove 141, or it can be formed after the first groove 141. The principle is similar to that of the gate insulating material layer 123a, and will not be described again.

[0128] See Figure 12 After forming the gate insulating material layer 123a, a work function regulating material layer 124a can be deposited on the gate insulating material layer 123a, exposing the substrate 110 of the second doped region 112. The work function regulating material layer 124a can be formed before the first groove 141, or it can be formed after the first groove 141. The principle is similar to that of the gate insulating material layer 123a and will not be described again. For example, forming the work function regulating material layer 124a may include sequentially depositing and forming a barrier material layer 1242a, a work function material layer 1241a, a barrier material layer 1242a, and a work function material layer 1241a.

[0129] It is understandable that when the gate insulating material layer 123a is formed before the first groove 141, the interface material layer 122a is also formed before the first groove 141. After the gate insulating material layer 123a is formed in the first groove 141, the work function regulating material layer 124a is also formed after the first groove 141. Before the work function regulating material layer 124a is formed in the first groove 141, both the interface material layer 122a and the gate insulating material layer 123a are formed before the first groove 141. After the interface material layer 122a is formed in the first groove 141, both the gate insulating layer 123a and the work function regulating material layer 124a can be formed after the first groove 141.

[0130] For example, in an embodiment where the interface material layer 122a, the gate insulating material layer 123a, and the work function adjustment material layer 124a are all formed before the first groove 141, the interface material layer 122a, the gate insulating material layer 123a, and the work function adjustment material layer 124a can be formed sequentially on the top surface of the substrate 110. Then, the interface material layer 122a, the gate insulating material layer 123a, and the work function adjustment material layer 124a located on the top surface of the substrate 110 in the second doped region 112 are removed, exposing the top surface of the substrate 110 in the second doped region 112. Then, the first groove 141 is formed in the substrate 110 in the second doped region 112. The interface material layer 122a, the gate insulating material layer 123a, and the work function adjustment material layer 124a located on the top surface of the substrate 110 in the second doped region 112 can be removed in the same step to simplify the fabrication process.

[0131] After forming the functional adjustment material layer 124a and the first groove 141, a gate 125, a first conductive layer 131, a dielectric layer 133, and a second conductive layer 132 can be formed. The gate 125 can be disposed in the same layer and with the same material as at least one of the first conductive layer 131 and the second conductive layer 132. When the gate 125 is fabricated in the same layer and with the same material as the first conductive layer 131 and the second conductive layer 132, the fabrication process of the semiconductor test structure 100 can be further simplified.

[0132] Taking the example of the first gate layer 1251 and the first conductive layer 131, and the second gate layer 1252 and the second conductive layer 132 being fabricated in the same layer and with the same material. See [link to example]. Figure 13 , Figure 15 and Figures 17-19 The formation of gate 125, first conductive layer 131, dielectric layer 133 and second conductive layer 132 may include: sequentially forming metal material layer 171a, dielectric material layer 133a and semiconductor material layer 172a, wherein the metal material layer 171a, dielectric material layer 133a and semiconductor material layer 172a are located in the groove and on the top surface of substrate 110. Partial removal of the metal material layer 171a, dielectric material layer 133a, and semiconductor material layer 172a leaves the remaining metal material layer 171a and semiconductor material layer 172a corresponding to the first doped region 111 and the second doped region 112. The metal material layer 171a corresponding to the first doped region 111 forms the first gate layer 1251 (i.e., gate metal layer) of the gate 125. The metal material layer 171a corresponding to the second doped region 112 forms the first conductive layer 131. The semiconductor material layer 172a corresponding to the first doped region 111 forms the second gate layer 1252 (i.e., doped semiconductor layer) of the gate 125. The semiconductor material layer 172a corresponding to the second doped region 112 forms the second conductive layer 132. The remaining dielectric material layer 133a corresponds to the second doped region 112 and forms the dielectric layer 133.

[0133] Among them, see Figure 17 and Figure 18 Before forming the semiconductor material layer 172a, the dielectric material layer 133a on the substrate 110 of the first doped region 111 can be removed to expose the top surface of the metal material layer 171a on the substrate 110 of the first doped region 111. This prevents the dielectric material layer 133a from affecting the electrical connection between the metal material layer 171a and the semiconductor material layer 172a on the substrate 110 of the first doped region 111. The removal of a portion of the metal material layer 171a can occur before or after the formation of the dielectric material layer 133a and the semiconductor material layer 172a. For example, a portion of the metal material layer 171a and the semiconductor material layer 172a can be removed simultaneously, thereby simplifying the fabrication process.

[0134] For example, see Figure 19 and Figure 20 After removing part of the metal material layer 171a, dielectric material layer 133a, and semiconductor material layer 172a, the remaining metal material layer 171a and semiconductor material layer 172a corresponding to the second doped region 112, and the remaining dielectric material layer 133a corresponding to the second doped region 112, may include: the remaining metal material layer 171a being located in the first groove 141 and extending to the top surface of the substrate 110 of the second doped region 112; or, the remaining metal material layer 171a being completely located in the first groove 141 and forming the first conductive layer 131. The remaining dielectric material layer 133a is located in the second groove 142 (…). Figure 14 The retained semiconductor material layer 172a is located in the third groove 143 and extends to the top surface of the dielectric material layer 171a, or the retained semiconductor material layer 133a is completely located in the third groove 143 and forms the second conductive layer 132.

[0135] For example, the active layer 121 and the substrate 110 may be made of different materials, see [reference]. Figure 3Forming transistor 120 may include forming an active layer 121, which may be formed before forming interface layer 122. Active layer 121 may include a source region, a drain region, and a channel region. The source and drain regions are connected by the channel region. The active layer 121 in the source region may be used to form source 1211, the active layer 121 in the drain region may be used to form drain 1212, and the active layer 121 in the channel region may be used to form channel 1213. After removing a portion of the metal material layer 171a, dielectric material layer 133a, and semiconductor material layer 172a, the remaining metal material layer 171a and semiconductor material layer 172a may correspond to the first doped region 111, and the remaining metal material layer 171a and semiconductor material layer 172a may correspond to the channel region to form the gate metal layer and doped semiconductor layer of transistor 120. For example, some of the metal material layer 171a, semiconductor material layer 172a, interface material layer 122a, gate insulating material layer 123a, and work function adjustment material layer 124a can be removed simultaneously, and the remaining metal material layer 171a, semiconductor material layer 172a, interface material layer 122a, gate insulating material layer 123a, and work function adjustment material layer 124a can all correspond to the first doped region 111. This can be achieved by having the remaining metal material layer 171a, semiconductor material layer 172a, interface material layer 122a, gate insulating material layer 123a, and work function adjustment material layer 124a correspond to the channel region, so as to form the gate metal layer, doped semiconductor layer, interface layer 122, gate insulating layer 123, and work function adjustment layer 124 of the transistor 120.

[0136] For example, the active layer 121 may be made of the same material as the substrate 110. See, for example, [link to relevant documentation]. Figure 1 An active layer 121 may be formed on the top of a portion of the substrate 110 of the first doped region 111.

[0137] In some embodiments, the method for fabricating the semiconductor test structure 100 may further include: see [link to documentation]. Figure 1 A source test pad 151, a drain test pad 152, a substrate test pad 153, and a gate test pad 154 are formed. The source test pad 151 is electrically connected to the source 1211 of the transistor 120, the drain test pad 152 is electrically connected to the drain 1212 of the transistor 120, the substrate test pad 153 is electrically connected to the first doped region 111, and the gate test pad 154 is electrically connected to the gate 125 and the first conductive layer 131. This embodiment does not limit the fabrication order of the source test pad 151, drain test pad 152, substrate test pad 153, and gate test pad 154.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor testing structure, characterized in that, Includes: a substrate, the substrate including a first doped region and a second doped region, wherein a transistor is disposed on the substrate in the first doped region, and a first conductive layer, a dielectric layer and a second conductive layer are sequentially stacked on the substrate in the second doped region; The first conductive layer is made of a metallic material, the substrate is made of a semiconductor material, the first conductive layer is electrically connected to the gate of the transistor, the first conductive layer forms a Schottky contact with the substrate, and the first conductive layer and the second conductive layer are electrically isolated through the dielectric layer.

2. The semiconductor test structure according to claim 1, characterized in that, The second doped region has a groove, in which at least a portion of the first conductive layer, the dielectric layer, and the second conductive layer are located.

3. The semiconductor test structure according to claim 1 or 2, characterized in that, The gate includes a gate metal layer, which is disposed in the same layer and with the same material as the first conductive layer. And / or, the gate includes a doped semiconductor layer, which is disposed in the same layer and of the same material as the second conductive layer.

4. The semiconductor test structure according to claim 1 or 2, characterized in that, Both the first doped region and the second doped region are N-type doped regions.

5. The semiconductor test structure according to claim 1 or 2, characterized in that, The material of the first conductive layer includes metal nitrides; And / or, the material of the second conductive layer includes polycrystalline silicon.

6. The semiconductor test structure according to claim 1 or 2, characterized in that, It also includes a source test pad, a drain test pad, a substrate test pad, and a gate test pad. The source test pad is electrically connected to the source of the transistor, the drain test pad is electrically connected to the drain of the transistor, the substrate test pad is electrically connected to the first doped region, and the gate test pad is electrically connected to the gate and the first conductive layer.

7. A method for fabricating a semiconductor test structure, characterized in that, include: A substrate is provided, the substrate comprising a first doped region and a second doped region; A transistor, a first conductive layer, a dielectric layer, and a second conductive layer are formed, the transistor being located on the substrate of the first doped region, and the first conductive layer, the dielectric layer, and the second conductive layer being sequentially stacked on the substrate of the second doped region; The first conductive layer is made of a metallic material, the substrate is made of a semiconductor material, the first conductive layer is electrically connected to the gate of the transistor, the first conductive layer forms a Schottky contact with the substrate, and the first conductive layer and the second conductive layer are electrically isolated through the dielectric layer.

8. The method for fabricating a semiconductor test structure according to claim 7, characterized in that, Forming the transistor, the first conductive layer, the dielectric layer, and the second conductive layer includes: A groove is formed in the second doped region, wherein at least a portion of the first conductive layer, the dielectric layer, and the second conductive layer are located in the groove.

9. The method for fabricating a semiconductor test structure according to claim 8, characterized in that, After forming the groove, the process includes: A metal material layer, a dielectric material layer, and a semiconductor material layer are sequentially formed, wherein the metal material layer, the dielectric material layer, and the semiconductor material layer are located in the groove and on the top surface of the substrate; Partial removal of the metal material layer, the dielectric material layer, and the semiconductor material layer leaves the remaining metal material layer and semiconductor material layer corresponding to the first doped region and the second doped region, respectively. The metal material layer corresponding to the first doped region forms the gate metal layer of the gate, the metal material layer corresponding to the second doped region forms the first conductive layer, the semiconductor material layer corresponding to the first doped region forms the doped semiconductor layer of the gate, the semiconductor material layer corresponding to the second doped region forms the second conductive layer, and the remaining dielectric material layer corresponds to the second doped region and forms the dielectric layer.

10. The method for fabricating a semiconductor test structure according to any one of claims 7-9, characterized in that, Also includes: Form source test pads, drain test pads, substrate test pads and gate test pads; The source test pad is electrically connected to the source of the transistor, the drain test pad is electrically connected to the drain of the transistor, the substrate test pad is electrically connected to the first doped region, and the gate test pad is electrically connected to the gate and the first conductive layer.

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