Chip heat dissipation structure and method for improving chip photoelectric conversion efficiency

Abstract

The present invention belongs to the field of semiconductor laser chip heat dissipation technology, and specifically relates to a chip heat dissipation structure and a method for improving the chip photoelectric conversion efficiency. The chip heat dissipation structure of the present invention is obtained by implanting ions into the damaged zone of the epitaxial wafer device layer precursor, combining surface activation bonding technology to transfer the device layer to a high thermal conductivity substrate material, and then repairing the lattice defects of the bonding interface by combining thermal annealing and femtosecond laser irradiation. The chip heat dissipation structure prepared by the present invention has the advantage of high heat dissipation efficiency, and the preparation process is simple, and is suitable for large-scale industrial production.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor laser chip heat dissipation, and more specifically, relates to a chip heat dissipation structure and a method for improving chip photoelectric conversion efficiency. Background Art

[0002] Semiconductor lasers have many advantages such as small size, light weight, low energy consumption, easy modulation, and batch production. They are widely used in industrial processing, information communication, medical treatment, life sciences, and military fields. Although semiconductor lasers have high electro-optical conversion efficiency, there are non-radiative recombination losses and free carrier absorption in the active area of ​​the laser chip, which will generate a lot of heat when working. At the same time, the resistance of each layer of material in the chip will also generate Joule heat, which converts a large part of the electrical energy into thermal energy. In addition, the thermal conductivity of the chip material is low, and the heat cannot be quickly conducted out, which leads to an increase in the temperature of the active area and a decrease in the bandgap width of the active area material. Traditional high-frequency and high-power chips face the problem of heat dissipation, which in turn reduces the performance and life of the device, reduces the electro-optical conversion efficiency of the device, and reduces the output optical power, which seriously affects the working stability of the device. The substrate material of the traditional semiconductor laser chip has a low thermal conductivity, while materials such as silicon carbide, diamond, and copper have good thermal conductivity. Transferring the device layer in the semiconductor laser chip to a high thermal conductivity substrate can improve the heat dissipation efficiency of the device.

[0003] In the prior art, the method of transferring semiconductor laser chips to high thermal conductivity materials is mainly wire bonding or flip-chip bonding. Although it shows good performance to a certain extent, it still has shortcomings in terms of thermal, electrical, process complexity and process cost. Summary of the invention

[0004] The present invention mainly aims at the problem that traditional high-frequency and high-power chips in the prior art are faced with the problem that internal heat cannot be dissipated, thereby reducing the defects and shortcomings of device performance and life. A chip heat dissipation structure is provided. The chip heat dissipation structure can effectively improve the heat dissipation performance by combining ion beam stripping, surface activation bonding, thermal annealing and femtosecond laser irradiation.

[0005] Another object of the present invention is to provide a method for improving the photoelectric conversion efficiency of a chip.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A chip heat dissipation structure, wherein the preparation method of the chip heat dissipation structure comprises the following steps:

[0008] S1. Making epitaxial wafer device layer precursor;

[0009] S2. Depositing a protective layer on the surface of the epitaxial wafer device layer precursor;

[0010] S3. After the protective layer is deposited, H ions are injected into the N-type substrate of the epitaxial wafer device layer precursor through the protective layer by ion implantation to form an ion implantation damage layer;

[0011] S4. After the ion implantation damage layer is formed, the protective layer is removed by etching with a slow-release oxide etchant, and the surface of the device layer is polished, and the roughness after polishing is reduced to less than 0.5 nm; the epitaxial wafer device layer is bonded to the P-type substrate by surface activation bonding technology to obtain a bonding pair;

[0012] S5. thermally annealing the bonded pair to peel off the ion implantation damaged layer; after peeling off, repairing the lattice defects of the bonding interface by femtosecond laser irradiation;

[0013] S6. After the femtosecond laser irradiation is completed, the table is etched, and after the etching is completed, the P-side electrode and the N-side electrode are produced by magnetron sputtering;

[0014] The P-type substrate includes a silicon carbide substrate, a diamond substrate, or a metal copper substrate.

[0015] The present invention can effectively realize the transfer of the chip epitaxial wafer device layer to the high thermal conductivity substrate material through ion beam stripping and surface activation bonding technology, thereby improving the heat dissipation efficiency of the high-frequency and high-power device layer. In addition, the lattice defects of the device layer and the substrate bonding interface can be effectively repaired by combining the thermal annealing process with femtosecond laser irradiation, improving the interface photoelectric properties and heat transfer effect, and effectively improving the heat dissipation problem.

[0016] Specifically, the N-type substrate is an N-type GaAs wafer, an N-type GaN wafer, or an N-type InP wafer.

[0017] Furthermore, the material of the N-side electrode is Ni / Au / Ge / Ni / Au; the material of the P-side electrode is Ti / Al / Ti / Au.

[0018] Specifically, the material of the N-side electrode is Ni / Au / Ge / Ni / Au, wherein the thickness of Ni is 1 to 20 nm, the thickness of Au is 10 to 500 nm, and the thickness of Ge is 1 to 20 nm; the material of the P-side electrode is Ti / Al / Ti / Au, wherein the thickness of Ti is 1 to 50 nm, and the thickness of Al is 100 to 500 nm.

[0019] The ion implantation energy can be selected according to the prior art. Further, in step S3, the H ion implantation energy is 0.1-700 MeV, and the implantation dose is 1×10 15 cm -2 ~1×10 19 cm -2 .

[0020] In S3., the ion implantation energy is determined based on the implantation depth, which is a prior art and can generally be calculated by the Stopping and Range of Ions in Material (SRIM) software, which is based on a Monte Carlo statistical algorithm model.

[0021] Furthermore, in step S3, He ions may be injected before injecting H ions. The subsequent stripping efficiency may be further improved by injecting He ions.

[0022] Furthermore, the He ion implantation energy is 0.1-700 MeV, and the implantation dose is 1×10 15 cm -2 ~1×10 19 cm -2 .

[0023] Furthermore, in step S4., the surface activation bonding technology is specifically as follows: first, an inductively coupled plasma etcher is used to perform plasma activation on the surface of the epitaxial wafer device layer and the surface of the P-type substrate, with an activation power of 50 to 600 W and an ion dose of 1×10 14 ~1×10 18 cm -2 After activation, the epitaxial wafer device layer and the P-type substrate are taken out from the etcher chamber and bonded at room temperature with a bonding force of 1 to 100 kN and a bonding time of 1 to 24 hours.

[0024] Furthermore, the activation plasma source used in the plasma activation is one or more of argon ions, oxygen ions or nitrogen ions.

[0025] Furthermore, in step S5., the thermal annealing temperature is 200-500° C., the temperature rise rate is 1-20° C. / min, and the thermal annealing time is 1-24 hours.

[0026] Furthermore, in step S5., the central wavelength of the femtosecond laser irradiation is 800-1600nm, the pulse width is 10-600fs, and the output power is 0.1-100W.

[0027] Furthermore, the protective layer in step S2 is SiO 2 Layer or Si 3 N 4 layer.

[0028] The present invention can use the deposition methods and parameters commonly used in the prior art, such as, but not limited to, plasma chemical vapor deposition, the deposition temperature is 100-500°C, the deposition time is 1-20 minutes, and the deposition power is 100-600W.

[0029] Further, in step S4., the slow-release oxide etchant is a 49% HF aqueous solution and a 40% NH 4 The F aqueous solution is prepared by mixing in a volume ratio of 1:6.

[0030] Furthermore, in step S5, the thermal annealing temperature is 200-500°C, the temperature rise rate is 1-20°C / min, and the thermal annealing time is 1-24 hours. During the thermal annealing process, the ion implantation damaged layer will split under the action of high temperature and thus be peeled off.

[0031] Furthermore, in step S5., the central wavelength of the femtosecond laser irradiation is 800-1600nm, the pulse width is 10-600fs, and the output power is 0.1-100W. Femtosecond laser irradiation can transfer energy to atoms by exciting the valence band electrons in the material, thereby returning the dislocated atoms to their original positions and reconstructing the chemical bonds, thereby repairing the defects, and will not produce material melting and ablation effects, and can make the light spot output by the femtosecond laser irradiation gather at the bonding interface between the device layer and the P-type substrate, and the lattice defect atoms at the interface absorb energy and return to their original positions, thereby repairing the defects.

[0032] Furthermore, the chip heat dissipation structure includes a P-type substrate, a P-type cap layer, a P-type Al x Ga 1-x As cladding, P-type Al x Ga 1-x As waveguide layer, first Al x Ga 1-x As quantum barrier layer, InAl x Ga 1-x As quantum well layer, the second Al x Ga 1-x As quantum barrier layer, N-type Al x Ga 1-x As waveguide layer, N-type Al x Ga 1-x As cladding layer, N-type GaAs buffer layer, N-type cap layer; a P-surface electrode is arranged on the P-type substrate, and an N-type electrode is arranged on the N-type cap layer.

[0033] Specifically, the thickness of the N-type cap layer is 0.1-2 μm, the thickness of the N-type GaAs buffer layer is 0.1-2 μm, and the thickness of the N-type Al x Ga 1-x The thickness of the As cladding is 0.1 to 2 μm. x Ga 1-x The thickness of the As waveguide layer is 0.1 to 2 μm. x Ga1-x As quantum barrier layer and the second Al x Ga 1-x The thickness of the As quantum barrier layer is 0.001 to 0.05 μm. x Ga 1-x The thickness of the As quantum well layer is 0.001 to 0.01 μm. x Ga 1-x The thickness of the As waveguide layer is 0.1 to 2 μm, and the P-type Al x Ga 1-x The thickness of the As cladding layer is 0.1-2 μm, and the thickness of the P-type cap layer is 0.1-2 μm.

[0034] It should be noted that Al x Ga 1-x The value range of x in As is 0<x<1.

[0035] Furthermore, the chip heat dissipation structure includes a P-type substrate, a P-type cap layer, a P-type DBR layer, a quantum well active area layer, an oxidation restriction layer, an N-type DBR layer, an N-type GaAs buffer layer, and an N-type cap layer connected in sequence; a P-surface electrode is arranged on the P-type substrate, and an N-type electrode is arranged on the N-type cap layer.

[0036] Specifically, the P-type cap layer is a GaAs layer, a GaN layer, or an InP layer.

[0037] Furthermore, the chip heat dissipation structure includes P + GaN layer, P-type GaN layer, P-type Al x Ga 1-x N electron blocking layer, InGaN / GaN multi-quantum well layer, N-type doped GaN buffer layer, N-type cap layer; a P-surface electrode is arranged on the P-type substrate, and an N-type electrode is arranged on the N-type cap layer.

[0038] It should be noted that Al x Ga 1-x The value range of x in N is 0<x<1.

[0039] Furthermore, the ion implantation damaged layer is located in the N-type cap layer.

[0040] Specifically, the N-type cap layer is a GaAs layer, a GaN layer, or an InP layer.

[0041] The invention also protects a method for improving the photoelectric conversion efficiency of a chip.

[0042] The above method comprises the following steps:

[0043] S1. Making epitaxial wafer device layer precursor;

[0044] S2. Depositing a protective layer on the surface of the epitaxial wafer device layer precursor;

[0045] S3. After the protective layer is deposited, H ions are injected into the N-type substrate of the epitaxial wafer device layer precursor through the protective layer by ion implantation to form an ion implantation damage layer;

[0046] S4. After the ion implantation damage layer is formed, the protective layer is removed by etching with a slow-release oxide etchant, and the surface of the device layer is polished, and the roughness after polishing is reduced to less than 0.5 nm; the epitaxial wafer device layer precursor is bonded to the P-type substrate by surface activation bonding technology to obtain a bonding pair;

[0047] S5. thermally annealing the bonded pair to peel off the ion implantation damaged layer; after peeling off, repairing the lattice defects of the bonding interface by femtosecond laser irradiation;

[0048] S6. After the femtosecond laser irradiation is completed, the table is etched, and after the etching is completed, the P-side electrode and the N-side electrode are produced by magnetron sputtering;

[0049] The P-type substrate includes a silicon carbide substrate, a diamond substrate, or a metal copper substrate.

[0050] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by terms such as "width", "up", "down", "front", "back", "left" and "right" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] The present invention provides a chip heat dissipation structure and a method for improving the photoelectric conversion efficiency of a chip. The chip heat dissipation structure is made by a specific processing method, specifically, firstly by injecting a damaged band into an N-type substrate by ion implantation, combining the surface activation bonding technology to transfer the epitaxial wafer device layer to a high thermal conductivity substrate material, and then repairing the lattice defects of the bonding interface by combining thermal annealing and femtosecond laser irradiation. The chip heat dissipation structure of the present invention has the advantages of high heat dissipation efficiency, and the interface photoelectric characteristics and heat transfer efficiency are also improved. The preparation process of the chip heat dissipation structure is simple and suitable for large-scale industrial production. The method for improving the photoelectric conversion efficiency of a chip adopts a combination of example input and surface activation bonding technology, and then combines thermal annealing and femtosecond laser irradiation to effectively improve the photoelectric conversion efficiency of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1This is a schematic structural diagram of an edge-emitting laser in an integrated device in which an edge-emitting laser is integrated onto a silicon carbide substrate in Example 1 of the present invention;

[0054] Figure 2 This is a schematic diagram of the structure after depositing the protective layer in step S2. of Example 1 of the present invention;

[0055] Figure 3 This is a schematic diagram of the ion implantation process in step S3. of Example 1 of the present invention;

[0056] Figure 4 This is a schematic diagram of the structure after the ion implantation in step S3. of embodiment 1 of the present invention is completed;

[0057] Figure 5 This is a schematic diagram of the structure after the corrosion of the protective layer in step S4. of Example 1 of the present invention is completed;

[0058] Figure 6 Schematic diagram of the structure of the SiC wafer in Example 1 of the present invention;

[0059] Figure 7 This is a schematic diagram of the structure after bonding in step S4. in Example 1 of the present invention;

[0060] Figure 8 This is a schematic diagram of the structure after the ion implantation damaged layer is stripped in step S5. of Example 1 of the present invention;

[0061] Fig. 9 This is a schematic diagram of the chip heat dissipation structure in which the N-side electrode and the P-side electrode are on the same surface in Example 1;

[0062] Fig.10 This is a schematic diagram of a chip heat dissipation structure in which the N-side electrode and the P-side electrode are on different surfaces in Example 1;

[0063] Fig.11 Schematic diagram of femtosecond laser irradiation bonding pair;

[0064] Fig.12 This is a schematic diagram of the chip heat dissipation structure in Example 2;

[0065] Fig.13 This is a schematic diagram of the chip heat dissipation structure in Example 4;

[0066] Fig.14 The input power and light output power curves of the chip heat dissipation structure in Example 1 and Comparative Examples 1 to 5;

[0067] Fig.15 The input power and light output power curves of the chip heat dissipation structure in Example 2 and Comparative Example 6;

[0068] Fig.16The input power and optical output power curves of the chip heat dissipation structure in Example 3 and Comparative Example 7;

[0069] Fig.17 The input power and light output power curves of the chip heat dissipation structure in Example 4 and Comparative Example 8;

[0070] Among them, 1-N type substrate, 1'-N type cap layer, 2-N type GaAs buffer layer, 3-N type Al x Ga 1-x As cladding, 4-N type Al x Ga 1-x As waveguide layer, 5-second Al x Ga 1-x As quantum barrier layer, 6-InAl x Ga 1-x As quantum well layer, 7-first Al x Ga 1-x As quantum barrier layer, 8-P type Al x Ga 1-x As waveguide layer, 9-P type Al x Ga 1-x As cladding, 10-P-type GaAs cap layer, 11-protective layer, 12-ion implantation damage layer, 13-P-type substrate, 14-N-surface electrode, 15-P-surface electrode, 201-P-type DBR layer, 202-quantum well active region layer, 203-oxidation restriction layer, 204-N-type DBR layer, 301-P+ type GaN layer, 302-P-type GaN layer, 303-P-type Al x Ga 1-x N electron blocking layer, 304-InGaN / GaN multiple quantum well layer, 305-N-type doped GaN buffer layer. DETAILED DESCRIPTION

[0071] The present invention is further described below in conjunction with the accompanying drawings and specific examples, but the examples do not limit the present invention in any form. Unless otherwise specified, the reagents, methods and equipment used in the present invention are conventional reagents, methods and equipment in the art.

[0072] Unless otherwise specified, the reagents and materials used in the following examples are commercially available.

[0073] Example 1

[0074] S1. Provide an N-type GaAs wafer 1 with a doping concentration of 2×10 18 cm -3 , with a thickness of 500 μm, a 0.5 μm N-type GaAs buffer layer 2 is epitaxially grown on the N-type GaAs wafer 1 by metal organic chemical vapor deposition (MOCVD), and the doping concentration is 2×1018 cm -3 ; 1.5μm N-type Al 0.35 Ga 0.65 As cladding 3, doping concentration is 5×10 17 cm -3 ; 1.2μm N-type Al 0.30 Ga 0.70 As waveguide layer 4, doping concentration is 2×10 17 cm -3 ; 0.05μm second Al 0.25 Ga 0.75 As quantum barrier layer 5, undoped; 0.008μm InAl 0.2 Ga 0.8 As quantum well layer 6, undoped; 0.05 μm first Al 0.25 Ga 0.75 As quantum barrier layer 7, undoped; 1.2μm P-type Al 0.30 Ga 0.70 As waveguide layer 8, doping concentration is 2×10 17 cm -3 ; 1.5μm P-type Al 0.35 Ga 0.65 As cladding 9, doping concentration is 5×10 17 cm -3 ; 0.2μm P-type GaAs cap layer 10, doping concentration is 3×10 19 cm -3 ( Figure 1 ) obtaining an epitaxial wafer device layer precursor;

[0075] S2. After the epitaxial growth is completed, a layer of SiO is deposited on the P-type GaAs cap layer 10. 2 The protective layer 11 is deposited with a thickness of 2 μm by plasma enhanced chemical vapor deposition (PECVD) at a temperature of 450°C, a deposition time of 10 min, and a deposition power of 400 W ( Figure 2 );

[0076] S3.SiO 2 After the protective layer 11 is deposited, an ion implanter is used to implant SiO 2 The protective layer 11 is injected with H ions into the N-type GaAs wafer 1 to form an ion implantation damage layer 12; the H ion implantation energy is 5 MeV, and the implantation dose is 6×10 16 cm -2 ( Figure 3 and Figure 4 );

[0077] S4. After the ion implantation damage layer 12 is formed, a 49% HF aqueous solution and a 40% NH 4 The slow-release oxide etchant prepared by mixing F aqueous solution in a volume ratio of 1:6 has a great effect on SiO 2 The protective layer 11 is removed by etching to expose the P-type GaAs cap layer 10 ( Figure 5 ), and polishing the P-type GaAs cap layer 10, the roughness after polishing is reduced to less than 0.5nm; then bonding the epitaxial wafer device layer precursor to the P-type substrate 13 to obtain a bonding pair ( Figure 7 ); the P-type substrate 13 is a P-type SiC wafer ( Figure 6 ), the doping concentration is 2×10 18 cm -3 The bonding process is as follows: the polished device and the P-type SiC wafer are placed in the ICP etching chamber at the same time, and the chamber is evacuated to reduce the pressure in the chamber to 1×10 -5 Pa; the P-type GaAs cap layer 10 and the P-type SiC wafer surface are plasma activated by Ar plasma, with an activation power of 200 W and an ion dose of 5×10 15 cm -2 After activation, the epitaxial wafer device layer and the P-type SiC wafer were taken out of the etcher chamber and bonded at room temperature with a bonding force of 10 kN and a bonding time of 4 hours;

[0078] S5. The bonded pair is placed in an annealing furnace for thermal annealing. The thermal annealing temperature is 300°C, the temperature rise rate is 2°C / min, and the thermal annealing time is 12 hours. During the thermal annealing process, nitrogen is introduced as a protective gas, and the nitrogen flow rate is 8L / min. The ion implantation damaged layer 12 is peeled off ( Figure 8 );

[0079] After stripping, the lattice defects at the bonding interface were repaired by femtosecond laser irradiation. The central wavelength of the femtosecond laser irradiation was 800nm, the pulse width was 32fs, and the output power was 20W.

[0080] S6. After the lattice repair is completed, the table is etched. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are made by magnetron sputtering to obtain a chip heat dissipation structure, such as Fig. 9 and Fig.10 As shown; the material of the N-side electrode is Ni / Au / Ge / Ni / Au; the material of the P-side electrode is Ti / Al / Ti / Au;

[0081] Specifically, the material of the N-side electrode 14 is Ni / Au / Ge / Ni / Au, wherein the thickness of Ni is 1 to 20 nm, the thickness of Au is 10 to 500 nm, and the thickness of Ge is 1 to 20 nm; the material of the P-side electrode 15 is Ti / Al / Ti / Au, wherein the thickness of Ti is 1 to 50 nm, and the thickness of Al is 100 to 500 nm.

[0082] Example 2

[0083] S1. Provide an N-type GaAs wafer 1 with a doping concentration of 2×10 18 cm -3 , with a thickness of 500 μm, a 0.5 μm N-type GaAs buffer layer 2 is epitaxially grown on the N-type GaAs wafer 1 by metal organic chemical vapor deposition (MOCVD) with a doping concentration of 4×10 18 cm -3 ; The N-type DBR layer 204 and the P-type DBR layer 201 are composed of 38.5 pairs of silicon-doped and 19 pairs of carbon-doped Al 0.12 Ga 0.88 As(0.05μm) / Al 0.90 Ga 0.10 As (0.05 μm) and 0.02 μm Al between the two x Ga 1-x As (x changes from 0.12 to 0.9 or from 0.9 to 0.12) gradient layers. The doping concentration of the N-type DBR layer 204 and the P-type DBR layer 201 is 4×10 18 cm -3 The quantum well active region layer 202 is composed of 5 pairs of In 0.2 Ga 0.8 As / Al 0.37 Ga 0.63 As compressive strain quantum well structure, and with Al on both sides 0.3 Ga 0.7 As confines the heterostructure layer to form a 1-λ cavity. 30nm AlAs is grown on the undoped 1-λ cavity as an oxidation confinement layer 303. The oxidation confinement layer 303 is prepared by a wet oxidation process and has a limiting effect on both current and light field. A 0.2μm thick P-type GaAs cap layer 10 with a doping concentration of 3×10 19 cm -3 Obtaining an epitaxial wafer device layer precursor;

[0084] S2. After the epitaxial growth is completed, a layer of SiO is deposited on the P-type GaAs cap layer 10. 2The protective layer 11 is deposited to a thickness of 1 μm by plasma enhanced chemical vapor deposition (PECVD) at a temperature of 450° C., a deposition time of 10 min, and a deposition power of 400 W.

[0085] S3.SiO 2 After the protective layer 11 is deposited, an ion implanter is used to implant SiO 2 The protective layer 11 is injected with H ions into the N-type GaAs wafer 1 to form an ion implantation damage layer 12; the injection energy of the H ions is 10 MeV, and the injection dose is 6×10 16 cm -2 ;

[0086] S4. After the ion implantation damage layer 12 is formed, a 49% HF aqueous solution and a 40% NH 4 The slow-release oxide etchant prepared by mixing F aqueous solution in a volume ratio of 1:6 has a great effect on SiO 2 The protective layer 11 is removed by etching to expose the P-type GaAs cap layer 10, and the P-type GaAs cap layer 10 is polished to reduce the roughness to less than 0.5 nm after polishing; then the epitaxial wafer device layer precursor is bonded to the P-type substrate 13 to obtain a bonding pair; the P-type substrate 13 is a P-type SiC wafer with a doping concentration of 2×10 18 cm -3 The bonding process is as follows: the polished device and the P-type SiC wafer are placed in the ICP etching chamber at the same time, and the chamber is evacuated to reduce the pressure in the chamber to 1×10 -5 Pa; the P-type GaAs cap layer 10 and the SiC wafer surface are plasma activated by Ar plasma, with an activation power of 200 W and an ion dose of 5×10 15 cm -2 After activation, the epitaxial wafer device layer and the P-type SiC wafer were taken out of the etcher chamber and bonded at room temperature with a bonding force of 10 kN and a bonding time of 4 hours;

[0087] S5. The bonded pair is placed in an annealing furnace for thermal annealing. The thermal annealing temperature is 300°C, the temperature rise rate is 2°C / min, and the thermal annealing time is 12 hours. During the thermal annealing process, nitrogen is introduced as a protective gas at a nitrogen flow rate of 8L / min. The ion implantation damaged layer 12 is peeled off.

[0088] After stripping, the lattice defects at the bonding interface were repaired by femtosecond laser irradiation. The central wavelength of the femtosecond laser irradiation was 800nm, the pulse width was 32fs, and the output power was 20W.

[0089] S6. After the lattice repair is completed, the table is etched. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are made by magnetron sputtering to obtain a chip heat dissipation structure, such as Fig.12 As shown; the material of the N-side electrode is Ni / Au / Ge / Ni / Au; the material of the P-side electrode is Ti / Al / Ti / Au.

[0090] Example 3

[0091] S1. Provide an N-type GaAs wafer 1 with a doping concentration of 2×10 18 cm -3 , with a thickness of 600 μm, a 0.5 μm N-type GaAs buffer layer 2 is epitaxially grown on the N-type GaAs wafer 1 by metal organic chemical vapor deposition (MOCVD) with a doping concentration of 2×10 18 cm -3 ; 1.5μm N-type Al 0.40 Ga 0.60 As cladding 3, doping concentration is 5×10 17 cm -3 ; 1.2μm N-type Al 0.30 Ga 0.70 As waveguide layer 4, doping concentration is 2×10 17 cm -3 ; 0.05μm second Al 0.25 Ga 0.75 As quantum barrier layer 5, undoped; 0.008μm InAl 0.2 Ga 0.8 As quantum well layer 6, undoped; 0.05 μm first Al 0.25 Ga 0.75 As quantum barrier layer 7, undoped; 1.2μm P-type Al 0.30 Ga 0.70 As waveguide layer 8, doping concentration is 2×10 17 cm -3 ; 1.5μm P-type Al 0.35 Ga 0.65 As cladding 9, doping concentration is 5×10 17 cm -3 ; 0.2μm P-type GaAs cap layer 10, doping concentration is 3×10 19 cm -3 Obtaining an epitaxial wafer device layer precursor;

[0092] S2. After the epitaxial growth is completed, a layer of Si is deposited on the P-type GaAs cap layer 10. 3 N 4The protective layer 11 is deposited to a thickness of 2 μm by plasma enhanced chemical vapor deposition (PECVD) at a temperature of 450° C., a deposition time of 10 min, and a deposition power of 400 W.

[0093] S3.Si 3 N 4 After the protective layer 11 is deposited, an ion implanter is used to implant the Si 3 N 4 The protective layer 11 is injected with H ions into the N-type GaAs wafer 1 to form an ion implantation damage layer 12; the H ion implantation energy is 5 MeV, and the implantation dose is 6×10 16 cm -2 ;

[0094] S4. After the ion implantation damage layer 12 is formed, a 49% HF aqueous solution and a 40% NH 4 The slow-release oxide etchant obtained by mixing the F aqueous solution in a volume ratio of 1:6 has an effect on Si 3 N 4 The protective layer 11 is removed by etching to expose the P-type GaAs cap layer 10, and the P-type GaAs cap layer 10 is polished to reduce the roughness to less than 0.5 nm after polishing; then the epitaxial wafer device layer precursor is bonded to the P-type substrate 13 to obtain a bonding pair; the P-type substrate 13 is a P-type diamond wafer with a doping concentration of 2×10 18 cm -3 The bonding process is as follows: the polished device and the P-type diamond wafer are placed in the ICP etching chamber at the same time, and the chamber is evacuated to reduce the pressure in the chamber to 1×10 -5 Pa; the P-type GaAs cap layer 10 and the SiC wafer surface are plasma activated by Ar plasma, with an activation power of 200 W and an ion dose of 5×10 15 cm -2 After activation, the epitaxial wafer device layer and the P-type diamond wafer were taken out from the etcher chamber and bonded at room temperature with a bonding force of 10 kN and a bonding time of 4 hours;

[0095] S5. The bonded pair is placed in an annealing furnace for thermal annealing. The thermal annealing temperature is 300°C, the temperature rise rate is 2°C / min, and the thermal annealing time is 12 hours. During the thermal annealing process, nitrogen is introduced as a protective gas at a nitrogen flow rate of 8L / min. The ion implantation damaged layer 12 is peeled off.

[0096] After stripping, the lattice defects at the bonding interface were repaired by femtosecond laser irradiation. The central wavelength of the femtosecond laser irradiation was 800nm, the pulse width was 32fs, and the output power was 20W.

[0097] S6. After the lattice is repaired, table etching is performed. After the etching is completed, magnetron sputtering is used to make N-side electrode 14 and P-side electrode 15 to obtain a chip heat dissipation structure; the material of the N-side electrode is Ni / Au / Ge / Ni / Au; the material of the P-side electrode is Ti / Al / Ti / Au.

[0098] Example 4

[0099] S1. Provide an N-type GaN wafer 1 with a doping concentration of 2×10 18 cm -3 , with a thickness of 430 μm, a 2.9 μm N-type doped GaN buffer layer 305 is sequentially epitaxially grown on the N-type GaN wafer 1 by metal organic chemical vapor deposition (MOCVD), with a doping concentration of 2×10 18 cm -3 11 periods of InGaN / GaN (4nm / 8.5nm) multi-quantum well layers (MQWs) are InGaN / GaN multi-quantum well layers 304, 20nm of P-type Al 0.25 Ga 0.75 N electron blocking layer 303, doping concentration is 2×10 17 cm -3 ; 100nm P-type GaN layer 302, doping concentration is 2×10 18 cm -3 ; 10nm P+ type GaN layer 301, doping concentration is 2×10 19 cm -3 Obtaining an epitaxial wafer device layer precursor;

[0100] S2. After the epitaxial growth is completed, + A layer of Si is deposited on the GaN layer 3 N 4 The protective layer 11 is deposited to a thickness of 2 μm by plasma enhanced chemical vapor deposition (PECVD) at a temperature of 450° C., a deposition time of 10 min, and a deposition power of 400 W.

[0101] S3.Si 3 N 4 After the protective layer 11 is deposited, an ion implanter is used to implant the Si 3 N 4 The protective layer 11 is injected with H ions into the N-type GaN wafer 1 to form an ion implantation damage layer 12; the H ion implantation energy is 5 MeV, and the implantation dose is 6×10 16 cm -2 ;

[0102] S4. After the ion implantation damage layer 12 is formed, a 49% HF aqueous solution and a 40% NH4 The slow-release oxide etchant obtained by mixing the F aqueous solution in a volume ratio of 1:6 has an effect on Si 3 N 4 The protective layer 11 is removed by etching to expose the P + type GaN layer, and P + The GaN layer is polished, and the roughness after polishing is reduced to less than 0.5 nm; then the epitaxial wafer device layer precursor is bonded to the P-type substrate 13 to obtain a bonding pair; the P-type substrate 13 is a P-type diamond wafer with a doping concentration of 2×10 18 cm -3 The bonding process is as follows: the polished device and the P-type diamond wafer are placed in the ICP etching chamber at the same time, and the chamber is evacuated to reduce the pressure in the chamber to 1×10 -5 Pa; P + The surface of the GaN layer and SiC wafer was plasma activated with an activation power of 200 W and an ion dose of 5×10 15 cm -2 After activation, the epitaxial wafer device layer and the P-type diamond wafer were taken out from the etcher chamber and bonded at room temperature with a bonding force of 10 kN and a bonding time of 4 hours;

[0103] S5. The bonded pair is placed in an annealing furnace for thermal annealing. The thermal annealing temperature is 300°C, the temperature rise rate is 2°C / min, and the thermal annealing time is 12 hours. During the thermal annealing process, nitrogen is introduced as a protective gas at a nitrogen flow rate of 8L / min. The ion implantation damaged layer 12 is peeled off.

[0104] After stripping, the lattice defects at the bonding interface were repaired by femtosecond laser irradiation. The central wavelength of the femtosecond laser irradiation was 800nm, the pulse width was 32fs, and the output power was 20W.

[0105] S6. After the lattice repair is completed, the table is etched. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are made by magnetron sputtering to obtain a chip heat dissipation structure, such as Fig.13 As shown; the material of the N-side electrode is Ni / Au / Ge / Ni / Au; the material of the P-side electrode is Ti / Al / Ti / Au.

[0106] Comparative Example 1

[0107] S1. Provide an N-type SiC wafer with a doping concentration of 2×10 18 cm -3 , with a thickness of 500 μm, a 0.5 μm N-type GaAs buffer layer 2 is epitaxially grown on the N-type SiC wafer by metal organic chemical vapor deposition (MOCVD) with a doping concentration of 2×10 18cm -3 ; 1.5μm N-type Al 0.35 Ga 0.65 As cladding 3, doping concentration is 5×10 17 cm -3 ; 1.2μm N-type Al 0.30 Ga 0.70 As waveguide layer 4, doping concentration is 2×10 17 cm -3 ; 0.05μm second Al 0.25 Ga 0.75 As quantum barrier layer 5, undoped; 0.008μm InAl 0.2 Ga 0.8 As quantum well layer 6, undoped; 0.05 μm first Al 0.25 Ga 0.75 As quantum barrier layer 7, undoped; 1.2μm P-type Al 0.30 Ga 0.70 As waveguide layer 8, doping concentration is 2×10 17 cm -3 ; 1.5μm P-type Al 0.35 Ga 0.65 As cladding 9, doping concentration is 5×10 17 cm -3 ; 0.2μm P-type GaAs cap layer 10, doping concentration is 3×10 19 cm -3 Obtaining an epitaxial wafer device layer;

[0108] S2. The device layer of the epitaxial wafer is subjected to mesa etching. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are manufactured by magnetron sputtering to obtain the control chip heat dissipation structure 1.

[0109] Comparative Example 2

[0110] The preparation method and steps of the control chip heat dissipation structure 2 are the same as those of Example 1, except that in step S3., SiO 2 After the protective layer 11 is deposited, a 49% HF aqueous solution and a 40% NH 4 The slow-release oxide etchant prepared by mixing F aqueous solution in a volume ratio of 1:6 has a great effect on SiO 2 The protective layer 11 is removed by etching, and a control chip heat dissipation structure 2 is obtained.

[0111] Comparative Example 3

[0112] The preparation method and steps of the control chip heat dissipation structure 3 are the same as those of Example 1, except that in step S4, the bonding process is as follows: after the ion implantation is completed, a 49% HF aqueous solution and a 40% NH 4 The slow-release oxide etchant prepared by mixing F aqueous solution in a volume ratio of 1:6 has a great effect on SiO 2 The protective layer 11 is removed by etching to expose the P-type GaAs cap layer 10. A metal layer is deposited on the P-type GaAs cap layer, and the metal layer is silver. Then a metal layer is also deposited on the P-type SiC wafer, and the metal is silver. The device layer is bonded to the P-type SiC wafer by metal bonding, and the control chip heat dissipation structure 3 is obtained.

[0113] Comparative Example 4

[0114] The preparation method and steps of the control chip heat dissipation structure 4 are the same as those of Example 1, except that in step S5, the bonding pair is directly irradiated with femtosecond laser without thermal annealing, and the control chip heat dissipation structure 4 is obtained.

[0115] Comparative Example 5

[0116] The preparation method and steps of the control chip heat dissipation structure 5 are the same as those of Example 1, except that in step S5, the bonding pair is only subjected to thermal annealing without femtosecond laser irradiation, and the control chip heat dissipation structure 5 is obtained.

[0117] Comparative Example 6

[0118] S1. Provide an N-type SiC wafer with a doping concentration of 2×10 18 cm -3 , with a thickness of 500 μm, a 0.5 μm N-type GaAs buffer layer 2 is epitaxially grown on the N-type SiC wafer by metal organic chemical vapor deposition (MOCVD) with a doping concentration of 4×10 18 cm -3 ; The N-type DBR layer 204 and the P-type DBR layer 201 are composed of 38.5 pairs of silicon-doped and 19 pairs of carbon-doped Al 0.12 Ga 0.88 As(0.05μm) / Al 0.90 Ga 0.10 As (0.05 μm) and 0.02 μm Al between the two x Ga 1-x As (x changes from 0.12 to 0.9 or from 0.9 to 0.12) gradient layers. The doping concentration of the N-type DBR layer 204 and the P-type DBR layer 201 is 4×10 18 cm -3 The quantum well active region layer 202 is composed of 5 pairs of In 0.2 Ga0.8 As / Al 0.37 Ga 0.63 As compressive strain quantum well structure, and with Al on both sides 0.3 Ga 0.7 As confines the heterostructure layer to form a 1-λ cavity. 30nm AlAs is grown on the undoped 1-λ cavity as an oxidation confinement layer 303. The oxidation confinement layer 303 is prepared by a wet oxidation process and has a limiting effect on both current and light field. A 0.2μm thick P-type GaAs cap layer 10 with a doping concentration of 3×10 19 cm -3 Obtaining an epitaxial wafer device layer;

[0119] S2. The epitaxial wafer device layer is subjected to mesa etching. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are manufactured by magnetron sputtering to obtain the control chip heat dissipation structure 6.

[0120] Comparative Example 7

[0121] S1. Provide an N-type diamond wafer with a doping concentration of 2×10 18 cm -3 , with a thickness of 600 μm, a 0.5 μm N-type GaAs buffer layer 2 is epitaxially grown on the N-type diamond wafer by metal organic chemical vapor deposition (MOCVD) with a doping concentration of 2×10 18 cm -3 ; 1.5μm N-type Al 0.40 Ga 0.60 As cladding 3, doping concentration is 5×10 17 cm -3 ; 1.2μm N-type Al 0.30 Ga 0.70 As waveguide layer 4, doping concentration is 2×10 17 cm -3 ; 0.05μm second Al 0.25 Ga 0.75 As quantum barrier layer 5, undoped; 0.008μm InAl 0.2 Ga 0.8 As quantum well layer 6, undoped; 0.05 μm first Al 0.25 Ga 0.75 As quantum barrier layer 7, undoped; 1.2μm P-type Al 0.30 Ga 0.70 As waveguide layer 8, doping concentration is 2×10 17 cm -3 ; 1.5μm P-type Al 0.35 Ga 0.65 As cladding 9, doping concentration is 5×10 17 cm-3 ; 0.2μm P-type GaAs cap layer 10, doping concentration is 3×10 19 cm -3 Obtaining an epitaxial wafer device layer;

[0122] S2. The device layer of the epitaxial wafer is subjected to mesa etching. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are manufactured by magnetron sputtering to obtain the control chip heat dissipation structure 7.

[0123] Comparative Example 8

[0124] S1. Provide an N-type diamond wafer with a doping concentration of 2×10 18 cm -3 , with a thickness of 430 μm, and a 2.9 μm N-type doped GaN buffer layer 305 is sequentially epitaxially grown on the N-type diamond wafer by metal organic chemical vapor deposition (MOCVD), with a doping concentration of 2×10 18 cm -3 11 periods of InGaN / GaN (4nm / 8.5nm) multi-quantum well layers (MQWs) are InGaN / GaN multi-quantum well layers 304, 20nm of P-type Al 0.25 Ga 0.75 N electron blocking layer 303, doping concentration is 2×10 17 cm -3 ; 100nm P-type GaN layer 302, doping concentration is 2×10 18 cm -3 ; 10nm P+ type GaN layer 301, doping concentration is 2×10 19 cm -3 Obtaining an epitaxial wafer device layer;

[0125] S2. The device layer of the epitaxial wafer is subjected to mesa etching. After the etching is completed, the N-side electrode 14 and the P-side electrode 15 are manufactured by magnetron sputtering to obtain the control chip heat dissipation structure 8.

[0126] Experimental Example 1: Determination of the photoelectric conversion efficiency of the chip heat dissipation structure prepared in the embodiment and the comparative example and the control chip heat dissipation structure

[0127] The determination method is: the test method adopts the comparison method, and the chip heat dissipation structure and the control chip heat dissipation structure are tested respectively. The output laser power of the chip heat dissipation structure and the control chip heat dissipation structure under the same input current is counted. The photoelectric conversion efficiency is the output optical power divided by the power supply power (current multiplied by voltage). The above data can be measured experimentally.

[0128] Test results such as Figures 14 to 17As shown. The photoelectric conversion efficiency of Example 1 is 80.0%, the photoelectric conversion efficiency of Comparative Example 1 is 46.7%, the photoelectric conversion efficiency of Comparative Example 2 is 53.3%, the photoelectric conversion efficiency of Comparative Example 3 is 60.0%, the photoelectric conversion efficiency of Comparative Example 4 is 66.7%, and the photoelectric conversion efficiency of Comparative Example 5 is 36.7%. The above photoelectric conversion efficiency is obtained by multiplying the output light power to the input power by 100%.

[0129] from Fig.15 It can be seen that the photoelectric conversion efficiency of Example 2 is 70.0%, and the photoelectric conversion efficiency of Comparative Example 6 is 30.0%. Fig.16 It can be seen that the photoelectric conversion efficiency of Example 3 is 82.5%, and the photoelectric conversion efficiency of Comparative Example 7 is 50.0%; Fig.17 It can be seen that the photoelectric conversion efficiency of Example 4 is 60.0%, and the photoelectric conversion efficiency of Comparative Example 8 is 38.0%. The increase in device temperature caused by thermal effects in semiconductor lasers, especially the sharp increase in the temperature of the active area, will lead to various non-irradiation composite enhancements inside the laser, resulting in a decrease in output optical power. The chip heat dissipation structure prepared in the embodiment of the present invention has higher photoelectric conversion efficiency and better heat dissipation effect.

[0130] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A chip heat dissipation structure, characterized in that: The method for preparing the chip heat dissipation structure comprises the following steps: S1. Preparing an epitaxial wafer device layer precursor; the epitaxial wafer device layer precursor comprises an N-type substrate and an epitaxial wafer device layer; S2. depositing a protective layer (11) on the upper surface of the epitaxial wafer device layer; S3. After the protective layer (11) is deposited, H ions are injected into the N-type substrate (1) of the epitaxial wafer device layer precursor through the protective layer (11) by ion implantation to form an ion implantation damage layer (12); S4. After the ion implantation damage layer (12) is formed, the protective layer (11) is removed by etching with a slow-release oxide etchant, and the surface of the epitaxial wafer device layer is polished, and the roughness after polishing is reduced to less than 0.5 nm; the epitaxial wafer device layer precursor is bonded to a P-type substrate (13) by a surface activation bonding technique to obtain a bonding pair; S5. thermally annealing the bonded pair to peel off the ion implantation damaged layer (12); after peeling off, repairing the lattice defects of the bonding interface by femtosecond laser irradiation; the thermal annealing temperature is 200-500°C, the temperature rise rate is 1-20°C / min, and the thermal annealing time is 1-24 hours; the central wavelength of the femtosecond laser irradiation is 800-1600nm, the pulse width is 10-600fs, and the output power is 0.1-100W; S6. After the femtosecond laser irradiation is completed, the table is etched, and after the etching is completed, the P-side electrode (14) and the N-side electrode (15) are produced by magnetron sputtering; The P-type substrate (13) comprises a silicon carbide substrate, a diamond substrate or a metal copper substrate.

2. The chip heat dissipation structure according to claim 1, characterized in that: In step S3, the H ion implantation energy is 0.1 ~ 700 MeV, and the implantation dose is 1×10 15 cm -2 ~ 1×10 19 cm -2 .

3. The chip heat dissipation structure according to claim 1, characterized in that: In step S4., the surface activation bonding technology is specifically as follows: first, an inductively coupled plasma etcher is used to perform plasma activation on the surface of the epitaxial wafer device layer and the surface of the P-type substrate (13), with an activation power of 50 to 600 W and an ion dose of 1×10 14 ~1×10 18 cm -2 After activation, the epitaxial wafer device layer and the P-type substrate (13) are taken out from the chamber of the etching machine and bonded at room temperature with a bonding force of 1 to 100 kN and a bonding time of 1 to 24 hours.

4. The chip heat dissipation structure according to claim 1, characterized in that: The chip heat dissipation structure comprises a P-type substrate (13), a P-type cap layer (10), and a P-type Al x Ga 1-x As cladding (9), P-type Al x Ga 1-x As waveguide layer (8), the first Al x Ga 1- x As quantum barrier layer (7), InAl x Ga 1-x As quantum well layer (6), the second Al x Ga 1-x As quantum barrier layer (5), N-type Al x Ga 1-x As waveguide layer (4), N-type Al x Ga 1-x As cladding layer (3), N-type GaAs buffer layer (2), and N-type cap layer (1'); a P-surface electrode (14) is provided on the P-type substrate (13), and an N-type electrode (15) is provided on the N-type cap layer (1').

5. The chip heat dissipation structure according to claim 1, characterized in that: The chip heat dissipation structure comprises a P-type substrate (13), a P-type cap layer (10), a P-type DBR layer (201), a quantum well active region layer (202), an oxidation restriction layer (203), an N-type DBR layer (204), an N-type GaAs buffer layer (2), and an N-type cap layer (1') which are connected in sequence; a P-surface electrode (14) is provided on the P-type substrate (13), and an N-type electrode (15) is provided on the N-type cap layer (1').

6. The chip heat dissipation structure according to claim 1, characterized in that: The chip heat dissipation structure comprises a P-type substrate (13), a P + type GaN layer (301), P-type GaN layer (302), P-type Al x Ga 1-x An N electron blocking layer (303), an InGaN / GaN multi-quantum well layer (304), an N-type doped GaN buffer layer (305), and an N-type cap layer (1'); a P-surface electrode (14) is provided on the P-type substrate (13), and an N-type electrode (15) is provided on the N-type cap layer (1').

7. The chip heat dissipation structure according to any one of claims 4 to 6, characterized in that: The N-type cap layer (1') is a GaAs layer, a GaN layer, or an InP layer.

8. A method for improving chip photoelectric conversion efficiency, characterized in that: The steps include: S1. Preparing an epitaxial wafer device layer precursor; the epitaxial wafer device layer precursor comprises an N-type substrate and an epitaxial wafer device layer; S2. depositing a protective layer (11) on the upper surface of the epitaxial wafer device layer; S3. After the protective layer (11) is deposited, H ions are injected into the N-type substrate (1) of the epitaxial wafer device layer precursor through the protective layer (11) by ion implantation to form an ion implantation damage layer (12); S4. After the ion implantation damage layer (12) is formed, the protective layer (11) is removed by etching with a slow-release oxide etchant, and the surface of the epitaxial wafer device layer is polished, and the roughness after polishing is reduced to less than 0.5 nm; the epitaxial wafer device layer precursor is bonded to a P-type substrate (13) by a surface activation bonding technique to obtain a bonding pair; S5. thermally annealing the bonded pair to peel off the ion implantation damaged layer (12); after peeling off, repairing the lattice defects at the bonding interface by femtosecond laser irradiation; S6. After the femtosecond laser irradiation is completed, the table is etched, and after the etching is completed, the P-side electrode (14) and the N-side electrode (15) are produced by magnetron sputtering; The P-type substrate (13) comprises a silicon carbide substrate, a diamond substrate or a metal copper substrate.

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