A vector network analyzer

Abstract

A kind of vector network analyzer includes: shell, circuit board being arranged in shell, radio frequency component module, circuit board includes: backboard, control module being electrically connected with backboard, radio frequency component module includes: shielded cavity, source component being arranged in shielded cavity, receiver component being arranged in shielded cavity, radio frequency port, with the docking interface of backboard electrically connected, backboard is provided with multiple docking slot positions with radio frequency component module docking, multiple docking slot positions are same, the docking interface of different radio frequency component module is same and is connected with docking slot position docking;The above-mentioned vector network analyzer is modularized design, radio frequency component module can be used to be combined into any port number VNA, improve the flexibility and efficiency of production assembly, reduce cost, backboard is provided with multiple docking slot positions with radio frequency component module docking, multiple docking slot positions are same, radio frequency component module can be plugged into any docking slot position according to need, improve assembly efficiency.

Description

Technical Field

[0001] This invention relates to the field of communication testing, and in particular to a vector network analyzer. Background Technology

[0002] A vector network analyzer (VNA) is an expensive measurement instrument used to measure radio frequency and microwave devices. Currently, most VNAs on the market are sold with a fixed number of ports (2 ports, 4 ports, or a specified number of ports), making it impossible to quickly assemble modules to produce customized port models such as 6-port or 8-port VNAs according to specific customer needs.

[0003] If the DUT (Device Under Test) that the customer needs to test is a 3-port device, it cannot be used if the VNA is 2-port. If the VNA is 4-port, one port will be idle, resulting in wasted resources. If it is a multi-port VNA, the cost may be greatly increased, which is unacceptable to the customer. Summary of the Invention

[0004] Therefore, it is necessary to provide a vector network analyzer with reduced cost.

[0005] A vector network analyzer includes: a housing, a circuit board disposed in the housing, and a radio frequency (RF) component module. The circuit board includes: a backplane, and a control module electrically connected to the backplane. The RF component module includes: a shielded cavity, a source component disposed in the shielded cavity, a receiver component disposed in the shielded cavity, an RF port, and a docking interface electrically connected to the backplane. The backplane has multiple docking slots for docking with the RF component module. The multiple docking slots are identical, and the docking interfaces of different RF component modules are identical and connected to the docking slots.

[0006] In a preferred embodiment, the interface is a PCI interface.

[0007] In a preferred embodiment, the radio frequency component module is provided with two radio frequency ports.

[0008] In a preferred embodiment, the back plate is provided with 16 docking slots.

[0009] In a preferred embodiment, each of the radio frequency component modules has an independent PCI driver and runs independently.

[0010] In a preferred embodiment, upon receiving a start command, the control module enumerates the PCI drivers of all the RF component modules in the vector network analyzer, traverses the enumerated driver list, obtains the corresponding docking slot information, binds the docking slot to the RF port information of the docked RF component, establishes the correspondence between the VNA port and the RF port of the RF module and the docking slot on the backplane, establishes the mapping between logical ports and physical ports, confirms the total number of VNA ports, initializes the software port information, and completes the start-up.

[0011] In a preferred embodiment, upon receiving a start command, the control module enumerates the PCI drivers of all the RF component modules in the vector network analyzer, determines whether the driver list is empty, and if it is empty, sets the total number of VNA ports and initializes other modules; if the driver list is not empty, it reads the backplane slot number, adds the mapping relationship between the VNA port and the RF port of the RF module and the docking slot of the backplane, increments the number of VNA ports, decrements the driver list by 1, and returns to determining whether the driver list is empty.

[0012] In a preferred embodiment, if multiple RF component modules are connected to the backplane, one of the docking slots on the backplane is designated as the main slot, and the other docking slots are designated as secondary slots. The main slot stores the sweep frequency data of the PCI driver of the RF component module to which it is plugged, and saves and integrates the sweep frequency data of the PCI driver of the RF component module to which the secondary slot is plugged. The secondary slot performs PCI driving, reads the sweep frequency data from the hardware, and forwards it to the main slot PCI driver for storage in kernel mode. When reading the sweep frequency data in user mode, it reads from the main slot PCI driver. During reading, the main slot traverses the data of all docking slots and combines the data. After reading the data of all docking slots, it sends it back to user mode.

[0013] In a preferred embodiment, when the control module receives a frequency sweep command and starts the frequency sweep, the PCI driver of each docking slot reads the frequency sweep data from the FPGA. After the main slot reads the data, it directly stores the data for later use. After the secondary slot reads the data, it forwards the data to the main slot, and the main slot saves the secondary slot data for later use. When the user space reads data from the kernel space, it reads the data from the PCI driver of the main slot. Before reading, it iterates through all the bits of the docking slot to determine whether the data is complete. If it is incomplete, it waits; if it is complete, it sends the data back to the user space. After the user space reads the data, it performs relevant business calculations and displays it on the UI interface.

[0014] In a preferred embodiment, when the control module receives a kernel-mode scan command, it controls the VNA to start scanning, the PCI driver to read data, and determines whether the current docking slot is the primary slot. If it is the primary slot, the primary slot stores the data and waits for user-mode to read it. If it is not the primary slot, the scanned frequency data is forwarded to the primary slot, which stores the data and waits for user-mode to read it. If a user-mode data read command is received, it controls the user-mode to start reading data, reading from the primary slot, and determines whether all docking slot data is complete. If not, it waits and continues to determine whether all docking slot data is complete. If complete, it parses and combines all docking slot data, sends the data back to user-mode, and performs compensation and calibration data processing in user-mode.

[0015] The aforementioned vector network analyzer, through its modular design, allows RF component modules to be combined into VNAs with any number of ports, improving production assembly flexibility and efficiency while reducing costs. The backplane features multiple identical docking slots for the RF component modules, enabling modules to be plugged into any slot as needed, enhancing assembly efficiency and convenience. If each module contains two ports, three RF component modules can be assembled into a 6-port VNA, allowing customers to simultaneously measure two DUTs, maximizing port utilization and reducing costs. Similarly, for VNA manufacturers, producing 2-, 4-, and 6-port VNAs uses the same modules, eliminating additional R&D and production costs beyond hardware. Modularizing VNA design and production blurs the concept of ports, allowing for on-demand assembly, flexibly supporting customer needs, and offering better scalability. Multiple modules' PCI drivers work collaboratively, effectively eliminating the need for traditional methods. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a vector network analyzer according to an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the radio frequency component module of a vector network analyzer connected to a backplane according to an embodiment of the present invention;

[0018] Figure 3 This is a flowchart of the VNA port loading process according to an embodiment of the present invention;

[0019] Figure 4 This is a flowchart of a kernel-mode frequency sweep according to an embodiment of the present invention;

[0020] Figure 5 This is a process for reading data in user mode according to an embodiment of the present invention. Detailed Implementation

[0021] The following examples are provided to help better understand the present invention, but are not intended to limit the invention.

[0022] like Figures 1 to 2 As shown, a vector network analyzer 100 of the present invention includes: a housing 20, a circuit board disposed in the housing 20, and a radio frequency component module 40. The circuit board includes: a backplate 60 and a control module electrically connected to the backplate 60. The radio frequency component module 40 includes: a shielded cavity, a source component disposed in the shielded cavity, a receiver component disposed in the shielded cavity, a radio frequency port 42, and a docking interface 44 electrically connected to the backplate 60.

[0023] In this embodiment, the backplate 60 is provided with a plurality of docking slots 62 for mating with the radio frequency component module 40. The plurality of docking slots 62 are identical. The docking interfaces 44 of the different radio frequency component modules 40 are identical and are connected to the docking slots 62.

[0024] Furthermore, in this embodiment, the interface 44 is a PCI interface.

[0025] In this embodiment, the source component is a signal transmitting unit, the receiver component is a signal receiving unit, and the device under test (DUT) passes through between them.

[0026] Furthermore, the radio frequency component module 40 in this embodiment is provided with two radio frequency ports 42.

[0027] Furthermore, preferably, the back plate of this embodiment is provided with 16 docking slots 62.

[0028] Furthermore, preferably, each radio frequency component module in this embodiment has an independent PCI driver and runs independently.

[0029] This invention modularizes the VNA (Vector Network Analyzer) and then assembles the modules as needed to form the complete unit. The RF ports 42 are grouped in pairs, meaning each RF component module 40 contains two RF ports 42. During the production of the RF component module 40, it is not necessary to know which port type of VNA this RF component module 40 will ultimately be used for.

[0030] The VNA provides a backplane 60 with multiple slots 62. Each slot 62 can connect to an RF component module 40. If the backplane 60 has 16 slots, a VNA with a maximum of 32 ports can be assembled. Chassis designs and manufacturing of various port counts are available for future use. During module assembly, the corresponding number of RF component modules 40 can be connected according to the required number of ports for the entire device. By installing the corresponding RF component modules 40 into the chassis, a VNA device with the corresponding number of ports can be produced.

[0031] This invention allows for the production of customized port VNAs by assembling a specified number of RF component modules 40 as needed. Each RF component module 40 has an independent PCI driver and runs independently. When the VNA software starts, it dynamically identifies the number of ports of the current device. The same software can be adapted to multiple port models of devices, reducing software maintenance costs.

[0032] Furthermore, preferably, in this embodiment, the control module receives a start command, enumerates the PCI drivers of all RF component modules 40 in the vector network analyzer, traverses the enumerated driver list, obtains the corresponding docking slot 62 information, binds the docking slot 62 to the RF port 42 information of the docked RF component module 40, establishes the correspondence between the VNA port and the RF port 42 of the RF module 40 and the docking slot 62 of the backplane 60, establishes the mapping between logical ports and physical ports, confirms the total number of VNA ports, initializes the software port information, and completes the start-up.

[0033] like Figure 3 As shown, further preferably, the process of loading the number of ports when starting the VNA software in this embodiment is as follows: The control module of this embodiment receives the start command, controls the enumeration of the PCI drivers of all RF component modules 40 in the vector network analyzer, and determines whether the driver list is empty. If it is determined to be empty, the total number of VNA ports is set, and other modules are initialized; if the driver list is determined not to be empty, the backplane slot number is read, the mapping relationship between the VNA port and the RF port 42 of the RF module 40 and the docking slot 62 of the backplane 60 is added, the number of VNA ports is incremented, the driver list is decremented by 1, and the process returns to determining whether the driver list is empty.

[0034] Furthermore, preferably, in this embodiment, if the backplane 60 is connected to multiple RF component modules 40, one of the docking slots 62 on the backplane 60 is designated as the main slot, and the other docking slots are designated as secondary slots. The main slot stores the sweep frequency data of the PCI driver of the RF component module 40 to which it is plugged, and saves and integrates the sweep frequency data of the PCI driver of the RF component module 40 to which the secondary slots are plugged. The secondary slots perform PCI (Peripheral Component Interconnect) driving, and after reading the sweep frequency data from the hardware, forward it to the main slot PCI driver for storage in kernel mode. When the user mode reads the sweep frequency data, it reads it from the main slot PCI driver. During reading, the main slot traverses the data of all docking slots and combines the data. After reading the data of all docking slots, it sends it back to the user mode.

[0035] In this embodiment, the primary slot is designated based on the ID of the docking slot 62. This can be done according to the ID sequence or order of the docking slots, or other rules. For example, slot 62 with ID 1 is the primary slot, and the others are secondary slots. All frequency sweep data from the secondary slots is first sent to the primary slot's driver program. After the primary slot's driver program collects all the data from the docking slots, it returns it to the host computer software.

[0036] Furthermore, preferably, when the control module of this embodiment receives the frequency sweep command and starts the frequency sweep, the PCI driver of each docking slot reads the frequency sweep data from the FPGA (Field Programmable Gate Array). After the main slot reads the data, it directly stores the data for later use. After the secondary slot reads the data, it forwards the data to the main slot, and the main slot saves the secondary slot data for later use. When the user space reads data from the kernel space, it reads the data from the main slot PCI driver. Before reading, it traverses all the bits of the docking slot to determine whether the data is complete. If it is incomplete, it waits; if it is complete, it sends the data back to the user space. After the user space reads the data, it performs relevant business calculations and displays it on the UI (User Interface).

[0037] The relevant business calculations in this embodiment vary depending on the type of component. For example, they differ depending on the device being tested, such as a filter or amplifier.

[0038] like Figure 4 As shown, further preferably, in this embodiment, when the control module receives a kernel-mode scan command, it controls the VNA to start scanning, the PCI driver reads data, and determines whether the currently docked slot is the primary slot. If it is the primary slot, the primary slot stores the data and waits for user-mode reading. If it is determined not to be the primary slot, the scanned frequency data is forwarded to the primary slot, the primary slot stores the data, and waits for user-mode reading. Figure 5 As shown, if a user-mode data read command is received, the system will start reading data in user mode, starting from the main slot. It will then determine whether all docking slot data is complete. If not, it will wait and continue to determine whether all docking slot data is complete. If complete, it will parse and combine all docking slot data and send the data back to user mode, where it will perform compensation and calibration data processing.

[0039] Kernel mode and user mode are two different operating states. Kernel mode has the highest privileges and can access all system resources, while user mode can only access limited resources. In user mode, applications need to request services from the operating system through system calls, while in kernel mode, the operating system can directly access system resources without needing system calls.

[0040] The switching between kernel mode and user mode is controlled by the operating system kernel. When a process needs to perform privileged operations (such as accessing hardware devices or modifying memory mappings), it must switch to kernel mode. This switching process includes the following steps:

[0041] A process initiates a system call or exception, triggering an interrupt.

[0042] The CPU saves the context of the current process into memory, including the program counter, registers, etc.

[0043] The CPU transfers control to kernel mode to execute the corresponding interrupt handlers or system call handlers.

[0044] After the kernel mode execution is complete, the process context is restored, including the program counter, registers, etc.

[0045] The CPU transfers control back to user mode and continues executing the process's code.

[0046] In this process, the CPU triggers interrupts or system calls through special instructions (such as int, syscall, etc.), and the operating system kernel is responsible for handling these events and switching the running state of processes when necessary.

[0047] This invention places the source component and receiver component of a vector network analyzer into a shielded cavity as a single radio frequency (RF) component module 40. The RF component module 40 exposes a PCI interface that can be inserted into the interface slot 62 of a backplane 60. The backplane 60 contains multiple interface slots 62, meaning it can selectively support multiple RF component modules 40, thereby enabling different port combinations.

[0048] Each RF component module 40 contains two RF ports 42, and each module has manufacturing costs. In some DUT (Device Under Test) testing scenarios, where the DUT is known to have two ports, using a four-port instrument would be wasteful. The VNA ports are determined by the assembly process at the factory, while the DUT ports are determined by the DUT's inherent characteristics. The number of ports on the VNA is determined at the factory by the number of RF component modules 40 that make up the VNA. The multi-port testing process and method involve sequentially stimulating the ports.

[0049] The VNA of this invention is not limited to a specific number of ports. Instead, the ports are grouped into modules that can be combined to form VNAs with any number of ports. Each module contains two ports, and three RF component modules 40 can be assembled into a 6-port VNA. This allows for simultaneous measurement of two DUTs, maximizing port utilization and reducing costs. Similarly, for VNA manufacturers, the entire module remains consistent whether producing 2-, 4-, or 6-port VNAs, without incurring additional R&D or production costs beyond hardware.

[0050] This invention modularizes the design and production of VNAs, blurring the concept of ports, and then assembles them on demand, flexibly supporting customer needs and offering better scalability. Multiple module PCI drivers work collaboratively, turning zero into positive.

[0051] Based on the above-described preferred embodiments according to this application, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the technical concept of this application. The technical scope of this application is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A vector network analyzer, characterized by, The application relates to a radio frequency module, which comprises a shell, a circuit board arranged in the shell, and a radio frequency component module, wherein the circuit board comprises a back plate and a control module electrically connected with the back plate; the radio frequency component module comprises a shielding cavity, a source component arranged in the shielding cavity, a receiver component arranged in the shielding cavity, a radio frequency port, and a docking interface electrically connected with the back plate; a plurality of docking slots for docking with the radio frequency component module are arranged on the back plate, the docking slots are identical, the docking interfaces of different radio frequency component modules are identical and are connected with the docking slots; the docking interface is a PCI interface; if the back plate is connected with a plurality of radio frequency component modules, one of the docking slots on the back plate is designated as a main slot, and the other docking slots are designated as auxiliary slots; the main slot stores the PCI driver sweep data of the radio frequency component module connected therewith and saves and integrates the PCI driver sweep data of the radio frequency component modules connected with the auxiliary slots; the auxiliary slots perform PCI driving, and after the sweep data is read from the hardware, the sweep data is forwarded to the main slot PCI driver in the kernel state for storage; when the user state reads the sweep data, the sweep data is read from the main slot PCI driver; when the sweep data is read, the main slot combines data of all the docking slots, and after the data of all the docking slots is read, the data is returned to the user state. The radio frequency component module is provided with two radio frequency ports.

2. The vector network analyzer of claim 1, wherein, The back plate is provided with 16 docking slots.

3. The vector network analyzer of claim 1, wherein, Each radio frequency component module has an independent PCI driver program and independently runs.

4. The vector network analyzer of claim 1, wherein, The control module receives a starting instruction, controls enumeration of PCI drivers of all the radio frequency component modules in a vector network analyzer, traverses the enumerated driver list, obtains corresponding docking slot information, binds the docking slot and radio frequency port information of the docked radio frequency component module, establishes a corresponding relationship between a VNA port and the radio frequency port of the radio frequency component module and the docking slot of the back plate, establishes a logical port and physical port mapping, confirms a VNA total port number, initializes software port information, and completes starting.

5. The vector network analyzer of claim 1, wherein, The control module receives a starting instruction, controls enumeration of PCI drivers of all the radio frequency component modules in a vector network analyzer, judges whether the driver list is empty, sets a VNA total port number and initializes other modules if the driver list is empty; if the driver list is not empty, reads a back plate slot number, adds a mapping relationship between a VNA port and the radio frequency port of the radio frequency component module and the docking slot of the back plate, accumulates the VNA port number, reduces the driver list by 1, and returns to the judgment of whether the driver list is empty.

6. The vector network analyzer of any one of claims 1 to 5, wherein, ​ 7. The vector network analyzer of claim 1, wherein, The control module receives the sweep instruction, and when starting the sweep, each pair of docking slot positions PCI drive reads sweep data from the FPGA. After the main slot reads the data, it directly stores the data for standby. After the secondary slot reads the data, it forwards the data to the main slot. The main slot saves the data of the secondary slot for standby. When the user state reads data from the kernel state, the data is read from the main slot PCI drive. Before reading, all docking slot positions are traversed to determine whether the data is complete. If not, it waits. If so, the data is returned to the user state. After the user state reads the data, it is calculated for related business and displayed on the UI interface.

8. The vector network analyzer of claim 1, wherein, The control module receives the kernel state scanning instruction, controls the VNA to start scanning, and the PCI drive reads the data. It is determined whether the current docking slot position is the main slot. If it is the main slot, the main slot stores the data and waits for the user state to read. If it is not the main slot, the sweep data is forwarded to the main slot, which stores the data and waits for the user state to read the data. If the user state reads the data instruction is received, the user state reads the data from the main slot. It is determined whether all docking slot positions have complete data. If not, it waits and continues to determine whether all docking slot positions have complete data. If so, all docking slot position data is parsed and combined, and the data is returned to the user state. The user state processes the compensation and calibration data.

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