Touch sensor mutual charge cancellation and related system, method and device

Abstract

A process includes receiving an associated input signal via a receiver electrode of a sensor array, the associated input signal indicating an associated mutual capacitance of the receiver electrode; adding a balancing signal to the associated input signal to generate a balanced input signal at least partially responsive to a number of sensor nodes at the receiver electrode; generating a voltage signal indicating the associated mutual capacitance of the receiver electrode at least partially responsive to the balanced input signal; and generating a digital value representing the voltage signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 198,877, filed on November 19, 2020, entitled “FREE-FORM TOUCH SENSOR MUTUAL CHARGE CANCELLATION,” and the entire disclosure of that U.S. Provisional Patent Application is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to capacitive sensors and mutual capacitance touch sensing. Background Art

[0004] Capacitive sensors are used in a variety of operating environments such as, but not limited to, touch screens, touch pads, and capacitive buttons. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which the element is first introduced.

[0006] Figure 1 is a schematic diagram depicting an apparatus according to one or more examples.

[0007] Figure 2 is a schematic diagram depicting a portion of a touch sensing device utilizing differential signal processing according to one or more examples.

[0008] Figure 3 is a schematic diagram depicting a portion of a touch sensing device utilizing differential signal processing according to one or more examples.

[0009] Figure 4 is a schematic diagram depicting a portion of a touch sensing device utilizing differential signal processing according to one or more examples.

[0010] Figure 5 is a diagram depicting a system for mutual touch sensing according to one or more examples.

[0011] Figure 6 is a flowchart depicting a process according to one or more examples.

[0012] Figure 7 is a block diagram of circuits that, in some examples, may be used to implement the various functions, operations, actions, processes and / or methods disclosed herein.

[0013] Fig. 8A , Figure 8B and Figure 8Cis a schematic diagram of an exemplary arrangement of a sensor layout. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of example specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples enabled herein may be utilized, and structural, material, and process changes may be made without departing from the scope of the present disclosure.

[0015] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. In some cases, similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity of numbering does not necessarily mean that the structures or components are identical in size, composition, construction, or any other attribute.

[0016] The following description may include examples to help those skilled in the art practice the examples disclosed in the present invention. The use of the terms "exemplary", "such as" and "for example" means that the relevant description is illustrative, and although the scope of the present disclosure is intended to cover the examples and legal equivalents, the use of such terms is not intended to limit the scope of the examples or the present disclosure to the specified components, steps, features, functions, etc.

[0017] It should be readily understood that the components of the examples generally described herein and shown in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of these examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0018] In addition, the specific embodiments shown and described are examples only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are exemplary only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between block definitions and individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0019] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some figures may show signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0020] The various exemplary logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or implemented with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to implement the functions described herein. A general purpose processor (which may also be referred to herein as a "host processor" or simply a "host") may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0021] Examples can be described according to the process depicted as a flow chart, a flow diagram, a structure diagram or a block diagram. Although the flow chart can describe the operable actions as a continuous process, many of these actions can be performed in accordance with another sequence, in parallel or substantially simultaneously. In addition, the order of the actions can be rearranged. The process herein may correspond to a method, a thread, a function, a process (procedure), a subroutine, a subprogram, other structures or a combination thereof. In addition, the method disclosed herein can be implemented by hardware, software or both. If implemented in software, these functions can be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media includes both computer storage media and communication media, and the communication media includes any medium that is conducive to transferring a computer program from one location to another.

[0022] Any reference to an element herein using names such as "first," "second," etc. does not limit the number or order of those elements unless such limitations are explicitly stated. Instead, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements can be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0023] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. For example, depending on the particular parameter, attribute, or condition being substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0024] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The terms "on" and "connected" may be used interchangeably with the term "coupled" in this description and have the same meaning, unless otherwise expressly indicated or the context would otherwise indicate to one skilled in the art.

[0025] Mutual capacitance is the capacitive coupling between objects, and in the case of a touch sensor, is the capacitive coupling between the intersections of electrodes that act as transmitters (transmitter electrodes) and electrodes that act as receivers (receiver electrodes), sometimes also referred to as "X electrodes" and "Y electrodes," respectively. In a typical arrangement for mutual capacitance sensing, the transmitter electrodes and receiver electrodes are arranged in a grid of rows and columns, respectively, and the intersections of the transmitter electrodes and receiver electrodes are each referred to as a "sensor node." The transmitter electrode is driven by a pulse that is coupled via the mutual capacitance (C M ) injects current into the capacitance of the receiver electrode. A grounded object that is appropriately close to the sensor node shunts off some of the charge via the capacitively coupled ground path and thus appears to an observer (i.e., measurement circuit) as a change (e.g., a decrease) in the mutual capacitance between the transmitter and receiver electrodes crossing at the sensor node. Mutual capacitance sensing involves detecting this change in mutual capacitance.

[0026] A typical two-dimensional (2D) arrangement of a sensor array for mutual capacitance sensing has a rectangular shape, and a typical touch controller is preconfigured to detect changes in capacitive load at a sensor array having a rectangular shape. Sometimes, multiple arrangements, each having a rectangular shape, are combined together and individually coupled to multiple touch controllers preconfigured to detect changes in capacitive load at a sensor array having a rectangular shape. In the rectangular arrangement of the sensor array, each row (and column) of the sensor array typically has the same number of sensor nodes. The number of sensor nodes per row may be the same as or different from the number of sensor nodes per column. This symmetry facilitates mutual capacitance sensing because the effect of the capacitive load on the sensor array is balanced (i.e., balanced), so by utilizing differential signal processing of adjacent lines, this capacitive load does not limit the operating gain range of the touch controller.

[0027] Sometimes it may be desirable to have a sensor array such as (but not limited to) a touch screen or touchpad in an arrangement having a non-rectangular shape (e.g., trapezoidal or elliptical, and regular or irregular shapes, but not limited thereto). For a non-rectangular arrangement of a sensor array, some rows (or columns) of the sensor array may have a different number of sensor nodes than other rows (or columns) of the sensor array, and the inventors of the present application understand that for certain types of capacitive loads (e.g., connector-connector capacitance or mutual capacitance, but not limited thereto), the impact on the touch sensing measurement varies depending on the number of sensor nodes, and the use of adjacent line differential signal processing is limited in certain areas.

[0028] The inventors of the present disclosure recognized that if each row (or column) of a sensor array has the same number of sensor nodes (as in the case of a rectangular sensor array), it is advantageous to adjust the associated input signal to the measurement circuit or its capacitance-to-voltage converter so that the adjusted associated input signal corresponds (e.g., in terms of magnitude or frequency, but not limited thereto) to the expected input signal, in other words, to reduce at least some of the charge imbalance caused by the capacitance imbalance. In other words, the input signal is changed to be more like the input signal associated with a balanced layout.

[0029] One or more examples are generally directed to an apparatus (e.g., a touch controller, but not limited thereto) comprising a connector, a capacitance-to-voltage converter, a signal balancing circuit, and an analog-to-digital converter. The connector is operable to couple to a receiver electrode of a sensor array. The capacitance-to-voltage converter may be coupled to the connector to generate a voltage signal indicating the associated mutual capacitance of the receiver electrode. The signal balancing circuit may be coupled to an input path of the capacitance-to-voltage converter to add a balanced signal to an associated input signal to generate a balanced input signal provided to the capacitance-to-voltage converter to generate a voltage signal that is in phase or out of phase with the associated input signal. The analog-to-digital converter may be coupled to the capacitance-to-voltage converter to generate a digital value representing the generated voltage signal.

[0030] Figure 1 is a schematic diagram depicting an apparatus 100 according to one or more examples. The apparatus 100 may include a connector 102 , a capacitance-to-voltage converter 104 , an analog-to-digital converter 106 , a signal balancing circuit 108 , and optional logic circuitry 122 .

[0031] The connector 102 is operable to couple with an optional receiver electrode 120 of a sensor array (sensor array not depicted). The receiver electrode 120 may have multiple associated sensor nodes, but for convenience only a single sensor node is depicted. The sensor node has an associated mutual capacitance C M (also referred to as the “associated mutual capacitance C of the receiver electrode 120 M ”). Connector 102 may be any suitable structure for providing electrical contact (e.g., with a mating structure of a sensor array as a non-limiting example), such as, but not limited to, pins or pads.

[0032] Capacitance-to-voltage converter 104 is coupled to connector 102 to generate an associated mutual capacitance C indicative of receiver electrode 120 based at least in part on associated input signal 126. M The voltage signal 112 is provided.

[0033] In one or more examples, capacitance-to-voltage converter 104 can include a capacitor for generating an indication of the associated mutual capacitance C according to any suitable technique. MA non-limiting example of a suitable technique is to utilize a relaxation oscillator that oscillates at a frequency indicative of the associated mutual capacitance. Another non-limiting example of a suitable technique is to utilize a circuit that tracks the time to charge the capacitance of the sensor node to a predetermined voltage or the amount of charge of the sensor node over a predetermined time period - the charging time or the amount of charge indicative of the mutual capacitance. Another non-limiting example of a suitable technique is to utilize a capacitive voltage divider circuit, where if the sensor node and the connector (e.g., connector 102, but not limited to) are each charged to a predetermined voltage and then share the charge, then the resulting voltage at the associated capacitor indicates the change in capacitance at the sensor node. Another non-limiting example of a suitable technique is to utilize a charge transfer circuit that accumulates charge onto an integrating capacitor, and the voltage on the integrating capacitor indicative of the mutual capacitance is compared to a reference voltage or read by an analog-to-digital converter for comparison with a threshold. Another non-limiting example of a suitable technique is to utilize sigma-delta modulation, where the voltage on the external capacitor is modulated around a reference voltage in charge up and charge down operations, and the duration of these operations indicates the mutual capacitance.

[0034] Signal balancing circuit 108 is coupled to input path 118 of capacitance-to-voltage converter 104 to add balanced signal 110 to associated input signal 116 received via connector 102 and receiver electrode 120. Capacitance-to-voltage converter 104 generates an associated mutual capacitance C indicative of receiver electrode 120 using associated input signal 116 to which balanced signal 110 is added. M The voltage signal 112 is provided.

[0035] The amount and phase of the balanced signal 110 added to the associated input signal 116 may be proportional to the number of sensor nodes present along the receiver electrode 120. In one or more examples, the signal balancing circuit 108 may generate the balanced signal 110 at least in part in response to the setting 128 representing the number of sensor nodes present at the receiver electrode. In the event that there are more sensor nodes than an equivalent balanced layout (additional sensor nodes), the balanced signal 110 may be out of phase (i.e., subtracted / cancelled) with the associated input signal 116, the magnitude of the balanced signal 110 may be proportional to the number of additional sensor nodes present, and the predetermined value of the setting 128 preset at the balancing circuit 108 may reflect this phase shift and magnitude. In the presence of fewer sensor nodes than an equivalent balanced layout (missing sensor nodes), the balanced signal 110 can be in phase (i.e., additive / constructive) with the associated input signal 116, the magnitude of the balanced signal 110 can be proportional to the number of missing sensor nodes, and the predetermined value of the setting 128 preset at the signal balancing circuit 108 can reflect this phase offset (in this case no phase offset or generally in phase) and magnitude.

[0036] In one or more examples, the equivalent balanced layout or the number of sensor nodes thereof may be known or predetermined and used to determine the number of additional sensor nodes or the number of missing sensor nodes. As a non-limiting example, the value for setting 128 may be preset at a touch controller including signal balancing circuit 108 for a sensor array arrangement having a predetermined shape. As a non-limiting example, the value for setting 128 may be preset at a touch controller including signal balancing circuit 108 for a sensor array arrangement integrated with such a touch controller. As a non-limiting example, respective values ​​of a plurality of settings 128 ("settings 128") may be preset at a touch controller including signal balancing circuit 108 for a plurality of sensor array arrangements, and respective settings in settings 128 may be selected (or alternatively selected) for respective sensor array arrangements in a plurality of sensor array arrangements optionally integrated with such a touch controller including device 100.

[0037] In one or more examples, the value of setting 128 can indicate a predetermined magnitude and phase expected to reduce at least some charge imbalance at input path 118 due to capacitive imbalance (eg, due to a non-rectangular arrangement of the sensor array).

[0038] Analog-to-digital converter 106 is coupled to capacitance-to-voltage converter 104 to generate a digital value 114 that represents the magnitude of voltage signal 112 and is therefore indicative of the associated mutual capacitance of receiver electrode 120 .

[0039] The mutual capacitance C of the receiver electrodes 120 M may change, so the observed mutual capacitance C of the receiver electrode 120 M The mutual capacitance C of the receiver electrode 120 may change and indicate M The digital value 114 of may change. An optional logic circuit 122 is coupled to the analog-to-digital converter 106 to detect the associated mutual capacitance C of the receiver electrode 120 at least in part in response to the generated digital value 114. M , and generates an indication 124 thereof. As a non-limiting example, logic circuit 122 may include or have access to a storage mutual capacitance C M A memory for a threshold value (e.g., corresponding to a baseline value with no objects near the sensor array including receiver electrodes 120, but not limited thereto) and logic for comparing digital value 114 to the threshold value (e.g., a comparator or threshold detector, but not limited thereto).

[0040] In one or more examples, differential signal processing is utilized in mutual touch sensing, for example, where a differential signal constructed from component signals of adjacent sensor electrodes (transmitters or receivers) is measured to determine a value indicative of mutual capacitance. As non-limiting examples, differential signals can be used for mutual touch sensing with a touch display to reduce the effects of display noise or to support higher signal path gain.

[0041] If the number of sensor nodes of adjacent sensor electrodes is different, the impact of some capacitive loading on the touch sensing measurement may also be correspondingly different. In the case of differential signal processing, the undesirable aspects of such effects may be increased, for example, because the sensor signals do not cancel and the signal path gain is reduced.

[0042] One or more examples generally relate to adding a balanced signal to an associated input signal to generate a differential signal. The added balanced signal is used to compensate for different numbers of sensor nodes along various receiver electrodes of a sensor array and more generally improve differential signal processing.

[0043] Figure 2 2 is a schematic diagram depicting a portion 200 of a touch sensing device utilizing differential signal processing according to one or more examples. Portion 200 includes input path 202, adjacent input path 216, and charge injection circuit 230. Input path 202 includes current amplifier 204 and summing block 208. Adjacent input path 216 includes current amplifier 218 and summing block 222. Charge injection circuit 230 includes voltage driver 232 and Figure 2 The charge compensation capacitor marked as "CC" in the figure.

[0044] exist Figure 2 In the particular non-limiting arrangement depicted, input path 202 is coupled to a receiver electrode 250 associated with a missing sensor node (such missing sensor nodes are referred to herein as "missing sensor nodes 214" for convenience, which does not imply that the present disclosure requires placeholder sensor nodes or inactive sensor nodes) via connector 246. An adjacent input path 216 is coupled to a receiver electrode 252 associated with sensor node 236 via connector 244. Sensor node 236 is present at a sensor array (not depicted) that includes receiver electrode 252, which is also characterized herein as "not missing."

[0045] At adjacent input path 216, current amplifier 218 amplifies associated input signal 238 (associated with receiver electrode 252) received via coupling connector 244 to generate component input signal 220. Component input signal 220 and adjacent component input signal 224 (e.g., originating from adjacent sensor electrodes not shown) are provided to positive and negative inputs, respectively, of summing block 222 to generate differential correlated input signal 228. At input path 202, current amplifier 204 amplifies associated input signal 212 (associated with receiver electrode 250) received via coupling connector 246 to generate component input signal 206. Component input signal 206 and adjacent component input signal 226 are provided to positive and negative inputs, respectively, of summing block 208 to generate differential correlated input signal 210. In one or more examples, differential correlated input signal 210 and differential correlated input signal 228 can be used to detect mutual capacitance at a sensor array including receiver electrodes 252 and 252.

[0046] Figure 2 The depictions of locally generated component input signals (e.g., component input signal 220 and component input signal 206) being provided to the positive input terminals of corresponding summing blocks 208 and summing blocks 222 and remotely generated component input signals (e.g., adjacent component input signal 224 and adjacent component input signal 226) being provided to the negative input terminals of corresponding summing blocks 208 and summing blocks 222 are merely for ease of description, do not limit the present disclosure in any way, and other arrangements are specifically contemplated.

[0047] The charge injection circuit 230 is coupled to a node at the input of the current amplifier 204 to add a charge transfer 240 to the associated input signal 212 (which exhibits a difference from the equivalent balanced layout due to the missing sensor node 214) to generate a balanced input signal 248. In the charge injection circuit 230, the voltage driver 232 generates a drive voltage 242 in response to the event signal 234 and applies it to the compensation capacitor CC. The first plate of the charge compensation capacitor CC is coupled to the output of the voltage driver 232, and the second plate of the charge compensation capacitor CC is coupled to a node, which is coupled to the input of the current amplifier 204 and further coupled to the connector 246. The compensation capacitor CC injects charge (in phase or out of phase) to the input of the current amplifier 204 in response to applying the drive voltage 242 to the second plate of the compensation capacitor CC, thereby adding the charge transfer 240 to the associated input signal 212. Therefore, the charge transfer 240 resolves the difference in charge associated with the input signal 212 and the input signal 238, respectively. As a non-limiting example, this difference may be at least partially affected by differences in capacitive coupling of connector 244 and connector 246.

[0048] In one or more examples, the charge compensation capacitor CC is optionally programmable to be tuned to a fixed voltage output by the voltage driver 232. The magnitude of the balanced signal generated via the charge transfer 240 can be tuned by changing the size (magnitude of capacitance) of the compensation capacitor CC, changing the driver voltage swing of the drive voltage 242, or changing the size of the compensation capacitor CC and changing the driver voltage swing of the drive voltage 242.

[0049] Figure 3 3 is a schematic diagram depicting a portion 300 of a touch sensing device utilizing differential signal processing according to one or more examples. Portion 300 includes input path 302, adjacent input path 316, and charge injection circuit 330. Input path 302 includes current amplifier 304 and summing block 308. Adjacent input path 316 includes current amplifier 318 and summing block 322. Charge injection circuit 330 includes voltage driver 332 and Figure 3 The compensation capacitor marked as CC.

[0050] In one or more examples, the number of sensor nodes 336 present at receiver electrode 352 is different from the number of sensor nodes 314 present at receiver electrode 350. Figure 3 In the particular non-limiting arrangement depicted, input path 302 is coupled to receiver electrode 350 at which a greater number of sensor nodes (sensor nodes 314) are present than a greater number of sensor nodes (sensor nodes 336) are present at receiver electrode 352 coupled to adjacent input path 316. In a particular non-limiting example, an equivalent balanced layout corresponds to a greater number of sensor nodes present at a receiver electrode coupled to input path 316.

[0051] The charge injection circuit 330 is coupled to the node at the input of the current amplifier 304 to add the charge transfer 340 to the associated input signal 312, thereby canceling the effect of the additional node of the sensor node 314 (compared to an equivalent balanced layout) on the associated input signal 312 to generate a balanced input signal 348. More specifically, the voltage driver 332 generates a drive voltage 342 that exhibits a polarity opposite (i.e., out of phase) to the event signal 334. In one or more examples, the polarity of the event signal 334 can be selected (selection not shown) to match the polarity exhibited by the transmitter signal driven at the transmitter electrode of the sensor node 314, so that the charge transfer 340 is out of phase with the associated input signal 312, which is substantially in phase with such transmitter signal and is generated at least partially in response thereto.

[0052] In one or more examples, respective numbers of sensor nodes (e.g., sensor node 336 and sensor node 314, but not limited thereto) may each differ from the number of sensor nodes in an equivalent balanced layout, and one or more charge injection circuits (e.g., charge injection circuit 330, but not limited thereto) may induce charge transfer to input paths (e.g., input path 316 and input path 302, but not limited thereto) to balance associated input signals (e.g., input signal 338 and input signal 312 received via connector 344 and connector 346, respectively, but not limited thereto). In such examples, respective amounts of induced charge transfer at the input paths may be the same or different.

[0053] At adjacent input path 316, current amplifier 318 amplifies associated input signal 338 to generate component input signal 320. Component input signal 320 and adjacent component input signal 324 are provided to positive and negative input terminals, respectively, of summing block 322 to generate differential associated input signal 328. At input path 302, current amplifier 304 amplifies balanced input signal 348 to generate component input signal 306, and component input signal 306 and adjacent component input signal 326 (which includes component input signal 320) are provided to positive and negative terminals, respectively, of summing block 308 to generate differential input signal 310.

[0054] In a single-ended processing example, it is desirable that the respective connector-connector capacitances between adjacent connectors be substantially matched. Differences in the number of sensor nodes along the receiver electrodes may result in different connector-connector capacitances.

[0055] Figure 4 4 is a schematic diagram depicting a portion 400 of a touch sensing device utilizing single-ended signal processing according to one or more examples. Portion 400 includes an input path 402 coupled to a receiver connector 426, a charge injection circuit 412 coupled to a node between the input path 402 and the receiver connector 426, and a voltage driver 422 coupled to an adjacent transmitter connector 424 (i.e., the transmitter connector 424 is disposed proximate to the receiver connector 426). Charge injection circuit 412 includes voltage driver 414 and compensation capacitor CC. Input path 402 includes amplifier 404. A mutual capacitance of a sensor node 428 formed by an intersection of a receiver electrode 430 (coupled to the receiver connector 426) and a driver electrode 432 (coupled to the transmitter connector 424) is denoted by mutual capacitance C. M The connector-connector capacitance between the receiver connector 426 and the transmitter connector 424 is represented by the connector-connector capacitance C P1 express.

[0056] exist Figure 4In the particular non-limiting arrangement depicted, the touch sensing system utilizes differential signal processing Figure 2 and Figure 3 In contrast, input path 402 is an input path of a touch sensing system utilizing single-ended signal processing. In contemplated operation, voltage driver 414 generates voltage signal 420 at least partially in response to event 416 (e.g., generated by a clock source or event logic, but not limited thereto) and applies it to a first plate of compensation capacitor CC. A second plate of compensation capacitor CC is coupled to receiver connector 426, and charge transfer 418 is added to associated input signal 408 in response to voltage signal 420 applied to charge compensation capacitor CC to generate balanced input signal 410. Amplifier 404 amplifies balanced input signal 410 to generate input signal 406. In various examples, charge transfer 418 is added to compensate for connector-connector capacitance C P1 The difference between the capacitance of the connector and the other connector (or the connector-connector capacitance in an equivalent balanced layout) and thus improves single-ended operation.

[0057] Figure 5 is a diagram depicting a system 500 for mutual touch sensing at a touch display according to one or more examples. The system 500 may include a measurement circuit 502, a signal balancing circuit 504, and an optional display 512. An arrangement 514 of receiver electrodes and transmitter electrodes overlies the display 512. Various intersections of the receiver electrodes and transmitter electrodes of the arrangement 514 form sensor nodes, respectively. The sensor nodes 516 are coupled to a plurality of sensors denoted as T X The transmitter electrode of the transmitter connector is coupled to the transmitter electrode denoted as R X The receiver electrodes of the receiver connectors of the sensor nodes are coupled to the measurement circuit 502. In various examples, the measurement logic 508 of the measurement circuit 502 can perform single-ended or differential signal processing for mutual touch sensing as discussed herein, and more specifically, measure the mutual capacitance C of the corresponding sensor nodes 516. M The signal balancing circuit 504 and one or more receiver electrodes R of the sensor node 516 X The signal balancing circuit 504 includes a setting 510 that can be set or preset, and a signal generating logic 506 that generates a balanced signal in response to the value of the setting 510. The value of the corresponding setting 510 can be based at least in part on the signal coupled to the receiver connector R X In various examples, the corresponding settings 510 and their preset values ​​can be associated with the corresponding receiver connectors R Xor associated with a receiver electrode coupled thereto. In one or more examples, the value of configuration setting 510 may relate to, but is not limited to, configuring a compensation capacitor, such as Figure 3 and Figure 4 The compensation capacitor CC is used to generate the required balanced signal.

[0058] It is noted that, although not depicted, the shape exhibited by arrangement 514 may be non-rectangular, such as, but not limited to, a trapezoid, a cone, a polygon, or an ellipse. It is noted that, as a non-limiting example, system 500 may be used for mutual touch sensing at a touch display where arrangement 514 is rectangular, by configuring setting 510 with a value indicating no compensation for charge imbalance.

[0059] Figure 6 is a flow diagram depicting a process 600 according to one or more examples.

[0060] In operation 602 , process 600 receives, via receiver electrodes of a sensor array, associated input signals indicative of associated mutual capacitances of the receiver electrodes.

[0061] In operation 604, process 600 adds the balancing signal to the associated input signal to generate a balanced input signal responsive at least in part to the number of sensor nodes present at the receiver electrode. In one or more examples, a balanced signal can be generated having a phase and magnitude responsive at least in part to the number of sensor nodes present at the receiver electrode or a setting (value) representative thereof. In one or more examples, the magnitude of the balanced signal can be set at a charge compensation capacitor programmed to respond to a voltage inputted by an associated driver (e.g., Figure 2 , Figure 3 or Figure 4 A certain amount of charge is generated by a charge compensation capacitor CC and a fixed voltage generated by the voltage driver 232, the voltage driver 332 or the voltage driver 414, but not limited thereto. As a non-limiting example, the compensation capacitor CC is a programmable capacitor array controlled by a digital value, which can be preset.

[0062] In optional operation 606, process 600 generates a balanced signal that is in phase with the associated input signal. This in-phase balanced signal is constructive with the associated input signal to compensate for the missing sensor node relative to the equivalent balanced layout.

[0063] In optional operation 608, process 600 generates a balanced signal that is out of phase with the associated input signal. This out-of-phase balanced signal cancels the associated input signal to compensate for the additional sensor node relative to the equivalent balanced layout.

[0064] In optional operation 610, process 600 provides charge transfer to or from an input path to add a balanced signal to an associated input signal. Charge transfer to an input path may be understood as constructive, and charge transfer from an input path may be understood as destructive. If a sensor node is missing in a mutual touch sensing system, the charge transferred from the transmitter to the receiver electrode is typically less, so the balance will increase the charge (in phase). If there are additional nodes or additional mutual capacitance coupling (compared to a balanced layout), the balanced signal will decrease the charge (out of phase).

[0065] It is worth noting that operation 610 can be understood as a result of operation 606 or operation 608, that is, providing charge transfer by generating an in-phase or out-of-phase balanced signal applied to the input path.

[0066] At operation 612 , process 600 generates a voltage signal indicative of an associated mutual capacitance of the receiver electrodes in response, at least in part, to the balanced input signal including the associated input signal to which the balanced signal is added.

[0067] At operation 614 , process 600 generates a digital value representing the voltage signal.

[0068] In optional operation 616 , process 600 determines a value representing an associated mutual capacitance of the receiver electrode in response, at least in part, to the generated digital value representing the voltage signal.

[0069] Those skilled in the art will appreciate that the functional elements (eg, functions, operations, acts, processes and / or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 7 Non-limiting examples of implementations of the functional elements disclosed herein are shown.In some examples, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0070] Figure 7700 is a block diagram of a circuit 700, which in some examples can be used to implement various functions, operations, actions, processes and / or methods disclosed herein. The circuit 700 includes one or more processors 702 (sometimes referred to herein as "processors 702") operably coupled to one or more data storage devices (sometimes referred to herein as "storage devices 704"). The storage device 704 includes a machine executable code 706 stored thereon, and the processor 702 includes a logic circuit 708. The machine executable code 706 includes information describing functional elements that can be implemented by the logic circuit 708 (e.g., executed by the logic circuit). The logic circuit 708 is suitable for implementing (e.g., executing) the functional elements described by the machine executable code 706. When executing the functional elements described by the machine executable code 706, the circuit 700 should be regarded as dedicated hardware configured to implement the functional elements disclosed herein. In some examples, the processor 702 can be configured to execute the functional elements described by the machine executable code 706 sequentially, simultaneously (e.g., on one or more different hardware platforms) or in one or more parallel process flows.

[0071] When implemented by the logic circuit 708 of the processor 702, the machine executable code 706 is configured to adapt the processor 702 to perform the operations of the examples disclosed herein. For example, the machine executable code 706 may be configured to adjust the processor 702 to perform Figure 6 For example, the machine executable code 706 may be configured to adjust the processor 702 to execute the process 600 for Figure 1 The device 100, Figure 2 Part 200, Figure 3 Part 300 or Figure 5 For example, the machine executable code 706 may be configured to cause the processor 702 to perform at least a portion or all of the operations discussed in section 400. Figure 5 At least a portion or all of the operations discussed for system 500.

[0072] Processor 702 may include a general purpose processor, a special purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general purpose computer including a processor is configured to execute functional elements corresponding to a machine executable code 706 (e.g., software code, firmware code, hardware description) associated with an example of the present disclosure, the general purpose computer is considered a special purpose computer. It should be noted that a general purpose processor (which may also be referred to as a host processor or simply a host in this article) may be a microprocessor, but in an alternative, processor 702 may include any conventional processor, controller, microcontroller, or state machine. Processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0073] In some examples, the storage device 704 includes a volatile data storage device (e.g., a random access memory (RAM)), a non-volatile data storage device (e.g., a flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, the processor 702 and the storage device 704 may be implemented as a single device (e.g., a semiconductor device product, a system on a chip (SOC), but not limited thereto). In some examples, the processor 702 and the storage device 704 may be implemented as separate devices.

[0074] In some examples, machine executable code 706 may include computer readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer readable instructions may be stored by storage device 704, directly accessed by processor 702, and executed by processor 702 using at least logic circuit 708. Also as a non-limiting example, the computer readable instructions may be stored on storage device 704, transferred to a memory device (not shown) for execution, and executed by processor 702 using at least logic circuit 708. Thus, in some examples, logic circuit 708 includes logic circuit 708 that can be configured in an electrically manner.

[0075] In some examples, machine executable code 706 may describe hardware (e.g., circuits) to be implemented in logic circuit 708 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). As a non-limiting example, a VERILOG TM 、SYSTEMVERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0076] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 708 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic component, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 706 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0077] In examples where the machine executable code 706 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 704) may be configured to implement the hardware description described by the machine executable code 706. As a non-limiting example, the processor 702 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 708 may be electrically controlled to implement circuits corresponding to the hardware description into the logic circuit 708. Also as a non-limiting example, the logic circuit 708 may include hard-wired logic components manufactured by a manufacturing system (not shown, but including the storage device 704) according to the hardware description of the machine executable code 706.

[0078] Regardless of whether the machine executable code 706 includes computer readable instructions or a hardware description, the logic circuit 708 is suitable for performing the functional elements described by the machine executable code 706 when implementing the functional elements of the machine executable code 706. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0079] Fig. 8A , Figure 8B and Figure 8C Non-limiting examples of non-rectangular shaped arrangements of sensor nodes are shown according to one or more examples. Fig. 8A Arrangement 800a is depicted exhibiting an oval shape 806. First receiver electrode 802 includes a plurality of sensor nodes, and second receiver electrode 804 includes a plurality of sensor nodes that is less than the number of sensor nodes of first receiver electrode 802. Examples of missing sensor nodes 808 and missing sensor nodes 810 are depicted to illustrate some sensor nodes that are present in an equivalent balanced layout of sensor nodes having a rectangular shape 812. Similarly, Figure 8B Arrangement 800b is depicted exhibiting a trapezoidal shape 818. First receiver electrode 814 includes a plurality of sensor nodes, and second receiver electrode 816 includes a plurality of sensor nodes that is less than the number of sensor nodes of first receiver electrode 814. Examples of missing sensor nodes 822 and missing sensor nodes 820 are depicted to represent some sensor nodes that would be present in an equivalent balanced layout of sensor nodes having a rectangular shape 824. Figure 8C Arrangement 800c is depicted exhibiting a trapezoidal shape 830. First receiver electrode 826 includes a plurality of sensor nodes, and second receiver electrode 828 includes a plurality of sensor nodes that is less than the number of sensor nodes of first receiver electrode 826. Figure 8C In the particular non-limiting example depicted, the equivalent balanced layout exhibits a rectangular shape 836 having an equivalent area that does not include sensor node 832 and sensor node 834 (which are examples of “additional sensor nodes” discussed above).

[0080] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, without limitation). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are possible and contemplated.

[0081] As used in this disclosure, the term "combination" referring to a plurality of elements may include a combination of all elements or any of various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0082] Terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims), are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to", the term "having" should be interpreted as "having at least", and the term "comprising" should be interpreted as "including but not limited to", without limitation). As used herein, "each" means some or all. As used herein, "each" means all.

[0083] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to an example containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more"); the same is true when a definite article is used to introduce a claim recitation.

[0084] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" means at least two recitations, or two or more recitations, without other modifiers). Moreover, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited thereto.

[0085] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0086] Additional non-limiting embodiments of the present disclosure include: [TBD]

[0087] Embodiment 1: A device comprising: a connector coupled to a receiver electrode of a sensor array; a capacitance-to-voltage converter coupled to the connector to generate a voltage signal indicating an associated mutual capacitance of the receiver electrode; a signal balancing circuit coupled to an input path of the capacitance-to-voltage converter to add a balanced signal to an associated input signal of the receiver electrode to generate a balanced input signal, the signal balancing circuit generating the balanced signal at least partially in response to a setting representing the number of sensor nodes present at the receiver electrode; and an analog-to-digital converter coupled to the capacitance-to-voltage converter to generate a digital value representing the generated voltage signal.

[0088] Embodiment 2: The apparatus of embodiment 1, wherein the balanced signal is in phase with the associated input signal.

[0089] Embodiment 3: The apparatus of embodiment 1 and embodiment 2, wherein the balanced signal is out of phase with the associated input signal.

[0090] Embodiment 4: The apparatus according to embodiments 1 to 3, wherein the signal balancing circuit comprises: a charge injection circuit coupled to provide charge transfer at an input path of a capacitance-to-voltage converter to generate a balancing signal to be added to an associated input signal.

[0091] Embodiment 5: The device according to embodiments 1 to 4, wherein the charge injection circuit comprises: a capacitor and a voltage driver, which are coupled to inject charge at the input path of the capacitor-to-voltage converter for charge transfer.

[0092] Embodiment 6: A device according to embodiments 1 to 5, wherein: a voltage driver is coupled to apply a voltage to a first plate of a capacitor; and a second plate of the capacitor is coupled to inject charge for charge transfer at an input path of a capacitor-to-voltage converter at least partially in response to the voltage applied to the first plate of the capacitor.

[0093] Embodiment 7: The apparatus of embodiments 1 to 6, wherein the charge of the charge transfer is in phase with the associated input signal.

[0094] Embodiment 8: The apparatus of embodiments 1 to 7, wherein the charge of the charge transfer is out of phase with the associated input signal.

[0095] Embodiment 9: An apparatus according to embodiments 1 to 8, wherein the input path comprises: a current amplifier coupled to amplify a balanced input signal; and a summing block for generating a differential signal at least partially in response to a component input signal and an adjacent component input signal, wherein the component input signal comprises an amplified balanced input signal, wherein the capacitance-to-voltage converter generates a voltage signal at least partially in response to the differential signal.

[0096] Embodiment 10: A method comprising: receiving an associated input signal via a receiver electrode of a sensor array, the associated input signal indicating an associated mutual capacitance of the receiver electrode; adding a balanced signal to the associated input signal to generate a balanced input signal at least partially in response to the number of sensor nodes present at the receiver electrode; generating a voltage signal indicating the associated mutual capacitance of the receiver electrode at least partially in response to the balanced input signal including the associated input signal to which the balanced signal is added; and generating a digital value representing the voltage signal.

[0097] Embodiment 11: The method of embodiment 10, comprising providing a charge transfer to or from the associated input signal to add a balancing signal to the associated input signal.

[0098] Embodiment 12: The method of Embodiment 10 and Embodiment 11, comprising determining a value representing an associated mutual capacitance of the receiver electrodes in response, at least in part, to the generated digital value representing the voltage signal.

[0099] Embodiment 13: The method according to embodiments 10 to 12, comprising: generating a balanced signal that is in phase with the associated input signal.

[0100] Embodiment 14: The method according to embodiments 10 to 13, comprising: generating a balanced signal that is out of phase with the associated input signal.

[0101] Embodiment 15: A system comprising: a display; an arrangement of receiver electrodes and transmitter electrodes, the receiver electrodes and transmitter electrodes arranged as capacitive sensor nodes of a sensor array; a measurement circuit coupled to the receiver electrodes and the transmitter electrodes to determine the mutual capacitance of the sensor nodes forming the intersection of the receiver electrodes and the transmitter electrodes; and at least one signal balancing circuit coupled to an input path of the measurement circuit to add a balanced signal to an associated input signal, the added balanced signal being responsive at least in part to the number of sensor nodes at the receiver electrode.

[0102] Embodiment 16: The system of embodiment 15, wherein the arrangement exhibits a non-rectangular shape.

[0103] Embodiment 17: A system according to Embodiment 16, wherein the non-rectangular shape is one of a trapezoid, a cone, a polygon, or an ellipse.

[0104] Although the present disclosure describes the present invention with respect to certain illustrated examples, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: a connector coupled to a receiver electrode of the sensor array; a capacitance-to-voltage converter coupled to the connector to generate a voltage signal indicative of an associated mutual capacitance of the receiver electrodes; a signal balancing circuit coupled to an input path of the capacitance-to-voltage converter to add a balanced signal to an associated input signal of the receiver electrode to generate a balanced input signal, the signal balancing circuit generating the balanced signal responsive at least in part to a setting representing a number of sensor nodes present at the receiver electrode; and An analog-to-digital converter is coupled to the capacitance-to-voltage converter to generate a digital value representing the generated voltage signal.

2. The apparatus of claim 1, wherein the balanced signal is in phase with the associated input signal.

3. The apparatus of claim 1, wherein the balanced signal is out of phase with the associated input signal.

4. The apparatus of claim 1, wherein the signal balancing circuit comprises: A charge injection circuit is coupled to provide a charge transfer at the input path of the capacitance-to-voltage converter to generate the balanced signal for addition to the associated input signal.

5. The apparatus of claim 4, wherein the charge injection circuit comprises: A capacitor and a voltage driver are coupled for injecting charge at the input path of the capacitance-to-voltage converter for the charge transfer.

6. The device according to claim 5, wherein: The voltage driver is coupled to apply a voltage to the first plate of the capacitor; and The second plate of the capacitor is coupled to inject charge of the charge transfer at the input path of the capacitance-to-voltage converter in response, at least in part, to the voltage applied to the first plate of the capacitor.

7. The apparatus of claim 4, wherein the charge of the charge transfer is in phase with the associated input signal.

8. The apparatus of claim 4, wherein the charge of the charge transfer is out of phase with the associated input signal.

9. The apparatus of claim 1, wherein the input path comprises: a current amplifier coupled to amplify the balanced input signal; and a summing block for generating a differential signal in response at least in part to a component input signal and an adjacent component input signal, the component input signal including the amplified balanced input signal, The capacitance-to-voltage converter generates the voltage signal at least partially in response to the differential signal.

10. A method comprising: receiving, via receiver electrodes of a sensor array, associated input signals indicative of associated mutual capacitances of the receiver electrodes; adding a balanced signal to the associated input signal to generate a balanced input signal responsive at least in part to a number of sensor nodes present at the receiver electrode; generating a voltage signal indicative of the associated mutual capacitance of the receiver electrodes in response, at least in part, to a balanced input signal including the associated input signal to which the balanced signal is added; and A digital value representing the voltage signal is generated.

11. The method according to claim 10, comprising: Charge transfer is provided to or from the associated input signal to add the balancing signal to the associated input signal.

12. The method according to claim 10, comprising: A value representing the associated mutual capacitance of the receiver electrode is determined at least in part in response to the generated digital value representing the voltage signal.

13. The method according to claim 10, comprising: The balanced signal is generated to be in phase with the associated input signal.

14. The method according to claim 10, comprising: The balanced signal is generated out of phase with the associated input signal.

15. A system, comprising: monitor; an arrangement of receiver electrodes and transmitter electrodes arranged as capacitive sensor nodes of a sensor array; a measurement circuit coupled to the receiver electrode and the transmitter electrode to determine a mutual capacitance of a sensor node forming an intersection of the receiver electrode and the transmitter electrode; and At least one signal balancing circuit is coupled to an input path of the measurement circuit to add a balanced signal to an associated input signal, the added balanced signal being responsive at least in part to a number of sensor nodes at the receiver electrode.

16. The system of claim 15, wherein the shape exhibited by the arrangement is a non-rectangular shape.

17. The system of claim 16, wherein the non-rectangular shape is one of a trapezoid, a cone, a polygon, or an ellipse.

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