A power semiconductor device health monitoring circuit and method

Abstract

The application provides a power semiconductor device health monitoring circuit and method, and belongs to the technical field of power semiconductor device measurement. The power semiconductor device health monitoring circuit comprises: a driving circuit used for receiving a pulse driving signal output by a control chip and outputting a driving signal to control a device to be measured to work; a first switch tube used for receiving a first pulse signal of the control chip and controlling the conduction or turn-off of the first switch tube according to the first pulse signal; a second switch tube used for receiving a second pulse signal of the control chip and controlling the conduction or turn-off of the second switch tube according to the second pulse signal; wherein a current source provides excitation current for the first switch tube and the second switch tube; and a voltage sampling module is used for sampling the voltage of the device to be measured. The problems of high bandwidth requirement of the measurement circuit, low measurement accuracy and difficulty in engineering practical application are solved, and the threshold voltage can be accurately measured.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device measurement technology, and relates to a power semiconductor device health monitoring circuit and method. Background Technology

[0002] Power electronics technology, with power semiconductors at its core, plays a vital role in various fields such as electric vehicles, renewable energy generation, and ultra-high voltage direct current transmission. As the requirements for power levels, response speeds, and power densities in power electronic devices increase, the reliability of power semiconductor devices seriously threatens their safe and reliable operation, making it necessary to monitor the status information of power semiconductor devices.

[0003] During the operation of power semiconductor devices, the junction temperature is crucial to their reliable operation, and the threshold voltage can be used to determine thermistor parameters. It is an important reference for the junction temperature of the device and whether it has good identification and higher linearity. Similarly, the threshold voltage is also a potential indicator of gate oxide degradation, so it is an important parameter for evaluating device reliability.

[0004] Existing methods for measuring threshold voltage include offline and online measurements. Offline measurements are mostly performed under laboratory conditions, measuring the static threshold voltage of a device individually to assess its reliability. However, this method is difficult to apply in practical power circuits. Online real-time measurement methods measure the voltage at the rising edge of the switching action of power semiconductor devices. This requires high-speed circuitry to sample the instantaneous threshold voltage. The faster the device switches, the higher the bandwidth requirement for the measurement circuit. Furthermore, in practical applications, many interferences can affect the accuracy of the threshold voltage measurement, making accurate threshold voltage measurement difficult to achieve online. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides a health monitoring circuit for power semiconductor devices. By adding a threshold voltage measurement circuit to the driving circuit of the power semiconductor device, the normal operation of the conventional drive is not affected when the device is working normally, and the threshold voltage can be accurately measured when the device stops working, realizing quasi-online measurement. This solves the problems of high bandwidth requirements, low measurement accuracy, and difficulty in practical engineering application of the existing technology.

[0006] The technical solution adopted in this invention is:

[0007] A first aspect of this invention provides a power semiconductor device health monitoring circuit, comprising: a driving circuit connected to a control chip, for receiving a pulse driving signal output by the control chip and outputting a driving signal to control the operation of a device under test (DUT); the output terminal of the driving circuit is connected to a first terminal of a second resistor Rgint, and the second terminal of the second resistor Rgint is connected to the gate of the DUT; a first switching transistor, the control terminal of which is connected to the control chip, for receiving a first pulse signal from the control chip and controlling the switching transistor to be turned on or off according to the first pulse signal; the gate of the first switch Q1 is connected to the first pulse signal, the source is grounded, and the drain, a current source, and the anode of a unidirectional diode T2 are connected; the cathode of the unidirectional diode T2 is connected to a first terminal of a first resistor R1, and the second terminal of the first resistor R1 is connected to the drain of the DUT. The device under test (DUT) consists of two transistors: a second switch and a second switch. The control terminal of the second switch is connected to the control chip to receive the second pulse signal from the control chip and control the second switch to turn on or off according to the second pulse signal. The gate of the second switch is connected to the second pulse signal, the drain is connected to the drain of the first switch Q1, and the source is connected to the first terminal of the second resistor Rgint. The second terminal of the second resistor Rgint is connected to the gate of the DUT. The current source provides excitation current for the first and second switches. A voltage sampling module is connected to the control chip and the DUT. Specifically, the sampling module is connected to the second terminal of the second resistor Rgint, i.e., the gate of the DUT. When the first pulse signal and the second pulse signal control the first switch to turn off and the second switch to turn on, respectively, the pulse drive signal controls the drive circuit to stop working and samples the voltage of the DUT.

[0008] In one embodiment, the driving circuit includes: a first transistor, a second transistor, an isolation capacitor, a high-frequency magnetic ring, a first diode, and a third resistor; the control terminals of the first transistor and the second transistor serve as input terminals of the driving circuit, connected to a control chip, and inputting pulse driving signals; the first terminal of the first transistor is connected to a built-in power supply; the first terminal of the isolation capacitor is connected to the second terminal of the first transistor and the first terminal of the second transistor; the first terminal of the primary side of the high-frequency magnetic ring is connected to the second terminal of the isolation capacitor; the second terminal of the primary side of the high-frequency magnetic ring is connected to the second terminal of the second transistor; the first terminal of the third resistor is connected to the first terminal of the secondary side of the high-frequency magnetic ring; the output terminal of the first diode is connected to the second terminal of the third resistor and the gate of the device under test; the second terminal of the third resistor serves as the output terminal of the driving circuit, outputting driving signals to the device under test.

[0009] In one embodiment, the driving circuit further includes a second diode, the output terminal of which is connected to the input terminal of the first diode; the input terminal of the second diode is connected to the second end of the secondary side of the high-frequency magnetic ring and the source of the device under test.

[0010] A second aspect of the present invention provides a power semiconductor device fault monitoring method, comprising: S1: detecting whether the driving circuit connected to the gate of the device under test is working normally; when the driving circuit is working normally, a pulse driving signal controls the driving circuit, and the driving signal controls the device under test to work; wherein, the pulse driving signal is output by the control chip, and the driving signal is output by the driving circuit; at this time, the first switch in the threshold voltage measurement circuit is turned on, the second switch is turned off, and the current source in the measurement circuit flows to ground through the first switch; when the driving circuit stops working, proceed to step 2; S2: the first switch is turned off, the second switch is turned on, the current source turns on the device under test, and when the drain current of the device under test increases to a preset value, the gate voltage of the device under test is clamped and proceed to step 3; S3: measuring the clamped gate voltage through a voltage sampling circuit.

[0011] In one embodiment, in S1, the control chip outputs a pulse drive signal to control the drive circuit. The control terminals of the first transistor and the second transistor serve as the input terminals of the drive circuit, and the pulse drive signal is input. The first transistor and the second transistor are complementary in conducting to control their drive circuits to conduct, so as to output a drive signal.

[0012] In one embodiment, S2 includes: during the t0-t1 stage, when the device under test (DUT) is in the cutoff region, the current source input current charges the DUT through the first circuit, and the gate voltage of the DUT continuously increases; after t1, when the gate voltage of the DUT reaches the threshold voltage, since the resistance value of the first resistor is less than the resistance value of the second resistor, the drain current of the DUT begins to increase, and the current begins to transfer from the first circuit to the second circuit; when the drain current of the DUT increases to the current preset value, the drain current of the DUT no longer increases, and the gate voltage of the DUT in the first circuit is clamped.

[0013] In one embodiment, S3 includes measuring the gate-source voltage value of the device under test when the second switch is turned on, the device under test is in the on state, and the gate voltage of the device under test is clamped to remain unchanged.

[0014] In one embodiment, when S3 measures the magnitude of the gate-source voltage, it uses the formula... The gate-source voltage value of the device under test is calculated; wherein, To measure the gate-source voltage of the device under test, This is the threshold voltage of the device under test.

[0015] The beneficial effects of this invention are as follows: The power semiconductor device health monitoring circuit receives the pulse drive signal output by the control chip through the drive circuit, and outputs a drive signal to control the operation of the device under test; the first switch is used to receive the first pulse signal from the control chip, and controls the first switch to be turned on or off according to the first pulse signal; the second switch is used to receive the second pulse signal from the control chip, and controls the second switch to be turned on or off according to the second pulse; wherein, the current source provides excitation current for the first switch and the second switch; the voltage sampling module samples the voltage of the device under test; without affecting the conventional drive operation, it combines the advantages of offline measurement and online measurement to achieve quasi-online measurement, which can accurately measure the threshold voltage of the power semiconductor device in the actual power circuit and reflect the threshold voltage change of the device in real time. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram of a power semiconductor device fault monitoring structure provided in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the signal and current flow direction during normal operation of a drive, provided by an embodiment of the present invention;

[0020] Figure 4 This is a conduction process diagram of a device under test under voltage and current sources according to an embodiment of the present invention;

[0021] Figure 5 This is a switching timing diagram of a driving circuit provided in an embodiment of the present invention;

[0022] Figure 6 This is a threshold voltage measurement waveform diagram provided in an embodiment of the present invention;

[0023] Figure 7 This is a flowchart of a power semiconductor intelligent drive provided by an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] See Figure 1 , Figure 1 This is a structural diagram of a power semiconductor device health monitoring circuit according to an embodiment of the present invention;

[0026] A first aspect of this invention provides a power semiconductor device health monitoring circuit, comprising: a driving circuit 10 connected to a control chip 11, for receiving pulse driving signals output by the control chip 11 and outputting driving signals to control the device under test (DUT). The device under test (DUT) operates as follows: A first switch Q1, whose control terminal is connected to the control chip 11, receives a first pulse signal from the control chip 11 and controls the first switch Q1 to turn on or off according to the first pulse signal; the first terminal of the first switch Q1 is connected to the current source S; the second terminal of the first switch Q1 is grounded; a second switch Q2, whose control terminal is connected to the control chip 11, receives a second pulse signal from the control chip 11 and controls the second switch Q2 to turn on or off according to the second pulse; the first terminal of the second switch Q2 is connected to the current source S; the second terminal of the second switch Q2 is connected to the drive circuit 10; wherein, the current source S provides excitation current for the first switch Q1 and the second switch Q2; a voltage sampling module 20, connected to the control chip 11 and the DUT, when the first pulse signal and the second pulse signal respectively control the first switch Q1 to turn off and the second switch Q2 to turn on, controls the drive circuit 10 to stop working and samples the voltage of the DUT.

[0027] In this embodiment, the power semiconductor device health monitoring circuit combines the power semiconductor device driving circuit 10 with the threshold voltage measurement circuit to form an intelligent drive that can measure the threshold voltage, i.e., an intelligent drive for power semiconductor device health monitoring; wherein, the driving circuit 10 is an intermediate circuit used to amplify the signal of the control circuit (i.e., amplify the signal of the control circuit so that it can drive the power transistor), that is, amplify the PWM (Pulse Width Modulation) pulse output by the control chip 11 to amplify the power transistor switching power.

[0028] It should be noted that the control chip 11 can be a control circuit, or a control system or other equipment or device used for the control (including detection) of mechanical and electrical equipment.

[0029] In this embodiment, the first switch Q1 and the second switch Q2 can be any one of a transistor, an IGBT (Insulated Gate Bipolar Transistor), or a field-effect transistor. The first switch Q1 and the second switch Q2 can be the same type of switch or different types of switch.

[0030] Preferably, the first switching transistor Q1 and the second switching transistor Q2 are transistors, and switching transistors are selected. The switching transistors operate in the cutoff region and the saturation region to realize the turn-off and turn-on of the switching transistors.

[0031] Specifically, the first switch Q1 is an N-MOSFET 2N-7002 type switch; the second switch Q2 is an N-MOSFET 2N-7002 type switch.

[0032] In this embodiment, the voltage sampling module 20 can be a general-purpose data acquisition module with an embedded high-performance ARM (Advanced RISC Machine) processor, designed for industrial automation control scenarios. It adopts technologies such as mutual isolation between power supply, measurement, and communication, and the input terminal adopts ESD (Electro-Static discharge), overvoltage, and overcurrent protection designs, which have stable performance and strong anti-interference capabilities. It can also be a device or apparatus with online general-purpose voltage acquisition function.

[0033] In this embodiment, the current source S, or ideal current source, is a model abstracted from a real power source. Regardless of the voltage across its terminals, it can always provide a certain current to the outside. The current source S has two fundamental properties: First, the current it provides is a constant value I or a certain time function I(t), independent of the voltage across its terminals. Second, the current of the current source S itself is determined, while the voltage across its terminals is arbitrary. Since the current of the current source S is fixed, the current source S cannot be open-circuited. When the current source S is connected in series with a resistor, its effect on the external circuit is the same as that of a single current source S. Furthermore, the current source S and voltage source can be equivalently converted; a current source S connected in parallel with a resistor can be equivalent to a voltage source connected in series with a resistor. Specifically, the current source S can be set to a current value of 5.2mA.

[0034] In this embodiment, the device under test (DUT) may also include at least one diode, which is connected in parallel with the internal switching device of the DUT to improve the reliability and stability of the circuit, as well as the efficiency and performance of the circuit.

[0035] See Figure 2 , Figure 2 This is a schematic diagram of a driving circuit according to an embodiment of the present invention. The driving circuit 10 includes: a first transistor V1, a second transistor V2, an isolation capacitor C, a high-frequency magnetic ring T1, a first diode Z1, and a third resistor R3. The control terminals of the first transistor V1 and the second transistor V2 serve as the input terminals of the driving circuit 10 and are connected to the control chip 11 to input pulse driving signals. The first terminal of the first transistor V1 is connected to the built-in power supply. The first terminal of the isolation capacitor C is connected to the second terminal of the first transistor V1 and the first terminal of the second transistor V2. The first terminal of the primary side of the high-frequency magnetic ring T1 is connected to the second terminal of the isolation capacitor C. The second terminal of the primary side of the high-frequency magnetic ring T1 is connected to the second terminal of the second transistor V2. The first terminal of the third resistor R3 is connected to the first terminal of the secondary side of the high-frequency magnetic ring T1. The output terminal of the first diode Z1 is connected to the second terminal of the third resistor R3 and the gate of the device under test (DUT). The second terminal of the third resistor R3 serves as the output terminal of the driving circuit 10 and outputs a driving signal to the DUT.

[0036] In this embodiment, the first transistor V1 and the second transistor V2 can be any one of a transistor, a field-effect transistor, or a thyristor; the first transistor V1 and the second transistor V2 can be the same type of transistor or different types of transistors.

[0037] Preferably, when the first transistor V1 and the second transistor V2 are transistors, the first transistor V1 and the second transistor V2 are complementary in conduction, so that the transistors can conduct or turn off each other.

[0038] In this embodiment, the first diode Z1 is an SBD (Schottky Barrier Diode). SBDs are not fabricated using the principle of forming a PN junction between P-type and N-type semiconductors, but rather using the principle of forming a metal-semiconductor junction between a metal and a semiconductor. Therefore, SBDs are also called metal-semiconductor (contact) diodes or surface barrier diodes; they are a type of hot-carrier diode.

[0039] In this embodiment, the isolation capacitor C can be an isolation capacitor, which has an insulator between two plates to provide anti-interference.

[0040] In this embodiment, the high-frequency magnetic ring T1 is a magnetic ring that suppresses higher harmonics, and can be a nickel-zinc magnetic ring.

[0041] In this embodiment, the built-in power supply is set to +15V. The specific voltage value can be replaced according to the experimental needs, and no specific restrictions are made here.

[0042] In one embodiment, the driving circuit 10 further includes a second diode Z2, the output terminal of which is connected to the input terminal of the first diode Z1; the input terminal of the second diode Z2 is connected to the second end of the secondary side of the high-frequency magnetic ring T1 and the source of the device under test (DUT).

[0043] In this embodiment, the second diode Z2 and the first diode Z1 are the same diodes, both of which are SBDs.

[0044] In one embodiment, the health monitoring circuit further includes: a first resistor R1, the first end of which is connected to the first end of the first switch Q1 and the current source S; the second end of the first resistor R1 is connected to the device under test (DUT); and / or, a second resistor Rgint, the first end of which is connected to the drive circuit 10 and the second end of the second switch Q2; and the second end of the second resistor Rgint is connected to the device under test (DUT).

[0045] In this embodiment, the second resistor Rgint and the second switch Q2 form a first loop, which is a loop formed in the direction of current conduction; the first resistor R1 and the unidirectional diode T2 form a second loop, which is a loop formed in the direction of current conduction. It should be noted that the second resistor Rgint is the gate drive resistor of the device under test (DUT), and the first resistor R1 is the resistor of the second loop. The resistance value of the second resistor Rgint is greater than the resistance value of the first resistor R1. The resistance range of the first resistor R1 and the second resistor Rgint can be selected according to experimental needs and the conduction parameters of the switch. Preferably, the second resistor Rgint can be 4.7 ohms and the first resistor R1 can be 1 ohm.

[0046] It should be noted that the first resistor R1 and the second resistor Rgint can be set simultaneously; or, when the corresponding switching transistor is controlled by setting the corresponding pulse parameters through the control chip, one of the first resistor R1 and the second resistor Rgint can be set. Specifically, the resistor can be set one or both resistors can be set simultaneously according to the experimental requirements.

[0047] In one embodiment, the health monitoring circuit further includes a unidirectional diode T2, the input terminal of which is connected to the first terminal of the first switch Q1 and the first terminal of the second switch Q2; the output terminal of the unidirectional diode is connected to the first terminal of the first resistor R1.

[0048] In this embodiment, the unidirectional diode T2 can be a Zener diode, which is a special type of surface-contact semiconductor silicon diode that has the function of stabilizing voltage. The Zener diode operates in the reverse breakdown state of the PN junction. By taking process measures during manufacturing and limiting the magnitude of the reverse current during use, it can be ensured that the Zener diode will not be damaged by overheating in the reverse breakdown state.

[0049] A second aspect of the present invention provides a power semiconductor device fault monitoring method, comprising: S1 detecting whether a drive circuit 10 connected to the gate of a device under test (DUT) is working normally; when the drive circuit 10 is working normally, a pulse drive signal controls the drive circuit 10, and the drive signal controls the DUT to work; wherein, the pulse drive signal is output by a control chip 11, and the drive signal is output by the drive circuit 10; at this time, the first switch Q1 in the threshold voltage measurement circuit is turned on, the second switch Q2 is turned off, and the current source S in the measurement circuit flows to ground through the first switch Q1; when the drive circuit 10 stops working, proceed to step 2; S2 the first switch Q1 is turned off, the second switch Q2 is turned on, the current source S turns on the DUT, and when the drain current of the DUT increases to a preset value, the gate voltage of the DUT is clamped and proceed to step 3; S3 measuring the clamped gate voltage through a voltage sampling circuit.

[0050] See Figure 3 , Figure 3 This is a schematic diagram of signal and current flow during normal operation of the drive circuit according to an embodiment of the present invention. The power semiconductor device fault monitoring method, combined with the circuit operating principle, first detects whether the gate drive is working properly. When the drive circuit 10 is working normally, the control chip 11 normally sends a PWMdrive signal to the drive circuit 10 to drive the device under test (DUT) to work normally. At this time, the first switch Q1 in the threshold voltage measurement circuit is turned on, and the second switch Q2 is turned off; the current source S in the measurement circuit flows to ground through the first switch Q1. Then, when the drive circuit 10 stops working, the switch Q2 is turned on.

[0051] At the same time, according to Figure 4 , Figure 4 This is a conduction diagram of a device under test (DUT) under voltage and current sources according to an embodiment of the present invention; the first switch Q1 is turned off, the second switch Q2 is turned on, and the threshold voltage measurement begins. The driving circuit 10 turns on the device by applying a positive voltage to the gate of the DUT, and the different measurement circuits turn on the switches through the current source S.

[0052] It should be noted that when a power semiconductor device has a voltage source or a current source at its gate, different effects are produced depending on the changes in various parameters during the device's conduction process. Specifically, the technical effects are produced according to the voltage source signal and the current source signal at corresponding time periods.

[0053] Furthermore, when the drive circuit is working, the PWMdrive generates a normal waveform, and the voltage source is applied to the gate of the power device to turn it on. At this time, the first switch Q1 is turned on, while the second switch Q2 is turned off. The current source of the measurement circuit is grounded through the first switch Q1 and does not work.

[0054] Furthermore, when PWMdrive is low, the drive circuit is not working, switching transistor Q1 is off, and Q2 is on. At this time, the current source will turn on the power devices, and the measurement circuit will operate. It should be noted that the signal changes of the voltage and current sources are controlled by three PWM waves. Figure 5 .

[0055] See Figure 5 , Figure 5 This is a timing diagram of a drive circuit switch provided in an embodiment of the present invention. During the t0-t1 stage, the switch is in the cutoff region, and the input current of the current source S charges the device under test (DUT) through the first circuit. At this time, the gate voltage of the DUT continuously increases. After t1, the gate voltage reaches the threshold voltage. Since the first resistor R1 of the second circuit is less than the second resistor Rgint of the first circuit, the drain current of the DUT begins to increase. The input current of the current source S is transferred from the first circuit to the second circuit. When the drain current of the DUT increases to the current preset value, the drain current of the DUT no longer increases, and the gate voltage of the DUT connected to the first circuit is clamped. At this time, the gate voltage of the DUT is the preset voltage value output by the current source S to the drain of the DUT.

[0056] It should be noted that when the PWMdrive signal is in the normal driving phase, it continuously switches between high and low levels. At this time, the voltage source enables the power device to operate normally in the main power circuit. The changes in different periods and within the same period ensure that the device maintains the correct operating condition in the power circuit. The PWM1 and PWM2 signals are not periodic. When the device is operating normally in the main power circuit, PWM1 is high, indicating that the first switch Q1 is turned on, and PWM2 is low, indicating that the second switch Q2 is turned off. When it is necessary to measure the threshold voltage, PWM1 is low, turning off the first switch Q1, and PWM2 is high, turning on the second switch Q2, so that the measurement circuit can work.

[0057] See Figure 6 , Figure 6This is a threshold voltage measurement waveform diagram provided in an embodiment of the present invention. When measuring the threshold voltage Vth, the second switch Q2 is turned on, the device under test (DUT) is in the on state, and its gate voltage is clamped and remains unchanged. At this time, the magnitude of the gate-source voltage of the DUT is measured, and its value is equal to the threshold voltage of the DUT. The threshold voltage is transmitted back to the control chip 11 through the voltage sampling circuit, thus completing the threshold voltage measurement. The measurement is then calculated using the formula... Indicates the magnitude of a numerical value.

[0058] It should be noted that the threshold voltage is the gate-source voltage at which the power device begins to conduct. Figure 6 The measured voltage is the clamped gate-source voltage, which is the threshold voltage that needs to be measured in the technical solution.

[0059] Furthermore, the measurement results are for the threshold voltage proposed in this application. However, during the measurement process, the PWM1 and PWM2 signals were periodically processed, so the power device was in a periodic on / off process. Figure 6 The measurement results exhibit periodicity, during which the drive circuit remains switched off. This method demonstrates good applicability in practical applications, where low bandwidth and stable measurement results are required.

[0060] See Figure 7 , Figure 7 This is a flowchart of a power semiconductor intelligent driving process according to an embodiment of the present invention. First, the gate drive of the device under test is checked for normal operation. If normal, the check is repeated; if abnormal, proceed to S2, and then the threshold voltage is measured. In S1, the control chip 11 outputs a pulse drive signal to control the drive circuit 10. The control terminals of the first transistor V1 and the second transistor V2 serve as the input terminals of the drive circuit 10, receiving the pulse drive signal. The first transistor V1 and the second transistor V2 are complementary in conduction, controlling the drive circuit 10 to conduct in order to output the drive signal.

[0061] In this embodiment, the first transistor V1 and the second transistor V2 use complementary transistor logic to implement logic gate circuits.

[0062] In one embodiment, S2 includes: during the t0-t1 stage, when the device under test (DUT) is in the cutoff region, the input current of the current source S charges the DUT through the first circuit, and the gate voltage of the DUT continuously increases; after t1, when the gate voltage of the DUT reaches the threshold voltage, since the resistance of the second resistor Rgint is greater than the resistance of the first resistor R1, the drain current of the DUT begins to increase, and the current is transferred from the first circuit to the second circuit; when the drain current of the DUT increases to the current preset value, the drain current of the DUT no longer increases, and the gate voltage of the DUT in the first circuit is clamped.

[0063] In this embodiment, the conduction process when the device under test (DUT) is connected to a voltage source or current source S can include multiple time periods, the specific time periods of which are divided according to experimental needs and test results.

[0064] In one embodiment, S3 includes measuring the gate-source voltage value of the device under test (DUT) when the second switch Q2 is turned on, the device under test (DUT) is in the on state, and the gate voltage of the DUT is clamped and remains unchanged.

[0065] It should be noted that the device under test (DUT) selected is a CREE SiC MOSFET (silicon carbide) C3M0120065D.

[0066] In one embodiment, when S3 measures the magnitude of the gate-source voltage, it uses the formula... The gate-source voltage value of the device under test (DUT) is calculated; where, The threshold voltage of the device under test (DUT) To measure the gate-source voltage of the device under test (DUT).

[0067] In this embodiment, the threshold voltage The input voltage corresponding to the midpoint of the inflection point where the output current changes drastically with the input voltage in the transfer characteristic curve is usually called the threshold voltage, which has different parameters when describing different devices.

Claims

1. A health monitoring circuit for a power semiconductor device, characterized in that, include: A driving circuit, connected to a control chip, is used to receive pulse driving signals output by the control chip and output driving signals to control the device under test. The output terminal of the driving circuit is connected to the first terminal of the second resistor Rgint, and the second terminal of the second resistor Rgint is connected to the gate of the device under test. The first switch Q1 has its control terminal connected to the control chip 11. It is used to receive the first pulse signal from the control chip 11 and control the first switch to turn on or off according to the first pulse signal. The gate of the first switch Q1 is connected to the first pulse signal, the source is grounded, and the drain, current source, and positive terminal of the unidirectional conduction diode T2 are connected. The negative terminal of the unidirectional conduction diode T2 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the drain of the device under test. The second switch Q2 has its control terminal connected to the control chip. It receives a second pulse signal from the control chip and controls the second switch to turn on or off based on the second pulse signal. The gate of the second switch is connected to the second pulse signal, its drain is connected to the drain of the first switch Q1, and its source is connected to the first terminal of the second resistor Rgint. The second terminal of the second resistor Rgint is connected to the gate of the device under test. The current source provides excitation current to both the first and second switches. The voltage sampling module is connected to the control chip and the device under test (DUT). Specifically, the sampling module is connected to the second terminal of the second resistor Rgint, which is the gate of the DUT. When the first pulse signal and the second pulse signal control the first switch to turn off and the second switch to turn on, respectively, the pulse drive signal controls the drive circuit to stop working and performs voltage sampling on the DUT.

2. The health monitoring circuit as described in claim 1, characterized in that, The driving circuit includes: a first transistor, a second transistor, an isolation capacitor, a high-frequency magnetic ring, a first diode, and a third resistor; The control terminals of the first transistor and the second transistor serve as the input terminals of the drive circuit, and are connected to the control chip to input the pulse drive signal. The first terminal of the first transistor is connected to the built-in power supply; The first terminal of the isolation capacitor is connected to the second terminal of the first transistor and the first terminal of the second transistor. The first end of the primary side of the high-frequency magnetic ring is connected to the second end of the isolation capacitor; the second end of the primary side of the high-frequency magnetic ring is connected to the second end of the second transistor. The first end of the third resistor is connected to the first end of the secondary side of the high-frequency magnetic ring. The output terminal of the first diode is connected to the second terminal of the third resistor and the gate of the device under test; The second end of the third resistor serves as the output terminal of the driving circuit, outputting a driving signal to the device under test.

3. The health monitoring circuit as described in claim 2, characterized in that, The driving circuit also includes a second diode; The output terminal of the second diode is connected to the input terminal of the first diode; The input terminal of the second diode is connected to the second end of the secondary side of the high-frequency magnetic ring and the source of the device under test.

4. A method for fault monitoring of power semiconductor devices, based on the health monitoring circuit according to any one of claims 1-3, characterized in that, include: S1: Detect whether the drive circuit connected to the gate of the device under test is working properly; When the drive circuit is working normally, the pulse drive signal controls the drive circuit, and the drive signal controls the device under test to work; wherein, the pulse drive signal is output by the control chip, and the drive signal is output by the drive circuit; at this time, the first switch in the threshold voltage measurement circuit is turned on, the second switch is turned off, and the current source in the measurement circuit flows to ground through the first switch; When the drive circuit stops working, proceed to step S2; S2: The first switch is turned off, the second switch is turned on, and the current source turns on the device under test. When the drain current of the device under test increases to a preset value, the gate voltage of the device under test is clamped and then proceeds to step S3. S3: Measure the clamped gate voltage through the voltage sampling circuit.

5. The fault monitoring method as described in claim 4, characterized in that, In S1, the control chip outputs a pulse drive signal to control the drive circuit. The control terminals of the first transistor and the second transistor serve as the input terminals of the drive circuit, and the pulse drive signal is input. The first transistor and the second transistor conduct in a complementary manner to control the drive circuit to conduct, so as to output a drive signal.

6. The fault monitoring method as described in claim 4, characterized in that, S2 include: During the t0-t1 stage, when the device under test is in the cutoff region, the current source input current charges the device under test through the first circuit, and at this time the gate voltage of the device under test continuously increases. After t1, when the gate voltage of the device under test reaches the threshold voltage, since the resistance value of the first resistor is less than the resistance value of the second resistor, the drain current of the device under test begins to increase, and the current shifts from the first circuit to the second circuit. When the drain current of the device under test increases to the preset current value, the drain current of the device under test no longer increases, and the gate voltage of the device under test in the first circuit is clamped.

7. The fault monitoring method as described in claim 4, characterized in that, S3 includes measuring the gate-source voltage value of the device under test when the second switch is turned on, the device under test is in the on state, and the gate voltage of the device under test is clamped to remain unchanged.

8. The fault monitoring method as described in claim 7, characterized in that, When S3 measures the gate-source voltage, according to the formula... The gate-source voltage value of the device under test is calculated; wherein, To measure the gate-source voltage of the device under test, This is the threshold voltage of the device under test.

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