A fully analog circuit system for handwritten digit recognition based on a storage-computing integrated architecture

Abstract

The present invention discloses a fully analog circuit system for handwritten digit recognition based on a storage-computing integrated architecture, comprising a first analog circuit and a second analog circuit. The first analog circuit is composed of the following circuit modules: an input drive circuit, a first resistor array with a scale of m columns and 2n rows, a first current-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit; the second analog circuit is composed of the following circuit modules: a second resistor array with a scale of n columns and 20 rows, a second current-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit. This system can eliminate the data handling problems brought about by the traditional von Neumann architecture and does not require the assistance of any digital modules, achieving ultra-low latency and accurate recognition. This system has very broad application prospects in the field of new neural network hardware system research, and is expected to provide a feasible non-von Neumann hardware solution for deep neural networks and edge computing.

Description

Technical Field

[0001] The present invention relates to the technical fields of electronic information, integrated circuits and artificial neural networks, and in particular to a fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture. Background Art

[0002] With the rapid development of computers and information technology, demands for information transmission speed and storage capacity, as well as the integration of electronic devices and circuits, are becoming increasingly stringent. Artificial neural networks, as widely used nonlinear networks, have become highly mature and achieved tremendous success, sparking a disruptive intelligent revolution worldwide. However, most current artificial neural networks run on traditional computers, which are designed based on the von Neumann architecture, with separate computing and storage units. This creates two major issues that severely limit neural network performance: the "memory wall" and the "power wall." The "memory wall" refers to the speed mismatch between the CPU and memory. The CPU's computational speed is much faster than the memory's read and write speed. While CPU speed increases with advancements, memory speed increases more rapidly. This results in the CPU wasting significant time waiting for memory reads and writes, limiting the performance of the entire computing system. The "power wall" refers to the data transmission involved in the CPU's instruction execution process: the CPU needs to read data from memory and write the computational results back to memory. Data transmission consumes a significant amount of energy. As CPU frequencies increase, the amount of data transmitted increases, leading to higher power consumption and thus limiting the performance of the entire computing system.

[0003] Currently, new neural network hardware circuit systems based on a storage-computing integrated architecture are based on a combination of digital and analog circuits. These solutions suffer from low integration, slow response speeds, and high power consumption, making it difficult to further improve system performance. Therefore, research and development of a new generation of fully analog neural network systems based on a storage-computing integrated architecture is urgent. Summary of the Invention

[0004] The purpose of this invention is to propose a fully analog circuit system for handwritten digit recognition based on an integrated storage and computing architecture. This system, implemented entirely with analog circuits based on this integrated storage and computing architecture, eliminates the "memory wall" and "power wall" issues that severely limit neural network performance, both of which are inherent in the traditional von Neumann architecture. Furthermore, without the assistance of any digital modules, it enables ultra-low latency recognition of handwritten digits by neural network hardware systems. Existing solutions based on a combination of digital and analog circuits have an operating speed of approximately 1 millisecond, consume approximately 4W of energy, and have low integration, making them difficult to fully integrate on a single circuit board. The system proposed in this invention operates at a speed of approximately 0.01 milliseconds, consumes approximately 0.5W of energy, and has a high level of integration, allowing it to be fully integrated on a single circuit board. Therefore, compared to existing solutions, this invention offers advantages such as faster operation, lower energy consumption, and higher integration. This invention has broad application prospects in the research field of novel neural network hardware systems based on an integrated storage and computing architecture, and is expected to provide a viable non-von Neumann hardware solution for deep neural networks and edge computing, bringing hope to the future of technological revolution.

[0005] The purpose of the present invention is achieved through the following technical means:

[0006] A fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture, such as Figure 1 , including a first analog circuit and a second analog circuit, wherein the first analog circuit is composed of the following circuit modules: an input drive circuit, a first resistor array with a scale of m columns and 2n rows, a first current-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit;

[0007] The second analog circuit is composed of the following circuit modules: a second resistor array with a scale of n columns and 20 rows, a second current-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit;

[0008] The input of the fully analog circuit system is m analog voltages, generated by an external microcontroller with a touch capacitive screen. The input drive circuit inputs the m analog voltages into a first resistor array with a size of m columns and 2n rows. The conductance of the first resistor array with m columns and 2n rows is multiplied by the input analog voltage to obtain a corresponding current value on each resistor. All current values ​​on each row are accumulated and output at the end of the row. The first current-voltage conversion circuit converts the current value outputted in each row into a voltage value and amplifies it to obtain 2n voltage values, which are recorded as V1, V2, ..., V 2n The first subtraction circuit performs subtraction difference processing on the first n voltage values ​​and the last n voltage values ​​of the 2n voltage values ​​to generate n analog voltages V1', V2'...V n ', V i '=Vi-V i+n, i is 1--n; the first activation function circuit performs nonlinear activation on the n-channel analog voltage and maps it to the voltage range of 0V-1V to generate n-channel voltage;

[0009] The conductance of the second resistor array with a scale of n columns and 20 rows is multiplied by the n voltages generated by the first activation function circuit, and a corresponding current value is obtained on each resistor. All current values ​​on each row are accumulated and output at the end of the row; the second current-voltage conversion circuit converts the current value output from each row into a voltage value and amplifies it to obtain 20 voltage values, which are recorded as U1, U2...U 20 The second subtraction circuit performs subtraction difference processing on the first 10 voltage values ​​and the last 10 voltage values ​​of the 20 voltage values ​​to generate 10 analog voltages, U1', U2'...U 20 ', U i '=U i -U i+10 , i is 1--10; the second activation function circuit performs nonlinear activation on the 10-channel analog voltage, maps it to the voltage range of 0V-1V to generate 10-channel voltage; the voltage comparison circuit compares the 10-channel voltage output by the second activation function circuit with the reference voltage 0.5V respectively, and each voltage greater than 0.5V outputs a high level to the corresponding digital tube. The number of the digital tubes is 10, corresponding to the 10-channel voltage and the ten digits 0-9, thereby lighting up the corresponding digits and completing the handwritten digit recognition function.

[0010] Furthermore, the input drive circuit in the circuit module is composed of a non-inverting MOSFET driver chip, which converts m 3.3V voltage signals generated by an external microcontroller with a touch capacitive screen into 5V voltage signals, and increases the driving load capacity of each voltage to 100mA.

[0011] Furthermore, the current-voltage conversion circuit includes a sampling resistor and an integrated operational amplifier. The sampling resistor has a resistance of 1Ω and converts current into voltage. The integrated operational amplifier is used to construct a common-mode amplifier to amplify the voltage obtained by the sampling resistor.

[0012] Furthermore, the subtraction circuit in the circuit module includes an integrated operational amplifier for converting V1, V2...V 2n These 2n voltage values ​​are amplified.

[0013] Furthermore, the first activation function circuit and the second activation function circuit are respectively composed of a cascade of three-stage amplification circuits, the first amplification circuit is composed of a biased in-phase operational amplifier, and the second and third amplification circuits are composed of inverting operational amplifiers; the activation function is a Sigmoid function, and the Sigmoid function is simplified to y=0.2x+0.5, where x and y are the independent variable and dependent variable respectively, and the input voltage signal of the activation function circuit is divided into the following three segments: (-∞,-2.5V), [-2.5V,2.5V], (2.5V,+∞), and the first amplification circuit maps the three segments of the signal to 0-5V in parallel; the second and third amplification circuits perform linear transformation in sequence, and finally map 0-5V to 0-1V to realize the Sigmoid function function.

[0014] Furthermore, the voltage comparison circuit includes an integrated operational amplifier, and the voltage comparison circuit is a single-threshold voltage comparison circuit. When the voltage value input to the voltage comparison circuit is greater than 0.5V, the output is a high level.

[0015] Furthermore, the high level is 1V.

[0016] The beneficial effects of the present invention are as follows: Compared with traditional neural network hardware systems, the present invention is entirely implemented by analog circuits based on a storage-computing integrated architecture, which can eliminate the data handling problems caused by the traditional von Neumann architecture and achieve ultra-low latency and accurate recognition without the assistance of any digital modules. The present invention has very broad application prospects in the research field of new neural network hardware systems based on a storage-computing integrated architecture, and is expected to provide a viable non-von Neumann hardware solution for deep neural networks and edge computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the circuit principle of the present invention;

[0018] Figure 2 is a circuit diagram of an input drive circuit according to an embodiment of the present invention;

[0019] Figure 3 1 is a circuit schematic diagram of a first current-voltage conversion circuit and a second current-voltage conversion circuit according to an embodiment of the present invention;

[0020] Figure 4 1 is a circuit schematic diagram of a first subtraction circuit and a second subtraction circuit of an embodiment of the present invention;

[0021] Figure 5 1 is a circuit schematic diagram of a first activation function circuit and a second activation function circuit of an embodiment of the present invention;

[0022] Figure 6 1 is a circuit diagram of a voltage comparison circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following examples are used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0024] The present invention provides a fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture. The circuit principle diagram of the system is shown in FIG. Figure 1 As shown, it includes a first analog circuit and a second analog circuit. The first analog circuit is composed of the following circuit modules: an input drive circuit, a first resistor array with a scale of 49 columns and 20 rows, a first current-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit;

[0025] The second analog circuit is composed of the following circuit modules: a second resistor array with a scale of 10 columns and 20 rows, a second current-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit.

[0026] The input of the full analog circuit system is 49 analog voltages, which are generated by an external microcontroller with a touch capacitive screen (the microcontroller used in this embodiment is an STM32F103ZET6 single-chip microcomputer, and the single-chip microcomputer is connected to a 4.3-inch capacitive touch screen as an input device for handwritten digits, which collects handwritten digits and converts them into 49 analog voltages). The input drive circuit enhances the load capacity of the 49 analog voltages to obtain 49 drive voltages. The input drive circuit is composed of a non-inverting MOSFET driver chip, which converts the 49 3.3V voltages generated by the external microcontroller with a touch capacitive screen into 5V voltages and increases the drive load capacity of each voltage to 100mA. The dual-channel high-speed power MOSFET driver TC4427 chip can be used to achieve this, which has the advantages of high output current, wide power supply voltage, etc. Its circuit schematic diagram is as shown in FIG. Figure 3 shown.

[0027] The input drive circuit inputs the drive voltage into the first resistor array of 49 columns and 20 rows. The conductance of the first resistor array of 49 columns and 20 rows is multiplied by the input drive voltage, and a corresponding current value is obtained on each resistor. All current values ​​on each row are accumulated and output at the end of the row. The first current-voltage conversion circuit converts the current value output from each row into a voltage value and amplifies it to obtain 20 voltage values, which are recorded as V1, V2...V 20The current-to-voltage conversion circuit is implemented by a sampling resistor and an integrated operational amplifier. The sampling resistor has a resistance of 1Ω and converts the current accumulated in each row of the resistor array into a voltage. The integrated operational amplifier is used to construct a common-mode amplifier to amplify the voltage obtained by the sampling resistor by a factor of 40. This circuit can be implemented using TI's OPA4317 series integrated operational amplifier, which has low offset, rail-to-rail output, high speed, and low noise. The circuit schematic is shown below. Figure 5 The first subtraction circuit performs subtraction and differential processing on the first 10 voltage values ​​and the last 10 voltage values ​​of the 20 voltage values ​​to generate 10 analog voltages V1', V2'...V 10 ', V i '=V i -V i+10 , i is 1--10; the subtraction circuit can be implemented using TI's OPA2227 series integrated operational amplifier, which has the characteristics of dual power supply, wide power supply voltage range, high precision and low noise. The circuit schematic is as follows Figure 6 The first activation function circuit performs nonlinear activation on the 10 analog voltages and maps them to a voltage range of 0V-1V to generate 10 voltages.

[0028] The activation function circuit consists of three cascaded amplifier circuits, implementing the Sigmoid function. The first amplifier circuit consists of a biased, non-inverting operational amplifier, while the second and third amplifier circuits are inverting operational amplifiers. The Sigmoid function is simplified to y = 0.2x + 0.5. The analog circuit input voltage signal is divided into three segments: (-∞, -2.5V), [-2.5V, 2.5V], and (2.5V, +∞). The first amplifier circuit maps these three segments in parallel to a 0-5V range. The second and third amplifier circuits sequentially perform linear transformations, ultimately mapping the 0-5V range to a 0-1V range. The first amplifier circuit is composed of a single-5V power supply, rail-to-rail output integrated operational amplifier with a 2.5V bias voltage and a 1x gain. This can be implemented using TI's OPA4350 series integrated operational amplifier, which features single-supply power, rail-to-rail output, high speed, and low noise. The second amplifier circuit consists of an integrated operational amplifier powered by a ±5V dual power supply, with an amplification factor of 0.2. This amplifier can be implemented using TI's OPA2227 series integrated operational amplifiers, which feature dual power supply, a wide supply voltage range, high precision, and low noise. The third amplifier circuit consists of an integrated operational amplifier powered by a ±5V dual power supply, with an amplification factor of 1. This amplifier can be implemented using TI's OPA2227 series integrated operational amplifiers.

[0029] The conductance of the second resistor array with a scale of 10 columns and 20 rows is multiplied by the 10 voltages generated by the first activation function circuit, and a corresponding current value is obtained on each resistor. All current values ​​on each row are accumulated and output at the end of the row; the second current-voltage conversion circuit converts the current value output from each row into a voltage value and amplifies it by 50 times to obtain 20 voltage values, which are recorded as U1, U2...U 20 The second subtraction circuit performs subtraction difference processing on the first 10 voltage values ​​and the last 10 voltage values ​​of the 20 voltage values ​​to generate 10 analog voltages, U1', U2'...U 20 ', U i '=U i -U i+10 , i is 1-10; the second activation function circuit performs nonlinear activation on the 10 analog voltages, mapping them to a voltage range of 0V-1V to generate 10 voltages; the voltage comparison circuit compares the 10 voltages output by the second activation function circuit with a reference voltage of 0.5V. Each voltage greater than 0.5V outputs a high level to the corresponding digital tube. There are 10 digital tubes, one corresponding to each of the 10 voltages and the ten digits 0-9, lighting up the corresponding digit, completing the handwritten digit recognition function. The voltage comparison circuit can be implemented using TI's OPA4317 series integrated operational amplifier, which features low offset, rail-to-rail output, high speed, and low noise.

[0030] As can be seen from the above embodiments, the present invention realizes the recognition of handwritten digits. The system is completely implemented by analog circuits based on a storage-computing integrated architecture, which can eliminate the data handling problems brought by the traditional von Neumann architecture and does not require the assistance of any digital modules. It can achieve ultra-low latency and accurate handwritten digit recognition. This system has very broad application prospects in the research field of new neural network hardware systems based on a storage-computing integrated architecture, and is expected to provide a feasible non-von Neumann hardware solution for deep neural networks and edge computing.

[0031] The examples described above provide a detailed description of the technical solutions and beneficial effects of the present invention. It should be noted that a person skilled in the art can make several improvements and substitutions without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture, characterized by: including a first analog circuit and a second analog circuit; The first analog circuit is composed of the following circuit modules: an input drive circuit, a first resistor array with a scale of m columns and 2n rows, a first current-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit; The second analog circuit is composed of the following circuit modules: a second resistor array with a scale of n columns and 20 rows, a second current-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit; The input of the fully analog circuit system is m analog voltages, generated by an external microcontroller with a touch capacitive screen. The input drive circuit enhances the load capacity of the m analog voltages to obtain m drive voltages. The input drive circuit inputs the drive voltages into a first resistor array with a size of m columns and 2n rows. The conductance of the first resistor array with m columns and 2n rows is multiplied by the input drive voltage to obtain a corresponding current value on each resistor. All current values ​​on each row are accumulated and output at the end of the row. The first current-voltage conversion circuit converts the current value outputted in each row into a voltage value and amplifies it to obtain 2n voltage values, which are recorded as V1, V2, ..., V 2n The first subtraction circuit performs subtraction difference processing on the first n voltage values ​​and the last n voltage values ​​of the 2n voltage values ​​to generate n analog voltages V1', V2'...V n ', V i '=V i -V i+n , i is 1-n; the first activation function circuit performs nonlinear activation on the n-channel analog voltage and maps it to the voltage range of 0V-1V to generate n-channel voltage; The conductance of the second resistor array with a scale of n columns and 20 rows is multiplied by the n voltages generated by the first activation function circuit, and a corresponding current value is obtained on each resistor. All current values ​​on each row are accumulated and output at the end of the row; the second current-voltage conversion circuit converts the current value output from each row into a voltage value and amplifies it to obtain 20 voltage values, which are recorded as U1, U2...U 20 The second subtraction circuit performs subtraction difference processing on the first 10 voltage values ​​and the last 10 voltage values ​​of the 20 voltage values ​​to generate 10 analog voltages, U1', U2'...U 10 ', U i '=U i -U i+10 , i is 1-10; the second activation function circuit performs nonlinear activation on the 10 analog voltages, mapping them to the voltage range of 0V-1V to generate 10 voltages; the voltage comparison circuit compares the 10 voltages output by the second activation function circuit with the reference voltage 0.5V respectively, and each voltage greater than 0.5V outputs a high level to the corresponding digital tube. The number of the digital tubes is 10, corresponding to the 10 voltages and the ten digits 0-9, thereby lighting up the corresponding digits and completing the handwritten digit recognition function.

2. The fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture according to claim 1 is characterized in that: The input drive circuit in the circuit module is composed of a non-inverting MOSFET driver chip, which converts m 3.3V voltage signals generated by an external microcontroller with a touch capacitive screen into 5V voltage signals and increases the driving load capacity of each voltage to 100mA.

3. The fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture according to claim 1 is characterized in that: The current-voltage conversion circuit includes a sampling resistor and an integrated operational amplifier. The sampling resistor has a resistance of 1Ω and converts current into voltage. The integrated operational amplifier is used to construct a common-mode amplifier to amplify the voltage obtained by the sampling resistor.

4. The fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture according to claim 1, characterized in that: The subtraction circuit in the circuit module includes an integrated operational amplifier for converting V1, V2...V 2n These 2n voltage values ​​are amplified.

5. The fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture according to claim 1 is characterized in that: The first activation function circuit and the second activation function circuit are respectively composed of a cascade of three-stage amplification circuits, the first amplification circuit is composed of a biased in-phase operational amplifier, and the second and third amplification circuits are composed of inverting operational amplifiers; the activation function is a Sigmoid function, and the Sigmoid function is simplified to y=0.2x+0.5, where x and y are the independent variable and dependent variable respectively, and the input voltage signal of the activation function circuit is divided into the following three segments: (-∞,-2.5V), [-2.5V,2.5V], (2.5V,+∞), and the three-segment signal is mapped in parallel to 0-5V by the first amplification circuit; the second and third amplification circuits perform linear transformation in sequence, and finally map 0-5V to 0-1V to realize the Sigmoid function function.

6. The fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture according to claim 1, characterized in that: The voltage comparison circuit includes an integrated operational amplifier. The voltage comparison circuit is a single-threshold voltage comparison circuit. When the voltage value input to the voltage comparison circuit is greater than 0.5V, the output is a high level.

7. The fully analog circuit system for handwritten digit recognition based on a storage and computing integrated architecture according to claim 6, characterized in that: The high level is 1V.

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