Driving method of display panel, display panel and display device

Abstract

Embodiments of the present application disclose a display panel driving method, a display panel and a display device. Different data output ends of a multiplexing unit are connected with the same row of pixel circuits, and data signal writing is performed in time division. Before the i-th data output end and the data input end are turned on, the pixel circuit connected with the (i-1)-th data output end is controlled to complete data signal writing, so that the pixel circuit connected with the (i-1)-th data output end has completed data signal writing before the i-th data output end and the data input end of the multiplexing unit are turned on. Even if the voltage on the data line to which the data signal has been written changes due to the coupling capacitance between lines, the voltage of the data signal written in the pixel circuit will not be affected when the i-th data output end and the data input end of the multiplexing unit are turned on, the crosstalk phenomenon of the display panel is reduced, and the picture display quality is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a driving method of display panel, display panel and display device. BACKGROUND

[0002] With the development of display technology, users have higher and higher requirements on picture display quality.

[0003] In the prior art, due to the limited output ports of the driving chip, a multiplexing circuit is usually arranged in the non-display area of the display device to realize that one output port of the driving chip can provide data signals for different data lines at different time.

[0004] However, the use of the multiplexing circuit makes the signals on the data lines connected to different output ends of the multiplexing circuit easily interfere with each other, which causes the problem of crosstalk of the display panel and affects the picture display quality. SUMMARY

[0005] The present application provides a driving method of display panel, display panel and display device to reduce the interference between the data signals on the data lines connected to different output ends of the multiplexing circuit and alleviate the problem of crosstalk of the display panel.

[0006] In a first aspect, embodiments of the present application provide a driving method of display panel, the display panel comprising pixel circuits arranged in an array and a plurality of multiplexing units, the multiplexing unit comprising a data input end, n data output ends, wherein n is an integer greater than or equal to 2; each data output end is connected to the pixel circuits in a corresponding column through a data line.

[0007] The driving method of the display panel comprises:

[0008] In each row period, the n data output ends and the data input end are controlled to be turned on at different time, and the same row pixel circuits connected to different data output ends of the multiplexing unit are scanned at different time to write data signals at different time; wherein before the i th data output end and the data input end are turned on, the pixel circuits connected to the i-1 th data output end are controlled to be scanned, wherein 2≤i≤n.

[0009] Optionally, the multiplexing unit comprises n gating switches, a first end of the gating switch is connected to the data input end, and a second end of the gating switch is electrically connected to the data output end one by one; each row of pixel circuits is connected to n first scan lines, and the first scan line is electrically connected to the control end of the data writing module of the corresponding pixel circuit; the array-arranged pixel circuits are divided into column pixel circuit groups corresponding to the multiplexing units one by one, and each column pixel circuit group comprises n column pixel circuits, and each column pixel circuit is connected to a data output end of the corresponding multiplexing unit through a data line; in the column pixel circuit group, the pixel circuits in the same row and different columns are connected to different first scan lines;

[0010] In each row period, the n data output ends and the data input end are controlled to be turned on at different times, and the same-row pixel circuits connected to different data output ends of the multiplexing unit are scanned at different times, comprising:

[0011] In each row period, valid gating signals are provided to the control ends of the n gating switches at different times, and first valid scan signals are provided to the n first scan lines connected to the same-row pixel circuits at different times, so that the data writing modules in the pixel circuits in the same row and different columns in the column pixel circuit group are turned on at different times;

[0012] The first valid scan signal on the first scan line and the valid gating signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit overlap; the first valid scan signal on the first scan line and the valid gating signal corresponding to the other gating switches in the multiplexing unit do not overlap.

[0013] Optionally, the pulse width length of the first valid scan signal on the first scan line is greater than the pulse width length of the corresponding valid gating signal.

[0014] The valid gating signal corresponding to the first valid scan signal on the first scan line is the valid gating signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit.

[0015] Optionally, the start time of the first valid scan signal on the first scan line and the valid gating signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit overlap,

[0016] and the end time of the first valid scan signal on the first scan line is later than the end time of the valid gating signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit.

[0017] Optionally, the first valid scan signals on different first scan lines connected to the same row of pixel circuits do not overlap, and the time of the valid scan signals on different first scan lines connected to the same row of pixel circuits is equal to the row period.

[0018] Optionally, each row of pixel circuits is further connected to a second scan line;

[0019] In each row period, before controlling the n data output terminals and the data input terminal to be turned on at different times and before scanning the pixel circuits connected to different data output terminals of the multiplexing unit at different times, the driving method of the display panel further comprises:

[0020] A second effective scan signal is provided to the second scan line connected to the pixel circuit to simultaneously write the initialization signal to the row of pixel circuits and initialize the gate of the driving transistor included in the pixel circuit.

[0021] Alternatively, each row of pixel circuits is further connected to n second scan lines; in the column pixel circuit group, the second scan lines connected to the pixel circuits in the same row and different columns are different; in each row period, before controlling the n data output terminals and the data input terminal to be turned on at different times and before scanning the pixel circuits connected to different data output terminals of the multiplexing unit at different times, the driving method of the display panel further comprises:

[0022] A second effective scan signal is provided to the different second scan lines connected to the pixel circuit at different times to write the initialization signal to the pixel circuits in the same row and different columns in the column pixel circuit group at different times to initialize the gate of the driving transistor included in the pixel circuit.

[0023] Optionally, the display area of the display panel includes an edge area and a center area; the data lines include first data lines located in the edge area and second data lines located in the center area; the multiplexing unit is located in the non-display area of the display panel, and along the extension direction of the data line, the multiplexing circuit formed by each multiplexing unit corresponds to the center area.

[0024] The data output terminal of the multiplexing unit is connected to the corresponding second data line or the connection line, the connection line is located in the display area, and the orthogonal projection of the connection line and at least part of the data lines not connected to the connection line on the substrate of the display panel overlaps.

[0025] In a second aspect, the embodiments of the present application further provide a display panel, which comprises an array of pixel circuits and a plurality of multiplexing units, and the multiplexing unit comprises a data input terminal, n data output terminals, wherein n is an integer greater than or equal to 2; each data output terminal is connected to the corresponding column of pixel circuits through a data line.

[0026] Optionally, the display area of the display panel includes an edge area and a center area; the data lines include first data lines located in the edge area and second data lines located in the center area; the multiplexing unit is located in the non-display area of the display panel, and along the extension direction of the data line, the multiplexing circuit formed by each multiplexing unit corresponds to the center area.

[0027] The data output end of the multiplexing unit is connected with a corresponding second data line or a connection line, the connection line is located in a display area, and a projection of the connection line and at least part of the data lines not connected with the connection line on a substrate of the display panel exists an overlap.

[0028] Optionally, a first end of the connection line connected with the data output end of the multiplexing unit is closer to a second data line located at a middle position of the center area than a second end of the connection line connected with the first data line.

[0029] Optionally, one of the data output ends of the multiplexing unit is connected with the second data line, and the one of the data output ends is connected to the first data line through the connection line, and a projection of the connection line and the second data line connected with the same multiplexing unit on the substrate of the display panel exists an overlap.

[0030] Optionally, in each row period, the n data output ends and the data input end are controlled to be turned on in time, and different pixel circuits in the same row connected with different data output ends of the multiplexing unit are scanned in time to write the data signal in time, wherein before the i-th data output end and the data input end are controlled to be turned on, the pixel circuits connected with the i-1-th data output end are controlled to be scanned, wherein 2≤i≤n.

[0031] Optionally, the display panel further comprises a plurality of first scan lines, and the arrayed pixel circuits are divided into column pixel circuit groups corresponding to the multiplexing units one by one, in the column pixel circuit group, the first scan lines connected with the pixel circuits in different columns in the same row are different; the first scan lines are used for transmitting first effective scan signals to the data writing modules of the pixel circuits to control the turn-on state of the corresponding connected data writing modules.

[0032] Optionally, each row of pixel circuits is further connected with a second scan line, wherein any first scan line connected with the j-th row of pixel circuits is multiplexed as a second scan line of the (j+1)-th row of pixel circuits, wherein j is an integer greater than or equal to 1.

[0033] Or each row of pixel circuits is further connected with n second scan lines, in the same column of pixel circuits, the first scan line connected with the pixel circuit located in the j-th row is multiplexed as a second scan line of the pixel circuit located in the (j+1)-th row, wherein j is an integer greater than or equal to 1.

[0034] The second scan line is used for transmitting a second effective scan signal to the gate initialization module of the pixel circuit to control the turn-on state of the corresponding connected gate initialization module.

[0035] In a third aspect, an embodiment of the present application further provides a display device comprising the display panel of the second aspect.

[0036] The driving method of the display panel, the display panel and the display device provided by the embodiment of the present application write data signals in time by scanning different data output terminals of the multiplexing unit in time, wherein before the i th data output terminal and the data input terminal are controlled to be conductive, the pixel circuit connected with the i-1 th data output terminal is controlled to be scanned, so that the pixel circuit connected with the i-1 th data output terminal has completed the writing of the data signal before the i th data output terminal and the data input terminal of the multiplexing unit are conductive, and then when the i th data output terminal and the data input terminal of the multiplexing unit are conductive, even if the voltage on the data line to which the data signal has been written changes due to the existence of the coupling capacitance between the lines, the voltage of the data signal written in the pixel circuit will not be affected, the crosstalk phenomenon of the display panel is reduced, and the display quality of the picture is improved. Moreover, the technical solution of the embodiment can increase the writing time of the data signal of the pixel circuit, so that the data writing time is more sufficient, the charging rate is improved, and the display picture quality is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a driving timing diagram of a display panel in the related art;

[0038] Figure 2 is a structural schematic diagram of a display panel provided by the embodiment of the present application;

[0039] Figure 3 is a flowchart of a driving method of a display panel provided by the embodiment of the present application;

[0040] Figure 4 is a structural schematic diagram of a pixel circuit in the related art;

[0041] Figure 5 is a flowchart of another driving method of a display panel provided by the embodiment of the present application;

[0042] Figure 6 is a driving timing diagram of a display panel provided by the embodiment of the present application;

[0043] Figure 7 is another driving timing diagram of a display panel provided by the embodiment of the present application,

[0044] Figure 8 is another structural schematic diagram of a display panel provided by the embodiment of the present application;

[0045] Figure 9 is a flowchart of another driving method of a display panel provided by the embodiment of the present application;

[0046] Figure 10 is another structural schematic diagram of a display panel provided by the embodiment of the present application;

[0047] Figure 11 is a flow chart of another driving method of the display panel provided by an embodiment of the present application;

[0048] Figure 12 is a driving timing diagram of another display panel provided by an embodiment of the present application;

[0049] Figure 13 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0050] Figure 14 is a partial enlarged view of the display panel provided by an embodiment of the present application;

[0051] Figure 15 is a partial sectional view of the display panel provided by an embodiment of the present application;

[0052] Figure 16 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0054] As described in the background, the use of the multiplexing circuit makes the signals on the data lines connected to different output terminals of the multiplexing circuit easily interfere with each other, causing the problem of crosstalk of the display panel, affecting the picture display quality. The inventor has found that the reason for the above problem is that there is a coupling capacitor between the data lines connected to different output terminals of the same multiplexing circuit, and in the existing display panel, the data signal writing to the pixel circuit is performed row by row, i.e. the pixel circuits in the same row are simultaneously written with data signals at the same time. Specifically, the multiplexing circuit includes a plurality of multiplexing units, each multiplexing unit includes an input terminal and a plurality of output terminals, and the input terminal and different output terminals of the multiplexing unit are turned on at different times, so that the driving chip writes data signals to the data lines connected to the multiplexing unit at different times through the multiplexing unit, and then outputs an effective scanning signal to the pixel circuit row through the scanning line, or after the multiplexing unit transmits data signals to the last data line connected to it for a certain period of time, an effective scanning signal is output to the pixel circuit row through the scanning line, so that a row of pixel circuits simultaneously write data signals. Figure 1is a driving timing diagram of a display panel in the related art, which can correspond to a case that a multiplexing unit is connected to two data lines. When the first gate signal MUX1 is an effective level signal, the multiplexing unit transmits a data signal to a data line connected to a first output end of the multiplexing unit. When the second gate signal MUX2 is an effective level signal, the multiplexing unit transmits the data signal to a data line connected to a second output end of the multiplexing unit. Referring to Figure 1 , the effective level signals of the first gate signal MUX1 and the second gate signal MUX2 are provided in time division, and when the effective level signal of the second gate signal MUX2 reaches a certain time length, an effective level signal is transmitted to a corresponding row of pixel circuits through the second scan line S10. The row of pixel circuits simultaneously performs writing of the data signal. However, when the input end and one output end of the multiplexing unit are turned on, due to the existence of coupling capacitances between different data lines, the voltage of the data signal that has been written on the data line connected to the output end that is turned on before the input end of the multiplexing unit is turned on changes, so that the display panel has a crosstalk problem, which finally affects the picture display quality.

[0055] Based on the above reasons, the embodiment of the present application provides a driving method of a display panel, Figure 2 is a structural schematic diagram of a display panel provided by the embodiment of the present application, referring to Figure 2 , the display panel includes pixel circuits 100 arranged in an array and a plurality of multiplexing units 200. The multiplexing unit 200 includes a data input end A0 and n data output ends B0. Each data output end B0 is connected to a corresponding column of pixel circuits 100 through a data line D. Wherein n is an integer greater than or equal to 2. Different data output ends B0 can be electrically connected to different data lines D. Different columns of pixel circuits 100 can be electrically connected to different data lines D. Optionally, each data output end B0 is connected to a column of pixel circuits 100 through a data line D. The data input end A0 of the multiplexing unit 200 can be electrically connected to the output end of the driving chip 300 one by one to receive the data signal output by the output end of the driving chip 300. Specifically, when the data input end A0 of the multiplexing unit 200 and one of the data output ends B0 are turned on, the driving chip 300 provides a corresponding data signal to the data input end A0 of the multiplexing unit 200, so that the data signal is transmitted through the data output end B0 of the multiplexing unit 200 and then through the data line D to the corresponding pixel circuit 100. In combination with the timing control of the scan line connected to the pixel circuit 100, the data signal writing to the pixel circuit 100 is realized. Wherein, the pixel circuit 100 includes a data writing module and a driving transistor, wherein writing the data signal to the pixel circuit 100 means writing the data signal to the gate of the driving transistor through the data writing module. Wherein, Figure 2The display panel structure shown in the figure exemplarily shows that the multiplexing unit 200 includes two data output terminals B0. The display panel further includes a first scanning circuit 510 and a second scanning circuit 520, wherein the first scanning circuit 510 is connected with the pixel circuits in odd-numbered columns through the first scanning line S1, and the second scanning circuit 520 is connected with the pixel circuits in even-numbered columns through the first scanning line S1, so as to provide effective scanning signals to the pixel circuits in odd-numbered columns and even-numbered columns in the same row in time division, so as to realize writing of data signals to the pixel circuits in odd-numbered columns and even-numbered columns in the same row in time division.

[0056] Figure 3 is a flow chart of a display panel driving method provided by an embodiment of the present application, referring to Figure 1 and Figure 3 The display panel driving method includes the following steps.

[0057] Step 10, dividing the writing time of the data signal corresponding to one frame of display picture into a plurality of row periods.

[0058] The data signal corresponding to one frame of display picture includes the data voltage (or data signal) corresponding to each pixel circuit. Specifically, when displaying one frame of picture, the data signal is written to the display panel in a plurality of row periods, wherein in each row period, the data signal can be written to one row of pixel circuits.

[0059] Step 20, in each row period, controlling the n data output terminals and the data input terminal to be turned on in time division, and scanning the same row of pixel circuits connected with different data output terminals of the multiplexing unit in time division to write the data signal; wherein before controlling the i th data output terminal and the data input terminal to be turned on, the pixel circuits connected with the i-1 th data output terminal are controlled to be scanned, wherein 2≤i≤n, i is an integer.

[0060] In this embodiment, in each row period, the n data output terminals are controlled to be turned on at different times, and when any data output terminal and the data input terminal are turned on, the data signal can be transmitted to the corresponding turned-on data output terminal through the data input terminal, and then transmitted to the data line connected to the data output terminal. In each row period, the pixel circuits connected to different data output terminals of the same multiplexing unit in the same row of pixel circuits are also scanned at different times, and before the i th data output terminal and the data input terminal of the multiplexing unit are controlled to be turned on, the pixel circuits connected to the i-1 th data output terminal are controlled to be scanned, so that before the i th data output terminal and the data input terminal of the multiplexing unit are turned on, the pixel circuits connected to the i-1 th data output terminal have completed the writing of the data signal, that is, the starting time of the period when the i th data output terminal and the data input terminal are turned on is later than the ending time of the period when the pixel circuits connected to the i-1 th data output terminal write the data signal; that is, before the i th data output terminal and the data input terminal of the multiplexing unit are turned on, the data line connected to the i-1 th data output terminal has transmitted the corresponding data signal to the gate of the driving transistor in the pixel circuit, and before the i th data output terminal and the data input terminal of the multiplexing unit are turned on, the data writing module in the pixel circuit connected to the i-1 th data output terminal has been turned off, and the data line and the gate of the driving transistor in the pixel circuit have been disconnected, so that when the i th data output terminal and the data input terminal of the multiplexing unit are turned on, even if the voltage on the data line connected to the i-1 th data output terminal where the data signal has been written changes due to the existence of the coupling capacitance between the lines, it will not affect the voltage of the data signal written to the gate of the driving transistor in the pixel circuit connected to the i-1 th data output terminal, reducing the crosstalk phenomenon of the display panel, and improving the picture display quality. Moreover, compared with the driving method in the prior art, in which the data input terminal and different data output terminals of the multiplexing unit are turned on at different times, and then the data voltage is written at the same time after charging the connected data line, the driving method of this embodiment can realize the writing of the data signal of the pixel circuit connected to the data output terminal when the data input terminal and the data output terminal of the multiplexing unit are turned on, thereby increasing the writing time of the data signal of the pixel circuit, that is, the charging time of the gate of the driving transistor can be prolonged, so that the data writing time is more sufficient, the charging rate is improved, and the display picture quality is further improved, and the display picture quality under high refresh is improved.

[0061] The driving method of the display panel of the embodiment writes data signals in time by time scanning the same row pixel circuits connected to different data output terminals of the multiplexing unit. Before the i th data output terminal and the data input terminal are turned on, the pixel circuits connected to the i-1 th data output terminal are controlled to be scanned, so that the pixel circuits connected to the i-1 th data output terminal have completed the writing of data signals before the i th data output terminal and the data input terminal of the multiplexing unit are turned on. Even if the voltage on the data line to which the data signal has been written changes due to the existence of the coupling capacitance between the lines, the voltage of the data signal written in the pixel circuit will not be affected when the i th data output terminal and the data input terminal of the multiplexing unit are turned on, thereby reducing the crosstalk of the display panel and improving the display quality of the picture. Moreover, the technical solution of the embodiment can increase the writing time of the data signal of the pixel circuit, so that the data writing time is more sufficient, the charging rate is improved, and the display picture quality is further improved.

[0062] Optionally, in the same row period, for the same multiplexing unit and the same row pixel circuit, the time periods when different data output terminals and data input terminals are turned on do not overlap, and the time period when the i th data output terminal and the data input terminal are turned on overlaps or does not overlap with the time period when the pixel circuit connected to the i th data output terminal is scanned to write data signals. In the same row period, if the time period when the i th data output terminal and the data input terminal are turned on does not overlap with the time period when the pixel circuit connected to the i th data output terminal is scanned to write data signals, the time period when the i th data output terminal and the data input terminal are turned on is before the time period when the pixel circuit connected to the i th data output terminal is scanned to write data signals. Optionally, in the same row period, for the same multiplexing unit and the same row pixel circuit, the time periods when different data output terminals and data input terminals are turned on are different and do not overlap, and the time period when each data output terminal and the data input terminal are turned on to charge the connected data line overlaps or does not overlap with the time period when the gate of the driving transistor in the pixel circuit connected to the data output terminal is written with data signals in response to the first active scanning signal on the first scanning line connected to the pixel circuit connected to the data output terminal. Optionally, in the same row period, for the same multiplexing unit and the same row pixel circuit, the time periods when different data output terminals and data input terminals are turned on are different and do not overlap, and when each data output terminal and the data input terminal are turned on, data signals are written to the gate of the driving transistor in the pixel circuit connected to the data output terminal at the same time as the connected data line is charged.

[0063] Figure 4 is a structural schematic diagram of a pixel circuit in the related art, referring to Figure 4The pixel circuit comprises a data writing module 110 and a driving transistor DT, the data writing module 110 is used for writing a data voltage to the gate of the driving transistor DT; the data writing module 110 can be directly connected or indirectly connected with the gate of the driving transistor DT, Figure 4 The indirect connection between the data writing module 110 and the gate of the driving transistor DT is schematically shown in FIG. 1B, specifically, the data writing module 110 is connected with the gate of the driving transistor DT through the driving transistor DT and a compensation module 120. The control end of the data writing module 110 and the control end of the compensation module 120 are both connected with a first scan line, the first end of the data writing module 110 is connected with a data voltage input end Vdata, the data voltage input end Vdata is connected with a data line, and the second end of the data writing module 110 is connected with the first electrode of the driving transistor DT, wherein the data writing module 110 comprises a first transistor T1. The compensation module 120 is connected between the second electrode and the gate of the driving transistor DT, and the compensation module 120 comprises a second transistor T2. The pixel circuit further comprises a light emitting control module 130, the light emitting control module 130 comprises a third transistor T3 and a fourth transistor T4, and the gate of the third transistor T3 and the gate of the fourth transistor T4 are both connected with a light emitting control signal EM.

[0064] With reference to the foregoing Figure 2 and Figure 4On the basis of the above technical solutions, optionally, the multiplexing unit comprises n gating switches M0, a first end of the gating switch M0 is connected to the data input end A0, and a second end of the gating switch M0 is electrically connected to the data output end B0 in a one-to-one correspondence; the gating switch M0 further comprises a control end, and the gating switch M0 can control the conduction state between the first end and the second end according to the signal of the control end, that is, the gating switch M0 can control the conduction state of the connected data input end A0 and the data output end B0 according to the signal of the control end. In the same multiplexing unit in the same row period, the n gating switches M0 are time-divisionally turned on to realize time-division conduction of the n data output ends and the data input end. The control ends of different gating switches M0 are connected to different gating control lines, and the gating switch M0 and the gating control line correspond to each other. Different multiplexing units can be connected to the same n gating control lines. Each row of pixel circuits is connected to n first scan lines S1, and the first scan line S1 is electrically connected to the control end of the data writing module 110 of the corresponding pixel circuit; the array-arranged pixel circuits are divided into column pixel circuit groups 400 corresponding to the multiplexing units 200, each column pixel circuit group comprises n column pixel circuits, and each column pixel circuit is connected to a data output end of the corresponding multiplexing unit through a data line; in the column pixel circuit group 400, the pixel circuits in different columns in the same row are connected to different first scan lines S1; that is, in the column pixel circuit group 400, the pixel circuits in the same row are electrically connected to the n first scan lines in a one-to-one correspondence. The display panel further comprises a gating control line electrically connected to the control end of the multiplexing unit 200 in a one-to-one correspondence, and the gating control line is used for transmitting a gating control signal to the corresponding control end. When the gating control signal is a valid gating signal, the corresponding gating switch M0 is turned on, and when the gating signal is an invalid gating signal, the corresponding gating switch M0 is turned off. The potentials of the valid gating signal and the invalid gating signal are opposite. Figure 1 When n is equal to 2, the multiplexing unit 200 comprises two gating switches M0, and the multiplexing unit 200 comprises two data output ends B0, which are a first data output end B0 and a second data output end B0. Each row of pixel circuits is connected to two first scan lines S1, for example, for the pixel circuit shown in Figure 1 The two first scan lines S1 connected to the first row of pixel circuits are a first scan line one S11 and a first scan line two S12, respectively, and the two first scan lines S1 connected to the second row of pixel circuits are a first scan line three S13 and a first scan line four S14, respectively. The control end of the data writing module 110 of the pixel circuit is denoted as a writing control end S10, and the control end of the compensation module 120 is denoted as a compensation control end S20. Figure 1The data writing module of the pixel circuit in the upper left corner of the shown display panel is connected with the first scan line one S11 through the writing control end S10 and the compensation control end S20 of the data writing module; the data writing module 110 of the adjacent pixel circuit in the same row as the upper left corner is connected with the first scan line two S12 through the writing control end S10 and the compensation control end S20 of the data writing module. When n is equal to 2, the display panel includes two gate control lines, which are the first gate control line SW1 and the second gate control line SW2; the two gate switches M0 of the multiplexing unit 200 are the first gate switch M1 and the second gate switch M2; the control end of the first gate switch M1 is connected with the first gate control line SW1; and the control end of the second gate switch M2 is connected with the second gate control line SW2.

[0065] Figure 5 is a flow chart of another driving method of a display panel provided by an embodiment of the present application, Figure 6 is a driving timing diagram of a display panel provided by an embodiment of the present application, referring to Figure 5 and Figure 6 The driving method of the display panel comprises the following steps.

[0066] In step 11, the writing time of the data signal corresponding to one frame of display picture is divided into multiple row periods; this step is the same as the process of step 10 in the above-mentioned embodiment, and will not be repeated here.

[0067] In step 21, in each row period, valid gate signals are provided to the control ends of the n gate switches in time, and the first valid scan signals are provided to the n first scan lines connected with the pixel circuits in the same row in time, so as to control the data writing modules in the pixel circuits in the same row and different columns in the column pixel circuit group to conduct in time.

[0068] The first valid scan signal on the first scan line and the valid gate signal corresponding to the gate switch of the same pixel circuit connected with the first scan line in the multiplexing unit overlap; the first valid scan signal on the first scan line and the valid gate signal corresponding to the other gate switches in the multiplexing unit do not overlap. That is, in the same row period, for the same multiplexing unit and the same row pixel circuit, the time period when the i th data output end and the data input end conduct overlaps the time period when the pixel circuit connected with the i th data output end writes the data signal. In the same row period, for the same multiplexing unit and the same row pixel circuit, the time period when the pixel circuit connected with the i th data output end writes the data signal does not overlap the time period when the remaining data output ends and the data input ends conduct.

[0069] In Figure 2The pixel circuit in the left upper corner is taken as an example. The first scanning line connected to the pixel circuit is the first scanning line S11. The pixel circuit connected to the first scanning line S11 in the multiplexing unit is connected to the first gate switch M1. The on-off state of the first gate switch M1 is controlled by the gate control signal on the first gate control line SW1. In combination with Figure 2 and Figure 6 It can be known that in the first row period H, the effective gate signals are transmitted on the first gate control line SW1 and the second gate control line SW2 in sequence. For example, the effective gate signals can be low level. When the gate control signal on the first gate control line SW1 is the effective gate signal, the first effective scanning signal is transmitted on the first scanning line S11. That is, for the pixel circuit in the left upper corner, the first effective scanning signal on the first scanning line S11 and the effective gate signal corresponding to the first gate switch M1 in the multiplexing unit are overlapped. At this time, the pixel circuit in the left upper corner writes the data signal. At the same time, the pixel circuits in all odd columns in the first row write the data signal. When the gate control signal on the second gate control line SW2 is the effective gate signal, the first effective scanning signal is transmitted on the second scanning line S12. The pixel circuits in all even columns in the first row write the data signal. The data writing process of the pixel circuits in other rows is similar to that in the first row. The data signal is written in odd columns and even columns in time division. Details are not described herein again. It should be noted that, Figure 2 and Figure 6 Only the case where n=2 is taken as an example. In other optional embodiments of the present application, n can be an integer greater than 2, for example, 3, etc. The present embodiment is not limited herein. When the first scanning line connected to the data writing module 110 transmits the first effective scanning signal, the data writing module 110 is turned on. When the first scanning line connected to the data writing module 110 transmits the first ineffective scanning signal, the data writing module 110 is turned off.

[0070] Specifically, valid selection signals are provided to the control ends of the n selection switches of the multiplexing unit in time division, so that the n selection switches of the multiplexing unit can be turned on in time division. Valid first scanning signals are provided to the n scanning lines connected to the pixel circuits in the same row in time division, so that the pixel circuits connected to different first scanning lines in the same row perform data signal writing in time division. In the embodiment, the first valid scanning signal on the first scanning line and the valid selection signal corresponding to the selection switch of the multiplexing unit connected to the same pixel circuit as the first scanning line overlap, so that the selection switch of the multiplexing unit is turned on at the same time as the pixel circuit connected to the selection switch performs data signal writing, realizing direct charging of the data signal to the gate of the driving transistor in the pixel circuit, which is conducive to avoiding the occurrence of crosstalk; and the first valid scanning signal on the first scanning line and the valid selection signal corresponding to the other selection switch of the multiplexing unit (except the selection switch of the multiplexing unit connected to the same pixel circuit as the first scanning line) do not overlap, which can avoid the data voltage on the data line connected to the selection switch turned on previously from being disconnected from the gate of the driving transistor in the pixel circuit in time, and the influence of the data voltage on the gate of the driving transistor in the pixel circuit connected to the selection switch turned on previously caused by the change of the data voltage on the data line connected to the selection switch turned on later, further avoiding the occurrence of crosstalk. Moreover, the first valid scanning signal on the first scanning line and the valid selection signal corresponding to the selection switch of the multiplexing unit connected to the same pixel circuit as the first scanning line overlap, realizing direct charging of the data signal to the gate of the driving transistor in the pixel circuit, which can increase the data signal writing time, improve the charging rate, and improve the display quality.

[0071] In combination Figure 6 On the basis of the above technical solutions, optionally, the pulse width length (denoted as a first pulse width length w1) of the first valid scanning signal on the first scanning line is greater than the pulse width length (denoted as a second pulse width length w2) of the corresponding valid selection signal; wherein the valid selection signal corresponding to the first valid scanning signal on the first scanning line is the valid selection signal corresponding to the selection switch of the multiplexing unit connected to the same pixel circuit as the first scanning line. That is, in the same row period, for the same multiplexing unit and the same row pixel circuit, the time length of the period in which the i th data output end is turned on with the data input end is less than the time length of the period in which the pixel circuit connected to the scanning i th data output end performs data signal writing.

[0072] Specifically, the pulse width length of the first valid scanning signal on the first scanning line is greater than the pulse width length of the corresponding valid selection signal, so that the on time of the data writing module in the pixel circuit is longer than the on time of the corresponding connected selection switch. Wherein, the pulse width length of the first valid scanning signal on the first scanning line being greater than the pulse width length of the corresponding valid selection signal includes but is not limited to the following three cases:

[0073] (1) the start time of the first effective scanning signal on the first scanning line is earlier than the start time of the effective gate signal corresponding to the gate switch of the same pixel circuit connected to the first scanning line in the multiplexing unit; and the end time of the first effective scanning signal on the first scanning line overlaps with the end time of the effective gate signal corresponding to the gate switch of the same pixel circuit connected to the first scanning line in the multiplexing unit.

[0074] The start time of the first effective scanning signal on the first scanning line is earlier than the start time of the effective gate signal corresponding to the gate switch of the same pixel circuit connected to the first scanning line in the multiplexing unit, so that when the effective gate signal of the gate switch arrives and the gate switch is turned on, the data writing module in the corresponding pixel circuit has been turned on, and thus the data signal can be written into the gate of the driving transistor of the pixel circuit in time. The end time of the first effective scanning signal on the first scanning line overlaps with the end time of the effective gate signal corresponding to the gate switch of the same pixel circuit connected to the first scanning line in the multiplexing unit, so that the first effective scanning signal on the first scanning line and the effective gate signal corresponding to the gate switch of the different pixel circuit connected to the first scanning line in the multiplexing unit do not overlap, and thus the occurrence of crosstalk is avoided.

[0075] (2) the start time of the first effective scanning signal on the first scanning line overlaps with the start time of the effective gate signal corresponding to the gate switch of the same pixel circuit connected to the first scanning line in the multiplexing unit; and the end time of the first effective scanning signal on the first scanning line is later than the end time of the effective gate signal corresponding to the gate switch of the same pixel circuit connected to the first scanning line in the multiplexing unit. Figure 5 The timing shown corresponds to this case

[0076] Specifically, the start time of the first effective scan signal on the first scan line overlaps with the start time of the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit. On the one hand, when the effective gate signal of the gating switch arrives and the gating switch is turned on, the data writing module in the corresponding pixel circuit is turned on in time, so that the data signal can be written to the gate of the driving transistor of the pixel circuit in time. On the other hand, when the effective gate signal of the gating switch does not arrive and the gating switch is turned off, the data writing module in the corresponding pixel circuit is also turned off, so that the data signal can be written to the pixel circuit within the time length of the pulse width of the first effective scan signal on the first scan line. In the overlapping time of the first effective scan signal on the first scan line and the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit, the data signal can be directly charged to the gate of the driving transistor, improving the charging rate. The end time of the first effective scan signal on the first scan line is later than the end time of the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit. After the end of the effective gate signal, that is, after the corresponding gating switch is turned off, the pixel circuit connected to the data line by the gating switch can still be charged by the line to charge the gate of the driving transistor, further realizing sufficient writing of the data signal to the gate of the driving transistor. That is, in the embodiment, by setting the timing relationship as above, the data signal can be written to the gate of the driving transistor of the pixel circuit, and there is direct charging and line charging, which improves the charging rate and makes the writing of the data signal to the gate of the driving transistor more sufficient.

[0077] (3) The start time of the first effective scan signal on the first scan line is earlier than the start time of the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit; and the end time of the first effective scan signal on the first scan line is later than the end time of the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit.

[0078] The start time of the first effective scan signal on the first scan line is earlier than the start time of the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit, which has the same beneficial effect as the above-mentioned first (1) case. The end time of the first effective scan signal on the first scan line is later than the end time of the effective gate signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit, which has the same beneficial effect as the above-mentioned second (2) case, and will not be described here.

[0079] That is, in the same row cycle, for the same multiplexing unit and the same row of pixel circuits, the starting time of the period in which the i-th data output terminal and the data input terminal are turned on is the same as the starting time of the period in which the pixel circuit connected with the i-th data output terminal writes the data signal, or the starting time of the period in which the i-th data output terminal and the data input terminal are turned on is later than the starting time of the period in which the pixel circuit connected with the i-th data output terminal writes the data signal. In the same row cycle, for the same multiplexing unit and the same row of pixel circuits, the ending time of the period in which the i-th data output terminal and the data input terminal are turned on is the same as the ending time of the period in which the pixel circuit connected with the i-th data output terminal writes the data signal, or the ending time of the period in which the i-th data output terminal and the data input terminal are turned on is earlier than the ending time of the period in which the pixel circuit connected with the i-th data output terminal writes the data signal.

[0080] In combination Figure 6 On the basis of the above technical solution, the first effective scanning signals on different first scanning lines connected with the same row of pixel circuits do not overlap, and the time and of the first effective scanning signals on different first scanning lines connected with the same row of pixel circuits is equal to the row cycle H.

[0081] Specifically, the first effective scanning signals on different scanning lines connected with the same row do not overlap, which can make the data writing time of the same row of pixel circuits connected with different data output terminals of the same multiplexing unit not overlap, and avoid the occurrence of crosstalk phenomenon. That is, in the same row cycle, for the same multiplexing unit and the same row of pixel circuits, the periods in which the pixel circuits connected with different data output terminals write the data signal are different and do not overlap. The time and of the first effective scanning signals on different first scanning lines connected with the same row of pixel circuits can make the time of the row cycle be fully utilized, and ensure that the data writing time is sufficient. That is, in the same row cycle, for the same multiplexing unit and the same row of pixel circuits, the starting time of the period in which the pixel circuit connected with the first data output terminal writes the data signal to the ending time of the period in which the pixel circuit connected with the last data output terminal writes the data signal is equal to the row cycle. Optionally, in the same row cycle, for the same multiplexing unit and the same row of pixel circuits, the lengths of the periods in which different data output terminals and the data input terminal are turned on are the same.

[0082] On the basis of the above technical solution, the pulse widths of the first effective scanning signals on different first scanning lines connected with the same row of pixel circuits can be equal or not equal, which is not limited in the embodiment. That is, in the same row cycle, for the same multiplexing unit and the same row of pixel circuits, the lengths of the periods in which the pixel circuits connected with different data output terminals write the data signal are the same.

[0083] Based on the above technical solution, in adjacent rows, the first valid scan signals on the first scan line connected to the pixel circuits located in the same column do not overlap, thus avoiding the mischarging phenomenon caused by the simultaneous charging of pixel circuits located in the same column. That is, the data signal writing time periods of pixel circuits located in the same column but different rows are different and do not overlap.

[0084] It should be noted that, Figure 6 The driving timing shown is the case where the first valid scan signal on the first scan line overlaps with the valid gating signal corresponding to the gating switch of the same pixel circuit connected to the first scan line in the multiplexing unit. Figure 7 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, for reference. Figure 7 In other optional embodiments of the present invention, the first valid scan signal on the first scan line and the valid gating signal corresponding to the gating switch of the pixel circuit connected to the first scan line in the multiplexing unit do not overlap. Figure 7 Taking the driving timing shown as an example, in the first row cycle H, the first gating control line SW1 transmits a valid gating signal, which can be a low level. After the valid gating signal of the gating control signal on the first gating control line SW1 is transmitted, the first valid scan signal is transmitted on the first scan line S11, which can be a low level. The pixel circuit of the first row odd column performs data signal writing. Then, the second gating control line SW2 transmits a valid gating signal, which can be a low level. After the valid gating signal of the gating control signal on the second gating control line SW2 is transmitted, the first valid scan signal is transmitted on the second scan line S12, and the pixel circuit of the first row even column performs data signal writing.

[0085] Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 8 In some optional embodiments of the present invention, each row of pixel circuits is further connected to a second scan line. Optionally, any first scan line connected to the j-th row of pixel circuits is multiplexed as the second scan line of the (j+1)-th row of pixel circuits, where j is an integer greater than or equal to 1. The second scan lines connected to pixel circuits in the same row are identical, which simplifies the wiring design. Figure 8 The diagram schematically illustrates the structure of the first two rows of pixel circuits. For the pixel circuits in the second row, the second scan line S2 connected to them is any of the first scan lines S1 connected to the pixel circuits in the first row. However, it should be noted that an additional second scan line S2 corresponding to the first row of pixel circuits needs to be provided in the display panel, such as... Figure 8As shown, when n=2, the second scan line one S21 can be connected to the output end of the upper shift register of the shift register connected to the first scan line one S11, for example, the second scan line one S21 is connected to the first stage shift register of the first scan circuit 510, and the first scan line one S11 is connected to the second stage shift register of the first scan circuit 510; and the second scan line two S22 can be connected to the output end of the upper shift register of the shift register connected to the first scan line two S12, for example, the second scan line two S22 is connected to the first stage shift register of the second scan circuit 520, and the first scan line two S12 is connected to the second stage shift register of the second scan circuit 520. Figure 8 As shown, the first row of pixel circuits are all connected to the second scan line one S21.

[0086] Figure 9 is a flowchart of another driving method of a display panel provided by an embodiment of the present application, referring to Figure 7 The driving method of the display panel comprises:

[0087] In step 31, a second effective scan signal is provided to the second scan line connected to the pixel circuit, so as to write an initialization signal to a row of pixel circuits at the same time and initialize the gate of the driving transistor included in the pixel circuit.

[0088] Continuing to refer to Figure 4 , specifically, the pixel circuit further comprises a gate initialization module 140 (the gate initialization module 140 comprises a fifth transistor T5), wherein the control end of the gate initialization module 140 is connected to the second scan line, the first end of the gate initialization module 140 is connected to the initialization signal line Vref, and the second end of the gate initialization module 140 is connected to the gate of the driving transistor DT; the gate initialization module 140 is turned on or turned off according to the signal of the control end thereof, when the control end of the gate initialization module 140 is the second effective scan signal, the gate initialization module 140 is turned on, the initialization voltage is transmitted to the gate of the driving transistor DT, and the initialization of the gate of the driving transistor DT is realized. The control end of the gate initialization module 140 of the pixel circuit is recorded as a first initialization control end S30, and as shown in the display panel, Figure 8 As shown in the display panel, the first initialization control end S30 of the first row of pixel circuits is connected to the second scan line one S21.

[0089] Step 32, in each row period, control the n data output terminals and the data input terminal to be turned on at different time, and scan the same row pixel circuits connected to different data output terminals of the multiplexing unit at different time to write the data signal; wherein before the i th data output terminal and the data input terminal are controlled to be turned on, the scanning of the pixel circuits connected to the i-1 th data output terminal is completed, wherein 2≤i≤n; this step is the same as the step 20 in the above embodiment, and will not be repeated here.

[0090] Figure 10 is another structural schematic diagram of a display panel provided by an embodiment of the present application, referring to Figure 10 In some optional embodiments of the present application, each row of pixel circuits is further connected to n second scan lines; in the same column of pixel circuits, the first scan line connected to the pixel circuit in the j th row is multiplexed as the second scan line of the pixel circuit in the (j+1) th row; wherein j is an integer greater than or equal to 1. In the column pixel circuit group, the second scan lines connected to the pixel circuits in different columns in the same row are different.

[0091] Figure 11 is a flow chart of another driving method of a display panel provided by an embodiment of the present application, referring to Figure 11 Optionally, the driving method of the display panel comprises:

[0092] Step 41, provide the second effective scan signal to different second scan lines connected to the pixel circuits at different time to write the initialization signal to the pixel circuits in the same row and different columns in the column pixel circuit group at different time to initialize the gate of the driving transistor included in the pixel circuit.

[0093] Specifically, the pixel circuit further comprises a gate initialization module, wherein the control end of the gate initialization module is connected to the second scan line, the first end of the gate initialization module is connected to the initialization signal line, the second end of the gate initialization module is connected to the gate of the driving transistor, and the gate initialization module is turned on or turned off according to the signal of the control end; when the control end of the gate initialization module is the second effective scan signal, the gate initialization module is turned on to transmit the initialization voltage (or initialization signal) to the gate of the driving transistor to initialize the gate of the driving transistor. With Figure 9 The difference between the corresponding driving method is that, in the present embodiment, the gates of the pixel circuits in the same row and different columns in the column pixel circuit group are initialized at different time. In combination with Figure 4 and Figure 11 The control end of the gate initialization module 140 of the pixel circuit is recorded as the first initialization control end S30, so that Figure 10For the display panel shown in FIG. 1, the first initialization control end S30 of the pixel circuit in the odd column in the first row of pixel circuits is connected to the second scan line one S21; and the first initialization control end S30 of the pixel circuit in the even column in the first row of pixel circuits is connected to the second scan line two S22.

[0094] Step 42, in each row period, control the n data output ends and the data input end to be turned on at different times, and scan the pixel circuits in the same row connected to different data output ends of the multiplexing unit at different times to write the data signal; wherein before the i th data output end and the data input end are controlled to be turned on, the scanning of the pixel circuit connected to the i-1 th data output end is completed, wherein 2≤i≤n; this step is the same as the process of step 20 in the above embodiment, and will not be repeated here.

[0095] Continuing to refer to Figure 4 , the pixel circuit further comprises an anode initialization module 150, the control end of the anode initialization module is marked as a second initialization control end S40, the first end of the anode initialization module 150 is connected to the initialization signal line Vref, and the second end of the anode initialization module 150 is connected to the anode of the light emitting device. In some optional embodiments, the second initialization control end S40 can be connected to the same signal line as the write control end S10 of the data write module 110 of the pixel circuit, and then the panel structure initializes the light emitting device of the pixel circuit in the same row at different times; in another optional embodiment, the second initialization control end S40 can be connected to any first scan line connected to the row of pixel circuits where the pixel circuit is located, and the first scan lines connected to the second initialization control ends S40 of the pixel circuits in the same row of pixel circuits are the same, and then the panel structure simultaneously initializes the light emitting device of the pixel circuit in the same row.

[0096] Figure 12 is another driving timing diagram of a display panel provided by the embodiment of the present application, and the driving timing diagram can be used to drive Figure 8 and Figure 10 the display panel shown in FIG. 1. Taking Figure 10 the display panel shown in FIG. 1 as an example, combining Figure 10 and Figure 12In the second scanning line one S21, the gate of the driving transistor included in the odd column pixel circuit of the first row pixel circuit is initialized when the second active scanning signal arrives; in the second scanning line two S22, the gate of the driving transistor included in the even column pixel circuit of the first row pixel circuit is initialized when the second active scanning signal arrives. In the first scanning line one S11, the odd column pixel circuit of the first row pixel circuit is subjected to data writing when the first active scanning signal arrives, and the gate of the driving transistor included in the odd column pixel circuit of the second row pixel circuit is initialized; in the first scanning line two S12, the even column pixel circuit of the first row pixel circuit is subjected to data writing when the first active scanning signal arrives, and the gate of the driving transistor included in the even column pixel circuit of the second row pixel circuit is initialized; and the initialization and data writing of other row pixel circuits are performed in the above manner, which will not be described herein.

[0097] The embodiment of the present application further provides a display panel, and a structure of the display panel is shown in the figure. Figure 1 The display panel comprises pixel circuits 100 arranged in an array and a plurality of multiplexing units 200, and the multiplexing unit comprises a data input end A0 and n data output ends B0, wherein n is an integer greater than or equal to 2; and each data output end B0 is connected to the pixel circuit 100 in the corresponding column through a data line.

[0098] The display panel can apply the driving method of the display panel in the above embodiment and has the beneficial effects in the above embodiment. In each row period, the n data output ends and the data input end are controlled to be turned on at different times, and the same row pixel circuits connected to different data output ends of the multiplexing unit are scanned at different times to write data signals at different times; wherein before the i th data output end and the data input end are turned on, the pixel circuits connected to the i-1 th data output end are controlled to be scanned. In this way, when the data input end of the multiplexing unit and any data output end are turned on, the writing of the data signals of the pixel circuits connected to the data output end can be performed at the same time, and thus the writing time of the data signals of the pixel circuits can be increased, that is, the charging time of the gate of the driving transistor can be prolonged, the data writing time is more sufficient, the charging rate is improved, the display picture quality is further improved, and the display picture quality under high refresh is improved.

[0099] Figure 13 is another structure diagram of a display panel provided by the embodiment of the present application, and the display panel is shown in the figure. Figure 13Optionally, the display area of the display panel comprises edge areas 101 and a center area 102; the center area 102 is located between the two edge areas 101; the data lines comprise first data lines D1 located in the edge areas 101 and second data lines D2 located in the center area 102; the multiplexing units 200 are located in the non-display area, and along the extension direction of the data lines, the multiplexing circuit formed by each multiplexing unit 200 corresponds to the center area 102.

[0100] The data output terminals of the multiplexing units 200 are connected to the corresponding second data lines D2 or connection lines D3, and the connection lines D3 are located in the display area; the projection of the connection lines D3 and at least part of the data lines (including the first data lines D1 and the second data lines D2) not connected to the connection lines D3 on the substrate of the display panel exists overlap.

[0101] At least one data output terminal B0 of the n data output terminals of the multiplexing unit is connected to the connection line D3, and the projection of the connection line D3 connected to the at least one data output terminal B0 and the data lines (including the first data lines D1 and the second data lines D2) connected to the remaining data output terminals B0 on the substrate of the display panel exists overlap, i.e. there exists coupling capacitance. For example, one of the i-1th data output terminal and the i th data output terminal of the multiplexing unit is connected to the connection line D3, and the projection of the data line connected to the other and the connection line D3 on the substrate of the display panel exists overlap, i.e. there exists coupling capacitance. Before the i th data output terminal of the multiplexing unit is turned on, the data writing module in the pixel circuit connected to the i-1th data output terminal has been turned off, and the data line has been disconnected from the gate of the driving transistor in the pixel circuit, so that when the i th data output terminal of the multiplexing unit is turned on, even if there exists coupling capacitance between the connection line D3 and at least part of the data lines not connected to the connection line D3, the voltage on the data line connected to the i-1th data output terminal to which the data signal has been written will not affect the voltage of the data signal written to the gate of the driving transistor in the pixel circuit connected to the i-1th data output terminal, so as to reduce the crosstalk phenomenon of the display panel and improve the picture display quality.

[0102] Optionally, one of the data output terminals of the multiplexing unit 200 is connected to the second data line D2, and one of the data output terminals is connected to the first data line D1 through the connection line D3. Optionally, the projection of the connection line D3 and the second data line D2 connected to the same multiplexing unit 200 on the substrate of the display panel exists overlap.

[0103] Specifically, the multiplexing circuit corresponds to the center area 102. In the prior art, the output end of the multiplexing unit 200 is usually in the non-display area, and the data line is connected through the fan-out signal line with an acute angle with the data line in the non-display area to form a fan-out area, which occupies a large area and is not conducive to the realization of a narrow frame. In the embodiment, the data output end is connected to the first data line D1 of the edge area 101 through the connection line D3 in the display area, and the first end of the connection line D3 connected to the data output end of the multiplexing unit 200 is closer to the second data line located at the middle position of the center area 102 than the second end of the connection line D3 connected to the first data line D1, thereby reducing the area of the non-display area and realizing a narrow frame of the display panel. To further reduce the frame, the second data line can also be provided with a corresponding connection line, and the second data line is connected to the multiplexing unit 200 through the corresponding connection line.

[0104] The connection line D3 can be a straight line, a broken line, a curve, etc. Optionally, as shown in Figure 13 , the connection line D3 in the form of a broken line can include a connected first wire and a second wire. The first wire is connected to the corresponding first data line D1, and the second wire is connected to the data output end of the corresponding multiplexing unit 200. The extension direction of the first wire can be the same as the extension direction of the first scan line (parallel to the first direction X), and the extension direction of the second wire can be the same as the extension direction of the first data line D1 (parallel to the second direction Y), and the first wire is connected to the data output end of the multiplexing unit 200 through the second part, so that the second wire can be gathered to the area corresponding to the center area 102, thereby reducing the area of the non-display area and realizing a narrow frame of the display panel. The first direction X and the second direction Y intersect, for example, can be perpendicular.

[0105] Figure 14 is a partial enlarged view of the display panel provided by the embodiment of the application, which corresponds to Figure 13 the area framed by the dashed line in Figure 15 , is a partial cross-sectional view of the display panel provided by the embodiment of the application, Figure 14 can be obtained by Figure 13 cutting along the cross-sectional line AA'. In combination with Figure 14 and Figure 15 , at least part of the connection line D3 and the corresponding connected first data line D1 are located in different metal layers, and the second data line D2 is located in different metal layers, and the connection line D3 is connected to the first data line D1 through a via hole. The connection line D3 overlaps with the first data line D1 and / or the second data line D2 to form a coupling capacitor C0, so that the display panel is prone to crosstalk phenomenon. By applying the driving method of the display panel of any of the above embodiments of the application to the display panel, the crosstalk phenomenon of the display panel can be improved.

[0106] The first and second traces of connector D3 can be located on different metal layers. The first and second traces of connector D3 are connected via vias. The second trace can be located on the same metal layer as the first data line D1.

[0107] Optionally, the first scanning circuit 510 can be a single unit, located on one side of the display panel opposite each other along the first direction X, i.e., single-sided driving. Optionally, the second scanning circuit 520 can be a single unit, located on one side of the display panel opposite each other along the first direction X, i.e., single-sided driving. Optionally, the first scanning circuit 510 can be two units, respectively located on both sides of the display panel opposite each other along the first direction X, i.e., double-sided driving. Optionally, the second scanning circuit 520 can be two units, respectively located on both sides of the display panel opposite each other along the first direction X, i.e., double-sided driving. That is, any first scan line S1 is connected to two first scanning circuits 510 or two second scanning circuits 520 on both sides opposite each other along the first direction X, to improve driving capability.

[0108] This invention also provides a display device. Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, for reference. Figure 16 The display device includes the display panel of any of the above embodiments of the present invention. The display device can be... Figure 16 The mobile phone shown can also be a computer, television, smart wearable display device, etc., and the embodiments of the present invention do not impose any special limitations on it. Optionally, the display device further includes a driver chip 300, which is electrically connected to the multiplexing unit 200. The driver chip 300 can be used to execute the display panel driving method in the above embodiments.

[0109] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A driving method of a display panel, characterized by, The display panel comprises pixel circuits arranged in an array and a plurality of multiplexing units, the multiplexing units comprising a data input end, n data output ends, wherein n is an integer greater than or equal to 2; Each data output end is connected to the pixel circuits of a corresponding column through a data line; The driving method of the display panel comprises: In each row period, the n data output ends and the data input end are controlled to be turned on at different times, and the pixel circuits of the same row connected to different data output ends of the multiplexing unit are scanned at different times to write data signals; wherein before the ith data output end and the data input end are controlled to be turned on, the pixel circuits connected to the i-1th data output end are controlled to be scanned, wherein 2≤i≤n; the multiplexing unit comprises n gating switches, the first end of the gating switch is connected to the data input end, and the second end of the gating switch is electrically connected to the data output end one by one; each row of pixel circuits is connected to n first scan lines, and the first scan line is electrically connected to the control end of the data writing module corresponding to the pixel circuit; the pixel circuits arranged in an array are divided into column pixel circuit groups corresponding to the multiplexing units one by one, and each column pixel circuit group comprises n column pixel circuits; each column pixel circuit is connected to a data output end of the corresponding multiplexing unit through a data line; in the column pixel circuit group, the first scan lines connected to the pixel circuits in different columns of the same row are different; In each row period, the n data output ends and the data input end are controlled to be turned on at different times, and the pixel circuits of the same row connected to different data output ends of the multiplexing unit are scanned at different times to write data signals; wherein before the ith data output end and the data input end are controlled to be turned on, the pixel circuits connected to the i-1th data output end are controlled to be scanned, wherein 2≤i≤n; the multiplexing unit comprises n gating switches, the first end of the gating switch is connected to the data input end, and the second end of the gating switch is electrically connected to the data output end one by one; each row of pixel circuits is connected to n first scan lines, and the first scan line is electrically connected to the control end of the data writing module corresponding to the pixel circuit; the pixel circuits arranged in an array are divided into column pixel circuit groups corresponding to the multiplexing units one by one, and each column pixel circuit group comprises n column pixel circuits; each column pixel circuit is connected to a data output end of the corresponding multiplexing unit through a data line; in the column pixel circuit group, the first scan lines connected to the pixel circuits in different columns of the same row are different; In each row period, the n data output ends and the data input end are controlled to be turned on at different times, and the pixel circuits of the same row connected to different data output ends of the multiplexing unit are scanned at different times to write data signals; wherein before the ith data output end and the data input end are controlled to be turned on, the pixel circuits connected to the i-1th data output end are controlled to be scanned, wherein 2≤i≤n; the multiplexing unit comprises n gating switches, the first end of the gating switch is connected to the data input end, and the second end of the gating switch is electrically connected to the data output end one by one; each row of pixel circuits is connected to n first scan lines, and the first scan line is electrically connected to the control end of the data writing module corresponding to the pixel circuit; the pixel circuits arranged in an array are divided into column pixel circuit groups corresponding to the multiplexing units one by one, and each column pixel circuit group comprises n column pixel circuits; each column pixel circuit is connected to a data output end of the corresponding multiplexing unit through a data line; in the column pixel circuit group, the first scan lines connected to the pixel circuits in different columns of the same row are different; The display area of the display panel comprises an edge area and a center area; the data line comprises a first data line located in the edge area and a second data line located in the center area; the multiplexing unit is located in the non-display area of the display panel, and the multiplexing circuit formed by each multiplexing unit corresponds to the center area in the extension direction of the data line. ​ The data output end of the multiplexing unit is connected with a corresponding second data line or a connection line, the connection line is located in the display area, and the connection line and at least part of the data line not connected with the connection line have overlapping projections on the base of the display panel.

2. The driving method of a display panel according to claim 1, wherein The pulse width length of the first active scanning signal on the first scanning line is greater than the pulse width length of the corresponding active gate signal. The active gate signal corresponding to the first active scanning signal on the first scanning line is the active gate signal corresponding to the gate switch of the same pixel circuit in the multiplexing unit connected with the first scanning line.

3. The driving method of the display panel according to claim 1 or 2, wherein The starting time of the first active scanning signal on the first scanning line overlaps with the starting time of the active gate signal corresponding to the gate switch of the same pixel circuit in the multiplexing unit connected with the first scanning line, and the ending time of the first active scanning signal on the first scanning line is later than the ending time of the active gate signal corresponding to the gate switch of the same pixel circuit in the multiplexing unit connected with the first scanning line.

4. The driving method of a display panel according to claim 1, wherein The first active scanning signals on different first scanning lines connected with the same row of pixel circuits do not overlap, and the time of the active scanning signals on the different first scanning lines connected with the same row of pixel circuits is equal to a row period.

5. The driving method of a display panel according to claim 1, wherein Each row of pixel circuits is further connected with a second scanning line. Before the step of controlling n data output ends and the data input end to be turned on in time and scanning the same row of pixel circuits connected with different data output ends of the multiplexing unit in time in each row period, the display panel driving method further comprises the steps of: providing a second active scanning signal to the second scanning line connected with the pixel circuit to simultaneously write an initialization signal to a row of pixel circuits and initialize the gate of the driving transistor included in the pixel circuit.

6. The driving method of a display panel according to claim 1, wherein Each row of pixel circuits is further connected with n second scanning lines; the second scanning lines connected with the pixel circuits in different columns in the same row in the column pixel circuit group are different; before the step of controlling n data output ends and the data input end to be turned on in time and scanning the pixel circuits connected with different data output ends of the multiplexing unit in time in each row period, the display panel driving method further comprises the steps of: providing a second active scanning signal to different second scanning lines connected with the pixel circuit in time to write an initialization signal to the pixel circuits in the same row and different columns in the column pixel circuit group in time and initialize the gate of the driving transistor included in the pixel circuit.

7. The driving method of the display panel according to claim 6, wherein The n first scanning lines include a first scanning line one and a first scanning line two, and the n second scanning lines include a second scanning line one and a second scanning line two. The two first scan lines connected with the first row of pixel circuits are a first scan line one and a first scan line two; the first initialization control end of the pixel circuit in the odd column in the first row of pixel circuits is connected with a second scan line one; and the first initialization control end of the pixel circuit in the even column in the first row of pixel circuits is connected with a second scan line two; The display panel further comprises a first scan circuit and a second scan circuit; The first scan line one is connected with a first stage shift register of the first scan circuit, and the first scan line two is connected with a second stage shift register of the first scan circuit; the second scan line one is connected with a first stage shift register of the second scan circuit, and the second scan line two is connected with a second stage shift register of the second scan circuit.

8. A driving method of a display panel, characterized by, The display panel comprises pixel circuits arranged in an array and a plurality of multiplexing units, the multiplexing units comprising a data input end and n data output ends, wherein n is an integer greater than or equal to 2; Each data output end is connected with the pixel circuit in the corresponding column through a data line; The driving method of the display panel comprises: In each row period, the n data output ends and the data input end are controlled to be turned on at different times, and the pixel circuits in the same row connected with different data output ends of the multiplexing unit are scanned at different times to write data signals at different times; wherein before the i-th data output end and the data input end are controlled to be turned on, the pixel circuits connected with the i-1-th data output end are controlled to be scanned, wherein 2≤i≤n; the multiplexing unit comprises n gating switches, the first end of the gating switch is connected with the data input end, and the second end of the gating switch is connected with the data output end one by one; each row of pixel circuits is connected with n first scan lines, the first scan line is connected with the control end of the data writing module of the corresponding pixel circuit; the pixel circuits arranged in an array are divided into column pixel circuit groups corresponding to the multiplexing units one by one, each column pixel circuit group comprises n column pixel circuits, and each column pixel circuit is connected with a data output end of the corresponding multiplexing unit through a data line; in the column pixel circuit group, the first scan lines connected with the pixel circuits in different columns in the same row are different; Each row of pixel circuits is further connected with n second scan lines; in the column pixel circuit group, the second scan lines connected with the pixel circuits in different columns in the same row are different; before the n data output ends and the data input end are controlled to be turned on at different times and the pixel circuits connected with different data output ends of the multiplexing unit are scanned at different times in each row period, the driving method of the display panel further comprises: A second effective scan signal is provided to different second scan lines connected with the pixel circuits at different times to write initialization signals into the pixel circuits in different columns in the same row in the column pixel circuit group to initialize the gate of the driving transistor included in the pixel circuit.

9. The driving method of the display panel according to claim 8, wherein The n first scan lines comprise a first scan line one and a second scan line two, and the n second scan lines comprise a second scan line one and a second scan line two. The two first scan lines connected with the first row of pixel circuits are a first scan line 1 and a first scan line 2; the first initialization control end of the pixel circuit in the odd column in the first row of pixel circuits is connected with a second scan line 1; and the first initialization control end of the pixel circuit in the even column in the first row of pixel circuits is connected with a second scan line 2; The display panel further comprises a first scan circuit and a second scan circuit; The first scan line 1 is connected with a second stage shift register of the first scan circuit, and the first scan line 2 is connected with a first stage shift register of the second scan circuit.

10. A display panel, characterized by, The display panel comprises pixel circuits arranged in an array and a plurality of multiplexing units, the multiplexing unit comprising a data input end, n data output ends, wherein n is an integer greater than or equal to 2; each data output end is connected with the pixel circuit in the corresponding column through a data line; The display panel is driven by the driving method of the display panel of any one of claims 1-9.

11. The display panel of claim 10, wherein, The display area of the display panel comprises an edge area and a center area; the data line comprises a first data line located in the edge area and a second data line located in the center area; the multiplexing unit is located in the non-display area of the display panel, and along the extension direction of the data line, the multiplexing circuit formed by each multiplexing unit corresponds to the center area; The data output end of the multiplexing unit is connected with the corresponding second data line or connection line, the connection line is located in the display area, and the orthogonal projection of the connection line and at least part of the data line not connected with the connection line on the substrate of the display panel overlaps.

12. The display panel of claim 11, wherein, The first end of the connection line connected with the data output end of the multiplexing unit is closer to the second data line located at the middle position of the center area than the second end of the connection line connected with the first data line.

13. The display panel of claim 12, wherein, One of the data output ends of the multiplexing unit is connected with the second data line, and one of the data output ends is connected to the first data line through a connection line, The orthogonal projection of the connection line and the second data line connected with the same multiplexing unit on the substrate of the display panel overlaps.

14. The display panel of claim 11, wherein, In each row period, the n data output ends are controlled to be turned on with the data input end in time, and the same row of pixel circuits connected with different data output ends of the multiplexing unit are scanned in time to write data signals in time; Before the i-th data output end is turned on with the data input end, the pixel circuit connected with the i-1-th data output end is controlled to be scanned, wherein 2≤i≤n.

15. The display panel of claim 10, wherein, The display panel further comprises a plurality of first scan lines, and the arrayed pixel circuits are divided into column pixel circuit groups corresponding to the plurality of multiplexing units one by one, in the column pixel circuit group, the first scan lines connected to the pixel circuits in different columns in the same row are different; the first scan lines are used for transmitting first effective scan signals to data writing modules of the pixel circuits to control the conduction state of the corresponding connected data writing modules.

16. The display panel of claim 15, wherein, Each row of the pixel circuits is further connected to a second scan line, wherein any first scan line connected to the pixel circuits in the jth row is multiplexed as a second scan line of the pixel circuits in the (j+1)th row, wherein j is an integer greater than or equal to 1; The second scan line is used for transmitting a second effective scan signal to a gate initialization module of the pixel circuit to control the conduction state of the corresponding connected gate initialization module.

17. The display panel of claim 15, wherein, Each row of the pixel circuits is further connected to n second scan lines, in the pixel circuits in the same column, the first scan line connected to the pixel circuit in the jth row is multiplexed as a second scan line of the pixel circuit in the (j+1)th row, wherein j is an integer greater than or equal to 1; The second scan line is used for transmitting a second effective scan signal to a gate initialization module of the pixel circuit to control the conduction state of the corresponding connected gate initialization module.

18. A display device comprising: The display panel of any one of claims 10-17.

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