Semiconductor device and method of manufacturing the same

Abstract

Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a source, a drain, a gate, a bottom dielectric layer, a gate dielectric layer, a channel structure, and a metal nitride layer. The drain and the source are arranged in a vertical direction. The gate is arranged between the drain and the source. The bottom dielectric layer is arranged between the source and the gate. The channel structure is arranged between the drain and the source and electrically connected to the drain and the source. The channel structure is partially arranged in the gate and includes a channel layer and an insulating layer arranged in a horizontal direction. The gate dielectric layer is arranged between the channel structure and the gate. The metal nitride layer is arranged between the gate dielectric layer and the gate. Thus, direct contact between the gate dielectric layer and the gate is prevented, and the operation performance of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a vertical channel structure and a method of fabricating the same. BACKGROUND

[0002] The technology of semiconductor integrated circuits has been growing over time, with each new generation of manufacturing process producing products with smaller and more complex circuit designs than the previous generation. Functional components on each wafer area must be increased in number and density to meet product innovation requirements, of course, the geometry of each component needs to be smaller and smaller. Since the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continue to shrink, the industry has proposed to replace the traditional planar transistor component with a three-dimensional or non-planar transistor component, thereby reducing the geometry of the transistor component or / and improving the operating performance of the transistor element. SUMMARY

[0003] The purpose of the present application is to provide a semiconductor device and a method of fabricating the same, an additional metal nitride layer is formed between the channel structure and the gate, to avoid the gate dielectric layer directly contacting the metal and easily producing high resistance products, thereby improving the operating performance of the semiconductor device.

[0004] To achieve the above-mentioned purpose, one embodiment of the present application provides a semiconductor device, comprising a source, a drain, a gate, a bottom dielectric layer, a gate dielectric layer, a channel structure and a metal nitride layer. The drain and the source are stacked in a vertical direction. The gate is disposed between the drain and the source in the vertical direction. The bottom dielectric layer is disposed between the source and the gate in the vertical direction. The channel structure is disposed between the drain and the source in the vertical direction and electrically connected to the drain and the source, wherein the channel structure is partially disposed in the gate and includes a channel layer and an insulating layer stacked in a horizontal direction. The gate dielectric layer is disposed between the channel structure and the gate in the horizontal direction. The metal nitride layer is disposed between the gate dielectric layer and the gate, wherein part of the bottom dielectric layer is sandwiched between the metal nitride layer and the source.

[0005] Optionally, the top surface of the metal nitride layer is lower than the top surface of the channel structure.

[0006] Optionally, the top surface of the metal nitride layer is between the top surface of the channel structure and the top surface of the gate.

[0007] Optionally, the drain, the source and the gate comprise the same metal material.

[0008] Optionally, the gate further comprises a gate layer and a gate barrier layer disposed below the gate layer, the gate barrier layer physically contacts the metal nitride layer.

[0009] Optionally, the metal nitride layer and the gate barrier layer comprise the same material.

[0010] Optionally, the metal nitride layer and the gate barrier layer collectively have an L-shaped cross section.

[0011] Optionally, a bottom surface of the metal nitride layer is lower than a bottom surface of the gate barrier layer and does not physically contact the source.

[0012] Optionally, a bottom surface of the metal nitride layer is flush with a bottom surface of the gate barrier layer and does not physically contact the source.

[0013] Optionally, the channel structure further comprises a first semiconductor layer stacked on the gate dielectric layer and does not physically contact the source, and a second semiconductor layer stacked between the first semiconductor layer and the insulating layer, the second semiconductor layer physically contacts the source and the drain.

[0014] Optionally, the first semiconductor layer comprises an I-shaped cross section and the second semiconductor layer comprises a U-shaped cross section.

[0015] Optionally, the channel structure comprises indium zinc oxide, aluminum zinc oxide or indium gallium zinc oxide.

[0016] To achieve the above object, one embodiment of the present application provides a method for manufacturing a semiconductor device, comprising the following steps. A source and a drain are formed, the drain and the source are stacked in a vertical direction. A gate is formed, the gate is formed between the drain and the source in the vertical direction. A channel structure is formed, the channel structure is formed between the drain and the source in the vertical direction and electrically connects the drain and the source, the channel structure is partially formed in the gate, wherein the channel structure comprises a channel layer and an insulating layer which are sequentially stacked in a horizontal direction. A gate dielectric layer is formed, the gate dielectric layer is formed between the channel structure and the gate in the horizontal direction. A metal nitride layer is formed between the gate dielectric layer and the gate.

[0017] Optionally, the method for manufacturing the semiconductor device further comprises: forming a via through the gate in the vertical direction; forming a metal nitride material layer in the via before forming the channel structure; and partially removing the metal nitride material layer to form the metal nitride layer.

[0018] Optionally, a top surface of the metal nitride layer is lower than a top surface of the channel structure.

[0019] Optionally, a top surface of the metal nitride layer is between a top surface of the channel structure and a top surface of the gate.

[0020] Optionally, the method for manufacturing the semiconductor device further comprises: sequentially forming a gate dielectric material layer and a first semiconductor material layer in the via; partially removing the gate dielectric material layer and the first semiconductor material layer to form the gate dielectric layer and the first semiconductor layer; forming a second semiconductor material layer and an insulating material layer in the via; and partially removing the second semiconductor material layer and the insulating material layer to form the second semiconductor layer and the insulating layer, the channel layer comprising the first semiconductor layer and the second semiconductor layer.

[0021] Optionally, the second semiconductor layer physically contacts the source and the drain, and the first semiconductor layer does not contact the source.

[0022] Optionally, the first semiconductor layer comprises a I-shaped cross section, and the second semiconductor layer comprises a U-shaped cross section.

[0023] Optionally, the drain is disposed on the insulating layer, and a bottom surface of the drain is flush with a top surface of the channel structure.

[0024] In summary, the semiconductor device and the method for manufacturing the semiconductor device of the present application form a metal nitride layer between the channel structure and the gate, so as to avoid the dielectric material of the gate dielectric layer directly contacting the metal material of the gate and easily generating a high resistance product, thereby improving the operation performance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of embodiments of the application, and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of some embodiments. It should be noted that all the drawings are schematic and for purposes of illustration and convenience in drawing, the relative sizes and proportions of the elements shown in the drawings have been shown exaggerated or reduced in size. Identical reference numerals have been used in different drawings to represent corresponding or similar elements.

[0026] Figure 1 A cross-sectional view of a semiconductor device according to a first embodiment of the present application is shown.

[0027] Figures 2 to 11 A schematic diagram illustrating a method of fabricating a semiconductor device in accordance with an embodiment of the present application;

[0028] Figure 2 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a metal nitride material layer;

[0029] Figure 3 A schematic diagram illustrating a cross-section of a semiconductor device after performing a back-etching process;

[0030] Figure 4 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a metal nitride layer;

[0031] Figure 5 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a gate dielectric material layer;

[0032] Figure 6 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a first semiconductor material layer;

[0033] Figure 7 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a first semiconductor layer;

[0034] Figure 8 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a second semiconductor material layer;

[0035] Figure 9 A schematic diagram illustrating a cross-section of a semiconductor device after formation of an insulating material layer;

[0036] Figure 10 A schematic diagram illustrating a cross-section of a semiconductor device after formation of an insulating layer; and

[0037] Figure 11 A schematic diagram illustrating a cross-section of a semiconductor device after formation of a channel structure.

[0038] Figure 12 A schematic diagram illustrating a cross-section of a semiconductor device in accordance with a second embodiment of the present application.

[0039] Wherein the reference numerals are explained as follows:

[0040] 10, 26, 38 dielectric layer

[0041] 12, 16, 40 barrier layer

[0042] 14, 42 conductive layer

[0043] 18 bottom semiconductor layer

[0044] 20 bottom dielectric layer

[0045] 22 gate barrier layer

[0046] 24 gate layer

[0047] 28 gate dielectric layer

[0048] 28a, 28b gate dielectric material layer

[0049] 28A first portion

[0050] 28B, 28C second portion

[0051] 30 first semiconductor layer

[0052] 30a first semiconductor material layer

[0053] 32 second semiconductor layer

[0054] 32a second semiconductor material layer

[0055] 34 insulating layer

[0056] 34a insulating material layer

[0057] 36 third semiconductor layer

[0058] 50, 51 metal nitride layer

[0059] 50a, 50b metal nitride material layer

[0060] 52, 52a semiconductor material layer

[0061] 54 recess

[0062] 101, 103 semiconductor device

[0063] D1 vertical direction

[0064] D2 horizontal direction

[0065] D3 opposite direction of D2

[0066] DE drain

[0067] GE gate

[0068] OP1, OP3 via

[0069] OP2 opening

[0070] SE source

[0071] SS channel structure DETAILED DESCRIPTION

[0072] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, along with accompanying drawings, to explain in detail the technical solutions and desired effects of this invention. Those skilled in the art can, without departing from the spirit of this invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0073] Please refer to Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of the semiconductor device 101 according to the first embodiment of the present invention. Figure 1 As shown, the semiconductor device 101 includes a source SE, a bottom dielectric layer 20, a gate GE, a gate dielectric layer 28, a channel structure SS, a drain DE, and a metal nitride layer 50. The drain DE and the source SE are stacked in the vertical direction D1, while the gate GE is disposed on top of the source SE and located between the drain DE and the source SE. The channel structure SS is partially disposed within the gate GE in the vertical direction D1 and is also located between the drain DE and the source SE to electrically connect the drain DE and the source SE. The channel structure SS includes a channel layer 46 and an insulating layer 34 sequentially stacked in the horizontal direction D2 or its opposite direction D3. The insulating layer 34 can be used to indirectly control the composition of the channel structure SS and / or support the channel structure SS. The metal nitride layer 50 is disposed between the channel structure SS and the gate GE to isolate the gate dielectric layer 28 from direct contact with the gate GE, preventing the dielectric material of the gate dielectric layer 28 from reacting with the metal material of the gate GE and producing high-resistivity products. In this embodiment, a portion of the bottom dielectric layer 20 is sandwiched between the metal nitride layer 50 and the source electrode SE, ensuring that the metal nitride layer 50 does not physically contact the source electrode SE. Furthermore, the top surface of the metal nitride layer 50 is preferably lower than the top surface of the channel structure SS, for example, located between the top surface of the channel structure SS and the top surface of the gate electrode GE, and further covered by the gate dielectric layer 28, similarly not physically contacting the drain electrode DE. In one embodiment, the metal nitride layer 50 includes, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or other suitable conductivity barrier materials, preferably including titanium nitride, but not limited thereto. Thus, the arrangement of the metal nitride layer 50 effectively improves the component performance of the gate electrode GE and the channel structure SS, thereby enhancing the operational performance of the semiconductor device 101.

[0074] For example Figure 1As shown, the semiconductor device 101 further includes a dielectric layer 10, a bottom semiconductor layer 18, a dielectric layer 26, a dielectric layer 38, a via OP1 and an opening OP2. The aforementioned source electrode SE, a bottom dielectric layer 20, a gate electrode GE, a gate dielectric layer 28, a channel structure SS, a drain electrode DE and a metal nitride layer 50 are disposed on the dielectric layer 10, and the dielectric layer 10 is disposed on a substrate (not shown), such as, but not limited to, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate or a substrate composed of other suitable materials. Those skilled in the art would readily understand that various active components and / or passive components can be further formed on or in the substrate according to actual device requirements. In the vertical direction D1, the bottom semiconductor layer 18 is disposed between the bottom dielectric layer 20 and the source electrode SE, the dielectric layer 26 is disposed between the gate electrode GE and the drain electrode DE, and the dielectric layer 38 is disposed on the dielectric layer 26 and the drain electrode DE is disposed in the dielectric layer 38, but not limited thereto. It is noted that the via OP1 penetrates the dielectric layer 26 and the gate electrode GE in the vertical direction D1, and the opening OP2 penetrates the bottom dielectric layer 20 in the vertical direction D1, so that the via OP1 and the opening OP2 are directly connected, wherein the via OP1 has a relatively large aperture to completely cover the opening OP2, but not limited thereto. In this way, the metal nitride layer 50, the gate dielectric layer 28 and a portion of the channel structure SS are sequentially disposed in the via OP1 in the horizontal direction D2 or the opposite direction D3 thereof, and another portion of the channel structure SS is disposed in the opening OP2, so that the channel structure SS further penetrates the bottom dielectric layer 20 in the vertical direction D1 and physically contacts the bottom semiconductor layer 18. Those skilled in the art would readily understand that the arrangement of the via OP1 and the opening OP2 in the present application is not limited to the foregoing, but can have other different arrangements or shapes according to actual device requirements.

[0075] In detail, the channel layer 46 further includes the first semiconductor layer 30, the second semiconductor layer 32, and the third semiconductor layer 36 arranged in sequence in the horizontal direction D2 or the opposite direction D3 thereof. The first semiconductor layer 30 is arranged in the via OP1, the second semiconductor layer 32 is partially arranged in the via OP1 and partially arranged in the opening OP2, and the third semiconductor layer 36 is also arranged in the via OP1 and is located between the insulating layer 34 and the drain DE. In the present embodiment, the first semiconductor layer 30 surrounds the second semiconductor layer 32 in the horizontal direction D2 and / or the opposite direction D3 thereof, and the second semiconductor layer 32 surrounds the third semiconductor layer 36 and the insulating layer 34 in the horizontal direction D2 and / or the opposite direction D3 thereof, such that the second semiconductor layer 32 has a U-shaped cross section in the cross section as shown in FIG. 6A and is located between the drain DE and the bottom semiconductor layer 18 in the vertical direction D1, and the first semiconductor layer 30 has an I-shaped cross section in the cross section as shown in FIG. 6B and is located between the drain DE and the gate dielectric layer 28 in the vertical direction D1. Figure 1 Figure 1 Thus, the second semiconductor layer 32 of the channel layer 46 is in physical contact with the first semiconductor layer 30, the third semiconductor layer 36, and the bottom semiconductor layer 18, and thus electrically connects the drain DE and the source SE when the gate GE is applied with the threshold voltage. In an embodiment, the bottom semiconductor layer 18 and the first semiconductor layer 30, the second semiconductor layer 32, and the third semiconductor layer 36 of the channel layer 46 each include a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide (IZO), aluminum zinc oxide (AZO), or indium gallium zinc oxide (IGZO), but the disclosure is not limited thereto. In addition, the materials of the first semiconductor layer 30, the second semiconductor layer 32, the third semiconductor layer 36, and the bottom semiconductor layer 18 can be the same as or different from each other.

[0076] ​The gate dielectric layer 28 further includes a first portion 28A extending along the vertical direction D1, and a second portion 28B, 28C extending along the horizontal direction D2 or the opposite direction D3 thereof, wherein the first portion 28A is sandwiched between the first semiconductor layer 30 and the gate electrode GE in the horizontal direction D2 or the opposite direction D3 thereof, and the second portion 28B, 28C is sandwiched between the first semiconductor layer 30 and the bottom dielectric layer 20, or between the drain electrode DE and the metal nitride layer 50, for example, in the vertical direction D1, but not limited thereto. In an embodiment, the dielectric layer 10, the bottom dielectric layer 20, the dielectric layer 26, the dielectric layer 38 and the gate dielectric layer 28 each include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbon nitride, or a high dielectric constant dielectric material, and preferably each include silicon oxide, but not limited thereto. In another embodiment, the gate dielectric layer 28 can selectively include a single film layer or a composite film layer, and preferably includes a silicon oxide layer (not shown) and a high dielectric constant dielectric layer (not shown) stacked in sequence.

[0077] Preferably, the source electrode SE, the gate electrode GE and the drain electrode DE each include a composite layer structure. For example, the source electrode SE includes the barrier layer 12, the conductive layer 14 and the barrier layer 16 stacked in sequence in the vertical direction D1, the gate electrode GE includes the gate barrier layer 22 and the gate electrode layer 24 stacked in sequence in the vertical direction D1, and the drain electrode DE includes the barrier layer 40 and the conductive layer 42 stacked in sequence in the vertical direction D1, but not limited thereto. In other embodiments, the barrier layer 12, the barrier layer 16, the gate barrier layer 22 and / or the barrier layer 40 can be selectively omitted or have a composite film layer according to actual device requirements, but not limited thereto. The barrier layer 12, the barrier layer 16, the gate barrier layer 22 and the barrier layer 40 each include titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or other suitable conductive barrier material, and the materials of the barrier layer 12, the barrier layer 16, the gate barrier layer 22 and the barrier layer 40 can be the same or different, and preferably each include titanium nitride, but not limited thereto. In an embodiment, the gate barrier layer 22 and the metal nitride layer 50 preferably include the same material, such as titanium nitride, but not limited thereto, so that the gate barrier layer 22 can be regarded as an extension of the metal nitride layer 50 in the horizontal direction D2 or the opposite direction D3 thereof. In this embodiment, the bottom surfaces of the gate barrier layer 22 and the metal nitride layer 50 are flush with each other and have a L-shaped cross section, as shown in FIG. 1C, but not limited thereto. In addition, the conductive layer 14, the gate electrode layer 24 and the conductive layer 42 each include copper, aluminum, tungsten or other suitable low-resistance metal material, and the materials of the conductive layer 14, the gate electrode layer 24 and the conductive layer 42 can be the same or different, and preferably each include tungsten, but not limited thereto. Figure 1 Preferably, the source electrode SE, the gate electrode GE and the drain electrode DE each include a composite layer structure. For example, the source electrode SE includes the barrier layer 12, the conductive layer 14 and the barrier layer 16 stacked in sequence in the vertical direction D1, the gate electrode GE includes the gate barrier layer 22 and the gate electrode layer 24 stacked in sequence in the vertical direction D1, and the drain electrode DE includes the barrier layer 40 and the conductive layer 42 stacked in sequence in the vertical direction D1, but not limited thereto. In other embodiments, the barrier layer 12, the barrier layer 16, the gate barrier layer 22 and / or the barrier layer 40 can be selectively omitted or have a composite film layer according to actual device requirements, but not limited thereto. The barrier layer 12, the barrier layer 16, the gate barrier layer 22 and the barrier layer 40 each include titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or other suitable conductive barrier material, and the materials of the barrier layer 12, the barrier layer 16, the gate barrier layer 22 and the barrier layer 40 can be the same or different, and preferably each include titanium nitride, but not limited thereto. In an embodiment, the gate barrier layer 22 and the metal nitride layer 50 preferably include the same material, such as titanium nitride, but not limited thereto, so that the gate barrier layer 22 can be regarded as an extension of the metal nitride layer 50 in the horizontal direction D2 or the opposite direction D3 thereof. In this embodiment, the bottom surfaces of the gate barrier layer 22 and the metal nitride layer 50 are flush with each other and have a L-shaped cross section, as shown in FIG. 1C, but not limited thereto. In addition, the conductive layer 14, the gate electrode layer 24 and the conductive layer 42 each include copper, aluminum, tungsten or other suitable low-resistance metal material, and the materials of the conductive layer 14, the gate electrode layer 24 and the conductive layer 42 can be the same or different, and preferably each include tungsten, but not limited thereto.

[0078] It is particularly noted that the first semiconductor layer 30, the second semiconductor layer 32 and the insulating layer 34 of the present embodiment collectively present columnar structures extending along the vertical direction D1, and the central axes of the columnar structures in the vertical direction D1 can substantially overlap, while the gate dielectric layer 28 presents a ring structure surrounding the channel structure SS and being interposed between the gate GE and the channel structure SS. Under this arrangement, the source SE, the gate GE, the gate dielectric layer 28, the channel structure SS and the drain DE can collectively form a three-dimensional transistor component, such that the channel structure SS serves as a vertical channel structure of the three-dimensional transistor component, and the gate GE surrounding the channel structure SS can achieve a similar effect of a gate-all-around (GAA). Thus, the semiconductor device 101 of the present embodiment can be electrically connected to other active components and / or passive components downward and / or upward through other connecting components in subsequent manufacturing processes, and the component performance of the gate GE and the channel structure SS inside the semiconductor device 101 can be effectively improved by the provision of the metal nitride layer 50, thereby achieving more optimized operation performance.

[0079] To enable those skilled in the art of the present application to easily understand the semiconductor device of the present application and to implement it, the manufacturing method of the semiconductor device 101 of the present application will be further described below.

[0080] Please refer to Figures 2 to 11 , which is a schematic diagram of the manufacturing method of the semiconductor device 101 of an embodiment of the present application. First, as shown in Figure 2 , the source SE, the bottom semiconductor layer 18, the bottom dielectric layer 20, the gate GE and the dielectric layer 26 are sequentially formed on the dielectric layer 10, and the via OP1 sequentially penetrating the dielectric layer 26 and the gate GE is formed to partially expose the bottom dielectric layer 20. Then, as shown in Figure 2 , the metal nitride material layer 50a and the semiconductor material layer 52 are sequentially formed, both conformally covering the top surface of the dielectric layer 26 and covering the bottom and sidewall of the via OP1. That is, the metal nitride material layer 50a and the semiconductor material layer 52 are both partially formed in the via OP1 and partially formed outside the via OP1. In an embodiment, the metal nitride material layer 50a includes, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or other suitable conductive barrier material, and preferably includes the same material as the gate barrier layer 22, such as titanium nitride, while the semiconductor material layer 52 includes, for example, doped polysilicon or doped amorphous silicon and the like, but is not limited thereto.

[0081] Next, a back-etching fabrication process is performed to remove the semiconductor material layer 52 and the metal nitride material layer 50a formed outside the via OP1, while removing the semiconductor material layer 52 and the metal nitride material layer 50a covering the bottom and sidewalls of the via OP1, to form a semiconductor material layer 52a and a metal nitride material layer 50b only on the sidewalls of the via OP1, as shown in Figure 3 The metal nitride material layer 50b and the semiconductor material layer 52a are sequentially stacked on the sidewalls of the via OP1 in a horizontal direction D2 or an opposite direction D3 thereof, and have L-shaped cross-sections and I-shaped cross-sections, respectively, wherein the top surfaces of the metal nitride material layer 50b and the semiconductor material layer 52a are coplanar with the top surface of the dielectric layer 26, for example, but not for limitation.

[0082] Then, an etching fabrication process is performed to completely remove the semiconductor material layer 52a, while partially removing the metal nitride material layer 50b and the underlying bottom dielectric layer 20 thereunder, to form a top-surface-lower metal nitride layer 50 on the sidewalls of the via OP1, and a top-surface-lower recess 54 on the bottom dielectric layer 20 exposed from the via OP1, as shown in Figure 4 The top surface of the metal nitride layer 50 is significantly lower than the top surface of the dielectric layer 26, and the sidewalls of the metal nitride layer 50 are flush with the sidewalls of the recess 54.

[0083] As shown in Figure 5 A gate dielectric material layer 28a is formed conformally covering the top surface of the dielectric layer 26 and the bottom and sidewalls of the via OP1, while completely covering the metal nitride layer 50 and filling the recess 54. That is, the gate dielectric material layer 28a is also partially formed in the via OP1 and partially formed outside the via OP1. In an embodiment, the gate dielectric material layer 28a includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or the like, or a high dielectric constant dielectric material, and preferably includes the same material as the dielectric layer 26 and the bottom dielectric layer 20, such as silicon oxide, or the like, but not for limitation. Furthermore, the gate dielectric material layer 28a can be fabricated by a film-forming process, such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable means, but not for limitation. In another embodiment, the gate dielectric material layer 28a can optionally include a single film layer or a composite film layer, such as a silicon oxide layer (not shown) and a high dielectric constant dielectric layer (not shown) sequentially stacked.

[0084] As shown in Figure 6As shown, a first semiconductor material layer 30a is formed on the gate dielectric material layer 28a, conformally covering the gate dielectric material layer 28a, such that the first semiconductor material layer 30a can be partially formed within and partially formed outside the through-hole OP1. In one embodiment, the first semiconductor material layer 30a includes, for example, a semiconductor material such as doped polycrystalline silicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, preferably indium zinc oxide or indium gallium zinc oxide, but is not limited thereto. Furthermore, the first semiconductor material layer 30a can also be fabricated using film deposition processes such as chemical vapor deposition, physical vapor deposition, or other suitable methods, but is not limited thereto.

[0085] After that, as Figure 7 As shown, the first semiconductor material layer 30a and the gate dielectric material layer 28a located outside the through-hole OP1 are removed, as are the first semiconductor material layer 30a and the gate dielectric material layer 28a located on the bottom of the through-hole OP1. Simultaneously, the bottom dielectric layer 20 exposed from the through-hole OP1 is further removed downwards, forming an opening OP2 that penetrates the bottom dielectric layer 20 to expose a portion of the bottom semiconductor layer 18. In one embodiment, the opening OP2 overlaps with the through-hole OP1 in the vertical direction D1, and the projected area of ​​the opening OP2 in the vertical direction D1 is smaller than the projected area of ​​the through-hole OP1 in the vertical direction D1, allowing direct communication between the opening OP2 and the through-hole OP1, but this is not a limitation. On the other hand, through the aforementioned removal process of the first semiconductor material layer 30a and the gate dielectric material layer 28a, after the opening OP2 is formed, the first semiconductor layer 30 and the gate dielectric layer 28 having a first portion 28A and second portions 28B and 28C are simultaneously formed on the sidewall of the through hole OP1. The first semiconductor layer 30 and the gate dielectric layer 28 have flush top surfaces and are both coplanar with the top surface of the dielectric layer 26, and the gate dielectric layer 28 completely covers the metal nitride layer 50.

[0086] like Figure 8As shown, after the aperture OP2 is formed, a second semiconductor material layer 32a is formed, partially located within the aperture OP1, partially located within the aperture OP2, and partially located outside both the aperture OP1 and aperture OP2. Specifically, the second semiconductor material layer 32a is conformally formed on the bottom and sidewalls of the aperture OP2, on the sidewalls of the gate dielectric layer 28, and on the sidewalls of the first semiconductor layer 30. The second semiconductor material layer 32a located outside the aperture OP1 and aperture OP2 covers the top surfaces of the dielectric layer 26, the gate dielectric layer 28, and the first semiconductor layer 30. In this embodiment, the first semiconductor layer 30 surrounds the second semiconductor material layer 32a within the aperture OP1, while the second semiconductor material layer 32a formed in the aperture OP2 physically contacts the exposed top surface of the bottom semiconductor layer 18. In one embodiment, the second semiconductor material layer 32a also includes a semiconductor material, such as doped polycrystalline silicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, etc., preferably including the same material as the first semiconductor layer 30, such as indium zinc oxide or indium gallium zinc oxide, but not limited thereto. Furthermore, the second semiconductor material layer 32a is fabricated, for example, by a film deposition process such as chemical vapor deposition, physical vapor deposition, or other suitable methods, but not limited thereto.

[0087] like Figure 9 As shown, after the second semiconductor material layer 32a is formed, an insulating material layer 34a is formed, filling the opening OP2 and the through-hole OP1, and further covering the second semiconductor material layer 32a outside the through-hole OP1. That is, the second semiconductor material layer 32a is partially formed inside the through-hole OP1, partially formed inside the opening OP2, and partially formed outside the through-hole OP1 and the opening OP2. In one embodiment, the insulating material layer 34a includes, for example, a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, preferably silicon oxide, but not limited thereto. Furthermore, the insulating material layer 34a can also be fabricated by film deposition processes such as chemical vapor deposition, physical vapor deposition, or other suitable methods, but not limited thereto.

[0088] Then, another etching process is performed to remove a portion of the insulating material layer 34a, for example, removing the insulating material layer 34a located outside the through hole OP1 and the opening OP2, while also partially removing the insulating material layer 34a located within the through hole OP1, thus forming an insulating layer 34. Figure 10 As shown. Thus, the top surface of the insulating layer 34 is lower than the top surface of the dielectric layer 26 in the vertical direction D1.

[0089] After the insulating layer 34 is formed, a third semiconductor material layer (not shown) is formed to fill the via OP1 and further cover the second semiconductor material layer 32a outside the via OP1. Then, another etching process is performed to remove the third semiconductor material layer and the second semiconductor material layer 32a outside the via OP1, thereby forming a third semiconductor layer 36 and a second semiconductor layer 32, as shown in Figure 11 In an embodiment, the third semiconductor material layer also comprises a semiconductor material, such as doped polysilicon, doped amorphous silicon, indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide, for example, and preferably comprises the same material as the first semiconductor layer 30 and / or the second semiconductor layer 32, such as indium zinc oxide or indium gallium zinc oxide, but is not limited thereto. The top surface of the gate dielectric layer 28, the top surface of the first semiconductor layer 30, the top surface of the second semiconductor layer 32, and the top surface of the third semiconductor layer 36 are flush with each other and substantially coplanar with the top surface of the dielectric layer 26, but are not limited thereto. In this way, the first semiconductor layer 30, the second semiconductor layer 32, and the third semiconductor layer 36, which are sequentially stacked in the horizontal direction D2 or the opposite direction D3 and disposed in the via OP1, collectively form a channel layer 46, and the channel layer 46 and the insulating layer 34 collectively form a channel structure SS. Those skilled in the art should understand that the channel structure SS can be formed by other suitable methods without being limited to the above method.

[0090] In addition, after the channel structure SS is formed, the dielectric layer 38 and the drain DE are formed such that the drain DE is formed on the channel structure SS and the gate dielectric layer 28 and completely covers the via OP1. That is, the bottom surface of the drain DE is coplanar with the top surface of the channel structure SS. In this way, the semiconductor device 101 shown in Figure 1 is formed, in which the second semiconductor layer 32 of the channel layer 46 simultaneously physically contacts the first semiconductor layer 30, the third semiconductor layer 36, and the bottom semiconductor layer 18, and is electrically connected to the drain DE and the source SE.

[0091] Thus, the fabrication of the semiconductor device 101 in this embodiment is completed. According to the fabrication method of this embodiment, the source SE is formed on the dielectric layer 10 first, and then the gate GE is formed on the source SE. Then, the via OP1 is formed through the gate GE in the vertical direction D1, and the metal nitride layer 50, the gate dielectric layer 28, the channel structure SS, and the insulating layer 34 are sequentially formed in the via OP1. In this arrangement, at least a portion of the channel structure SS is located within the gate GE and between the drain DE and the source SE, and electrically connects the drain DE and the source SE through the second semiconductor layer 32. Also, the metal nitride layer 50 is arranged between the channel structure SS and the gate GE to prevent the gate dielectric layer 28 from directly contacting the gate GE, so as to avoid the dielectric material of the gate dielectric layer 28 from reacting with the metal material of the gate GE and generating a product with high resistance. In this way, the arrangement of the metal nitride layer 50 effectively improves the assembly performance of the gate GE and the channel structure SS, so as to improve the operation performance of the fabricated semiconductor device 101.

[0092] Those skilled in the art of the present application should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and the fabrication method thereof of the present application can also have other forms or can be achieved by other means, and are not limited to the foregoing. Further embodiments or variations of the semiconductor device and the fabrication method thereof of the present application will be described below. For simplicity, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeated. In addition, the same components in the embodiments of the present application are denoted by the same reference numerals for ease of mutual comparison between the embodiments.

[0093] Please refer to Figure 12 , Figure 12 is a sectional view of a semiconductor device 103 according to a second embodiment of the present application. As Figure 12 shown, the structure of the semiconductor device 103 of this embodiment is generally the same as that of the semiconductor device 101 in the first embodiment described above, and also includes the source SE, the bottom dielectric layer 20, the gate GE, the gate dielectric layer 28, the channel structure SS, and the drain DE, and the same parts will not be repeated. The main difference between the semiconductor device 103 of this embodiment and the first embodiment described above is that the bottom surface of the metal nitride layer 51 is lower than the bottom surface of the gate barrier layer 22 and does not physically contact the source SE.

[0094] In detail, the present embodiment is to form a via OP3 through the dielectric layer 26, the gate electrode GE and a portion of the bottom dielectric layer 20 in the vertical direction D1, so that the metal nitride layer 51, the gate dielectric layer 28 and the first semiconductor layer 30 formed subsequently in the via OP3 have a bottom surface lower than the bottom surface of the gate blocking layer 22, and the metal nitride layer 51 is still not in physical contact with the source electrode SE. On the other hand, the top surface of the metal nitride layer 51 is also lower than the top surface of the channel structure SS, for example, is between the top surface of the channel structure SS and the top surface of the gate electrode GE, and is further covered by the gate dielectric layer 28 so as not to be in physical contact with the drain electrode DE. In this arrangement, the metal nitride layer 51 of the present embodiment can also isolate the direct contact between the gate dielectric layer 28 and the gate electrode GE, so as to avoid the reaction between the dielectric material of the gate dielectric layer 28 and the metal material of the gate electrode GE and to generate a product with high resistance. In this way, the arrangement of the metal nitride layer 51 can also effectively improve the assembly performance of the gate electrode GE and the channel structure SS, so as to improve the operation performance of the semiconductor device 103.

[0095] In summary, the semiconductor device of the present application is to form a metal nitride layer between the channel structure and the gate electrode, so as to avoid the direct contact between the dielectric material of the gate dielectric layer and the metal material of the gate electrode and to easily generate a product with high resistance, so as to improve the operation performance of the semiconductor device.

[0096] The above descriptions are only the preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that, include: Source pole; Drain electrode, wherein the drain electrode and the source electrode are stacked in a vertical direction; A gate is disposed in the vertical direction between the drain and the source. A bottom dielectric layer is disposed in the vertical direction between the source and the gate; A channel structure is disposed in the vertical direction between the drain and the source and electrically connects the drain and the source. The channel structure is partially disposed in the gate and includes a channel layer and an insulating layer stacked sequentially in the horizontal direction. A gate dielectric layer is disposed in the horizontal direction between the channel structure and the gate; as well as A metal nitride layer is disposed between the gate dielectric layer and the gate, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source. The gate dielectric layer is in direct contact with the top surface of the metal nitride layer, and the bottom dielectric layer is in direct contact with the bottom surface of the metal nitride layer.

2. The semiconductor device according to claim 1, characterized in that, The top surface of the metal nitride layer is lower than the top surface of the channel structure.

3. The semiconductor device according to claim 1, characterized in that, The top surface of the metal nitride layer is located between the top surface of the channel structure and the top surface of the gate.

4. The semiconductor device according to claim 1, characterized in that, The drain, the source, and the gate are made of the same metallic material.

5. The semiconductor device according to claim 1, characterized in that, The gate also includes: Gate layer; and A gate barrier layer is disposed below the gate layer, and the gate barrier layer is in physical contact with the metal nitride layer.

6. The semiconductor device according to claim 5, characterized in that, The metal nitride layer and the gate barrier layer are made of the same material.

7. The semiconductor device according to claim 5, characterized in that, The metal nitride layer and the gate barrier layer together have an L-shaped cross-section.

8. The semiconductor device according to claim 5, characterized in that, The bottom surface of the metal nitride layer is lower than the bottom surface of the gate barrier layer and does not physically contact the source electrode.

9. The semiconductor device according to claim 5, characterized in that, The bottom surface of the metal nitride layer is flush with the bottom surface of the gate barrier layer and does not physically contact the source electrode.

10. The semiconductor device according to claim 1, characterized in that, The channel layer also includes: A first semiconductor layer, stacked on the gate dielectric layer, and not physically in contact with the source electrode; and A second semiconductor layer is stacked between the first semiconductor layer and the insulating layer, and the second semiconductor layer physically contacts the source and the drain.

11. The semiconductor device according to claim 10, characterized in that, The first semiconductor layer has an I-shaped cross-section, and the second semiconductor layer has a U-shaped cross-section.

12. The semiconductor device according to claim 1, characterized in that, The channel layer includes indium zinc oxide, aluminum zinc oxide, or indium gallium zinc oxide.

13. A method for fabricating a semiconductor device, characterized in that, include: A source and a drain are formed, and the drain and the source are stacked in the vertical direction; A gate is formed in the vertical direction between the drain and the source; A bottom dielectric layer is formed, wherein the bottom dielectric layer is formed in the vertical direction between the source and the gate; A channel structure is formed, the channel structure is formed in the vertical direction between the drain and the source and electrically connects the drain and the source, the channel structure is partially formed in the gate, wherein the channel structure includes a channel layer and an insulating layer stacked sequentially in the horizontal direction; A gate dielectric layer is formed, wherein the gate dielectric layer is formed in the horizontal direction between the channel structure and the gate; as well as A metal nitride layer is formed between the gate dielectric layer and the gate; The gate dielectric layer is in direct contact with the top surface of the metal nitride layer, and the bottom dielectric layer is in direct contact with the bottom surface of the metal nitride layer.

14. A method for manufacturing a semiconductor device according to claim 13, characterized in that, Also includes: A through-hole is formed in the vertical direction, penetrating the gate electrode; Before forming the channel structure, a metal nitride material layer is formed inside the perforation; as well as The metal nitride material layer is partially removed to form the metal nitride layer.

15. A method for manufacturing a semiconductor device according to claim 14, characterized in that, The top surface of the metal nitride layer is lower than the top surface of the channel structure.

16. A method for manufacturing a semiconductor device according to claim 14, characterized in that, The top surface of the metal nitride layer is located between the top surface of the channel structure and the top surface of the gate.

17. A method for manufacturing a semiconductor device according to claim 14, characterized in that, Also includes: A gate dielectric material layer and a first semiconductor material layer are sequentially formed within the perforation; Partially remove the gate dielectric material layer and the first semiconductor material layer to form the gate dielectric layer and the first semiconductor layer; A second semiconductor material layer and an insulating material layer are formed within the perforation; as well as Partial removal of the second semiconductor material layer and the insulating material layer forms a second semiconductor layer and the insulating layer, wherein the channel layer includes the first semiconductor layer and the second semiconductor layer.

18. A method for manufacturing a semiconductor device according to claim 17, characterized in that, The second semiconductor layer physically contacts the source and the drain, while the first semiconductor layer does not contact the source.

19. A method for manufacturing a semiconductor device according to claim 17, characterized in that, The first semiconductor layer has an I-shaped cross-section, and the second semiconductor layer has a U-shaped cross-section.

20. A method for manufacturing a semiconductor device according to claim 13, characterized in that, The drain electrode is disposed on the insulating layer, and the bottom surface of the drain electrode is flush with the top surface of the channel structure.

Images