Memory device and method of forming the same

Abstract

A memory device and a method for forming the same. The memory device includes a semiconductor substrate having a plurality of active regions separated by a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, a third trench extending in the first direction in the semiconductor substrate at the bottom of the first trenches, bit line doped regions in the semiconductor substrate on both sides of the third trench, a gate dielectric layer on the sidewalls of the first and second trenches, a first dielectric layer filling the third trench, metal gates in the first trenches on the first dielectric layer and in the second trenches, the metal gates in the second trenches being broken in the second direction, source regions on the top surface of the active regions, and capacitors on the surface of the semiconductor substrate connected to the source regions. The memory device of the present invention has improved storage density.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory, and in particular to a memory device and a forming method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, which is composed of a plurality of repeated memory cells. Each memory cell usually includes a capacitor and a transistor, the gate of the transistor is connected with a word line, the drain region is connected with a bit line, and the source is connected with the capacitor. A voltage signal on the word line can control the opening or closing of the transistor, and then the data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.

[0003] In order to improve the integration of the storage structure, the transistor in the existing Dynamic Random Access Memory (DRAM) usually adopts a trench type transistor structure. However, the line width of the existing trench type transistor structure has been shrunk to the limit and cannot further improve the storage capacity of the DRAM, so how to further improve the storage capacity and storage density of the DRAM is a problem to be solved by those skilled in the art. SUMMARY

[0004] In view of this, the present application provides a new type of memory device and a forming method thereof, which can further improve the storage capacity and storage density of the memory device.

[0005] To this end, some embodiments of the present application provide a forming method of a memory device, comprising:

[0006] providing a semiconductor substrate, a plurality of active regions are formed in the semiconductor substrate, the plurality of active regions are separated by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, the first trench is communicated with the corresponding second trench; forming a third trench extending along the first direction in the semiconductor substrate at the bottom of the first trench, the width of the third trench is smaller than the width of the bottom of the first trench; forming a bit line doping region in the semiconductor substrate on both sides of the third trench and the bottom of the first trench by ion implantation process; forming a gate dielectric layer on the side wall surface and the bottom surface of the first trench and the second trench; forming a first dielectric layer filling the third trench; forming a metal gate in the second trench and the first trench on the first dielectric layer, the top surface of the metal gate is lower than the top surface of the active region; filling a second dielectric layer in the first trench and the second trench on the metal gate; etching part of the metal gate in the second trench to disconnect the metal gate in the second trench along the second direction; forming a source region on the top surface of the active region; forming a capacitor connected with the source region on the surface of the semiconductor substrate.

[0007] In some embodiments, the plurality of active regions are arranged in a matrix.

[0008] In some embodiments, the plurality of active regions are formed by: forming a plurality of first mask patterns extending along a first direction and parallel to each other on the semiconductor, with a first opening between adjacent first mask patterns; forming a plurality of second mask patterns extending along a second direction and parallel to each other on the first mask patterns, with a second opening between adjacent second mask patterns; etching the first mask patterns along the second openings to disconnect the first mask patterns along the second direction, forming a plurality of discrete block mask patterns; and etching the semiconductor substrate to form first trenches corresponding to the first openings and second trenches corresponding to the second openings in the semiconductor substrate, with the semiconductor substrate remaining between the first trenches and the second trenches as the plurality of active regions.

[0009] In some embodiments, the first mask patterns and the second mask patterns are formed by a self-aligned double patterning process.

[0010] In some embodiments, the first mask patterns are formed by: forming a first hard mask layer on the semiconductor substrate; forming a plurality of first strip structures extending along a first direction and parallel to each other on the first hard mask layer; forming a first sacrificial sidewall layer on the sidewalls and top surfaces of the first strip structures and the first hard mask layer between the first strip structures; filling a first filling layer between the first strip structures; removing the first sacrificial sidewall layer from the sidewalls of the first strip structures to form third openings between the first strip structures and the first filling layer; and etching the first hard mask layer along the third openings to form first openings in the first hard mask layer, with the remaining first hard mask layer as the first mask patterns.

[0011] In some embodiments, the second mask patterns are formed by: forming a second hard mask layer on the semiconductor substrate and the first mask patterns; forming a plurality of second strip structures extending along a second direction and parallel to each other on the second hard mask layer; forming a second sacrificial sidewall layer on the sidewalls and top surfaces of the second strip structures and the second hard mask layer between the second strip structures; filling a second filling layer between the second strip structures; removing the second sacrificial sidewall layer from the sidewalls of the second strip structures to form fourth openings between the second strip structures and the second filling layer; and etching the second hard mask layer along the fourth openings to form second openings in the second hard mask layer, with the remaining second hard mask layer as the second mask patterns.

[0012] In some embodiments, the third trench has a width of 3 / 4-1 / 4 of the first trench bottom width.

[0013] In some embodiments, the third trench is formed by: forming a third mask layer in the first trench, the third mask layer having a sixth opening exposing a portion of the semiconductor substrate surface along the first direction and exposing the first trench bottom; etching the semiconductor substrate along the sixth opening to form the third trench.

[0014] In some embodiments, the process of forming the bit line doping region in the semiconductor substrate on both sides of the third trench and the first trench bottom by the ion implantation process includes: forming a fourth mask layer in the third trench and on the top surface of the active region, the fourth mask layer having a seventh opening exposing the semiconductor substrate on both sides of the third trench along the first direction; performing a first ion implantation on the semiconductor substrate at the bottom of the seventh opening along the seventh opening to form the bit line doping region in the semiconductor substrate on both sides of the third trench and the first trench bottom.

[0015] In some embodiments, the impurity ions implanted by the first ion implantation are N-type impurity ions or P-type impurity ions, the first ion implantation has an energy of 20 kev-100 kev, a dose of 1E13-1E22 atom / cm 2 , and an angle of 0-20 degrees.

[0016] In some embodiments, the source region is formed by a second ion implantation, and the type of impurity ions implanted in the source region is the same as the type of impurity ions implanted in the bit line doping region.

[0017] In some embodiments, the process of forming the capacitor connected to the source region on the semiconductor substrate surface includes: forming a third dielectric layer on the active region and the second dielectric layer; forming a via exposing the surface of the source region in the third dielectric layer; forming a contact plug in the via; forming a fourth dielectric layer on the third dielectric layer; forming a capacitor hole exposing the contact plug in the fourth dielectric layer; and forming a capacitor in the capacitor hole.

[0018] In some embodiments, the semiconductor substrate is doped with a well region, and the type of impurity ions doped in the well region is opposite to the type of impurity ions doped in the source region and the bit line doping region.

[0019] Some other embodiments of the present application also provide a memory device, including:

[0020] A semiconductor substrate having a plurality of active regions therein, the plurality of active regions being separated by a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, the first trench being in communication with a corresponding second trench; a third trench in the semiconductor substrate extending in the first direction at the bottom of the first trench, the third trench having a width smaller than the width of the bottom of the first trench; a bit line doping region in the semiconductor substrate on both sides of the third trench and the bottom of the first trench; a gate dielectric layer on the sidewalls of the first and second trenches; a first dielectric layer filling the third trench; a metal gate in the first trench on the first dielectric layer and in the second trench, the top surface of the metal gate being lower than the top surface of the active region, and the metal gate in the second trench being broken in the second direction; a second dielectric layer filling the first and second trenches on the metal gate; a source region on the top surface of the active region; and a capacitor on the surface of the semiconductor substrate connected to the source region.

[0021] In some embodiments, the plurality of active regions are arranged in a row and column arrangement.

[0022] In some embodiments, the width of the third trench is 3 / 4-1 / 4 of the width of the bottom of the first trench.

[0023] In some embodiments, the impurity ions doped in the bit line doping region are N-type impurity ions or P-type impurity ions.

[0024] In some embodiments, the type of impurity ions doped in the source region is the same as the type of impurity ions doped in the bit line doping region.

[0025] In some embodiments, further comprising: a third dielectric layer on the active region and the second dielectric layer, the third dielectric layer having a contact plug therein connected to the source region; a fourth dielectric layer on the third dielectric layer, the fourth dielectric layer having a capacitor hole exposing the contact plug, the capacitor being in the capacitor hole.

[0026] In some embodiments, the material of the metal gate is one or more of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, WSi.

[0027] The method for forming the memory device in some of the foregoing embodiments of the present application forms a plurality of active regions in a semiconductor substrate, the plurality of active regions are separated by a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, a third trench extending in the first direction is formed in the semiconductor substrate at the bottom of the first trench, the width of the third trench is smaller than the width of the bottom of the first trench; a bit line doping region is formed in the semiconductor substrate on both sides of the third trench and at the bottom of the first trench by an ion implantation process; a gate dielectric layer is formed on the sidewall surfaces and bottom surfaces of the first trenches and the second trenches; a first dielectric layer is formed to fill the third trench; a metal gate is formed in the second trenches and the first trenches on the first dielectric layer, the top surface of the metal gate is lower than the top surface of the active region; a second dielectric layer is filled in the first trenches and the second trenches on the metal gate; part of the metal gate in the second trenches is etched to disconnect the metal gate in the second trenches in the second direction; a source region is formed on the top surface of the active region; and a capacitor connected to the source region is formed on the surface of the semiconductor substrate. In the manufacturing process of the memory device of the present application, a plurality of vertical transistors are formed by the foregoing process, each vertical transistor includes a corresponding active region, a gate dielectric layer on the sidewall surface of the active region, a bit line doping region in the semiconductor substrate at the bottom of the first trench and on both sides of the third trench, a source region on the top surface of the active region, and a metal gate surrounding the active region in the first trenches and the second trenches. The vertical transistor with the foregoing specific structure has the source region and the drain region on the upper and lower sides of the active region, and the channel region is formed on the sidewall of the active region, so that the vertical transistor occupies a smaller area of the semiconductor substrate, the number of vertical transistors formed per unit area can be increased, and accordingly the number of capacitors connected to the source region of each transistor per unit area can also be increased, thereby improving the storage capacity and storage density of the memory device. Moreover, the vertical transistor with the foregoing specific structure can reduce the body effect and reduce the leakage current generated by the subsequently formed capacitor to the substrate, thereby improving the electrical performance of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figures 1-39 The structural schematic diagram of the manufacturing process of the memory device of the present application. DETAILED DESCRIPTION

[0029] As described in the background, how to further improve the storage capacity and storage density of DRAM is a problem to be solved by those skilled in the art.

[0030] The research finds that the trench transistor generally comprises at least one buried word line in a semiconductor substrate and a drain region and at least one source region in the semiconductor substrate on both sides of the buried word line. Such a trench transistor occupies a large semiconductor substrate area, which is not conducive to the improvement of the integration of DRAM, thereby limiting the storage capacity and storage density of DRAM.

[0031] To this end, the application provides a novel memory device and a forming method thereof, which can further improve the storage capacity and storage density of the memory device.

[0032] To make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application are described in detail below with reference to the drawings. In the detailed description of the embodiments of the application, the schematic diagrams are partially enlarged without the general proportion for the convenience of description, and the schematic diagrams are only examples, which should not limit the protection scope of the application here. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0033] Reference Figures 13-15 , Figure 13 To Figure 15 A cross-sectional structure schematic diagram along the direction of the cutting line AB, Figure 14 To Figure 15 A cross-sectional structure schematic diagram along the direction of the cutting line CD, a semiconductor substrate 201 is provided, a plurality of active regions 213 are formed in the semiconductor substrate 201, the plurality of active regions 213 are separated by a plurality of first trenches 214 extending in a first direction and a plurality of second trenches 215 extending in a second direction, and the first trench 214 communicates with the corresponding second trench 215.

[0034] The material of the semiconductor substrate 201 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); can also be silicon on insulator (SOI), germanium on insulator (GOI); or can also be other materials, such as gallium arsenide and other group III-V compounds. The material of the semiconductor substrate 201 in the embodiment is silicon. The semiconductor substrate 201 is doped with certain impurity ions according to the type of the vertical transistor to be formed subsequently, for example, the semiconductor substrate can be doped with a well region. The impurity ions can be N-type impurity ions or P-type impurity ions. The P-type impurity ions are one or more of boron ions, gallium ions or indium ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions.

[0035] The active region 213 is used for forming a channel region of a vertical transistor subsequently. The plurality of active regions 213 are discrete, and adjacent active regions 213 are separated by the first trench 214 and the second trench 215 distributed in cross.

[0036] In some embodiments, the formed active regions 213 are arranged in a matrix (see Figure 15 In other embodiments, the active regions can also be arranged in other manners.

[0037] In some embodiments, the first direction and the second direction are perpendicular to each other, and the included angle between the two is 90 degrees. In other embodiments, the first direction and the second direction can not be perpendicular, such as the included angle between the first direction and the second direction being an acute angle.

[0038] In some embodiments, the semiconductor substrate 201 can be etched to form a plurality of first grooves 214, and then the semiconductor substrate 201 can be etched to form a plurality of second grooves 215, thereby forming a plurality of discrete active regions 213. In other embodiments, the first grooves 214 and the second grooves 215 can also be etched at the same time to form the semiconductor substrate 201.

[0039] In this embodiment, the plurality of active regions 213 are formed by a self-aligned double pattern mask process, which will be described in detail below. Figures 1-15 with reference to

[0040] Referring to Figure 1 , a first hard mask layer 202 is formed on the semiconductor substrate 201; and a first material layer 203 is formed on the first hard mask layer 202.

[0041] The first hard mask layer 202 is used for subsequent formation of a first mask pattern. In some embodiments, the first hard mask layer 202 can be a single layer or a multi-layer stacked structure, and the material of the first hard mask layer 202 can be one or more of polycrystalline silicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon oxide, silicon carbide, and germanium silicon. The formation process of the first hard mask layer 202 can be atmospheric pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering, electroplating, spin coating, other suitable methods, and / or combinations thereof. In this embodiment, the material of the first hard mask layer 202 is polycrystalline silicon.

[0042] In some embodiments, a first etching stop layer (not shown in the figure) can be formed between the first hard mask layer 202 and the semiconductor substrate 201, which is used to protect the underlying material layer from over-etching when the first hard mask layer is patterned. The material of the first etching stop layer is different from that of the first hard mask layer, and can be one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, and silicon carbon oxide. In this embodiment, the material of the first etching stop layer is silicon oxide.

[0043] The first material layer 203 is used to form first strip structures. In some embodiments, the first material layer 203 can be a single layer or a multi-layer stack structure, and the material of the first material layer 203 can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon oxide, silicon carbide, and silicon germanium. In this embodiment, the material of the first material layer 203 is amorphous carbon.

[0044] In some embodiments, a second etching stop layer (not shown in the figure) can be formed between the first material layer 203 and the first hard mask layer 202, which is used to protect the underlying material layer from over-etching when the first material layer 203 is patterned. The material of the second etching stop layer is different from that of the first material layer 203. The material of the second etching stop layer can be one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, and silicon carbon oxide. In this embodiment, the material of the second etching stop layer is silicon oxynitride.

[0045] Reference is made to Figure 2 and Figure 3 , Figure 2 is Figure 3 A cross-sectional structure along the cutting line AB is shown in FIG. 4, in which the first material layer 203 is patterned (refer to FIG. 3), and a plurality of first strip structures 204 extending along a first direction and arranged in parallel to each other are formed on the first hard mask layer. Figure 1

[0046] The first strip structures 204 are long strips, and the plurality of first strip structures 204 are discrete and parallel to each other, and have fourth openings 205 between adjacent first strip structures 204.

[0047] In some embodiments, the first material layer 203 is patterned by using an anisotropic dry etching process, which can be an anisotropic plasma etching process.

[0048] ​In some embodiments, before patterning the first material layer 203, a patterned photoresist layer (not shown in the figure) may be formed on the first material layer 203, and the first material layer 203 is etched using the patterned photoresist layer as a mask to form a first strip structure 204; the patterned photoresist layer is then removed.

[0049] refer to Figure 4 , Figure 4 exist Figure 2 Based on this, a first sacrificial sidewall layer 206 is formed on the sidewall and top surface of the first strip structure 204 and on the first hard mask layer 202 between the first strip structure 204.

[0050] The material of the first sacrificial sidewall layer 206 is different from that of the first strip structure. The material of the first sacrificial sidewall layer 206 can be one or more of polycrystalline silicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon oxide, silicon carbide, silicon carbide, and silicon germanide. The first sacrificial sidewall layer 206 is formed by a deposition process, including atomic layer deposition.

[0051] refer to Figure 5 A first filling layer 207 is filled between the first strip structures 204, and the first filling layer 207 fills the remaining fourth opening.

[0052] Subsequently, by removing the first sacrificial sidewall layer from the sidewall surface of the first strip structure 204, a third opening is formed between the first strip structure 204 and the first filling layer 207.

[0053] The material of the first filler layer 207 is different from the material of the first sacrificial sidewall layer 206. In some embodiments, the material of the first filler layer 207 may be one or more of polycrystalline silicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, silicon carbide, silicon germanide, and organic materials. The formation process of the first filler layer 207 may be atmospheric or low-pressure chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering plating, electroplating, spin coating, other suitable methods, and / or combinations thereof.

[0054] In some embodiments, the surface of the formed first filler layer 207 may be flush with the first sacrificial sidewall layer 206 on the top surface of the first strip structure 204. Specifically, after forming a first filler material layer covering the first sacrificial sidewall layer 206 and filling the remaining fourth opening, the first filler layer above the surface of the first sacrificial sidewall layer 206 on the top surface of the first strip structure 204 is removed by a chemical mechanical masking process, and the remaining first filler material layer in the fourth opening is used as the first filler layer 207.

[0055] In some embodiments, the surface of the first filling layer formed can be flush with the top surface of the first strip structure 204. Specifically, after forming the first filling material layer covering the first sacrificial sidewall layer 206 and filling the remaining fourth opening, the first sacrificial sidewall layer 206 and the first filling material layer above the top surface of the first strip structure 204 are removed by a chemical mechanical masking process, exposing the top surface of the first strip structure 204. The remaining first filling material layer in the fourth opening is used as the first filling layer, so the top surface of the first filling layer is flush with the top surface of the first strip structure. Subsequently, after forming the third opening, when etching the first hard mask layer, the etching load effect caused by the difference in height between the filling layer and the first strip structure can be reduced, improving the position and size accuracy of the formed first mask pattern and maintaining a better sidewall morphology. This results in higher position and size accuracy of the block mask pattern formed after disconnecting the first mask pattern and maintaining a better sidewall morphology. Ultimately, this results in higher position and size accuracy of the active region formed by etching the semiconductor substrate using the block mask pattern as a mask and maintaining a better sidewall morphology.

[0056] refer to Figure 6 The first sacrificial sidewall layer on the sidewall surface of the first strip structure 204 is removed, and a third opening 208 is formed between the first strip structure 204 and the first filling layer 207.

[0057] In some embodiments, the removal of the first sacrificial sidewall layer from the sidewall surface of the first strip structure 204 employs an anisotropic dry etching process, including anisotropic plasma etching.

[0058] It should be noted that in some embodiments, when the first sacrificial sidewall layer on the sidewall surface of the first strip structure 204 is removed, the first sacrificial sidewall layer on the top surface of the first strip structure 204 is also removed.

[0059] refer to Figures 7-9 , Figure 7 exist Figure 6 Based on this, Figure 7 for Figure 9 A schematic diagram of the cross-sectional structure along the cutting line AB. Figure 8For Figure 9 A cross-sectional structure schematic diagram along the direction of the cutting line CD, along the third opening 208 (refer to Figure 6 ) etching the first hard mask layer 202 (refer to Figure 6 ), forming a first opening 210 in the first hard mask layer, and the remaining first hard mask layer as a first mask pattern 209.

[0060] In some embodiments, the etching of the first hard mask layer 202 adopts an anisotropic dry etching process, including an anisotropic plasma etching process.

[0061] The formed first mask patterns 209 are discrete, specifically, the formed first mask patterns 209 extend along a first direction and are parallel to each other, and there is a first opening 210 between adjacent first mask patterns 209.

[0062] The aforementioned first mask patterns 209 in the present application are formed by the aforementioned self-aligned double patterning process, and subsequently when the active region is formed, the first trench width between the active regions can be smaller, so that the area of the active region can be larger.

[0063] Reference is made to Figures 10-12 , Figure 10 For Figure 12 A cross-sectional structure schematic diagram along the direction of the cutting line AB, Figure 11 For Figure 12 A cross-sectional structure schematic diagram along the direction of the cutting line CD, the first mask pattern 209 (refer to Figures 7-9 ) is disconnected along a second direction to form a plurality of discrete block mask patterns 211.

[0064] The first mask pattern 209 (refer to Figures 7-9 ) is disconnected along the second direction by an anisotropic dry etching process. In some embodiments, before the first mask pattern 209 is disconnected along the second direction, a plurality of second mask patterns extending along the second direction and parallel to each other are formed on the first mask pattern 209 as a mask for etching the first mask pattern 209, and there is a second opening between adjacent second mask patterns; taking the second mask pattern as a mask, etching the first mask pattern 209 along the second opening, disconnecting the first mask pattern along the second direction to form a plurality of discrete block mask patterns 211; and removing the second mask pattern.

[0065] In some embodiments, the second mask pattern can be formed by a self-aligned double patterning process, and the forming process of the second mask pattern includes: forming a second hard mask layer on the semiconductor substrate and the first mask pattern; forming a plurality of second strip structures parallel to each other in a second direction on the second hard mask layer; forming a second sacrificial sidewall layer on the sidewalls and top surfaces of the second strip structures and the surfaces of the second hard mask layer between the second strip structures; filling a second filling layer between the second strip structures; removing the second sacrificial sidewall layer on the sidewalls of the second strip structures to form fourth openings between the second strip structures and the second filling layer; etching the second hard mask layer along the fourth openings to form second openings in the second hard mask layer, and the remaining second hard mask layer serving as the second mask pattern.

[0066] The material of the second hard mask layer can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon oxide, silicon carbide, and silicon germanide. The forming process of the second hard mask layer can be normal pressure or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (Thermal CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering plating, electroplating, spin coating, other suitable methods, and / or combinations thereof.

[0067] In some embodiments, a fourth etching stop layer can be further formed between the second hard mask layer and the first mask pattern 209. The material of the fourth etching stop layer is different from that of the second hard mask layer, and the material of the fourth etching stop layer is one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, and silicon carbon oxide.

[0068] The material of the second strip structure can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon oxide, silicon carbide, and silicon germanide. In some embodiments, the second strip structure can be formed by etching a second material layer on the second hard mask layer. In some embodiments, a fifth etching stop layer can be further formed between the second material layer and the second hard mask layer. The material of the fifth etching stop layer is different from that of the second material layer. The material of the fifth etching stop layer is one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, and silicon carbon oxide.

[0069] The material of the second sacrificial sidewall layer is different from the material of the second strip structure. The material of the second sacrificial sidewall layer can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, and silicon germanide. The second sacrificial sidewall layer is formed by a deposition process, which can be atomic layer deposition.

[0070] The material of the second fill layer is different from the material of the second sacrificial sidewall layer. In some embodiments, the material of the second fill layer can be one or more of polysilicon, amorphous silicon, amorphous carbon, silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbide, silicon carbide, silicon germanide, and organic material. The second fill layer can be formed by a process such as atmospheric or low pressure chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, sputtering plating, electroplating, spin coating, other suitable methods, and / or combinations thereof.

[0071] In some embodiments, the surface of the formed second fill layer can be flush with the second sacrificial sidewall layer on the top surface of the second strip structure. Specifically, after forming the second fill material layer covering the space between the second strip structure and the second sacrificial sidewall layer, the second fill layer above the surface of the second sacrificial sidewall layer on the top surface of the second strip structure is removed by a chemical mechanical polishing process, and the remaining second fill material layer between the second strip structure is used as the second fill layer.

[0072] In some embodiments, the surface of the formed second fill layer can be flush with the top surface of the second strip structure. Specifically, after forming the second fill material layer covering the space between the second strip structure and the second sacrificial sidewall layer, the second fill material layer and the second sacrificial sidewall layer above the top surface of the second strip structure are removed by a chemical mechanical polishing process, exposing the top surface of the second strip structure, and the remaining second fill material layer between the second strip structure is used as the second fill layer. Thus, the top surface of the formed second fill layer is flush with the top surface of the second strip structure, which can reduce the etching loading effect caused by the height difference between the fill layer and the second strip structure when etching the second hard mask layer after forming the fourth opening, improve the accuracy of the position and size of the second mask pattern formed, and maintain a good sidewall profile. Furthermore, the position and size of the block mask pattern formed after breaking the first mask pattern have high accuracy and maintain a good sidewall profile, and finally the position and size of the active region formed by etching the semiconductor substrate using the block mask pattern as a mask have high accuracy and maintain a good sidewall profile.

[0073] In some embodiments, the first sacrificial side wall layer of the second strip structure side wall surface is removed by using an anisotropic dry etching process, including an anisotropic plasma etching process.

[0074] Reference is made to Figures 13-15 , Figure 13 For Figure 15 A cross-sectional structure diagram along the direction of the cutting line AB, Figure 14 For Figure 15 A cross-sectional structure diagram along the direction of the cutting line CD, using the block mask pattern (reference Figure 11 ) as a mask, etching the semiconductor substrate 201 to form a first trench 214 corresponding to the first opening and a second trench 215 corresponding to the second opening in the semiconductor substrate 201, a plurality of first trenches 214 extend along the first direction and are parallel to each other, a plurality of second trenches 215 extend along the second direction and are parallel to each other, each first trench 214 and the corresponding second trench 215 are in communication with each other, and the remaining semiconductor substrate between the first trench 214 and the second trench 215 is a plurality of active regions 213.

[0075] In some embodiments, reference is made to Figure 16 and Figure 17 , Figure 16 On the basis of Figure 13 , Figure 17 On the basis of Figure 14 , a protective layer 236 is formed on the surface of the active region 213 and the side wall and bottom surface of the first trench and the second trench.

[0076] The protective layer 236 protects the active region 213 during subsequent processes (such as etching or implantation processes). The material of the protective layer 236 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride. In this embodiment, the material of the protective layer 236 can be silicon oxide, which can be formed by a furnace tube oxidation, thermal oxidation, or deposition process.

[0077] Reference is made to Figure 18 and Figure 19 , a third trench 217 extending along the first direction is formed in the semiconductor substrate 201 at the bottom of the first trench 214, and the width of the third trench 217 is smaller than the width of the bottom of the first trench 214.

[0078] The purpose of forming the third trench 217 is to separate adjacent active regions 213 when arranged along the second direction, and to define the position of the bit line doping region (specifically, the semiconductor substrate on both sides of the third trench as the bit line doping region of the corresponding transistor).

[0079] Each semiconductor substrate 201 at the bottom of the first trench 214 has a third trench 217 formed therein. The width of the first trench 214 is less than the width of the bottom of the first trench 214. In some embodiments, the width of the first trench 214 is 1 / 4-3 / 4 of the width of the bottom of the first trench 214.

[0080] In some embodiments, the third trench 217 extending in the first direction is formed by etching the semiconductor substrate 201 at the bottom of the first trench 214. Before etching the semiconductor substrate 201, a third mask layer is formed in the first trench 214 and on the semiconductor substrate 201, the third mask layer has a sixth opening extending in the first direction and exposing a portion of the surface of the semiconductor substrate 201 at the bottom of the first trench 214; the semiconductor substrate 201 is etched along the sixth opening to form the third trench 217, the etching is anisotropic dry etching, which can be anisotropic plasma etching; and the third mask layer is removed.

[0081] Referring to Figures 20-23 The bit line doping region 217 is formed in the semiconductor substrate 201 on both sides of the third trench 217 and at the bottom of the first trench 214 by an ion implantation process.

[0082] The bit line doping region 217 serves as a bit line of a memory later, and the portion of the bit line doping region 217 in contact with each active region 213 can serve as a drain region of a vertical transistor formed later in each active region, and the row of memories arranged in the first direction can be read or written through the bit line after the vertical transistor is formed.

[0083] The bit line doping region 217 is formed by ion implantation, and the type of impurity ions implanted in the bit line doping region 217 is different from the type of impurity ions implanted in the active region 213, for example, when P-type impurity ions are implanted in the active region 213, N-type impurity ions are implanted in the bit line doping region 217, and when N-type impurity ions are implanted in the active region 213, P-type impurity ions are implanted in the bit line doping region 217. The impurity ions implanted in the bit line doping region 217 are N-type impurity ions or P-type impurity ions, the P-type impurity ions are one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions, or antimony ions.

[0084] In some embodiments, before ion implantation, referring to Figures 20-21 A fourth mask layer 238 is formed in the third trench 217 and on the top surface of the active region 213, the fourth mask layer 238 has a seventh opening extending in the first direction and exposing the semiconductor substrate 201 on both sides of the third trench 217; referring to Figures 22-23A first ion implantation is performed through the seventh opening to the semiconductor substrate 201 at the bottom of the seventh opening to form bit line doping regions 218 in the semiconductor substrate 201 on both sides of the third trench 217 and at the bottom of the first trench 214. After the formation of the bit line doping regions 218, the fourth mask layer 238 is removed. The bit line doping regions 218 are formed in the semiconductor substrate 201 on both sides of the active region 213, which can improve the control ability of the bit line and improve the electrical performance of the memory.

[0085] In some embodiments, the first ion implantation has an energy of 20 kev to 100 kev and a dose of 1E13 to 1E22 atom / cm 2 at an angle of 0 to 20 degrees.

[0086] Referring to Figure 24 and Figure 25 a gate dielectric layer 216 is formed on the sidewall and bottom surfaces of the first trench 214 and the second trench 215.

[0087] The material of the gate dielectric layer 216 can be silicon oxide or a high-K dielectric material, such as one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0088] The gate dielectric layer 216 can be formed by an oxidation or deposition process.

[0089] In some embodiments, the gate dielectric layer 216 can be formed after the protective layer 236 is removed. In another embodiment, the protective layer 236 can not be removed and the gate dielectric layer can be formed directly on the protective layer 236.

[0090] In some embodiments, when the gate dielectric layer 216 is formed, the gate dielectric layer 216 can also be formed on the sidewall and bottom surfaces of the third trench, or the third trench can be filled directly with the gate dielectric layer.

[0091] In some embodiments, when the third trench is not filled with the gate dielectric layer material, referring to Figure 24 after the formation of the gate dielectric layer 216, a first dielectric layer 219 is formed to fill the third trench.

[0092] The first dielectric layer 219 is formed for electrical isolation between adjacent word line doping regions 218. In some embodiments, the material of the first dielectric layer 219 is silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), a low-K (K less than 2.8) material, other suitable materials, and / or combinations thereof.

[0093] In some embodiments, the forming of the first dielectric layer 219 includes: forming a first dielectric material layer on the surface of the active region 213 and in the first trench 214, the second trench 215 and the third trench by a deposition process; and removing part of the first dielectric material layer by etching back to form the first dielectric layer 219 filling the third trench.

[0094] In some embodiments, the formed first dielectric layer 219 fills the third trench, and a surface of the first dielectric layer 219 can be higher than an opening of the third trench and partially located in the first trench 214.

[0095] Referring to Figure 26 and Figure 27 a metal gate 220 is formed in the second trench 215 and the first trench 214 on the first dielectric layer 219, and a top surface of the metal gate 220 is lower than a top surface of the active region 213.

[0096] The formed metal gate 220 is located in the first trench 214 and the second trench 215, i.e., the formed metal gate 220 surrounds the sidewall of each active region, which can improve the control ability of the metal gate 220 on the channel formed in the sidewall of the active region and improve the performance of the vertical transistor.

[0097] In some embodiments, the material of the metal gate 220 can be one or more of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN and WSi.

[0098] In some embodiments, the forming of the metal gate 220 includes: forming a metal layer on the surface of the active region and in the first trench and the second trench; and removing part of the metal layer by etching back to leave the metal layer in the first trench and the second trench as the metal gate 220, and a surface of the metal gate 220 is lower than a top surface of the active region 213.

[0099] Referring to Figure 28 and Figure 29 a second dielectric layer 221 is filled in the first trench and the second trench on the metal gate 220; and part of the metal gate 220 in the second trench 215 is etched to disconnect the metal gate 220 in the second trench along the second direction.

[0100] By disconnecting the metal gate 220 along the second direction, a plurality of sub-metal gates extending along the second direction and parallel to each other can be formed, and each sub-metal gate can correspondingly control a plurality of vertical transistors formed in a row of active regions along the second direction.

[0101] In some embodiments, the metal gate 220 in the second trench is disconnected along a second direction, a fifth mask layer 222 is formed on the surface of the second dielectric layer 221 and on the top surface of the active region 213, the fifth mask layer 222 has an eighth opening extending along the second direction and exposing a portion of the surface of the second dielectric layer 221 in the second trench; the second dielectric layer 221 and the metal gate 220 in the second trench are etched along the eighth opening to disconnect the metal gate in the second trench.

[0102] In some embodiments, the material of the second dielectric layer 221 is silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon glass (FSG), low dielectric constant (K less than 2.8) material, other suitable material and / or combination thereof.

[0103] Referring to Figure 30 and Figure 31 , the second mask layer 222 is removed (refer to 28- Figure 29 ); a dielectric material is filled in the gap of the disconnected metal gate 220 and in the second trench, the filled dielectric material is part of the second dielectric layer 221; a source region 223 is formed on the top surface of the active region 213.

[0104] The type of the impurity ions doped in the source region 223 is the same as that of the impurity ions doped in the bit line doping region 218, and is different from that of the impurity ions doped in the well region. The source region 223 is formed by a second ion implantation process. The (doped) impurity ions implanted in the bit line doping region 217 are N-type impurity ions or P-type impurity ions, the P-type impurity ions are one or more of boron ions, gallium ions or indium ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions or antimony ions.

[0105] In the present application, a plurality of vertical transistors are formed by the foregoing process, each vertical transistor comprising a corresponding active region 213, a gate dielectric layer 216 located on the sidewall surface of the active region 213, a bit line doped region 218 in the semiconductor substrate located at the bottom of the first trench and on both sides of the third trench, a source region 223 located on the top surface of the active region 213, and a metal gate 220 located in the first and second trenches and surrounding the active region 213. Due to the specific structure of the vertical transistors, the source and drain regions are located on the upper and lower sides of the active region, and the channel region is formed on the sidewall of the active region. As a result, the vertical transistors occupy a smaller area of the semiconductor substrate, and the number of vertical transistors formed per unit area can be increased, and accordingly the number of capacitors connected to the source region of each transistor formed per unit area in the subsequent process can also be increased, thereby improving the storage capacity and storage density of the memory. Moreover, the specific structure of the vertical transistors can reduce the body effect, reduce the leakage current generated by the subsequently formed capacitors into the substrate, and improve the electrical performance of the memory device.

[0106] In some embodiments, after the source region 223 is formed, the process further comprises forming a capacitor connected to the source region 223 on the surface of the semiconductor substrate 201.

[0107] In some embodiments, the process of forming a capacitor connected to the source region 223 on the surface of the semiconductor substrate 201 comprises: Figure 32 and Figure 33 forming a third dielectric layer 224 on the active region 213 and the second dielectric layer 221, and forming a via 225 exposing the surface of the source region 223 in the third dielectric layer 224. In some embodiments, after the via 225 is formed, the process further comprises: Figure 34 and Figure 34 expanding the opening of the via 225 to facilitate the subsequent formation of a contact plug and to increase the contact area of the subsequently formed capacitor with the top surface of the contact plug. In some embodiments, the process further comprises: Figure 36 and Figure 37 forming a contact plug 226 in the via, the contact plug 226 being made of metal. In some embodiments, the process further comprises: Figure 38 and Figure 39 forming a fourth dielectric layer 227 on the third dielectric layer 224, forming a capacitor hole 229 exposing the contact plug in the fourth dielectric layer 227, and forming a capacitor 228 in the capacitor hole 229.

[0108] In some embodiments, the capacitor 228 comprises a lower electrode layer, a dielectric layer located on the lower electrode layer, and an upper electrode layer located on the dielectric layer.

[0109] In some embodiments, the dielectric layer can be made of high-K dielectric material, such as HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO3, or a stack of two or more of the above materials.

[0110] The material of the upper and lower electrode layers can be one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or a stack of two or more of the above materials. The electrode layers can also include one or both of metal nitride and metal silicide, such as titanium nitride, titanium silicide, nickel silicide, titanium silicide nitride (TiSixNy), etc.

[0111] In some other embodiments, the capacitor can also be formed using existing double-sided capacitor formation processes.

[0112] Some embodiments of the present application also provide a memory device, which is described in combination with reference to Figures 13-15 and Figures 38-39 , comprising:

[0113] a semiconductor substrate 201 having a plurality of active regions 213 therein, the plurality of active regions 213 being separated by a plurality of first trenches 214 extending in a first direction and a plurality of second trenches 215 extending in a second direction, the first trenches 214 being in communication with the corresponding second trenches 215;

[0114] a third trench 217 extending in the first direction in the semiconductor substrate 201 at the bottom of the first trenches 214, the width of the third trench 217 being smaller than the width of the bottom of the first trenches 214;

[0115] a bit line doped region 218 in the semiconductor substrate at both sides of the third trench 217 and the bottom of the first trenches 214;

[0116] a gate dielectric layer 216 on the sidewall surface of the first and second trenches 214 and 215;

[0117] a first dielectric layer 219 filling the third trench 217;

[0118] a metal gate 220 in the first trench 214 and on the second dielectric layer 221, a top surface of the metal gate 220 is lower than a top surface of the active region 213, and the metal gate 220 in the second trench 215 is disconnected in a second direction;

[0119] a second dielectric layer 221 filled in the first trench and the second trench on the metal gate 220;

[0120] a source region 223 on a top surface of the active region 213;

[0121] a capacitor 228 on the semiconductor substrate 201 surface and connected with the source region 223.

[0122] In some embodiments, the active regions 213 are arranged in a matrix.

[0123] In some embodiments, a width of the third trench 217 is 3 / 4-1 / 4 of a width of a bottom of the first trench 214.

[0124] In some embodiments, the impurity ions doped in the bit line doped region 218 are N-type impurity ions or P-type impurity ions. The type of the impurity ions doped in the source region 223 is the same as the type of the impurity ions doped in the bit line doped region 218, and is different from the type of the impurity ions in the well region formed in the active region.

[0125] In some embodiments, further comprising: a third dielectric layer 224 on the active region 213 and the second dielectric layer 221, a contact plug 226 connected with the source region 223 in the third dielectric layer 224; a fourth dielectric layer 227 on the third dielectric layer 224, the fourth dielectric layer 227 has a capacitor hole exposing the contact plug 226, and the capacitor 228 is in the capacitor hole.

[0126] In some embodiments, further comprising: the material of the metal gate is one or more of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, WSi.

[0127] It should be noted that the definition or description of the same or similar structures in the present embodiment (memory device) and the foregoing embodiment (forming process of memory device) will not be repeated in the present embodiment, and the specific definition or description can be referred to the definition or description of the corresponding part in the foregoing embodiment.

[0128] Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A method for forming a memory device, comprising: providing a semiconductor substrate, wherein a plurality of active regions are formed in the semiconductor substrate, and the plurality of active regions are separated by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, and the first trench is communicated with a corresponding second trench; forming a third trench extending along the first direction in the semiconductor substrate at the bottom of the first trench, wherein the width of the third trench is smaller than the width of the bottom of the first trench; forming a bit line doping region in the semiconductor substrate at both sides of the third trench and the bottom of the first trench by an ion implantation process; forming a gate dielectric layer on the sidewall surface and the bottom surface of the first trench and the second trench; forming a first dielectric layer filling the third trench; forming a metal gate in the first trench and the second trench on the first dielectric layer, wherein the top surface of the metal gate is lower than the top surface of the active region; filling a second dielectric layer in the first trench and the second trench on the metal gate; etching part of the metal gate in the second trench to disconnect the metal gate in the second trench along the second direction; forming a source region on the top surface of the active region; forming a capacitor connected with the source region on the surface of the semiconductor substrate; and the process of forming the bit line doping region in the semiconductor substrate at both sides of the third trench and the bottom of the first trench by the ion implantation process comprises: forming a fourth mask layer in the third trench and on the top surface of the active region, wherein the fourth mask layer has a seventh opening exposing the semiconductor substrate at both sides of the third trench extending along the first direction; and performing a first ion implantation on the semiconductor substrate at the bottom of the seventh opening along the seventh opening to form the bit line doping region in the semiconductor substrate at both sides of the third trench and the bottom of the first trench.

2. The method for forming a memory device according to claim 1, wherein the plurality of active regions are arranged in a matrix.

3. The method for forming a memory device according to claim 1 or 2, wherein the process of forming the plurality of active regions comprises: forming a plurality of first mask patterns extending along the first direction and parallel to each other on the semiconductor substrate, wherein adjacent first mask patterns have a first opening therebetween; forming a plurality of second mask patterns extending along the second direction and parallel to each other on the first mask patterns, wherein adjacent second mask patterns have a second opening therebetween; etching the first mask patterns along the second opening to disconnect the first mask patterns along the second direction and form a plurality of discrete block mask patterns by taking the second mask patterns as a mask; and etching the semiconductor substrate by taking the block mask patterns as a mask to form a first trench corresponding to the first opening and a second trench corresponding to the second opening in the semiconductor substrate, wherein the semiconductor substrate remaining between the first trench and the second trench is the plurality of active regions.

4. The method for forming a memory device according to claim 3, wherein the first mask patterns and the second mask patterns are formed by a self-aligned double patterning process.

5. The method for forming a memory device according to claim 4, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The forming process of the first mask pattern comprises: forming a first hard mask layer on the semiconductor substrate; forming a plurality of first strip structures extending along a first direction and arranged in parallel with each other on the first hard mask layer; forming a first sacrificial side wall layer on the side walls and top surfaces of the first strip structures and the first hard mask layer between the first strip structures; filling a first filling layer between the first strip structures; removing the first sacrificial side wall layer on the side wall surfaces of the first strip structures to form third openings between the first strip structures and the first filling layer; etching the first hard mask layer along the third openings to form first openings in the first hard mask layer, and the remaining first hard mask layer serving as the first mask pattern.

6. The forming method of the memory device according to claim 4, wherein, The forming process of the second mask pattern comprises: forming a second hard mask layer on the semiconductor substrate and the first mask pattern; forming a plurality of second strip structures arranged in parallel along a second direction on the second hard mask layer; forming a second sacrificial side wall layer on the side walls and top surfaces of the second strip structures and the surface of the second hard mask layer between the second strip structures; filling a second filling layer between the second strip structures; removing the second sacrificial side wall layer on the side wall surfaces of the second strip structures to form fourth openings between the second strip structures and the second filling layer; etching the second hard mask layer along the fourth openings to form second openings in the second hard mask layer, and the remaining second hard mask layer serving as the second mask pattern.

7. The forming method of the memory device according to claim 1, wherein, The width of the third trench is 3 / 4-1 / 4 of the width of the bottom of the first trench.

8. The forming method of the memory device according to claim 1, wherein, The forming process of the third trench comprises: forming a third mask layer in the first trench, the third mask layer having a sixth opening extending along the first direction and exposing part of the surface of the semiconductor substrate at the bottom of the first trench; etching the semiconductor substrate along the sixth opening to form the third trench.

9. The forming method of the memory device according to claim 1, wherein, The impurity ions implanted by the first ion implantation are N-type impurity ions or P-type impurity ions, the energy of the first ion implantation is 20 kev-100 kev, the dose is 1E13-1E22 atom / cm2, and the angle is 0-20 degrees.

10. The forming method of the memory device according to claim 1, wherein, The source region is formed by a second ion implantation, and the type of the impurity ions implanted in the source region is the same as that of the impurity ions implanted in the bit line doped region.

11. The forming method of the memory device according to claim 1, wherein, The process of forming a capacitor connected with the source region on the surface of the semiconductor substrate comprises: forming a third dielectric layer on the active region and the second dielectric layer; forming a via exposing the surface of the source region in the third dielectric layer; forming a contact plug in the via; forming a fourth dielectric layer on the third dielectric layer; forming a capacitor hole exposing the contact plug in the fourth dielectric layer; and forming a capacitor in the capacitor hole.

12. The method of claim 1, wherein: The semiconductor substrate is doped with a well region, and the type of impurity ions of the well region is opposite to that of the source region and the bit line doping region.

13. A memory device formed by the method of any one of claims 1-12, comprising: A semiconductor substrate having a plurality of active regions therein, the plurality of active regions being separated by a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction, the first trenches being in communication with the corresponding second trenches; A third trench extending in the first direction in the semiconductor substrate at the bottom of the first trench, the width of the third trench being smaller than the width of the bottom of the first trench; A bit line doping region in the semiconductor substrate at both sides of the third trench and the bottom of the first trench; A gate dielectric layer on the sidewall surface of the first trench and the second trench; A first dielectric layer filling the third trench; A metal gate in the first trench on the first dielectric layer and in the second trench, the top surface of the metal gate being lower than the top surface of the active region, and the metal gate in the second trench being broken in the second direction; A second dielectric layer filling the first trench and the second trench on the metal gate; A source region on the top surface of the active region; A capacitor connected with the source region on the surface of the semiconductor substrate.

14. The memory device of claim 13, wherein: The plurality of active regions are arranged in rows and columns.

15. The memory device of claim 13, wherein: The width of the third trench is 3 / 4-1 / 4 of the width of the bottom of the first trench.

16. The memory device of claim 13, wherein: The impurity ions doped in the bit line doping region are N-type impurity ions or P-type impurity ions.

17. The memory device of claim 16, wherein: The type of impurity ions doped in the source region is the same as that of the bit line doping region.

18. The memory device of claim 13, further comprising: A third dielectric layer on the active region and the second dielectric layer, the third dielectric layer having a contact plug connected with the source region therein; A fourth dielectric layer on the third dielectric layer, the fourth dielectric layer having a capacitor hole exposing the contact plug therein, and the capacitor being in the capacitor hole.

19. The memory device of claim 13, wherein: ​ ​ The material of the metal gate is one or more of W, Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, WN, WSi.

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