A pure hardware-based rotary transformer signal conditioning circuit and conditioning method

Abstract

This invention belongs to the field of resolver signal processing technology, specifically relating to a pure hardware resolver signal conditioning circuit and method; the resolver decoding circuit includes a sine excitation circuit, a synchronous demodulation circuit, a first n-bit multiplicative D / A circuit, a second n-bit multiplicative D / A circuit, a subtraction circuit, a hysteresis comparator (DOWN counter), a hysteresis comparator (UP counter), an n-bit counter, a clock unit, an n-bit sine LUT lookup table logic, and an n-bit cosine LUT lookup table logic; when the subtraction circuit output voltage is 0, θ D The angle information of the rotary transformer is calculated by approximating θ, without the need for complex calculations such as arctangent. The principle is simple and the cost is low.

Description

Technical Field

[0001] This invention belongs to the field of rotary transformer signal processing technology, specifically relating to a pure hardware rotary transformer signal conditioning circuit and conditioning method. Background Technology

[0002] Rotary transformers are characterized by high precision, good stability, and strong resistance to shock and interference. They are widely used as fuel metering sensors in FADEC systems for aero engines, such as the CFM56-7 (used in B737-600 / 700 / 800 aircraft) and V2500 (used in A320 and MD-90 aircraft). Accurate fuel flow acquisition is fundamental to controlling aero engines during start-up, acceleration, deceleration, and cruise. FADEC systems have high precision requirements for the angle signal acquisition from the rotary transformer. Currently, the rotary transformer conditioning circuit mainly uses dedicated RDC conditioning integrated chips, which offer high speed and precision, but are expensive. However, this requires designing the interface circuit between the rotary transformer and the RDC chip. This interface circuit includes operational amplifiers, resistors, capacitors, and diodes, which typically exhibit errors such as temperature drift. Furthermore, the parameters of these components change over time, affecting the accuracy of the rotary transformer angle acquisition. Summary of the Invention

[0003] In view of this, the present invention provides a pure hardware resolver signal conditioning circuit, studies the characteristics of the resolver output signal, and designs a pure hardware resolver decoding circuit based on this, which greatly reduces the number of interface circuit components.

[0004] To achieve the above-mentioned technical objectives, the specific technical solution adopted by the present invention is as follows:

[0005] A pure hardware rotary transformer decoding circuit, characterized in that it includes a sine excitation circuit, a synchronous demodulation circuit, a first n-bit multiplicative D / A circuit, a second n-bit multiplicative D / A circuit, a subtraction circuit, a counter DOWN hysteresis comparator, a counter UP hysteresis comparator, an n-bit counter, a clock unit, an n-bit sine LUT lookup table logic, and an n-bit cosine LUT lookup table logic.

[0006] The sinusoidal excitation circuit provides a standard sinusoidal excitation drive V for the rotary transformer. REF And provides a demodulation control signal V to the synchronous demodulation circuit. DEMU The synchronous demodulation circuit has two input terminals connected to the sinusoidal feedback signal VS and the cosine feedback signal VC of the rotary transformer, respectively. The sinusoidal feedback signal VS is demodulated to obtain the modulation signal V. SIN(θ) The cosine feedback signal VC is demodulated to obtain the modulated signal V. COS(θ) VSIN(θ) and V COS(θ) The circuit is connected to the reference terminals of the multiplication D / A circuit and the second n-bit multiplication D / A circuit, respectively. The output terminal of the first n-bit multiplication D / A circuit is connected to the non-inverting input terminal of the subtraction circuit, and the output terminal of the second n-bit multiplication D / A circuit is connected to the inverting input terminal of the subtraction circuit. The output terminal of the subtraction circuit is simultaneously connected to the input terminals of the DOWN hysteresis comparator and the UP hysteresis comparator. The output terminal of the DOWN hysteresis comparator is connected to the DOWN control terminal of the n-bit counter, the UP hysteresis comparator is connected to the UP control terminal of the n-bit counter, and the clock unit output terminal is connected to the CLK control terminal of the n-bit counter. The counter outputs a count value CNT that is simultaneously connected to both the cosine LUT lookup table logic and the sine LUT lookup table logic. The output of the cosine LUT lookup table logic is connected to the data input of the first n-bit multiplicative D / A circuit, and the output of the sine LUT lookup table logic is connected to the data input of the second n-bit multiplicative D / A circuit. The count value output by the n-bit counter is the digital decoding result of the resolver angle.

[0007] Furthermore, the sinusoidal excitation circuit outputs a standard sinusoidal signal V with driving capability. REF =U0*SIN(ωt), when the sinusoidal excitation signal V REF When the voltage reaches U0, the demodulation control signal V DEMU It will output a short-duration high pulse.

[0008] Furthermore, the synchronous demodulation circuit includes a first sample-and-hold S / H circuit and a second sample-and-hold S / H circuit; both the first sample-and-hold S / H circuit and the second sample-and-hold S / H circuit operate on the demodulation control signal V. DEMU Sampling begins at the rising edge, and the circuit remains in a hold state at all other times. The input of the first sample-and-hold S / H circuit is connected to VS, and the input of the second sample-and-hold S / H circuit is connected to VC. The control terminals of both the first and second sample-and-hold S / H circuits are simultaneously connected to the demodulation control signal V. DEMU Connected; the first sample-and-hold S / H circuit and the sample-and-hold circuit, the output of the first sample-and-hold S / H circuit is the modulation signal V of VS. SIN The output of the second sample-and-hold S / H circuit is the modulated signal V of VC. COS .

[0009] Furthermore, the range of the n-bit counter value CNT is 0 to 2. n -1; CNT and rotary transformer decoding angle θ DA linear relationship exists; when the value CNT of the n-bit counter is 0, it corresponds to the angle θ of the rotary transformer. D -90°; when the value of the n-bit counter CNT is 2 n When -1 corresponds to the angle θ of the rotary transformer D It is 90°.

[0010] Furthermore, the logic input of the n-bit cosine LUT lookup table is the count value CNT of the n-bit counter, and the logic output of the n-bit cosine LUT lookup table is D. cos =round[(2 n -1)*cos(θ D The logic input of the n-bit sine LUT lookup table is the count value of the n-bit counter, and the logic output of the n-bit sine LUT lookup table is D. sin =round[(2 n -1) / 2*sin(θ D )+(2 n -1) / 2].

[0011] Furthermore, the output voltage of the first n-bit multiplicative D / A circuit is V. OUT1 =[(D cos -2 n-1 ) / 2 n-1 ]*V SIN The output voltage of the second n-bit multiplication type D / A circuit is V. OUT2 =[(D sin -2 n-1 ) / 2 n-1 ]*V COS .

[0012] Furthermore, the input voltage of the counter UP hysteresis comparator is in [0, V]. TH When the input voltage changes, the output level of the counter UP hysteresis comparator remains unchanged; when the input voltage is less than 0, the counter UP hysteresis comparator outputs a logic high level; when the input voltage is greater than V... TH When this occurs, the UP counter hysteresis comparator outputs a logic low level.

[0013] Furthermore, the input voltage of the counter DOWN hysteresis comparator is in [-V TH When the input voltage changes within the range of 0, the output level of the counter DOWN hysteresis comparator remains unchanged; when the input voltage is greater than 0, the output level of the counter UP hysteresis comparator is logic high; when the input voltage is less than -V... TH When this occurs, the UP counter hysteresis comparator outputs a logic low level.

[0014] Furthermore, the count value of the n-bit counter follows the following rule:

[0015] Rule 1: When the UP input of the n-bit counter is at a logic high level and the DOWN input of the n-bit counter is at a logic low level, and a rising edge occurs at the CLK input of the n-bit counter, the count value of the n-bit counter is decremented by 1;

[0016] Rule 2: When the UP input of the n-bit counter is at a logic low level and the DOWN input of the n-bit counter is at a logic high level, and a rising edge occurs at the CLK input of the n-bit counter, the count value of the n-bit counter is incremented by 1;

[0017] Rule 3: When the logic level state of the UP input terminal of the n-bit counter is the same as the logic level state of the DOWN input terminal of the n-bit counter, the count value of the n-bit counter remains unchanged.

[0018] This invention also proposes a pure hardware resolver signal conditioning method based on the above-mentioned pure hardware resolver decoding circuit, comprising the following steps:

[0019] Step 1: The sinusoidal excitation circuit outputs a standard sinusoidal signal V with driving capability. REF Applied to a rotary transformer, and in a standard sinusoidal signal V REF When the voltage reaches its positive peak, the demodulation control signal V is set... DEMU Output a short-time pulse signal;

[0020] Step 2: When a sinusoidal excitation is applied to the rotary transformer, the sinusoidal feedback signal VS and the cosine feedback signal VC output by the rotary transformer are connected to the synchronous demodulation circuit to obtain the modulation signal V. SIN(θ) and V COS(θ) ;

[0021] Step 3: When the decoding angle θ output by the n-bit counter... D When the angle is greater than the actual angle θ of the rotary transformer, the output voltage of the subtraction circuit is less than -V. TH When the counter DOWN hysteresis comparator outputs a low logic level and the counter UP hysteresis comparator outputs a high logic level, the count value of the n-bit counter decreases until the output voltage of the subtraction circuit is greater than 0. Afterward, the counter DOWN hysteresis comparator outputs a high logic level and the counter UP hysteresis comparator outputs a high logic level, and the count value remains unchanged. At this point, θ... D It is approximately equal to θ;

[0022] When the decoding angle θ output by the n-bit counter D When the angle is less than the true angle θ of the rotary transformer, the output voltage of the subtraction circuit is greater than V. THWhen the counter DOWN hysteresis comparator outputs a high logic level and the counter UP hysteresis comparator outputs a low logic level, the count value of the n-bit counter increases until the output voltage of the subtraction circuit is less than 0. Afterward, when both the counter DOWN and counter UP output high logic levels, the count value remains unchanged. At this point, θ... D It is approximately equal to θ.

[0023] The beneficial effects of this invention are:

[0024] 1. This invention achieves signal decoding of the rotary transformer using only components such as counters and multiplicative D / A chips. The principle is simple and the cost is low. Furthermore, it can obtain the digital decoding result of the rotary transformer angle without complex calculations such as A / D conversion and arctangent.

[0025] 2. This invention provides a purely hardware solution for decoding rotary transformers, and its accuracy can reach 0.2% as verified by actual products.

[0026] 3. The pure hardware-based rotary transformer decoding circuit and method of this invention has been applied to the FADEC control system of multiple types of aero-engines. It has undergone various system tests and aircraft installation verifications. The system operates stably and reliably and can accurately collect the position information of the rotary transformer. The proposed decoding method ensures the real-time performance of the system. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a functional principle block diagram of a purely hardware-based rotary transformer conditioning circuit according to a specific embodiment of the present invention.

[0029] Figure 2 This is a block diagram of the synchronous demodulation circuit in a specific embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the counter UP hysteresis comparator circuit in a specific embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the counter DOWN hysteresis comparator circuit in a specific embodiment of the present invention. Detailed Implementation

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0033] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0034] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0035] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0037] In one embodiment of the present invention, a pure hardware rotary transformer decoding circuit is proposed, including a sine excitation circuit, a synchronous demodulation circuit, a first n-bit multiplicative D / A circuit, a second n-bit multiplicative D / A circuit, a subtraction circuit, a counter DOWN hysteresis comparator, a counter UP hysteresis comparator, an n-bit counter, a clock unit, an n-bit sine LUT lookup table logic, and an n-bit cosine LUT lookup table logic;

[0038] The sinusoidal excitation circuit provides a standard sinusoidal excitation drive V for the rotary transformer. REFAnd provides demodulation control signal V for the synchronous demodulation circuit. DEMU The two input terminals of the synchronous demodulation circuit are connected to the sinusoidal feedback signal VS and the cosine feedback signal VC of the rotary transformer, respectively. After demodulation, the sinusoidal feedback signal VS is used to obtain the modulated signal V. SIN(θ) The cosine feedback signal VC is demodulated to obtain the modulated signal V. COS(θ) V SIN(θ) and V COS(θ) The circuit is connected to the reference terminals of the multiplication-type D / A circuit and the second n-bit multiplication-type D / A circuit, respectively. The output terminal of the first n-bit multiplication-type D / A circuit is connected to the non-inverting input terminal of the subtraction circuit, and the output terminal of the second n-bit multiplication-type D / A circuit is connected to the inverting input terminal of the subtraction circuit. The output terminal of the subtraction circuit is simultaneously connected to the input terminals of the DOWN hysteresis comparator and the UP hysteresis comparator. The output terminal of the DOWN hysteresis comparator is connected to the control terminal of the n-bit counter DOWN, and the output terminal of the UP hysteresis comparator is connected to the control terminal of the n-bit counter UP. The clock unit output terminal is connected to the control terminal of the n-bit counter CLK. The counter output value CNT is simultaneously connected to the cosine LUT lookup table logic and the sine LUT lookup table logic. The output terminal of the cosine LUT lookup table logic is connected to the data input terminal of the first n-bit multiplication-type D / A circuit, and the output terminal of the sine LUT lookup table logic is connected to the data input terminal of the second n-bit multiplication-type D / A circuit. The count value output by the n-bit counter is the digital decoding result of the resolver angle.

[0039] In this embodiment, the sinusoidal excitation circuit outputs a standard sinusoidal signal V with driving capability. REF =U0*SIN(ωt), when the sinusoidal excitation signal V REF When the voltage reaches U0, the demodulation control signal V DEMU It will output a short-duration high pulse.

[0040] In this embodiment, the synchronous demodulation circuit includes a first sample-and-hold S / H circuit and a second sample-and-hold S / H circuit; both the first sample-and-hold S / H circuit and the second sample-and-hold S / H circuit operate in response to the demodulation control signal V. DEMU Sampling begins at the rising edge of the signal and remains in a hold state at all other times. The input of the first sample-and-hold S / H circuit is connected to VS, and the input of the second sample-and-hold S / H circuit is connected to VC. The control terminals of the first and second sample-and-hold S / H circuits are simultaneously connected to the demodulation control signal V. DEMU Connected; the first sample-and-hold S / H circuit and the sample-and-hold circuit. The output of the first sample-and-hold S / H circuit is the modulation signal V of VS. SIN The output of the second sample-and-hold S / H circuit is the modulated signal V of VC. COS .

[0041] In this embodiment, the count value CNT of the n-bit counter varies from 0 to 2. n -1; CNT and rotary transformer decoding angle θ D A linear relationship exists; when the value of the n-bit counter CNT is 0, it corresponds to the angle θ of the rotary transformer. D -90°; when the value of the n-bit counter CNT is 2 n When -1 corresponds to the angle θ of the rotary transformer D It is 90°.

[0042] In this embodiment, the logic input of the n-bit cosine LUT lookup table is the count value CNT of an n-bit counter, and the logic output of the n-bit cosine LUT lookup table is D. cos =round[(2 n -1)*cos(θ D The logic input of the n-bit sine LUT lookup table is the count value of an n-bit counter, and the logic output of the n-bit sine LUT lookup table is D. sin =round[(2 n -1) / 2*sin(θ D )+(2 n -1) / 2].

[0043] In this embodiment, the output voltage of the first n-bit multiplicative D / A circuit is V. OUT1 =[(D cos -2 n-1 ) / 2 n-1 ]*V SIN The output voltage of the second n-bit multiplicative D / A circuit is V. OUT2 =[(D sin -2 n-1 ) / 2 n-1 ]*V COS .

[0044] In this embodiment, the input voltage of the counter UP hysteresis comparator is in the range [0, V]. TH When the input voltage changes, the output level of the counter UP hysteresis comparator remains unchanged; when the input voltage is less than 0, the counter UP hysteresis comparator outputs a logic high level; when the input voltage is greater than V... TH When the counter UP hysteresis comparator outputs a logic low level.

[0045] In this embodiment, the input voltage of the DOWN hysteresis comparator is in the range of [-V]. TH When the input voltage changes within the range of 0, the output level of the hysteresis comparator DOWN remains unchanged; when the input voltage is greater than 0, the output level of the hysteresis comparator UP is logic high; when the input voltage is less than -V... TH When the counter UP hysteresis comparator outputs a logic low level.

[0046] In this embodiment, the count value of the n-bit counter follows the following rules:

[0047] Rule 1: When the UP input of the n-bit counter is at logic high level and the DOWN input of the n-bit counter is at logic low level, and a rising edge occurs at the CLK input of the n-bit counter, the count value of the n-bit counter is decremented by 1.

[0048] Rule 2: When the UP input of the n-bit counter is at logic low and the DOWN input of the n-bit counter is at logic high, and a rising edge occurs at the CLK input of the n-bit counter, the count value of the n-bit counter is incremented by 1;

[0049] Rule 3: When the logic level state of the UP input terminal of the n-bit counter is the same as the logic level state of the DOWN input terminal of the n-bit counter, the count value of the n-bit counter remains unchanged.

[0050] Based on the same inventive concept, in one embodiment, the present invention also proposes a pure hardware rotary transformer signal conditioning method based on the above-mentioned pure hardware rotary transformer decoding circuit, comprising the following steps:

[0051] Step 1: The sinusoidal excitation circuit outputs a standard sinusoidal signal V with driving capability. REF Applied to a rotary transformer, and in a standard sinusoidal signal V REF When the voltage reaches its positive peak, the demodulation control signal V is set... DEMU Output a short-time pulse signal;

[0052] Step 2: When a sinusoidal excitation is applied to the rotary transformer, the sinusoidal feedback signal VS and the cosine feedback signal VC output by the rotary transformer are connected to the synchronous demodulation circuit to obtain the modulation signal V. SIN(θ) and V COS(θ) ;

[0053] Step 3: When the decoding angle θ output by the n-bit counter... D When the angle is greater than the actual angle θ of the rotary transformer, the output voltage of the subtraction circuit is less than -V. TH When the counter DOWN hysteresis comparator outputs a low logic level and the counter UP hysteresis comparator outputs a high logic level, the count value of the n-bit counter decreases until the output voltage of the subtraction circuit is greater than 0. Afterward, the counter DOWN hysteresis comparator outputs a high logic level and the counter UP hysteresis comparator outputs a high logic level, and the count value remains unchanged. At this point, θ... D It is approximately equal to θ;

[0054] When the decoding angle θ output by the n-bit counter D When the angle is less than the true angle θ of the rotary transformer, the output voltage of the subtraction circuit is greater than V. THWhen the counter DOWN hysteresis comparator outputs a high logic level and the counter UP hysteresis comparator outputs a low logic level, the count value of the n-bit counter increases until the output voltage of the subtraction circuit is less than 0. Afterward, when both the counter DOWN and counter UP output high logic levels, the count value remains unchanged. At this point, θ... D It is approximately equal to θ.

[0055] The following describes a rotary transformer with an excitation frequency requirement of 3500Hz±50Hz, an amplitude requirement of 7.07Vrms±0.14Vrms, a primary coil DC impedance of 56Ω±5.6Ω, and a conversion factor T. R The above embodiments are further explained by the values ​​of 0.492 ± 0.025 and the rotation angle θ ranging from -33.2° to 85.5°.

[0056] The circuit diagram of the rotary transformer signal conditioning circuit in the above embodiment is shown below. Figure 1 As shown, the circuit mainly includes a sinusoidal excitation circuit, a synchronous demodulation circuit, a 12-bit first n-bit multiplication type D / A circuit, a 12-bit second n-bit multiplication type D / A circuit, a subtraction circuit, a counter DOWN hysteresis comparator, a counter UP hysteresis comparator, a 12-bit counter, a clock unit, a 12-bit sine LUT lookup table logic, and a 12-bit cosine LUT lookup table logic;

[0057] The sinusoidal excitation circuit provides a standard sinusoidal excitation drive V for the rotary transformer. REF =10V*SIN(ωt), and when the sinusoidal excitation signal V REF When the voltage reaches the positive peak value of 10V, the sinusoidal excitation circuit causes the demodulation control signal V to... DEMU It will output a high pulse with a width of 10µs. When the angle of the rotary transformer is θ, the sinusoidal excitation signal V REF When applied to the resolver, the sinusoidal feedback signal VS of the resolver's secondary winding is 10V*T. R *SIN(ωt)*SIN(θ), the cosine feedback signal of the secondary winding of the rotary transformer, VC = 10V*T R *SIN(ωt)*COS(θ).

[0058] The synchronous demodulation circuit includes a first sample-and-hold (S / H) circuit (S / H circuit 1 shown in the figure) and a second sample-and-hold (S / H) circuit (S / H circuit 2 shown in the figure). Both the first and second sample-and-hold S / H circuits operate on the demodulation control signal V. DEMUSampling begins at the rising edge, and the circuit remains in a hold state at all other times. The input of the first sample-and-hold S / H circuit is connected to the sinusoidal feedback signal VS, and the input of the second sample-and-hold S / H circuit is connected to the cosine feedback signal VC. Therefore, the modulated signal V output by the first sample-and-hold S / H circuit is VS modulated by the following signal: SIN =10V*T R *SIN(θ), the VC modulated signal V output by the second sample-and-hold S / H circuit. COS =10V*T R *COS(θ).

[0059] V SIN and V COS The circuit is connected to the voltage reference terminals of the first and second n-bit multiplication D / A circuits, respectively. The output of the first n-bit multiplication D / A circuit is connected to the non-inverting input of the subtraction circuit, and the output of the second n-bit multiplication D / A circuit is connected to the inverting input of the subtraction circuit. The output of the subtraction circuit is simultaneously connected to the inputs of the DOWN hysteresis comparator and the UP hysteresis comparator of the counter. The output of the DOWN hysteresis comparator is connected to the DOWN control terminal of the 12-bit counter, and the output of the UP hysteresis comparator is connected to the UP control terminal of the 12-bit counter. The clock unit output is connected to the CLK control terminal of the 12-bit counter. The counter output value CNT is simultaneously connected to the cosine LUT lookup table logic and the sine LUT lookup table logic. The output of the cosine LUT lookup table logic is connected to the data input terminal of the first n-bit multiplication D / A circuit, and the output of the sine LUT lookup table logic is connected to the data input terminal of the second n-bit multiplication D / A circuit. The count value CNT output by the 12-bit counter is the decoded angle θ of the rotary transformer. D The specific conversion relationship is as follows:

[0060] θ D = (CNT-2048) / 2048*90°.

[0061] The logic input of the 12-bit cosine LUT lookup table is the count value CNT of a 12-bit counter, and the logic output is D. cos =round[4095 / 2*cos(θ)] D )+4095 / 2], that is, when θ D When D = ±90°, cos ＝ 2048; when θ D When = 0°, D cos ＝ 4095; The logic input of the 12-bit sine LUT lookup table is the count value CNT of a 12-bit counter, and the logic output of the 12-bit sine LUT lookup table is...

[0062] Dsin =round[4095 / 2*sin(θ)] D )+4095 / 2], that is, when θ D When D = -90°, sin ＝ 0; when θ D When D = +90°, sin ＝ 4095.

[0063] The output voltage of the 12-bit first n-bit multiplication type D / A circuit is V. OUT1 =V SIN *[(D cos -2048) /

[0064] 2048]; Specifically as follows: when θ D When V = 0, OUT1 =V SIN *1=10V*T R *SIN(θ)*COS(θ D ); when θ D When V = 90°, OUT1 =V SIN *0 = 10V*T R *SIN(θ)*COS(θ D ), then V OUT1 =10V*T R *

[0065] SIN(θ)*COS(θ D The output voltage of the 12-bit second n-bit multiplication type D / A circuit is V. OUT2 =V COS *

[0066] [(D sin -2048) / 2048]; specifically as follows: when θ D When V = -90°, OUT2 =V COS *(-1)=

[0067] 10V*T R *COS(θ)*SIN(θ D ); when θ D When V = 90°, OUT2 =V COS *1=10V*T R *

[0068] COS(θ)*SIN(θ D ), then V OUT2 =10V*T R *COS(θ)*SIN(θ DThe subtraction circuit output voltage V OUT =V OUT1 -V OUT2 =10V*T R *SIN(θ-θ D This is represented as the decoding angle θ. D The deviation from the actual angle θ of the rotary transformer.

[0069] In this example, the schematic diagram of the counter UP hysteresis comparator circuit is as follows: Figure 3 As shown, the circuit includes resistors R1 and R2, a positive feedback resistor R3, a pull-up resistor R4, and a voltage comparator U1. The output of the error detection circuit is connected to one end of resistor R2, and the other end of resistor R2 is connected to the inverting input of voltage comparator U1. One end of resistor R1 is connected to reference ground GND. The non-inverting input of voltage comparator U1 is connected to both the other end of resistor R1 and one end of the positive feedback resistor R3. The output of voltage comparator U1 is connected to both the other end of the positive feedback resistor R3 and the pull-up resistor R4. The other end of the pull-up resistor R4 is connected to the power supply VCC. Based on the operating characteristics of voltage comparator U1, it can be theoretically calculated that when the input voltage V... OUT The output voltage of voltage comparator U1 remains constant when the input voltage V varies within the range [0, VCC·R1 / (R1+R3+R4)]. OUT When the input voltage V is less than 0, the voltage comparator U1 outputs a logic high level. OUT When the voltage is greater than VCC·R1 / (R1+R3+R4), the voltage comparator U1 outputs a logic low level.

[0070] The schematic diagram of the DOWN counter hysteresis comparator circuit in this example is as follows: Figure 4 As shown, the circuit includes resistors R5 and R6, a positive feedback resistor R7, a pull-up resistor R8, and a voltage comparator U2. The output of the error detection circuit is connected to one end of resistor R5. The non-inverting input of voltage comparator U1 is connected to both the other end of resistor R5 and one end of the positive feedback resistor R7. One end of resistor R6 is connected to reference ground GND, and the other end of resistor R6 is connected to the inverting input of voltage comparator U2. The output of voltage comparator U2 is connected to both the other end of the positive feedback resistor R7 and the pull-up resistor R8. The other end of the pull-up resistor R8 is connected to the power supply VCC. Based on the operating characteristics of voltage comparator U2, it can be theoretically calculated that when the input voltage V... OUT The output voltage of voltage comparator U2 remains constant when the input voltage V varies within the range of [-VCC·R5 / (R7+R8), 0]. OUT When the voltage is greater than the reference ground (GND) level, voltage comparator U1 outputs a logic high level. When the input voltage V... OUT When the voltage is less than -VCC·R5 / (R7+R8), the voltage comparator U2 outputs a logic low level.

[0071] In this example, the threshold voltage V TH =0.01V, VCC voltage is +5V, then in the selector counter UP hysteresis comparator circuit R1=2KΩ, R3=1MΩ, R4=1KΩ, then VCC·R1 / (R1+R3+R4)≈0.01V; in the selector counter DOWN hysteresis comparator circuit R5=2KΩ, R7=1MΩ, R8=1KΩ, then VCC·R5 / (R7+R8)≈0.01V.

[0072] The count value of the above 12-bit counter must follow the following rules:

[0073] Rule 1: When the UP input of the 12-bit counter is at logic high level and the DOWN input of the 12-bit counter is at logic low level, and a rising edge occurs at the CLK input of the 12-bit counter (clock frequency is 500KHz in this example), the count value of the 12-bit counter is decremented by 1.

[0074] Rule 2: When the UP input of the 12-bit counter is at logic low and the DOWN input of the 12-bit counter is at logic high, and a rising edge occurs at the CLK input of the 12-bit counter, the count value of the 12-bit counter is incremented by 1.

[0075] Rule 3: When the logic level of the UP input of a 12-bit counter is the same as the logic level of the DOWN input of a 12-bit counter, the count value of the 12-bit counter remains unchanged.

[0076] The specific working process of the purely hardware-based rotary transformer decoding circuit in this example includes the following steps:

[0077] Step 1: The sinusoidal excitation circuit outputs a standard sinusoidal signal V with driving capability. REF Applied to a rotary transformer, and in a standard sinusoidal signal V REF When the voltage reaches its positive peak value, it also causes the demodulation control signal V to... DEMU Output a short-time pulse signal;

[0078] Step 2: A sinusoidal excitation is applied to the rotary transformer. The sinusoidal feedback signal VS and the cosine feedback signal VC output by the rotary transformer are then connected to the synchronous demodulation circuit to obtain the modulation signal V. SIN and V COS ;

[0079] Step 3: As can be seen from the above analysis, the output voltage of the subtraction circuit is represented by the decoding angle θ. D The deviation from the actual angle θ of the rotary transformer. When the decoded angle θ is output by the 12-bit counter. D When the angle is greater than the actual angle θ of the rotary transformer, the output voltage V of the subtraction circuit is... OUTWhen the voltage is less than -1mV, the hysteresis comparator outputs a low logic level when the counter is down and a high logic level when the counter is up; the counter value will then decrease until the output voltage V of the subtraction circuit is reached. OUT Greater than 0; at this time V OUT =10V*T R *SIN(θ-θ D If the value is in the range [0, 0.01V], then 0 < θ - θ D <0.11°;

[0080] Step 4: When the decoding angle θ output by the 12-bit counter... D When the voltage is less than the actual angle θ of the rotary transformer, the output voltage of the subtraction circuit is greater than 1mV. The DOWN hysteresis comparator of the counter outputs a logic high level, and the UP hysteresis comparator outputs a logic low level. The count value of the 12-bit counter increases until the output voltage of the subtraction circuit is less than 0. When both the DOWN and UP hysteresis comparators output a logic high level, the count value remains unchanged. At this point, θ... D It is approximately equal to θ. At this time, V OUT =10V*T R *SIN(θ-θ D If the value is in the range [-0.01V, 0], then -0.11° < θ - θ D <0.

[0081] In summary, considering the errors caused by the D / A chip and the subtraction circuit, the maximum error of this conditioning circuit will not exceed ±0.2°, which is consistent with the measured results.

[0082] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pure hardware rotary transformer decoding circuit, characterized in that: It includes a sine excitation circuit, a synchronous demodulation circuit, a first n-bit multiplicative D / A circuit, a second n-bit multiplicative D / A circuit, a subtraction circuit, a counter DOWN hysteresis comparator, a counter UP hysteresis comparator, an n-bit counter, a clock unit, an n-bit sine LUT lookup table logic, and an n-bit cosine LUT lookup table logic; The sinusoidal excitation circuit provides standard sinusoidal excitation drive for the rotary transformer. V REF And provide demodulation control signals for the synchronous demodulation circuit. V DEMU The two input terminals of the synchronous demodulation circuit are respectively connected to the sinusoidal feedback signal VS and the cosine feedback signal VC of the rotary transformer. The sinusoidal feedback signal VS is demodulated to obtain the modulated signal. V SIN(θ) The cosine feedback signal VC is demodulated to obtain the modulated signal. V COS(θ) ; V SIN(θ) and V COS(θ) The circuit is connected to the reference terminals of the first n-bit multiplication D / A circuit and the second n-bit multiplication D / A circuit, respectively. The output terminal of the first n-bit multiplication D / A circuit is connected to the non-inverting input terminal of the subtraction circuit, and the output terminal of the second n-bit multiplication D / A circuit is connected to the inverting input terminal of the subtraction circuit. The output terminal of the subtraction circuit is simultaneously connected to the input terminals of the DOWN hysteresis comparator and the UP hysteresis comparator. The output terminal of the DOWN hysteresis comparator is connected to the DOWN control terminal of the n-bit counter, the UP hysteresis comparator is connected to the UP control terminal of the n-bit counter, and the clock unit output terminal is connected to the CLK control terminal of the n-bit counter. The output value CNT of the n-bit counter is simultaneously connected to both the n-bit cosine LUT lookup table logic and the n-bit sine LUT lookup table logic. The output of the n-bit cosine LUT lookup table logic is connected to the data input of the first n-bit multiplicative D / A circuit, and the output of the n-bit sine LUT lookup table logic is connected to the data input of the second n-bit multiplicative D / A circuit. The count value output by the n-bit counter is the digital decoding result of the resolver angle. The input voltage of the counter UP hysteresis comparator is in [0, V]. TH When the range changes, the output level of the counter UP hysteresis comparator remains unchanged; When the input voltage is less than 0, the counter UP hysteresis comparator outputs a logic high level; when the input voltage is greater than V... TH When the counter UP hysteresis comparator outputs a logic low level; The input voltage of the counter DOWN hysteresis comparator is in [-V] TH When the input voltage changes within the range of 0, the output level of the counter DOWN hysteresis comparator remains unchanged; when the input voltage is greater than 0, the output level of the counter UP hysteresis comparator is logic high; when the input voltage is less than -V... TH When the counter UP hysteresis comparator outputs a logic low level; The count value of the n-bit counter follows the following rules: Rule 1: When the UP input of the n-bit counter is at a logic high level and the DOWN input of the n-bit counter is at a logic low level, and a rising edge occurs at the CLK input of the n-bit counter, the count value of the n-bit counter is decremented by 1; Rule 2: When the UP input of the n-bit counter is at a logic low level and the DOWN input of the n-bit counter is at a logic high level, and a rising edge occurs at the CLK input of the n-bit counter, the count value of the n-bit counter is incremented by 1; Rule 3: When the logic level state of the UP input terminal of the n-bit counter is the same as the logic level state of the DOWN input terminal of the n-bit counter, the count value of the n-bit counter remains unchanged.

2. The pure hardware rotary transformer decoding circuit according to claim 1, characterized in that: The sinusoidal excitation circuit outputs a standard sinusoidal signal with driving capability. V REF =U0 SIN(ωt), when the sinusoidal excitation signal V REF When the voltage reaches U0, the demodulation control signal is activated. V DEMU It will output a short-duration high pulse.

3. The pure hardware rotary transformer decoding circuit according to claim 1, characterized in that: The synchronous demodulation circuit includes a first sample-and-hold S / H circuit and a second sample-and-hold S / H circuit; both the first sample-and-hold S / H circuit and the second sample-and-hold S / H circuit are in operation when the demodulation control signal is active. V DEMU Sampling begins at the rising edge, and the circuit remains in a hold state at all other times. The input of the first sample-and-hold S / H circuit is connected to VS, and the input of the second sample-and-hold S / H circuit is connected to VC. The control terminals of both the first and second sample-and-hold S / H circuits are simultaneously connected to the demodulation control signal. V DEMU Connected; the output of the first sample-and-hold S / H circuit is the modulated signal of VS. V SIN The output of the second sample-and-hold S / H circuit is a modulated signal of VC. V COS .

4. The pure hardware rotary transformer decoding circuit according to claim 1, characterized in that: The count value CNT of the n-bit counter varies from 0 to 2. n -1; CNT and rotary transformer decoding angle θ D A linear relationship exists; when the value CNT of the n-bit counter is 0, it corresponds to the angle θ of the rotary transformer. D -90°; when the value of the n-bit counter CNT is 2 n When -1 corresponds to the angle θ of the rotary transformer D It is 90°.

5. The pure hardware rotary transformer decoding circuit according to claim 1, characterized in that: The logic input of the n-bit cosine LUT lookup table is the count value CNT of the n-bit counter, and the logic output of the n-bit cosine LUT lookup table is D. cos =round[(2 n -1) cos(θ D The logic input of the n-bit sine LUT lookup table is the count value of the n-bit counter, and the logic output of the n-bit sine LUT lookup table is D. sin =round[(2 n -1) / 2 sin(θ D ) + (2 n -1) / 2].

6. The pure hardware rotary transformer decoding circuit according to claim 1, characterized in that: The output voltage of the first n-bit multiplicative D / A circuit is V OUT1 =[(D cos -2 n-1 ) / 2 n-1 ] V SIN The output voltage of the second n-bit multiplication type D / A circuit is V. OUT2 =[(D sin -2 n-1 ) / 2 n-1 ] V COS .

7. A pure hardware resolver signal conditioning method based on the pure hardware resolver decoding circuit according to any one of claims 1-6, characterized in that, Includes the following steps: Step 1: The sinusoidal excitation circuit outputs a standard sinusoidal signal with driving capability. V REF Applied to a rotary transformer, and in the presence of a standard sinusoidal signal. V REF When the voltage reaches its positive peak, the demodulation control signal is activated. V DEMU Output a short-time pulse signal; Step 2: When a sinusoidal excitation is applied to the rotary transformer, the sinusoidal feedback signal VS and the cosine feedback signal VC output by the rotary transformer are connected to the synchronous demodulation circuit to obtain the modulation signals respectively. V SIN(θ) and V COS(θ) ; Step 3: When the decoding angle θ output by the n-bit counter... D When the angle is greater than the actual angle θ of the rotary transformer, the output voltage of the subtraction circuit is less than -V. TH When the counter DOWN hysteresis comparator outputs a low logic level and the counter UP hysteresis comparator outputs a high logic level, the count value of the n-bit counter decreases until the output voltage of the subtraction circuit is greater than 0. Afterward, the counter DOWN hysteresis comparator outputs a high logic level and the counter UP hysteresis comparator outputs a high logic level, and the count value remains unchanged. At this point, θ... D It is approximately equal to θ; When the decoding angle θ output by the n-bit counter D When the angle is less than the true angle θ of the rotary transformer, the output voltage of the subtraction circuit is greater than V. TH When the counter DOWN hysteresis comparator outputs a high logic level and the counter UP hysteresis comparator outputs a low logic level, the count value of the n-bit counter increases until the output voltage of the subtraction circuit is less than 0. Afterward, when both the counter DOWN and counter UP output high logic levels, the count value remains unchanged. At this point, θ... D It is approximately equal to θ.

Images