Display panel and electronic device

Abstract

The application provides a display panel and an electronic device. The display panel comprises a power supply circuit, a power management circuit, a delay circuit, a level shift circuit and a display circuit. The power supply circuit is configured to provide an input voltage rising from 0 volts for the power management circuit. The power management circuit generates a first voltage signal and a second voltage signal according to the input voltage, and transmits the first voltage signal to the level shift circuit and transmits the first voltage signal and the second voltage signal to the delay circuit. The delay circuit is configured to control the power-on timing of the second voltage signal transmitted to the level shift circuit to be later than the power-on timing of the first voltage signal transmitted to the level shift circuit according to the first voltage signal. The level shift circuit is configured to generate a driving signal according to the first voltage signal and the second voltage signal. By ensuring the timing of the voltage signal received by the level shift circuit is normal, the level shift circuit can normally generate a driving signal, and the normal display of the display panel is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and electronic equipment. BACKGROUND

[0002] Display technology has always been one of the important research directions in electronic equipment. At present, the demand for resolution and refresh rate of display panel in electronic equipment is increasing, which leads to excessive in-plane load of display panel. When the display panel starts at low voltage, that is, the power supply voltage gradually rises from 0 volts, the power management integrated circuit (PMIC) in the display panel is severely loaded, the power-on timing of two voltage signals generated by the PMIC is abnormal, and the level shift circuit in the display panel needs to generate gate IC in array (GIA) signals using the two voltage signals generated by the PMIC, which eventually leads to abnormal GIA signal waveform output by the level shift circuit, and the display panel cannot display normally. SUMMARY

[0003] The present application discloses a display panel, which can solve the technical problem of abnormal power-on timing of two voltage signals received by the level shift circuit, resulting in abnormal GIA signal waveform output by the level shift circuit, and the display panel cannot display normally.

[0004] In a first aspect, the present application provides a display panel, which comprises a power supply circuit, a power management circuit, a delay circuit, a level shift circuit and a display circuit, the power supply circuit is electrically connected with the power management circuit, the power management circuit is electrically connected with the delay circuit and the level shift circuit, the level shift circuit is electrically connected with the display circuit, the power supply circuit is used for providing an input voltage rising from 0 volts for the power management circuit, the power management circuit generates a first voltage signal and a second voltage signal according to the input voltage, and transmits the first voltage signal to the level shift circuit and transmits the first voltage signal and the second voltage signal to the delay circuit, the delay circuit is used for controlling the power-on timing of the second voltage signal transmitted to the level shift circuit to be later than the first voltage signal according to the first voltage signal, the level shift circuit is used for generating a driving signal according to the first voltage signal and the second voltage signal, and the display circuit is used for receiving the driving signal to drive the display panel to display a picture.

[0005] The delay circuit is controlled by the first voltage signal, so that the second voltage signal is transmitted to the level shift circuit later than the first voltage signal in power-on timing, thereby ensuring the timing of the voltage signal received by the level shift circuit to be normal, so that the level shift circuit can normally generate the driving signal to realize normal display of the display panel.

[0006] Optionally, when the absolute value of the voltage value of the first voltage signal is greater than or equal to a preset voltage threshold, the delay circuit is turned on to make the second voltage signal start to be transmitted to the level shift circuit through the delay circuit.

[0007] Optionally, when the absolute value of the voltage value of the first voltage signal is greater than or equal to a first power-on threshold, the absolute value of the voltage value of the second voltage signal is less than a second power-on threshold within a preset time threshold, wherein the first power-on threshold is a voltage value at which the first voltage signal powers on the level shift circuit, and the second power-on threshold is a voltage value at which the second voltage signal powers on the level shift circuit; wherein the first power-on threshold is greater than the preset voltage threshold.

[0008] Optionally, the delay circuit comprises a switching unit, a first resistor and a second resistor, a control end of the switching unit is electrically connected to one end of the first resistor, and the first resistor receives the first voltage signal through the second resistor, a first end of the switching unit is electrically connected to the other end of the first resistor and is used to receive the second voltage signal, and a second end of the switching unit is electrically connected to the level shift circuit.

[0009] Optionally, the threshold voltage between the first end of the switching unit and the second end of the switching unit is:

[0010] V GS (th)=V G -V S =-1.14 volts;

[0011] wherein the switching unit is a PMOS transistor, V GS (th) is the threshold voltage of the switching unit, V G is the potential of the control end of the switching unit, V S is the potential of the first end of the switching unit.

[0012] Optionally, the ratio of the resistance values of the first resistor and the second resistor is:

[0013] R1: R2 = |V GS (th) | / [V VGH -(V1) ] = 0.0423;

[0014] Wherein, R1 is the resistance value of the first resistor, R2 is the resistance value of the second resistor, V VGH is the voltage value of the second voltage signal, and V1 is the preset voltage threshold value.

[0015] Optionally, the resistance value of the first resistor is 20 kilo-ohms, and the resistance value of the second resistor is 450 kilo-ohms.

[0016] Optionally, the delay circuit further comprises a voltage stabilizing capacitor, one end of the voltage stabilizing capacitor being electrically connected to the second end of the switch unit, and the other end of the voltage stabilizing capacitor being grounded.

[0017] Optionally, the delay circuit further comprises a third resistor and a fourth resistor, one end of the third resistor being electrically connected to the second end of the switch unit, and the other end of the third resistor being electrically connected to the level shift circuit; one end of the fourth resistor being electrically connected to the second end of the switch unit, and the other end of the fourth resistor being grounded.

[0018] In a second aspect, the present application further provides an electronic device, comprising a housing and the display panel as described in the first aspect, the housing being used to carry the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0020] Figure 1 A display panel frame schematic diagram provided by an embodiment of the present application.

[0021] Figure 2 A power-on timing waveform diagram of a level shift circuit provided by an embodiment of the present application.

[0022] Figure 3 A possible power-on timing waveform diagram in the related art.

[0023] Figure 4 A delay circuit schematic diagram provided by an embodiment of the present application.

[0024] Figure 5 A simulation signal waveform schematic diagram provided by an embodiment of the present application.

[0025] Figure 6 A top view schematic diagram of an electronic device provided by an embodiment of the present application.

[0026] Explanation of reference numerals: first voltage signal - VGL, second voltage signal - VGH, display panel - 1, power supply circuit - 11, power management circuit - 12, delay circuit - 13, switch unit - Q1, control end - g, first end - s, second end - d, first resistor - R1, second resistor - R2, voltage stabilizing capacitor C, third resistor - R3, fourth resistor - R4, level shift circuit - 14, display circuit - 15, electronic device - 2, shell - 21. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0028] The present application provides a display panel 1, please refer to Figure 1 , Figure 1 The present application provides a display panel frame diagram provided by an embodiment of the present application. The display panel 1 includes a power supply circuit 11, a power management circuit 12, a delay circuit 13, a level shift circuit 14 and a display circuit 15, the power supply circuit 11 is electrically connected with the power management circuit 12, the power management circuit 12 is electrically connected with the delay circuit 13 and the level shift circuit 14, the level shift circuit 14 is electrically connected with the display circuit 15, the power supply circuit 11 is used for providing the input voltage rising from 0 volts for the power management circuit 12, the power management circuit 12 generates the first voltage signal VGL and the second voltage signal VGH according to the input voltage, and transmits the first voltage signal VGL to the level shift circuit 14, and transmits the first voltage signal VGL and the second voltage signal VGH to the delay circuit 13, the delay circuit 13 is used for controlling the power-on timing of the second voltage signal VGH transmitted to the level shift circuit 14 to be later than the first voltage signal VGL according to the first voltage signal VGL, the level shift circuit 14 is used for generating a driving signal according to the first voltage signal VGL and the second voltage signal VGH, and the display circuit 15 is used for receiving the driving signal to drive the display panel 1 to display a picture.

[0029] It should be noted that low-voltage starting, i.e. the power supply circuit 11 is used to provide the power management circuit 12 with an input voltage rising from 0 volts, as a common, safe starting mode. Similarly, the absolute value of the voltage values of the first voltage signal VGL and the second voltage signal VGH generated by the power management circuit 12 is also gradually increasing until stable. With the increasing demand for resolution and refresh rate of the display panel 1, resulting in the in-plane load of the display panel 1 being too heavy, so that in low-voltage starting, the power management circuit 12 is seriously overloaded, and the power-on timing of the first voltage signal VGL and the second voltage signal VGH generated by the power management circuit 12 is abnormal.

[0030] For example, please refer to Figure 2 and Figure 3 , Figure 2 the power-on timing waveform diagram of the level shift circuit provided by an embodiment of the present application; Figure 3 is a possible power-on timing waveform diagram in the related art. The so-called power-on timing refers to the process of the first voltage signal VGL or the second voltage signal VGH being transmitted to the level shift circuit 14 and gradually decreasing or increasing to the power-on threshold voltage or power-off threshold required by the level shift circuit 14. As Figure 2 shown, where the abscissa is time and the ordinate is the voltage value of the voltage signal, under normal power-on conditions of the level shift circuit 14, the first voltage signal VGL reaches the power-on threshold voltage required by the level shift circuit 14 before the second voltage signal VGH. As Figure 3 shown, due to the low-voltage starting, the power management circuit 12 is overloaded, causing the voltage of the first voltage signal VGL to be pulled high and restarted. During the first power-on of the first voltage signal VGL, the first voltage signal VGL maintains the power-on threshold voltage for only 6-7 ms, while the voltage value of the second voltage signal VGH has risen to about 12 volts, reaching the power-on threshold voltage required by the level shift circuit 14, but the voltage of the first voltage signal VGL is then pulled high for up to 13 ms, and then the voltage of the first voltage signal VGL is pulled low again to the power-on threshold voltage, resulting in the power-on signal timing received by the level shift circuit 14 being: the first voltage signal VGL-the second voltage signal VGH-the first voltage signal VGL, while the level shift circuit 14 will default to receiving the power-on timing as the second voltage signal VGH-the first voltage signal VGL, which does not meet the power-on timing requirements of the level shift circuit 14, causing the drive signal generated by the level shift circuit 14 to be abnormal, ultimately resulting in abnormal display of the display circuit 15.

[0031] In the embodiment, the first voltage signal VGL is used as a control signal. After the voltage value of the first voltage signal VGL starts to decrease, the second voltage signal VGH is transmitted to the level shift circuit 14 through the delay circuit 13. Before the voltage value of the first voltage signal VGL reaches the power-on voltage threshold required by the level shift circuit 14, the voltage value of the second voltage signal VGH does not reach the power-on voltage threshold required by the level shift circuit 14. Thus, the power-on timing of the second voltage signal VGH transmitted to the level shift circuit 14 is later than that of the first voltage signal VGL, the power-on timing required by the level shift circuit 14 is achieved, and the level shift circuit 14 can generate the correct drive signal according to the first voltage signal VGL and the second voltage signal VGH.

[0032] It can be understood that, in the embodiment, the delay circuit 13 controls the power-on timing of the second voltage signal VGH transmitted to the level shift circuit 14 to be later than that of the first voltage signal VGL, so that the timing of the voltage signal received by the level shift circuit 14 is normal, and the level shift circuit 14 can normally generate the drive signal to achieve the normal display of the display panel 1.

[0033] In a possible implementation, when the absolute value of the voltage value of the first voltage signal VGL is greater than or equal to a preset voltage threshold, the delay circuit 13 is turned on to enable the second voltage signal VGH to be transmitted to the level shift circuit 14 through the delay circuit 13.

[0034] In the embodiment, the delay circuit 13 controls the conduction of the path between the second voltage signal VGH and the level shift circuit 14 according to the voltage value of the first voltage signal VGL, so that the voltage value of the first voltage signal VGL has decreased at least partially before the second voltage signal VGH is transmitted to the level shift circuit 14. Thus, the first voltage signal VGL reaches the power-on voltage threshold required by the level shift circuit 14 earlier than the second voltage signal VGH, the power-on timing of the second voltage signal VGH transmitted to the level shift circuit 14 is later than that of the first voltage signal VGL, the power-on timing required by the level shift circuit 14 is achieved, and the level shift circuit 14 can generate the correct drive signal according to the first voltage signal VGL and the second voltage signal VGH.

[0035] It can be understood that, since the delay circuit 13 only turns on the path between the second voltage signal VGH and the level shift circuit 14 when the absolute value of the voltage value of the first voltage signal VGL is greater than or equal to the preset voltage threshold, if the voltage value of the first voltage signal VGL is pulled up due to the serious load of the power management circuit 12, so that the absolute value of the voltage value of the first voltage signal VGL is less than the preset voltage threshold, the delay circuit 13 no longer turns on the path between the second voltage signal VGH and the level shift circuit 14, thereby avoiding the level shift circuit 14 from generating the driving signal according to the power-on timing of the first voltage signal VGL and the second voltage signal VGH, so as to avoid the false display of the display panel 1.

[0036] It can be understood that, in other possible embodiments, the delay circuit 13 can also make the power-on timing of the second voltage signal VGH to the level shift circuit 14 later than that of the first voltage signal VGL in other ways, which is not limited in the present application.

[0037] In a possible embodiment, when the absolute value of the voltage value of the first voltage signal VGL is greater than or equal to a first power-on threshold, the absolute value of the voltage value of the second voltage signal VGH is less than a second power-on threshold within a preset time threshold, wherein the first power-on threshold is the voltage value of the first voltage signal VGL for the power-on of the level shift circuit 14, and the second power-on threshold is the voltage value of the second voltage signal VGH for the power-on of the level shift circuit 14; wherein the first power-on threshold is greater than the preset voltage threshold.

[0038] It should be noted that the first power-up threshold refers to the power-up voltage threshold of the first voltage signal VGL required by the level shift circuit 14, and the second power-up threshold refers to the power-up voltage threshold of the second voltage signal VGH required by the level shift circuit 14. Therefore, in the present embodiment, when the absolute value of the voltage value of the first voltage signal VGL is greater than or equal to the first power-up threshold, the voltage value of the first voltage signal VGL has already met the power-up voltage threshold of the first voltage signal VGL required by the level shift circuit 14, that is, the first voltage signal VGL has completed power-up. Since the first power-up threshold is greater than the preset voltage threshold, when the absolute value of the voltage value of the first voltage signal VGL is greater than or equal to the first power-up threshold, the voltage value of the first voltage signal VGL has also been greater than the preset voltage threshold, that is, the level shift circuit 14 turns on the path between the second voltage signal VGH and the level shift circuit 14 according to the first voltage signal VGL, so that the second voltage signal VGH is transmitted to the level shift circuit 14 through the delay circuit 13, at this time the second voltage signal VGH has also risen by a certain voltage value, but the absolute value of the voltage value of the second voltage signal VGH is less than the second power-up threshold, that is, the second voltage signal VGH has not completed power-up. Then, within the preset time threshold, when the absolute value of the voltage value of the first voltage signal VGL remains greater than or equal to the first power-up threshold, the absolute value of the voltage value of the second voltage signal VGH continues to rise until it is greater than the second power-up threshold, then the second voltage signal VGH also completes power-up, and the level shift circuit 14 receives the correct power-up timing: the first voltage signal VGL-the second voltage signal VGH.

[0039] In the present embodiment, the preset time threshold is 10 seconds. It can be understood that the larger the preset time threshold, the longer the time required for the voltage value of the second voltage signal VGH to reach the power-up voltage threshold required by the level shift circuit 14, and therefore the level shift circuit 14 is more likely to receive the correct power-up timing. By reducing the size of the preset time threshold, the time required for the level shift circuit 14 to receive the correct power-up timing can also be reduced.

[0040] It can be understood that by adjusting the preset voltage threshold, the time at which the delay circuit 13 turns on the path between the second voltage signal VGH and the level shift circuit 14 can be changed, thereby changing the time at which the voltage value of the second voltage signal VGH starts to rise, and ultimately achieving the purpose of adjusting the preset time threshold. In other possible embodiments, the preset time threshold can also be other values, which are not limited by the present application.

[0041] In a possible implementation, please refer to Figure 4 , Figure 4 The schematic diagram of the delay circuit provided in an embodiment of the present application. The delay circuit 13 comprises a switching unit Q1, a first resistor R1 and a second resistor R2, a control end g of the switching unit Q1 is electrically connected to one end of the first resistor R1, and the first voltage signal VGL is received through the second resistor R2, a first end s of the switching unit Q1 is electrically connected to the other end of the first resistor R1, and is used for receiving the second voltage signal VGH, and a second end d of the switching unit Q1 is electrically connected to the level shift circuit 14.

[0042] In the embodiment, the switching unit Q1 is a positive channel metal oxide semiconductor (PMOS), and the control end g of the switching unit Q1 is loaded with the first voltage signal VGL having a certain voltage value, so that a source-drain channel is formed between the first end s of the switching unit Q1 and the second end d of the switching unit Q1 to turn on, so as to transmit the second voltage signal VGH to the level shift circuit 14 through the first end s of the switching unit Q1 and the second end d of the switching unit Q1 and start power-on.

[0043] It can be understood that when the absolute value of the voltage value of the first voltage signal VGL is greater than the preset voltage threshold, the first end s of the switching unit Q1 and the second end d of the switching unit Q1 are turned on, so that the power-on timing of the second voltage signal VGH transmitted to the level shift circuit 14 is later than the first voltage signal VGL.

[0044] It can be understood that in other possible embodiments, the switching unit Q1 can also be other types of electronic components, and correspondingly, the peripheral circuit thereof is also adaptively changed, as long as the power-on timing of the second voltage signal VGH transmitted to the level shift circuit 14 is later than the first voltage signal VGL, the present application does not limit this.

[0045] In a possible implementation, the threshold voltage of the switching unit Q1 is:

[0046] V GS (th)=V G -V S =-1.14 volts;

[0047] Wherein, the switching unit Q1 is a PMOS transistor, V GS (th) is the threshold voltage of the switching unit Q1, V GV S V

[0048] In the embodiment, the threshold voltage between the control terminal g of the switching unit Q1 and the first terminal s of the switching unit Q1 is -1.14 volts, that is, when the absolute value of the voltage between the control terminal g of the switching unit Q1 and the first terminal s of the switching unit Q1 is greater than or equal to 1.14 volts, the first terminal s of the switching unit Q1 and the second terminal d of the switching unit Q1 are turned on, so as to transmit the second voltage signal VGH to the level shift circuit 14 through the first terminal s of the switching unit Q1 and the second terminal d of the switching unit Q1 to start power-on.

[0049] For example, generally, the voltage value of the second voltage signal VGH is 22 volts, and in combination with the resistance values of the corresponding first resistance R1 and second resistance R2, when the voltage value of the first voltage signal VGL is -5 volts, that is, the preset voltage threshold value is -5 volts, the voltage value between the control terminal g of the switching unit Q1 and the first terminal s of the switching unit Q1 loaded can be -1.14 volts, so as to turn on the first terminal s of the switching unit Q1 and the second terminal d of the switching unit Q1.

[0050] It can be understood that in other possible embodiments, by changing the specifications of the switching unit Q1, thereby changing the threshold voltage of the switching unit Q1, the voltage values of different first voltage signals VGL and second voltage signals VGH can be adapted, which is not limited in the present application.

[0051] In a possible embodiment, the ratio of the resistance values of the first resistance R1 and the second resistance R2 is:

[0052] R1:R2=|V GS (th)| / [V VGH -(V1)]=0.0423;

[0053] Wherein, R1 is the resistance value of the first resistance R1, R2 is the resistance value of the second resistance R2, V VGH is the voltage value of the second voltage signal VGH, and V1 is the preset voltage threshold value.

[0054] Specifically, the first resistor R1 and the second resistor R2 play a role of voltage division, and the resistance values of the first resistor R1 and the second resistor R2 determine the potential of the control end g of the switch unit Q1 and the first end s of the switch unit Q1, thereby indirectly determining when the switch unit Q1 is turned on, under the condition that the voltage values of the first voltage signal VGL and the second voltage signal VGH are unchanged.

[0055] In the embodiment, the absolute value |V GS (th) of the threshold voltage of the switch unit Q1 is 1.14 volts, the voltage value V VGH of the second voltage signal VGH is 22 volts, and the preset voltage threshold V1 is -5 volts. According to the resistance value ratio calculation formula of the first resistor R1 and the second resistor R2, the resistance value ratio of the first resistor R1 and the second resistor R2 is 0.0423, so that the resistance values of the first resistor R1 and the second resistor R2 can be determined according to the voltage value of the second voltage signal VGH, the threshold voltage of the switch unit Q1, and the preset threshold voltage. Correspondingly, under the condition that the resistance values of the first resistor R1 and the second resistor R2 are determined, the voltage value of the second voltage signal VGH, the threshold voltage of the switch unit Q1, and the preset threshold voltage required can also be deduced by the resistance values of the first resistor R1 and the second resistor R2, which is not limited in the application.

[0056] In a possible implementation, the resistance value of the first resistor R1 is 20 kilo-ohms, and the resistance value of the second resistor R2 is 450 kilo-ohms.

[0057] It should be noted that the current flowing through the electronic components will generate certain power consumption, and the greater the resistance value of the electronic components, the greater the power consumption. In addition, the resistance value of the resistance component is usually a plurality of fixed values, so in the embodiment, the resistance value of the first resistor R1 is 20 kilo-ohms, and the resistance value of the second resistor R2 is 450 kilo-ohms, so that the resistance value ratio of the first resistor R1 and the second resistor R2 is close to 0.0423, that is, the delay circuit 13 can turn on the path between the second voltage signal VGH and the level shift circuit 14 according to the voltage value of the first voltage signal VGL being greater than or equal to the preset voltage threshold. In addition, the selection of the resistance values of the first resistor R1 and the second resistor R2 can save certain power consumption loss compared with other selections.

[0058] For example, by determining any one of the resistance values of the first resistance R1 and the second resistance R2, and then determining the resistance value of the other resistance according to the ratio of R2 / (R1+R2) in the range of 4.25%-5.25%, the resistance values of the first resistance R1 and the second resistance R2 are determined, and further, the ratio of R2 / (R1+R2) is 5%.

[0059] It can be understood that in other possible embodiments, the resistance values of the first resistance R1 and the second resistance R2 can also be other values, which are not limited in the present application.

[0060] In a possible embodiment, referring again to Figure 4 , the delay circuit 13 further comprises a voltage stabilizing capacitor C, one end of the voltage stabilizing capacitor C is electrically connected to the second end d of the switch unit Q1, and the other end of the voltage stabilizing capacitor C is grounded.

[0061] It can be understood that according to the charging and discharging effect of the capacitor, the power-up and discharging time of the second voltage signal VGH can be adjusted by changing the capacitance value of the voltage stabilizing capacitor C. For example, the larger the capacitance value of the voltage stabilizing capacitor C, the longer the power-up and discharging time of the second voltage signal VGH, i.e., the longer the time for the voltage value of the second voltage signal VGH to reach the required power-up voltage threshold of the level shifting circuit 14, so that the level shifting circuit 14 is more likely to receive the correct power-up timing. The smaller the capacitance value of the voltage stabilizing capacitor C, the shorter the power-up and discharging time of the second voltage signal VGH, i.e., the shorter the time for the voltage value of the second voltage signal VGH to reach the required power-up voltage threshold of the level shifting circuit 14, thereby reducing the time required for the level shifting circuit 14 to receive the correct power-up timing.

[0062] It can be understood that in the present embodiment, the capacitance value of the voltage stabilizing capacitor C is 30 microfarads, and in other possible embodiments, the capacitance value of the voltage stabilizing capacitor C can also be other values, which are not limited in the present application.

[0063] In a possible embodiment, referring again to Figure 4 , the delay circuit 13 further comprises a third resistance R3 and a fourth resistance R4, one end of the third resistance R3 is electrically connected to the second end d of the switch unit Q1, and the other end of the third resistance R3 is electrically connected to the level shifting circuit 14; one end of the fourth resistance R4 is electrically connected to the second end d of the switch unit Q1, and the other end of the fourth resistance R4 is grounded.

[0064] Specifically, the third resistor R3 serves as a back-end load resistor, the second voltage signal VGH is transmitted to the level shift circuit 14 through the third resistor R3, and the fourth resistor R4 serves as a pull-down resistor and functions to limit current and pull down potential. In this embodiment, the resistance value of the third resistor R3 is 70 ohms, and the resistance value of the fourth resistor R4 is 10 kilo-ohms. It can be understood that in other possible embodiments, the resistance values of the third resistor R3 and the fourth resistor R4 can also be other values, which are not limited in the present application.

[0065] The present application also provides simulation results based on the display panel 1 provided in the present application, please refer to Figure 5 and Table 1, Figure 5 is a simulation signal waveform diagram provided by an embodiment of the present application. The voltage value of the first voltage signal VGL is -7 volts, the voltage falling time of the first voltage signal VGL is 5 milliseconds, and the voltage value of the second voltage signal VGH is 22 volts. Thus, the simulation result data table shown in Figure 5 and Table 1 below, wherein T1, T2, T3, and T4 represent different time instants and the voltage values of the first voltage signal VGL and the second voltage signal VGH recorded at different time instants, respectively. As shown at time T2, when the absolute value of the voltage value of the first voltage signal VGL is greater than the preset voltage threshold, i.e., |-5.098 volts| is greater than |-5 volts|, the second voltage signal VGH is just transmitted to the level shift circuit 14 for power-up, at which time the power-up voltage of the second voltage signal VGH is still small, being 372.399 millivolts. After the voltage value of the first voltage signal VGL reaches the first power-up threshold, as shown between time T3 and time T4, within the preset time threshold, i.e., within -10.147 milliseconds, the second voltage signal VGH rises from 1.727 volts to 7.865 volts, and does not reach the second power-up threshold, thereby ensuring that the level shift circuit 14 can receive correct power-up timing.

[0066] Table 1 shows a display panel simulation result data table

[0067] \ Time First voltage signal VGL Second voltage signal VGH T1 14.994 ms -6.992V 1.850V T2 13.641 ms -5.098V 372.399 mV T2-T1 -1.353 ms 1.894V -1.478V T3 25.028 ms -7.000V 7.865V T4 14.882 ms -6.834V 1.727V T4-T3 -10.147 ms 165.727 mV -6.138V

[0068] The present application also provides an electronic device 2, please refer to Figure 6 , Figure 6 is a top view schematic diagram of an electronic device provided by an embodiment of the present application. The electronic device 2 includes a housing 21 and a display panel 1 as described above, and the housing 21 is used to carry the display panel 1. Specifically, the display panel 1 is described above, which will not be repeated here.

[0069] It should be noted that the electronic device 2 in the embodiments of the present application can be a television, a mobile phone, a smart phone, a tablet computer, an electronic reader, a portable device when worn, a notebook computer, etc. The electronic device 2 can communicate with a data transfer server through the Internet, and the data transfer server can be an instant messaging server, an SNS (Social Networking Services) server, etc. The embodiments of the present application are not limited in this regard.

[0070] It can be understood that, in the embodiments, the delay circuit 13 is controlled by the first voltage signal VGL, so that the second voltage signal VGH is transmitted to the level shift circuit 14 later than the first voltage signal VGL in the power-on timing, thereby ensuring that the timing of the voltage signal received by the level shift circuit 14 is normal, so that the level shift circuit 14 can normally generate the driving signal, and the normal display of the electronic device 2 is realized.

[0071] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above description of the embodiments is only used to help understand the core idea of the present application; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description of the present application should not be understood as a limitation of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a power supply circuit, a power management circuit, a delay circuit, a level shift circuit and a display circuit, the power supply circuit is electrically connected with the power management circuit, the power management circuit is electrically connected with the delay circuit and the level shift circuit, the level shift circuit is electrically connected with the display circuit, the power supply circuit is used for providing an input voltage rising from 0V for the power management circuit, the power management circuit generates a first voltage signal and a second voltage signal according to the input voltage, and transmits the first voltage signal to the level shift circuit and transmits the first voltage signal and the second voltage signal to the delay circuit, the delay circuit is used for controlling the power-on time sequence of the second voltage signal transmitted to the level shift circuit to be later than the power-on time sequence of the first voltage signal transmitted to the level shift circuit according to the first voltage signal, and the level shift circuit is used for generating a driving signal according to the first voltage signal and the second voltage signal, and the display circuit is used for receiving the driving signal to drive the display panel to display a picture. When the absolute value of the voltage value of the first voltage signal is greater than or equal to a preset voltage threshold, the delay circuit is turned on, so that the second voltage signal starts to be transmitted to the level shift circuit through the delay circuit. The delay circuit comprises a switching unit, a first resistor and a second resistor, the control end of the switching unit is electrically connected with one end of the first resistor and receives the first voltage signal through the second resistor, the first end of the switching unit is electrically connected with the other end of the first resistor and is used for receiving the second voltage signal, and the second end of the switching unit is electrically connected with the level shift circuit. The ratio of the resistance values of the first resistor and the second resistor is: R1: R2 = |V GS (th)| / [V VGH -(V1)]=0.0423; wherein R1 is a resistance value of the first resistor, R2 is a resistance value of the second resistor, V GS (th) is a threshold voltage of the switch unit, V VGH is a voltage value of the second voltage signal, and V1 is the preset voltage threshold.

2. The display panel of claim 1, wherein, When the absolute value of the voltage value of the first voltage signal is greater than or equal to a first power-on threshold, the absolute value of the voltage value of the second voltage signal is less than a second power-on threshold within a preset time threshold, wherein the first power-on threshold is the voltage value of the first voltage signal for powering on the level shift circuit, and the second power-on threshold is the voltage value of the second voltage signal for powering on the level shift circuit, and the first power-on threshold is greater than the preset voltage threshold.

3. The display panel of claim 1, wherein, The threshold voltage of the switching unit is: V GS (th)=V G -V S =-1.14 volts; Wherein, the switch unit is a PMOS transistor, V G is a potential of a control end of the switch unit, S is a potential of a first end of the switch unit.

4. The display panel of claim 1, wherein, The resistance value of the first resistor is 20 kΩ, and the resistance value of the second resistor is 450 kΩ.

5. The display panel of claim 1, wherein, The delay circuit further comprises a voltage stabilizing capacitor, one end of the voltage stabilizing capacitor is electrically connected with the second end of the switching unit, and the other end of the voltage stabilizing capacitor is grounded.

6. The display panel of claim 1, wherein, The delay circuit further comprises a third resistor and a fourth resistor, one end of the third resistor is electrically connected with the second end of the switching unit, the other end of the third resistor is electrically connected with the level shift circuit, one end of the fourth resistor is electrically connected with the second end of the switching unit, and the other end of the fourth resistor is grounded.

7. An electronic device, comprising: The electronic device comprises a housing and the display panel according to any one of claims 1-6, and the housing is used for carrying the display panel.

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