Gamma circuit and display device

Abstract

The present disclosure provides a gamma circuit and a display device. The gamma circuit includes a digital-to-analog converter and an operational amplifier. The digital-to-analog converter includes a plurality of voltage-dividing resistors connected in series between a first voltage terminal and a second voltage terminal. The number of the voltage-dividing resistors is less than 2. N ; The first switch array is configured to control the on / off between the first resistor and the first output terminal according to the low N1 bit in the N-bit digital signal, and according to different digital signals, different numbers of first resistors are connected to the path between the first voltage terminal and the first output terminal; the second switch array is configured to control the on / off between the second resistor and the second output terminal according to the high N2 bit, and according to different signals, different numbers of voltage divider resistors are connected to the path between the second voltage terminal and the second output terminal; N is an integer greater than 1; N1 and N2 are both positive integers, N1+N2=N; the operational amplifier is configured to output a gamma reference voltage according to the sum of the output voltages of the first output terminal and the second output terminal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gamma circuit and a display device. Background Art

[0002] The display panel of a thin-film transistor liquid crystal display (TFT-LCD) has multiple pixel units, each of which includes three color sub-pixels: red, green, and blue. The brightness displayed by each sub-pixel is determined by the gamma voltage. The function of the gamma circuit is to set the gamma voltage according to the gamma curve required by the LCD, which serves as the reference voltage for the TFT-LCD to display grayscale. The existing gamma circuit includes a digital to analog converter (DAC) and an operational amplifier (OP). The DAC converts the received digital signal used to generate the pixel grayscale reference voltage into an analog signal. The OP amplifies the analog signal processed by the DAC. The amplified voltage signal is output as the pixel grayscale reference voltage to the source driver circuit, so that the source driver circuit drives the sub-pixel according to the pixel grayscale reference voltage for display.

[0003] Current DACs use a resistor divider architecture, which causes the number of resistors and connections in the DAC to grow exponentially with the number of bits of the digital signal to be converted. This makes the DAC layout and wiring difficult and the chip area larger. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the problems in the prior art and provides a gamma circuit and a display device.

[0005] The present disclosure provides a gamma circuit, comprising: a digital-to-analog converter and an operational amplifier, wherein the digital-to-analog converter is configured to convert an input N-bit digital signal into an analog signal; wherein the digital-to-analog converter comprises:

[0006] A plurality of voltage-dividing resistors connected in series between a first voltage terminal and a second voltage terminal, wherein the voltage of the second voltage terminal is greater than the voltage of the first voltage terminal; the plurality of voltage-dividing resistors include at least two first resistors and at least one second resistor, wherein the at least one second resistor is connected in series between the at least two first resistors and the second voltage terminal; the number of the voltage-dividing resistors is less than 2 N ;

[0007] a first switch array configured to control the connection between the first resistor and the first output terminal of the digital-to-analog converter according to a digital signal of lower N1 bits in the N-bit digital signal, and to connect different numbers of first resistors to the path between the first voltage terminal and the first output terminal according to different digital signals;

[0008] a second switch array configured to control the connection between the second resistor and the second output terminal of the digital-to-analog converter based on a digital signal having upper N2 bits in the N-bit digital signal, and to connect different numbers of voltage divider resistors to the path between the second voltage terminal and the second output terminal based on different digital signals; N is an integer greater than 1; N1 and N2 are both positive integers, and N1+N2=N;

[0009] The operational amplifier is configured to output a gamma reference voltage according to the sum of the output voltages of the first output terminal and the second output terminal.

[0010] In some embodiments, the number of the first resistors is 2 N1 The number of the second resistor is 2 N2 -1; wherein the resistance of the second resistor is 2 times the resistance of the first resistor N1 times.

[0011] In some embodiments, the first switch array includes 2 N1 A first switch is provided, each of the first switches corresponds to the first resistor in a one-to-one manner, one end of the first switch is connected to an end of the corresponding first resistor close to the first power supply end, and the other end of the first switch is connected to the first output end.

[0012] In some embodiments, the second switch array includes 2 N2 -1 second switch and one third switch, the second switches corresponding to the second resistors one-to-one, one end of the second switch connected to the end of the corresponding second resistor close to the first power supply end, and the other end of the second switch connected to the second output end; the two ends of the third switch are respectively connected to the first voltage end and the second voltage end.

[0013] In some embodiments, the operational amplifier includes: an error amplification circuit, an impedance attenuation buffer circuit, and an output stage circuit;

[0014] The error amplifier circuit is configured to amplify a difference between a total output voltage of the digital-to-analog converter and an output voltage of the operational amplifier; wherein the total output voltage of the digital-to-analog converter is the sum of the output voltages of the first output terminal and the second output terminal;

[0015] The impedance attenuation buffer circuit is configured to provide a control voltage to the control terminal of the output stage circuit according to the output voltage of the error amplifier, and attenuate the output impedance of the control terminal of the output stage circuit;

[0016] The output stage circuit is configured to output the gamma reference voltage according to the control voltage.

[0017] In some embodiments, the error amplifier circuit includes:

[0018] a first bias transistor and a second bias transistor, wherein the gate of the first bias transistor and the gate of the second bias transistor are both connected to the bias voltage terminal, and the first electrode of the first bias transistor and the first electrode of the second bias transistor are both connected to a third voltage terminal;

[0019] a first transistor and a second transistor, wherein the gate of the first transistor is connected to the second output terminal, and the first electrode of the first transistor is connected to the second electrode of the first bias transistor; the gate of the second transistor is connected to the first output terminal, and the first electrode of the second transistor is connected to the second electrode of the second bias transistor;

[0020] a third transistor and a fourth transistor, wherein the gate of the third transistor is connected to the fourth voltage terminal, the first electrode of the third transistor is connected to the second electrode of the second bias transistor, the gate of the fourth transistor is connected to the output terminal of the operational amplifier, and the first electrode of the fourth transistor is connected to the second electrode of the first bias transistor;

[0021] a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor and the gate of the sixth transistor are both connected to a fifth voltage terminal, a first electrode of the fifth transistor is connected to the second electrode of the third transistor and the second electrode of the fourth transistor, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are connected to the fourth voltage terminal; and a first electrode of the sixth transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor;

[0022] a seventh transistor and an eighth transistor, wherein the gate of the seventh transistor and the gate of the eighth transistor are connected to the sixth voltage terminal, the second electrode of the seventh transistor is connected to the first electrode of the fifth transistor; the first electrode of the eighth transistor is connected to the output terminal of the error amplifier, and the second electrode of the eighth transistor is connected to the first electrode of the sixth transistor;

[0023] A ninth transistor and a tenth transistor, wherein the gate and the second electrode of the ninth transistor and the gate of the tenth transistor are connected to the first electrode of the seventh transistor, and the first electrode of the ninth transistor and the first electrode of the tenth transistor are connected to the third voltage terminal.

[0024] In some embodiments, the output stage circuit comprises:

[0025] a power tube, a gate of which is connected to the control terminal of the output stage circuit, a first electrode of which is connected to the third voltage terminal, and a second electrode of which is connected to the output terminal of the operational amplifier;

[0026] a nineteenth transistor, a gate of which is connected to the fifth voltage terminal, a first electrode of which is connected to the output terminal of the operational amplifier, and a second electrode of which is connected to the fourth voltage terminal;

[0027] A load resistor, two ends of which are respectively connected to the output end of the operational amplifier and the fourth voltage end.

[0028] In some embodiments, the impedance attenuation buffer circuit includes:

[0029] an eleventh transistor and a twelfth transistor, wherein a gate of the eleventh transistor is connected to the first electrode and the gate of the twelfth transistor, and a second electrode of the eleventh transistor and a second electrode of the twelfth transistor are connected to the first voltage terminal and the fourth voltage terminal;

[0030] a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the first electrode of the twelfth transistor, the first electrode of the thirteenth transistor is connected to the control terminal of the output stage circuit, and a second electrode of the thirteenth transistor is connected to the first electrode of the twelfth transistor;

[0031] a fourteenth transistor, wherein a gate of the fourteenth transistor is connected to the first bias terminal, a first electrode is connected to the third voltage terminal, and a second electrode is connected to the first electrode of the eleventh transistor;

[0032] a fifteenth transistor, having a gate connected to the gate of the power transistor, a first electrode connected to the third voltage terminal, and a second electrode connected to the first electrode of the eleventh transistor;

[0033] A sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the second bias terminal, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the gate of the power tube.

[0034] In some embodiments, the impedance attenuation buffer circuit further comprises:

[0035] a seventeenth transistor, wherein a gate of the seventeenth transistor is connected to the second electrode of the thirteenth transistor, a first electrode of the seventeenth transistor is connected to the gate of the power transistor, and a second electrode of the seventeenth transistor is connected to the fourth voltage terminal;

[0036] An eighteenth transistor, wherein the gate and the second electrode of the eighteenth transistor are connected to the gate of the power tube, and the first electrode of the eighteenth transistor is connected to the third voltage end.

[0037] In some embodiments, the gamma circuit further includes a voltage-stabilizing capacitor, and two ends of the voltage-stabilizing capacitor are respectively connected to the output end of the operational amplifier and the first voltage end.

[0038] The present disclosure further provides a source driving circuit, comprising the gamma circuit according to any one of the above embodiments.

[0039] The present disclosure also provides a display device, comprising the source driving circuit described in the above embodiments.

[0040] The present disclosure has the following technical effects:

[0041] The digital-to-analog converter in the gamma circuit disclosed herein can save significant amounts of switching branches, voltage-divider resistors, and wiring when converting high-bit digital signals, thereby reducing chip area. Furthermore, the impedance-reducing buffer in the operational amplifier connected to the digital-to-analog converter can function as a compensation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0043] Figure 1 Schematic diagram of the structure of a gamma circuit provided in some embodiments.

[0044] Figure 2 This is a schematic structural diagram of a digital-to-analog conversion circuit provided in some embodiments.

[0045] Figure 3 This is a schematic structural diagram of another digital-to-analog conversion circuit provided in some embodiments.

[0046] Figure 4 A schematic diagram of the structure of a gamma circuit provided in an embodiment of the present disclosure.

[0047] Figure 5 A schematic diagram of the structure of a digital-to-analog conversion circuit provided in an embodiment of the present disclosure.

[0048] Figure 6 A schematic diagram of the structure of an operational amplifier provided in some embodiments of the present disclosure.

[0049] Figure 7 A circuit diagram of an operational amplifier provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0050] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0051] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is intended solely to facilitate the description of this specification and simplify the description, and is not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may vary appropriately depending on the direction in which the components are described. Therefore, the terms and phrases described in this specification are not limited to those used in the specification and may be replaced as appropriate. Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the same meaning as those generally understood by persons of ordinary skill in the art to which the present disclosure pertains. The use of "first," "second," and similar terms in this disclosure does not denote any order, quantity, or importance, but is merely used to distinguish between different components. Similarly, words and phrases such as "include" or "comprising" mean that the element or object preceding the word includes the elements or objects listed after the word and their equivalents, but does not exclude other elements or objects. "Connect" or "connected" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. For those skilled in the art, the specific meanings of the above terms in this disclosure can be understood by those skilled in the art in specific circumstances.

[0052] Figure 1 is a schematic structural diagram of a gamma circuit provided in some embodiments, Figure 2 is a structural diagram of a digital-to-analog conversion circuit provided in some embodiments, such as Figure 1 and Figure 2 As shown, the gamma circuit includes: a digital-to-analog converter 1 and an operational amplifier 2, wherein the digital-to-analog converter 1 is configured to convert an input N-bit digital signal into an analog signal; wherein the digital-to-analog converter 1 includes: a plurality of voltage-dividing resistors R0 and a switch array connected in series between a first voltage terminal 5 and a second voltage terminal Vref.

[0053] The voltage of the second voltage terminal Vref is greater than the voltage of the first voltage terminal 5. For example, the first voltage terminal 5 can be a ground terminal. The resistance of the voltage divider resistor R0 is R.

[0054] The switch array is configured to control 2 NThe switch array controls the connection and disconnection between the voltage-dividing resistors R0 and the output terminal Vout of the digital-to-analog converter 1, and connects different voltage-dividing resistors R0 to the path between the first voltage terminal 5 and the output terminal Vout according to different digital signals. The switch array includes multiple switches, each corresponding to a voltage-dividing resistor R0. One end of each switch is connected to an end of the corresponding voltage-dividing resistor R0 near the first voltage terminal 5, and the other end of the switch is connected to the output terminal Vout.

[0055] The operational amplifier 2 is configured to output a gamma reference voltage according to the output voltage of the first output terminal Vout.

[0056] Furthermore, the gamma circuit further includes a voltage-stabilizing capacitor CL, wherein two ends of the voltage-stabilizing capacitor CL are respectively connected to the output end out of the operational amplifier 1 and the first voltage end 5 .

[0057] For example, Figure 2 As shown, a digital-to-analog converter 1 performs digital-to-analog conversion on a 2-bit digital signal, and a switch array includes four switches, with different switches being turned on according to different digital signals. The four switches are arranged in a direction away from the first voltage terminal 5, and the digital signal controlling the conduction of the i-th switch is the N-bit binary signal converted from the decimal value i-1.

[0058] Specifically, if Figure 2 As shown, the four switches are arranged in the direction away from the first voltage terminal 5, namely K00, K01, K02, and K03. Among them, the first switch K00 is controlled by the digital signal 00 (when the input digital signal is 00, the first switch is turned on), the second switch K01 is controlled by the digital signal 01, the third switch K02 is controlled by the digital signal 10, and the fourth switch K03 is controlled by the digital signal 11.

[0059] Assuming that the input 2-bit digital signal is code<1:0>=a1a0, the relationship between the output voltage of the DAC 1 controlled by the 2-bit digital signal and the input digital signal code<1:0>=a1a0 is shown in formula (1):

[0060]

[0061] Figure 3 FIG. 1 is a schematic structural diagram of another digital-to-analog conversion circuit provided in some embodiments, such as Figure 3 As shown, the digital-to-analog converter 1 performs digital-to-analog conversion on a 4-bit digital signal, and the switch array includes 16 switches, with different switches turning on according to different digital signals. The 16 switches are arranged in a direction away from the first voltage terminal 5, and the digital signal controlling the conduction of the i-th switch is the N-bit binary signal converted from the decimal value i-1.

[0062] Specifically, if Figure 3 As shown, the 16 switches are arranged in the direction away from the first voltage terminal 5, namely K00, K01, ..., K14, K15, among which the first switch K00 is controlled by the digital signal 0000 (when the input digital signal is 0000, the first switch is turned on), the second switch K01 is controlled by the digital signal 0001, the third switch K02 is controlled by the digital signal 0010, the fourth switch K03 is controlled by the digital signal 0011, ..., the fifteenth switch K14 is controlled by the digital signal 1110, and the sixteenth switch K15 is controlled by the digital signal 1111.

[0063] Assuming that the input 4-bit digital signal is code<3:0>=a3a2a1a0, the relationship between the output voltage of the DAC 1 controlled by the 4-bit digital signal and the input digital signal code<3:0>=a3a2a1a0 is shown in formula (2):

[0064]

[0065] like Figure 3 As shown, the multiple switches in the digital-to-analog converter 1 are turned on and off according to the input 4-bit digital signal. The 4-bit digital signal has 2 4 values, so 2 4 switches and 2 4 A voltage divider resistor R0.

[0066] By analogy, assuming that the input N-bit digital signal is code <n-1:0>=a N-1 a N-2 …a0, then we can deduce the output voltage of the digital-to-analog converter 1 controlled by the N-bit digital signal and the input digital signal code <n-1:0>=a N-1 a N-2 …a0, as shown in formula (3):

[0067]

[0068] It can be seen that the number of switch branches in the DAC 1 in the gamma circuit is exponentially related to the number of bits N of the digital signal, which makes the layout and wiring of the DAC 1 very challenging. At the same time, the switch branches will also occupy a large chip area.

[0069] Figure 4 Schematic diagram of a gamma circuit provided in an embodiment of the present disclosure. Figure 5 A schematic diagram of the structure of a digital-to-analog converter provided in an embodiment of the present disclosure is shown in FIG. Figure 4 and Figure 5 As shown, the gamma circuit provided in the embodiment of the present disclosure includes a digital-to-analog converter 3 and an operational amplifier 4.

[0070] The digital-to-analog converter 3 provided by the present disclosure includes: a plurality of voltage-dividing resistors connected in series between the first voltage terminal 5 and the second voltage terminal Vref, a first switch array K1 and a second switch array K2.

[0071] The voltage of the second voltage terminal Vref is greater than the voltage of the first voltage terminal 5, and the plurality of voltage divider resistors include at least two first resistors R1 and at least one second resistor R2, at least one second resistor R2 is connected in series between the at least two first resistors R1 and the second voltage terminal Vref, and the number of the voltage divider resistors is less than 2. N .

[0072] The first switch array K1 is configured to control the connection between the first resistor R1 and the first output terminal VL of the digital-to-analog converter 3 according to the digital signal of the lower N1 bits in the N-bit digital signal, and to connect different numbers of first resistors R1 to the path between the first voltage terminal and the first output terminal VL according to different digital signals.

[0073] The second switch array K2 is configured to control the connection between the second resistor R2 and the second output terminal VH of the digital-to-analog converter 3 based on the digital signal of the upper N2 bits in the N-bit digital signal, and to connect different numbers of voltage divider resistors to the path between the second voltage terminal Vref and the second output terminal VH according to different digital signals. N is an integer greater than 1; N1 and N2 are both positive integers, and N1 + N2 = N. The relationship between N1 and N2 is not limited; for example, N1 can be greater than N2, less than N2, or equal to N2.

[0074] The first output terminal VL outputs a low-bit voltage converted from a low-N1-bit digital signal; and the second output terminal VH outputs a high-bit voltage converted from a high-N2-bit digital signal.

[0075] The operational amplifier 4 is configured to output a gamma reference voltage according to the sum of the output voltages of the first output terminal VL and the second output terminal VH.

[0076] exist Figure 2 and Figure 3 In the embodiment shown, the multiple switches in the digital-to-analog converter 1 are turned on and off according to the input N-bit digital signal, which has a total of 2 N values, so 2 N switches and 2 N A voltage divider resistor R0. In the embodiment of the present disclosure, Figure 5 As shown, each switch in the first switch array K1 is turned on and off according to the lower N1 bits in the N-bit digital signal. The lower N1 bits have a total of 2 N1 Therefore, the first switch array K1 needs 2 N1 Each switch in the second switch array k2 is turned on and off according to the high N2 bits in the N-bit digital signal, and the high N2 bits have 2 N2 Therefore, the second switch array K2 requires 2 N2 switches; the total number of switches is less than 2 N , accordingly, the number of voltage divider resistors will be less than 2 N Therefore, in the embodiment of the present disclosure, when the number of bits of the digital signal to be converted by the digital-to-analog converter 3 is large, more switch branches, voltage divider resistors and connections can be saved, thereby solving the layout and wiring difficulties of the digital-to-analog converter and saving chip area.

[0077] In some embodiments, the number of the first resistor R1 is 2 N1 The number of the second resistor R2 is 2 N2 -1. The resistance of the second resistor R2 is 2 times the resistance of the first resistor R1. N1 The first switch array K1 includes 2 N1 A first switch (such as Figure 5 The first switches correspond to the first resistors R1 in a one-to-one manner, one end of the first switch is connected to the end of the corresponding first resistor R1 close to the first power supply end, and the other end of the first switch is connected to the first output end VL. The second switch array K2 includes 2 N2 - 1 second switch (such as Figure 5 K21~K23 in the figure) and a third switch K30, the second switches correspond to the second resistors R2 one by one, one end of the second switch is connected to the end of the corresponding second resistor R2 close to the first power supply end, and the other end of the second switch is connected to the second output end VH; the two ends of the third switch K30 are respectively connected to the first voltage end and the second voltage end Vref.

[0078] In the first switch array K1, the plurality of first switches are arranged in a direction away from the first voltage terminal 5. The digital signal controlling the conduction of the i-th first switch is an N1-bit binary signal converted from the decimal number i-1. In the second switch array K2, the plurality of second switches are arranged in a direction away from the first voltage terminal 5. The digital signal controlling the conduction of the i-th second switch is an N2-bit binary signal converted from the decimal number i. When the upper N2 bits of the N-bit digital signal received by the digital-to-analog converter 3 are all 0, the third switch K30 is turned on.

[0079] In some embodiments, N is an even number, N1=N2. In this case, when N is large, the total number of switches in the first switch array K1 and the second switch array K2 will not be excessive.

[0080] In one example, if Figure 5 As shown, for example, if N=4, N1=N2=2, the first switch array K1 is controlled by the digital signals of the lower two bits, and the second switch array K2 is controlled by the digital signals of the upper two bits. The first switch array K1 includes four first switches, and the four first switches are arranged in a direction away from the first voltage terminal 5, namely K10, K11, K12, and K13. The second switch array K2 includes three second switches and one third switch K30, and the three second switches are arranged in a direction away from the first voltage terminal 5, namely K21, K22, and K23. The two ends of the third switch K30 are connected to the first voltage terminal 5 and the second voltage terminal Vref, respectively.

[0081] The first first switch K10 is controlled by the digital signal 00 , the second first switch K11 is controlled by the digital signal 01 , the third first switch K12 is controlled by the digital signal 10 , and the fourth first switch K13 is controlled by the digital signal 11 .

[0082] Similarly, the first second switch K21 is controlled by the digital signal 01, the second second switch K22 is controlled by the digital signal 10, the third first switch K23 is controlled by the digital signal 11, and the third switch K30 is controlled by the digital signal 00.

[0083] The resistance of the first resistor R1 is denoted as R, and the resistance of the second resistor R2 is The second output terminal VH outputs a high-order voltage converted from the high-order 2-bit digital signal. Similarly, the first output terminal VL outputs a low-order voltage converted from the low-order 2-bit digital signal. The high-order voltage and the low-order voltage are then superimposed to obtain the voltage converted from the N-bit digital signal.

[0084] The relationship between the output voltage converted from the 4-bit digital signal and the input digital signal code<3:0>=b3b2b1b0 is shown in formula (4):

[0085]

[0086] Wherein, Vout is the sum of the output voltages of the first output terminal VL and the second output terminal VH.

[0087] like Figure 5 As shown in FIG, the 4-bit digital signal controlled DAC 3 only needs 8 switches and 7 resistors. Figure 3 Compared with the DAC 1 shown in FIG. 1 , the DAC 3 of the present disclosure requires significantly fewer resistors, switches, and wires.

[0088] Similarly, the output voltage of the digital-to-analog converter 3 controlled by the N-bit digital signal is equal to the input digital signal code <n-1:0>=b N-1 …b N1+2 b N1+1 b N1 b N1-1 …b0, as shown in formula (5):

[0089]

[0090] Assume that the digital signal received by the DAC 3 is N bits and the high Used to control the second switch array K2, low The bit is used to control the first switch array K1, and the total number of the second switch and the third switch K30 in the second switch array K2 is The first switch array K1 includes When N is large, compared with Figure 1 and Figure 3 As shown in the digital-to-analog converter, the number of switches required by the digital-to-analog converter 3 of the present disclosure is significantly reduced, thereby achieving the function of saving chip area.

[0091] Figure 6 is a structural diagram of an operational amplifier provided in some embodiments of the present disclosure, Figure 7 A circuit diagram of an operational amplifier provided in some embodiments of the present disclosure is shown in FIG. Figure 6 and Figure 7 As shown, in the embodiment of the present disclosure, the operational amplifier 4 includes: an error amplifier circuit 401, an impedance attenuation buffer circuit 402, and an output stage circuit 403. The error amplifier circuit 401 is configured to amplify the difference between the total output voltage of the digital-to-analog converter 3 and the output voltage of the operational amplifier 4. The total output voltage of the digital-to-analog converter 3 is the sum of the output voltages of the first output terminal VL and the second output terminal VH. The impedance attenuation buffer circuit 402 is configured to provide a control voltage to the control terminal N2 of the output stage circuit based on the output voltage of the error amplifier 401 and to attenuate the output impedance of the control terminal N2 of the output stage circuit. The output stage circuit 403 is configured to output a gamma reference voltage based on the control voltage.

[0092] like Figure 7 As shown, in some embodiments, the error amplifier circuit 402 includes a first bias transistor Mb1 and a second bias transistor Mb2, wherein the gate of the first bias transistor Mb1 and the gate of the second bias transistor Mb2 are both connected to the bias voltage terminal Vb, and the first electrode of the first bias transistor Mb1 and the first electrode of the second bias transistor Mb2 are both connected to the third voltage terminal AVDD. The first bias transistor Mb1 and the second bias transistor Mb2 can generate two bias currents of the same magnitude and direction under the voltage generated by the third voltage terminal AVDD.

[0093] The error amplifier circuit 402 further includes: first to tenth transistors M1 to M10, wherein the gate of the first transistor M1 is connected to the second output terminal VH, and the first electrode of the first transistor M1 is connected to the second electrode of the first bias transistor Mb1; the gate of the second transistor M2 is connected to the first output terminal VB, and the first electrode of the second transistor M2 is connected to the second electrode of the second bias transistor Mb2.

[0094] The gate of the third transistor M3 is connected to the fourth voltage terminal 6, where the fourth voltage terminal 6 can be a ground terminal. The first electrode of the third transistor M3 is connected to the second electrode of the second bias transistor Mb2. The gate of the fourth transistor M4 is connected to the output terminal out of the operational amplifier. The first electrode of the fourth transistor M4 is connected to the second electrode of the first bias transistor Mb1.

[0095] The first transistor M1 and the fourth transistor M4 form an input differential pair, and the second transistor M2 and the third transistor M3 form another input differential pair.

[0096] The fifth transistor M5 and the sixth transistor M6, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are both connected to the fifth voltage terminal V2, the first electrode of the fifth transistor M5 is connected to the second electrode of the third transistor M3 and the second electrode of the fourth transistor M4, the second electrode of the fifth transistor M5 and the second electrode of the sixth transistor M6 are connected to the fourth voltage terminal 6; the first electrode of the sixth transistor M6 is connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2.

[0097] The seventh transistor M7 and the eighth transistor M8, the gate of the seventh transistor M7 and the gate of the eighth transistor M8 are connected to the sixth voltage terminal V1, the second electrode of the seventh transistor M7 is connected to the first electrode of the fifth transistor M5; the first electrode of the eighth transistor M8 is connected to the output end of the error amplifier, and the second electrode of the eighth transistor M8 is connected to the first electrode of the sixth transistor M6.

[0098] The fifth transistor M5 , the sixth transistor M6 , the seventh transistor M7 , and the eighth transistor M8 constitute a common-source common-gate amplifier circuit.

[0099] The ninth transistor M9 and the tenth transistor M10, wherein the gate and second electrode of the ninth transistor M9 and the gate of the tenth transistor M10 are connected to the first electrode of the seventh transistor M7, and the first electrode of the ninth transistor M9 and the first electrode of the tenth transistor M10 are connected to the third voltage terminal AVDD. The ninth transistor M9 and the tenth transistor M10 form a current mirror.

[0100] The voltage signal passing through the error amplifier circuit has an amplification factor of 1. The error amplifier 4 amplifies the error signal (the difference between the output of the error amplifier and the voltage output from the first output terminal VL and the second output terminal VH) to improve the sensitivity of the gamma control circuit, thereby improving the adjustment accuracy and reducing the adjustment error.

[0101] In some embodiments, the output stage circuit includes: a power transistor Mp, a nineteenth transistor M19, and a load resistor. The power transistor Mp has a gate connected to the control terminal N2 of the output stage circuit, a first electrode connected to the third voltage terminal AVDD, and a second electrode connected to the output terminal out of the operational amplifier 3.

[0102] The gate of the nineteenth transistor M19 is connected to the fifth voltage terminal V2 , the first electrode is connected to the output terminal out of the operational amplifier 3 , and the second electrode is connected to the fourth voltage terminal 6 .

[0103] Two ends of the load resistor are connected to the output terminal out of the operational amplifier 3 and the fourth voltage terminal 6 respectively.

[0104] Since the power tube Mp is large, its gate parasitic capacitance is large, and thus the impedance of the power tube Mp is high. Figure 7 Inserting an impedance attenuation buffer between the N1 node in the circuit and the gate of the power tube Mp can avoid the generation of a low-frequency pole, which is beneficial to the stability compensation of the operational amplifier 4.

[0105] In some embodiments, the impedance attenuation buffer circuit includes:

[0106] The eleventh transistor M11 to the sixteenth transistor M16 , wherein the gate of the eleventh transistor M11 is connected to the first electrode and the gate of the twelfth transistor M12 , and the second electrode of the eleventh transistor M11 and the second electrode of the twelfth transistor M12 are connected to the fourth voltage terminal 6 .

[0107] A gate of the thirteenth transistor M13 is connected to the first electrode of the twelfth transistor M12 , a first electrode of the thirteenth transistor M13 is connected to the control terminal N2 of the output stage circuit, and a second electrode of the thirteenth transistor M13 is connected to the first electrode of the twelfth transistor M12 .

[0108] The gate of the fourteenth transistor M14 is connected to the first bias terminal Vb1 , the first electrode is connected to the third voltage terminal AVDD, and the second electrode is connected to the first electrode of the eleventh transistor M11 .

[0109] The fifteenth transistor M15 has a gate connected to the gate of the power transistor Mp, a first electrode connected to the third voltage terminal AVDD, and a second electrode connected to the first electrode of the eleventh transistor M11.

[0110] The sixteenth transistor M16 has a gate connected to the second bias terminal Vb2 , a first electrode connected to the third voltage terminal AVDD, and a second electrode connected to the gate of the power transistor Mp.

[0111] The fifteenth transistor M15 and the power transistor Mp form a current mirror structure. Therefore, the current flowing through the fifteenth transistor M15 is proportional to the current flowing through the power transistor Mp. When the current flowing through the power transistor Mp changes, the current flowing through the fifteenth transistor M15 changes, which in turn causes the current flowing through the eleventh transistor M11 and the twelfth transistor M12 connected to the fifteenth transistor M15 to change, thereby affecting the current flowing through the thirteenth transistor M13, thereby causing the impedance of the control terminal N2 of the output stage circuit to change, thereby achieving impedance attenuation.

[0112] Therefore, when the load current changes, the fifteenth transistor M15 can sample the load current to enable the output impedance of the control terminal N2 of the output stage circuit to track the load current changes in the gamma circuit. Therefore, the impedance attenuation buffer 402 is conducive to maintaining system stability even when the load current changes greatly.

[0113] Furthermore, in some other embodiments, the impedance attenuation buffer circuit further includes:

[0114] a seventeenth transistor M17, wherein a gate of the seventeenth transistor M17 is connected to the second electrode of the thirteenth transistor M13, a first electrode of the seventeenth transistor M17 is connected to the gate of the power transistor Mp, and a second electrode of the seventeenth transistor M17 is connected to the fourth voltage terminal 6;

[0115] An eighteenth transistor M18 has a gate and a second electrode connected to the gate of the power transistor Mp, and a first electrode connected to the third voltage terminal AVDD.

[0116] In the impedance attenuation buffer, the eighteenth transistor M18 and the power transistor Mp form a current mirror structure. Since the fifteenth transistor M15 and the power transistor Mp also form a current mirror structure, the currents flowing through the fifteenth transistor M15, the eighteenth transistor M18, and the power transistor Mp are proportional in magnitude and have the same direction. Therefore, the operational amplifier with the seventeenth transistor M17 and the eighteenth transistor M18, when the load current changes, samples the load current, thereby further helping the output impedance of the control terminal N2 of the output stage circuit track changes in the load current in the gamma circuit. This, in turn, makes the impedance attenuation buffer 402 more conducive to maintaining system stability even when the load current changes significantly.

[0117] The output impedance of the control terminal N2 of the output stage circuit 403 can be expressed as shown in formula (6):

[0118]

[0119] Among them, g m13 is the transconductance of the thirteenth transistor M13; g m17 is the transconductance of the seventeenth transistor M17; g m18 is the transconductance of the eighteenth transistor M18.

[0120] It should be noted that, in the embodiment of the present disclosure, the first bias transistor Mb1, the second bias transistor Mb2, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the first transistor M9, the first transistor M10, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the eighteenth transistor M18 and the power transistor Mp are N-type transistors, and the remaining transistors are P-type transistors.

[0121] The impedance attenuation buffer circuit 402 provided in the embodiment of the present disclosure outputs a control voltage for the gate of the power transistor Mp based on the output voltage of the error amplifier circuit 401. The output voltage of the error amplifier circuit 401 and the magnitude of the control voltage outputted to the gate of the power transistor Mp are positively correlated. Therefore, when the gamma reference voltage tends to decrease, the current flowing through the fourth transistor M4 increases, while the current flowing through the first transistor M1 decreases. This in turn causes the voltage of the first-stage output N1 to decrease, and the voltage of the control terminal N2 of the output-stage circuit connected to the gate of the power transistor Mp to decrease, thereby causing the current flowing through the power transistor Mp to increase, and thus increasing the gamma reference voltage. This adjusts the gamma reference voltage, thereby maintaining the balance of the gamma circuit.

[0122] When the gamma circuit is balanced, the sum of the currents flowing through the first transistor M1 and the second transistor M2 is equal to the sum of the currents flowing through the third transistor M3 and the fourth transistor M4. Therefore, the gamma circuit can achieve the function of adding the voltages output by the first output terminal VL and the second output terminal VH.

[0123] Furthermore, the gamma circuit also includes a voltage stabilizing capacitor CL, wherein two ends of the voltage stabilizing capacitor CL are respectively connected to the output end out of the operational amplifier 1 and the first voltage end 5, thereby stabilizing the voltage across the output end out of the operational amplifier 1 and the first voltage end 5.

[0124] The present disclosure also provides a display device, comprising the gamma circuit described in any one of the above embodiments.

[0125] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A gamma circuit, characterized in that: The circuit includes: a digital-to-analog converter and an operational amplifier, wherein the digital-to-analog converter is configured to convert an input N-bit digital signal into an analog signal; wherein the digital-to-analog converter includes: A plurality of voltage-dividing resistors connected in series between a first voltage terminal and a second voltage terminal, wherein the voltage of the second voltage terminal is greater than the voltage of the first voltage terminal; the plurality of voltage-dividing resistors include at least two first resistors and at least one second resistor, wherein the at least one second resistor is connected in series between the at least two first resistors and the second voltage terminal; the number of the voltage-dividing resistors is less than 2 N ; a first switch array configured to control the connection between the first resistor and the first output terminal of the digital-to-analog converter according to a digital signal of lower N1 bits in the N-bit digital signal, and to connect different numbers of first resistors to the path between the first voltage terminal and the first output terminal according to different digital signals; a second switch array configured to control the connection between the second resistor and the second output terminal of the digital-to-analog converter based on a digital signal having upper N2 bits in the N-bit digital signal, and to connect different numbers of voltage divider resistors to the path between the second voltage terminal and the second output terminal based on different digital signals; N is an integer greater than 1; N1 and N2 are both positive integers, and N1+N2=N; wherein the operational amplifier is configured to output a gamma reference voltage according to the sum of the output voltages of the first output terminal and the second output terminal; The operational amplifier comprises: an error amplification circuit, an impedance attenuation buffer circuit and an output stage circuit; The error amplifier circuit is configured to amplify a difference between a total output voltage of the digital-to-analog converter and an output voltage of the operational amplifier; wherein the total output voltage of the digital-to-analog converter is the sum of the output voltages of the first output terminal and the second output terminal; The impedance attenuation buffer circuit is configured to provide a control voltage to the control terminal of the output stage circuit according to the output voltage of the error amplifier circuit, and attenuate the output impedance of the control terminal of the output stage circuit; The output stage circuit is configured to output the gamma reference voltage according to the control voltage; The impedance attenuation buffer circuit comprises: an eleventh transistor and a twelfth transistor, wherein a gate of the eleventh transistor is connected to the first electrode and the gate of the twelfth transistor, and a second electrode of the eleventh transistor and a second electrode of the twelfth transistor are connected to a fourth voltage terminal; a thirteenth transistor, wherein a gate of the thirteenth transistor is connected to the output end of the error amplifier circuit, a first electrode of the thirteenth transistor is connected to the control end of the output stage circuit, and a second electrode of the thirteenth transistor is connected to the first electrode of the twelfth transistor; a fourteenth transistor, wherein the gate of the fourteenth transistor is connected to the first bias terminal, the first electrode is connected to the third voltage terminal, and the second electrode is connected to the first electrode of the eleventh transistor; a fifteenth transistor, wherein a gate of the fifteenth transistor is connected to the control terminal of the output stage circuit, a first electrode is connected to the third voltage terminal, and a second electrode is connected to the first electrode of the eleventh transistor; a sixteenth transistor, wherein a gate of the sixteenth transistor is connected to the second bias terminal, a first electrode is connected to the third voltage terminal, and a second electrode is connected to the control terminal of the output stage circuit; a seventeenth transistor, wherein a gate of the seventeenth transistor is connected to the second electrode of the thirteenth transistor, a first electrode of the seventeenth transistor is connected to the control terminal of the output stage circuit, and a second electrode of the seventeenth transistor is connected to the fourth voltage terminal; An eighteenth transistor, wherein the gate and the second electrode of the eighteenth transistor are connected to the control end of the output stage circuit, and the first electrode of the eighteenth transistor is connected to the third voltage end.

2. The gamma circuit according to claim 1, wherein: The number of the first resistors is 2 N1 The number of the second resistor is 2 N2 -1; The resistance of the second resistor is twice the resistance of the first resistor. N1 times.

3. The gamma circuit according to claim 2, wherein: The first switch array includes 2 N1 A first switch is provided, each of the first switches corresponds to the first resistor in a one-to-one manner, one end of the first switch is connected to an end of the corresponding first resistor close to the first power supply end, and the other end of the first switch is connected to the first output end.

4. The gamma circuit according to claim 2, wherein: The second switch array includes 2 N2 -1 second switch and one third switch, the second switches corresponding to the second resistors one-to-one, one end of the second switch connected to the end of the corresponding second resistor close to the first power supply end, and the other end of the second switch connected to the second output end; the two ends of the third switch are respectively connected to the first voltage end and the second voltage end.

5. The gamma circuit according to any one of claims 1 to 4, characterized in that The error amplification circuit comprises: a first bias transistor and a second bias transistor, wherein the gate of the first bias transistor and the gate of the second bias transistor are both connected to the bias voltage terminal, and the first electrode of the first bias transistor and the first electrode of the second bias transistor are both connected to a third voltage terminal; a first transistor and a second transistor, wherein the gate of the first transistor is connected to the second output terminal, and the first electrode of the first transistor is connected to the second electrode of the first bias transistor; the gate of the second transistor is connected to the first output terminal, and the first electrode of the second transistor is connected to the second electrode of the second bias transistor; a third transistor and a fourth transistor, wherein the gate of the third transistor is connected to the fourth voltage terminal, the first electrode of the third transistor is connected to the second electrode of the second bias transistor, the gate of the fourth transistor is connected to the output terminal of the operational amplifier, and the first electrode of the fourth transistor is connected to the second electrode of the first bias transistor; a fifth transistor and a sixth transistor, wherein the gate of the fifth transistor and the gate of the sixth transistor are both connected to a fifth voltage terminal, a first electrode of the fifth transistor is connected to the second electrode of the third transistor and the second electrode of the fourth transistor, and the second electrode of the fifth transistor and the second electrode of the sixth transistor are connected to the fourth voltage terminal; and a first electrode of the sixth transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor; a seventh transistor and an eighth transistor, wherein the gate of the seventh transistor and the gate of the eighth transistor are connected to the sixth voltage terminal, and the second electrode of the seventh transistor is connected to the first electrode of the fifth transistor; A first electrode of the eighth transistor is connected to the output end of the error amplifier circuit, and a second electrode of the eighth transistor is connected to the first electrode of the sixth transistor; A ninth transistor and a tenth transistor, wherein the gate and the second electrode of the ninth transistor and the gate of the tenth transistor are connected to the first electrode of the seventh transistor, and the first electrode of the ninth transistor and the first electrode of the tenth transistor are connected to the third voltage terminal.

6. The gamma circuit according to claim 5, characterized in that The output stage circuit comprises: a power tube, a gate of which is connected to the control terminal of the output stage circuit, a first electrode of which is connected to the third voltage terminal, and a second electrode of which is connected to the output terminal of the operational amplifier; a nineteenth transistor, a gate of which is connected to the fifth voltage terminal, a first electrode of which is connected to the output terminal of the operational amplifier, and a second electrode of which is connected to the fourth voltage terminal; A load resistor, two ends of which are respectively connected to the output end of the operational amplifier and the fourth voltage end. 7 . The gamma circuit according to claim 1 , further comprising a voltage-stabilizing capacitor, wherein two ends of the voltage-stabilizing capacitor are respectively connected to the output end of the operational amplifier and the fourth voltage end.

8. A display device, characterized in that: The gamma circuit comprises the gamma circuit according to any one of claims 1 to 7.

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