Abnormality processing method, device and equipment of optical module I2C circuit and medium

Abstract

The application relates to an abnormality processing method of an optical module I2C circuit, characterized in that the optical module I2C circuit comprises a CPU and at least one optical module, the CPU is connected with each optical module through an I2C bus, the method comprises the following steps: the CPU sends an access instruction to a current optical module; when the access fails, the CPU acquires the signal state of the I2C bus; when the SCL in the signal state of the I2C bus is in a lock state, the CPU skips the current optical module to access a next optical module, and the CPU gives an alarm prompt to the current optical module. The method can more accurately locate the abnormality problem of the optical module I2C circuit, and the located problem is processed.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method, apparatus, device and medium for handling abnormalities in an optical module I2C circuit. Background Technology

[0002] With the development of communication technology, switching devices have emerged. Switches are widely used in enterprise networks, large campus networks, and data centers, acting as bridges connecting various network devices in these large network environments. Their stability and reliability determine the performance and stability of the entire network.

[0003] Optical modules are critical components of switches. Due to their hot-swappable nature, they are prone to various issues such as improper insertion and oxidation of the gold fingers. Especially when dealing with problems with customers' online equipment, on-site troubleshooting is often required, severely impacting response speed and resulting in a poor customer experience.

[0004] In low-cost designs, multiple optical modules are often connected to a single I2C bus. Currently, I2C faults in optical modules are typically handled by CPU software. When an I2C access error occurs and the circuit locks, nine consecutive clock cycles are sent to attempt to unlock it. If unlocking fails, the entire I2C switch is continuously reset for isolation. This method cannot pinpoint the exact problem area, resulting in imprecise fault localization. Summary of the Invention

[0005] Therefore, it is necessary to provide a method, apparatus, device, and medium for handling abnormalities in the I2C circuit of an optical module to address the aforementioned technical problems.

[0006] An anomaly handling method for an optical module I2C circuit, the optical module I2C circuit including a CPU and at least one optical module, wherein the CPU is connected to each of the optical modules via an I2C bus, and the method includes:

[0007] The CPU sends an access command to the current optical module;

[0008] When an access fails, the CPU obtains the signal status of the I2C bus;

[0009] When the SCL signal status of the I2C bus is locked, the CPU skips the current optical module and accesses the next optical module, and issues an alarm to the current optical module.

[0010] In one embodiment, the aforementioned optical module I2C circuit further includes a CPLD connected to the CPU. The CPLD is also connected to the I2C bus, and the CPU acquires the signal status of the I2C bus, including:

[0011] The CPLD monitors the signal state of the I2C bus in real time and stores the signal state of the I2C bus into an I2C state register;

[0012] The CPU reads the I2C state register to obtain the signal state of the I2C bus; or

[0013] When the CPLD monitors that the signal state of the I2C bus is a lock state, the CPLD reports an exception information to the CPU.

[0014] In one of the embodiments, the signal state of the I2C bus further includes a signal state of SDA, and the method further includes:

[0015] When the signal state of SDA is a lock state, the CPU performs unlocking, and when the unlocking is unsuccessful, the CPU performs a step of skipping the current optical module to access a next optical module.

[0016] In one of the embodiments, the method further includes:

[0017] When the access fails and the signal state of the I2C bus is not locked, the CPU re-sends an access instruction to the current optical module;

[0018] When the access fails and the access times reach a preset number of times, the CPU performs a step of skipping the current optical module to access a next optical module.

[0019] In one of the embodiments, the optical module I2C circuit further includes a Switch connected with each optical module, the Switch is connected with the CPU through the I2C bus, and before the CPU skips the current optical module to access a next optical module and performs an alarm prompt to the current optical module, the method further includes:

[0020] The CPU controls the Switch to reset and reset to release the I2C bus between the Switch and the CPU;

[0021] The CPU creates an exception mark for the current optical module and skips the current optical module to access a next optical module according to the exception mark.

[0022] In one of the embodiments, the method further includes:

[0023] The CPU controls an indicator corresponding to the current optical module to light; and / or

[0024] The CPU generates a prompt information according to the exception mark and a lock state of SCL in the signal state of the I2C bus, and prints the prompt information through a serial port; and / or

[0025] The CPU stores the prompt information in a form of a log in a local.

[0026] In one of the embodiments, the above-mentioned Switches include a plurality of Switches, each of which is connected to an isolation circuit, a power supply and a plurality of optical modules, and the above-mentioned method further includes:

[0027] When a short circuit occurs in a power supply domain to which a target Switch and corresponding optical modules belong, the isolation circuit connected to the target Switch isolates the power supply domain to which the target Switch belongs from the power supply domains to which other Switches belong, so that the CPU skips the optical modules in the power supply domain to which the target Switch belongs and accesses the optical modules connected to other Switches.

[0028] An abnormality processing device of an optical module I2C circuit, the optical module I2C circuit including a CPU and at least one optical module, the CPU being connected to each of the optical modules through an I2C bus, and the device including:

[0029] a sending module configured to send an access instruction from the CPU to a current optical module;

[0030] an obtaining module configured to obtain a signal state of the I2C bus when the access fails;

[0031] a processing module configured to, when the SCL in the signal state of the I2C bus is in a lock state, skip the current optical module to access a next optical module and perform an alarm prompt on the current optical module.

[0032] A computer device including a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the following steps when executing the computer program:

[0033] the CPU sends an access instruction to a current optical module;

[0034] the CPU obtains a signal state of the I2C bus when the access fails;

[0035] when the SCL in the signal state of the I2C bus is in a lock state, the CPU skips the current optical module to access a next optical module and performs an alarm prompt on the current optical module.

[0036] A computer readable storage medium having a computer program stored thereon, the computer program being executable on a processor to implement the following steps:

[0037] the CPU sends an access instruction to a current optical module;

[0038] the CPU obtains a signal state of the I2C bus when the access fails;

[0039] when the SCL in the signal state of the I2C bus is in a lock state, the CPU skips the current optical module to access a next optical module and performs an alarm prompt on the current optical module.

[0040] The abnormality processing method, device, equipment and medium of the optical module I2C circuit can accurately locate the problem of the access failure, take the processing measure of skipping the next optical module by the current optical module according to the located problem, accurately locate the abnormality and skip the optical module, and do not affect the normal access of other optical modules. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 FIG. 1 is a flowchart of an abnormality processing method of an optical module I2C circuit in an embodiment;

[0042] Figure 2 FIG. 4 is a flowchart of the CPU obtaining the signal state of the I2C bus in an embodiment;

[0043] Figure 3 FIG. 5 is a circuit diagram of an optical module I2C circuit in an embodiment;

[0044] Figure 4 FIG. 1 is a flowchart of an abnormality processing method of an optical module I2C circuit in an embodiment;

[0045] Figure 5 FIG. 7 is a structural block diagram of an abnormality processing device of an optical module I2C circuit in an embodiment;

[0046] Figure 6 FIG. 8 is an internal structure diagram of a computer equipment in an embodiment. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0048] In one embodiment, as shown in FIG. 1, an abnormality processing method of an optical module I2C circuit is provided, the optical module I2C circuit comprising a CPU and at least one optical module, the CPU being connected with each optical module through an I2C bus, comprising the following steps: Figure 1

[0049] S11, the CPU sends an access instruction to the current optical module.

[0050] ​The optical module I2C circuit in the present application refers to a design circuit in which multiple optical modules are connected to one I2C bus. The optical module described above is an important component of a switch, and due to its hot-plug supporting characteristics, there are often various problems such as insertion out of position and gold finger oxidation, so when designing the optical module I2C circuit, the design circuit in which multiple optical modules are connected to one I2C bus is often used. Among them, the current optical module here refers to the optical module currently accessed by the CPU.

[0051] The I2C (Inter-Integrated Circuit, Inter-Integrated Circuit) described above is a serial communication protocol used for data transmission between microcontrollers and peripheral devices. The I2C serial bus generally includes two signal lines, one is a bidirectional data line SDA, and the other is a clock line SCL.

[0052] Specifically, SCL is the clock signal line on the I2C bus, which is controlled by the master device. The master device uses the SCL signal to synchronize data transmission, that is, each data bit is transmitted on the edge of the SCL signal when transmitting data.

[0053] SDA is the data signal line on the I2C bus, used for transmitting data between the master device and the slave device. When the master device needs to transmit data to the slave device, it writes data to the SDA line and transmits it on the edge of the SCL signal. The slave device also receives data through the SDA line when receiving data.

[0054] In the present application, the optical module I2C circuit described above includes a CPU, and the CPU connects at least one optical module through the I2C bus. The CPU can access the at least one optical module through the I2C bus, and handle abnormal situations when access fails.

[0055] S12, when the access fails, the CPU obtains the signal state of the I2C bus.

[0056] In the present application, when the CPU sends an access instruction to the current optical module, the current optical module returns a response signal, and when the CPU receives the response signal of the current optical module, it is determined that the access is successful, otherwise, it is determined that the access fails.

[0057] In the present application, the signal state of the I2C bus refers to the signal state of the clock line SCL and the data line SDA in the I2C bus. Among them, the signal state refers to the state of whether the signal is normal, for example, the signal state in the present application can include SCL lock, SDA lock and normal state.

[0058] S13, when the SCL in the signal state of the I2C bus is in a locked state, the CPU skips the current optical module and accesses the next optical module, and alarms the current optical module.

[0059] In the present application, when the low level of SCL lasts for a preset time length, it can be determined that SCL is in a locked state. When SCL is in the locked state, the CPU cannot access the current optical module.

[0060] In the present application, the SCL signal lock may be a problem with the link, or it may be that the current optical module itself has an abnormality. At this time, the CPU needs to output an alarm information to prompt manual processing.

[0061] Specifically, the CPU can generate a prompt information according to the identification information of the current optical module and the signal state of SCL, and remind the relevant personnel to process in the form of an alarm prompt.

[0062] Please refer to Figure 2 In one embodiment, the optical module I2C circuit described above further comprises a CPLD connected with the CPU, and the CPLD is further connected with the I2C bus. The CPU obtaining the signal state of the I2C bus can include:

[0063] S21, the CPLD monitors the signal state of the I2C bus in real time, and stores the signal state of the I2C bus into an I2C state register;

[0064] S22, the CPU reads the I2C state register to obtain the signal state of the I2C bus; or the CPLD reports an abnormal information to the CPU when it monitors that the signal state of the I2C bus is in a locked state.

[0065] In the present application, the CPLD (Complex Programmable Logic Device) described above is used to monitor the signal state of the I2C bus in real time, and store the signal state of the I2C bus into an I2C state register.

[0066] In the present application, the signal state of the I2C bus can include the signal state of SCL and the signal state of SDA. The signal state of SCL can include the level value of SCL at each time. The signal state of SDA can include the level value of SDA at each time.

[0067] In the present application, the CPLD includes the following two implementation manners when obtaining the signal state of the I2C bus:

[0068] One, the CPLD monitors the signal state of the I2C bus in real time, analyzes the signal state of SCL and SDA, that is, analyzes the level value of SCL and SDA in a preset time period, determines that SCL or SDA is in a lock state when the time length of SCL or SDA in a low state exceeds a preset time length, and stores the information that SCL or SDA is in the lock state into an I2C state register, so that the CPU reads the information that SCL or SDA is in the lock state.

[0069] Two, the CPLD monitors the signal state of the I2C bus in real time, and analyzes the level value of SCL and SDA in a preset time period, determines that SCL or SDA is in a lock state when the time length of SCL or SDA in a low state exceeds a preset time length, generates abnormal information according to SCL or SDA in the lock state, and reports the abnormal information to the CPU.

[0070] In another embodiment, the CPLD also records the last I2C data, analyzes the last I2C data, obtains analyzed data, and stores the analyzed data into the I2C state register, where the analyzed data can include identification information of the current optical module accessed last time.

[0071] Through the embodiment, the signal state of the I2C bus can be monitored in real time, and when an access exception occurs, the abnormal link can be located according to the signal state of the I2C bus, so that corresponding measures are taken.

[0072] In one embodiment, the signal state of the I2C bus further includes the signal state of SDA, and the method can further include:

[0073] When the signal state of SDA is in a lock state, the CPU performs unlocking, and when the unlocking is unsuccessful, the CPU performs a step of skipping the current optical module to access the next optical module.

[0074] Specifically, the lock of the SDA signal can be caused by an exception of the current optical module, in this case, if the lock is caused by a timing problem, the fault can be removed by unlocking of the CPU, and if the unlocking is unsuccessful, the SDA can be pulled down by a short circuit or other exceptions, and an alarm needs to be prompted for manual intervention.

[0075] In the application, the CPU performs unlocking, which can specifically include:

[0076] The CPU sends a preset number of clocks for unlocking, where the preset number can be set according to actual needs, and the preset number can be set to 9 as an example.

[0077] The application can skip the current optical module by the CPU to perform software isolation of the current optical module through this embodiment.

[0078] In one of the embodiments, the method can further include:

[0079] When the access fails and the signal state of the I2C bus is not locked, the CPU re-sends the access instruction to the current optical module.

[0080] When the access fails and the access times reach the preset times, the CPU performs the step of skipping the current optical module to access the next optical module.

[0081] In the application, when the I2C bus receives the start signal in the data transmission process, the data transmission is started, that is, when the SCL is high, the SDA jumps from high to low to start the data transmission. When the end signal is received, the data transmission is ended, that is, when the SCL is high, the SDA jumps from low to high to end the data transmission. When the response signal is received, it is determined that the access is successful. Specifically,

[0082] After the current optical module receives the 8-bit data, a specific low-level pulse is sent to the CPU to indicate that the data has been received. After the CPU sends a signal to the current optical module, it waits for a response signal from the current optical module. After the CPU receives the response signal, it determines whether to continue to send the signal according to the actual situation. If the response signal is not received, it is determined that the access fails and the access circuit is abnormal.

[0083] Further, when the CPU determines that the access fails, the signal state of the I2C bus is obtained. According to the signal state of the I2C bus, it is determined whether the I2C bus is locked. When it is determined that the I2C bus is not locked, the access is re-initiated. When the access times reach the preset times, the step of skipping the current optical module to access the next optical module is performed.

[0084] In the application, if the access is not successful, the I2C bus is not locked, and the access is not successful for multiple times, it can be determined that the current optical module itself may be abnormal. At this time, the CPU skips the current optical module to access the next optical module, and an alarm prompt is given to the current optical module, so that the software isolation of the current optical module is realized.

[0085] In one of the embodiments, the optical module I2C circuit further includes a Switch connected with each optical module. The CPU skips the current optical module to access the next optical module and gives an alarm prompt to the current optical module. Before the method further includes:

[0086] The CPU controls the reset and un-reset of the switch to release the I2C bus between the switch and the CPU;

[0087] The CPU creates an exception mark for the current optical module and skips the current optical module to access the next optical module according to the exception mark.

[0088] In the present application, the switch is used to expand one I2C bus into multiple buses. In the present application, the switch can adopt the PCA9548 chip of the NXP company. The chip is an expansion device of the I2C bus. Through the chip, one I2C bus can be expanded into 8 buses. After corresponding configuration of the internal control register, one or multiple downstream I2C buses can be simultaneously selected to be connected with the upstream I2C bus to realize expansion. The PCA9548 in the present application is an 8-channel I2C-bus switch with a reset pin. The upstream connection is connected with the CPU through the I2C bus, and the downstream 8 channels are connected with 8 optical modules.

[0089] In the present application, after the CPU controls the reset and un-reset of the switch, all channels of the switch downstream are closed, the I2C bus between the switch and the CPU is released, and the normal operation of the I2C bus by the CPU is restored.

[0090] Further, the CPU marks the current optical module as an exception. After the I2C bus between the switch and the CPU is released, the CPU skips the current optical module and continues to access other optical modules downstream of the switch through the released I2C bus.

[0091] In the present application, through the above-mentioned embodiment, after the reset and un-reset of the switch, the I2C bus between the switch and the CPU is released, and the current optical module is marked as an exception. Based on the above two reasons, the CPU can skip the current optical module to continue to access other optical modules downstream of the switch, realize software isolation of the current optical module with exception, and do not affect the normal access of other optical modules.

[0092] In one of the embodiments, the above-mentioned method can further include:

[0093] The CPU controls the lighting of the indicator corresponding to the current optical module; and / or

[0094] The CPU generates a prompt information according to the exception mark and the lock state of the SCL state in the signal state of the I2C bus, and prints the prompt information through the serial port; and / or

[0095] The CPU stores the prompt information in the form of a log in the local.

[0096] In the present application, when the CPU monitors that the access of the current optical module is abnormal, if the SCL is locked, the reset and the reset switch are executed, and an alarm is given at the same time. If the SDA is locked, the unlocking is executed, and if the unlocking is unsuccessful, the reset and the reset switch are executed, and an alarm is given at the same time.

[0097] Further, the form of the alarm executed by the CPU in the present application includes:

[0098] The light is turned on, the prompt information is printed, and / or the prompt information is stored in the local in the form of a log.

[0099] In the present application, the related personnel can be prompted to find the problem in time and handle the problem through the light. The related personnel can be shown the detailed information of the abnormality in time through the serial port printing prompt information, so as to locate the problem and solve the problem faster. The related personnel can check the abnormal information through the storage of the prompt information in the local in the form of a log.

[0100] In one embodiment, the above-mentioned switch can include a plurality of switches, each switch being connected to an isolation circuit, a power supply and a plurality of optical modules, and the above-mentioned method further includes:

[0101] When a short circuit occurs in the power supply domain of one target switch and the corresponding optical modules, the isolation circuit connected to the target switch is used to isolate the power supply domain of the target switch from the power supply domains of other switches, so that the CPU skips the optical modules in the power supply domain of the target switch and accesses the optical modules connected to other switches.

[0102] In the present application, the optical module I2C circuit can include a plurality of switches. The downstream of each switch is connected to a plurality of optical modules, and the link in which each switch is located includes a power supply and an isolation circuit.

[0103] The isolation circuit is composed of two MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide semiconductor field-effect transistor, abbreviated as metal-oxide semiconductor field-effect transistor). The isolation circuit is built by MOS, placed in front of the I2C switch, and isolates the I2C switch and the I2C bus. If an abnormality occurs, it does not affect the access of other I2C switches.

[0104] The isolation circuit is used for isolating the power supply of the CPU and the power supply of the optical module to prevent electric leakage, and is also used for isolating the power supply domain of the current optical module and the power supply domain of other optical modules to prevent the access of other optical modules from being affected when the power supply of the current optical module is short-circuited.

[0105] Please refer to Figure 3 , Figure 3 In an embodiment, an optical module I2C circuit diagram is provided. In Figure 3 , the optical module I2C circuit includes a plurality of switches, each switch being connected with eight optical modules, each switch being connected with an isolation circuit and a power supply, and a CPU being connected with the switches through an I2C bus. Figure 3 In addition, a CPLD is also included, which is connected with the CPU through a control bus. The CPLD includes an I2C monitoring logic module, an I2C reset logic module and an I2C state register.

[0106] The I2C monitoring logic module is used for monitoring the signal state of the I2C bus in real time and recording the last I2C data, and analyzing the last I2C data to obtain analyzed data, which can include the identification information of the last accessed optical module and the channel to which the I2C switch is switched, and storing the analyzed data and the signal state of the I2C bus into the I2C state register. Further, the I2C reset logic module includes a reset register, and the CPU controls the reset and reset of the switch by writing the value of the reset register.

[0107] The I2C reset logic module is used for resetting the I2C switch after the I2C is locked, and provides the I2C switch reset register for the CPU.

[0108] The I2C state register is used for state indication, and mainly includes the I2C bus state (whether the SCL and SDA signals are locked), the last I2C switch channel access record and the I2C switch reset record.

[0109] In a possible application scenario, please refer to Figure 4 , Figure 4 In an embodiment, a flowchart of an abnormality processing method of an optical module I2C circuit is provided. In Figure 4 , the abnormality processing method of the optical module I2C circuit can include the following steps:

[0110] S42, the CPU sends an instruction for accessing the information of the current optical module.

[0111] S43, CPLD real-time monitoring I2C signal state, and record the last I2C data.

[0112] S44, the recorded data is analyzed, including the last time which optical module is accessed, I2C

[0113] Switch to which channel, determine whether the SCL signal and SDA signal appear lock, etc. And store these information in I2C state register.

[0114] S45, CPU determines whether the access optical module is successful, if the access is successful, the access operation ends.

[0115] S46, if the access fails, the CPU reads the I2C state register.

[0116] S47, according to the value of I2C state register to determine whether the I2C bus is locked.

[0117] S48, if the I2C bus is not locked, determine whether the access times reaches 3 times, if not, jump to step S42 to re-access.

[0118] If the access times reaches 3 times, jump to step S53 to execute write CPLD register to execute a reset and reset operation for corresponding I2C Switch.

[0119] S49, if the I2C bus is locked, determine whether it is SCL signal lock, if so, jump to step S53 to execute write CPLD register to execute a reset and reset operation for corresponding I2C Switch.

[0120] S50, if the SCL signal is not locked, it is SDA signal lock.

[0121] S51, CPU sends 9 clock software unlock.

[0122] S52, determine whether the unlock is successful, when the unlock is successful, the process ends.

[0123] When the unlock is not successful, S53 is executed.

[0124] S53, write CPLD register to execute a reset and reset operation for corresponding I2C Switch.

[0125] S54, after the reset operation is executed, the CPU alarms and performs software isolation for corresponding optical module (record abnormal optical module position, temporarily skip access later), so as to manual processing according to the alarm prompt.

[0126] In another embodiment, the step S50 can be:

[0127] If the SCL signal is not locked, it is determined whether the SDA signal is locked.

[0128] If the SDA signal is locked, the step S51 is executed.

[0129] If the SDA signal is not locked, it is determined that it is a problem of the optical module itself, and the result is printed in the form of a prompt message through the serial port to prompt manual processing.

[0130] In a possible application scenario, the CPU in the present application can be Xeon-D of Intel Corporation

[0131] D1527, connected to the I2C isolation circuit through the I2C connection, connected to the CPLD through the I2C connection.

[0132] The isolation circuit described above can use the MOS tube L2N7002SLT1G of LRC company to build, and isolate the I2C switch and the CPU.

[0133] The I2C switch described above can be PCA9548 of NXP company, which is an 8-channel I2C-bus switch with a reset pin. The upstream is connected to the I2C isolation circuit, and the downstream 8 channels are connected to 8 optical modules.

[0134] The CPLD described above can be LCMXO2-2000HC-4TG100C of Lattice company, which is interconnected with the CPU through the control bus and monitors the I2C signal of the I2C switch and connects the reset signal of the I2C switch.

[0135] The I2C monitoring logic module described above is a logic module implemented by the CPLD, which monitors the I2C signal state in real time, records the latest I2C data and analyzes it, and determines whether the SCL signal and the SDA signal are locked.

[0136] The I2C reset logic module described above is a logic module implemented by the CPLD, which provides the CPU with a register to reset the I2C switch.

[0137] The I2C state register described above is a logic module implemented by the CPLD, which provides a register for the CPU to indicate the I2C signal state.

[0138] In one embodiment, as Figure 5As shown, the abnormality processing device of the optical module I2C circuit is provided, the optical module I2C circuit comprises a CPU and at least one optical module, the CPU is connected with each optical module through an I2C bus, and the device comprises a sending module 11, an acquisition module 12 and a processing module 13, wherein:

[0139] The sending module 11 is used for sending an access instruction by the CPU to a current optical module;

[0140] The acquisition module 12 is used for acquiring a signal state of the I2C bus by the CPU when the access fails;

[0141] The processing module 13 is used for skipping, by the CPU, the current optical module to access a next optical module and performing an alarm prompt on the current optical module when the SCL in the signal state of the I2C bus is in a lock state.

[0142] In one embodiment, the optical module I2C circuit further comprises a CPLD connected with the CPU, the CPLD is further connected with the I2C bus, the acquisition module 12 can monitor the signal state of the I2C bus in real time by the CPLD, and the signal state of the I2C bus is stored into an I2C state register, the CPU reads the I2C state register to acquire the signal state of the I2C bus, or the CPLD reports an abnormality information to the CPU when the signal state of the I2C bus is monitored to be in a lock state.

[0143] In one embodiment, the signal state of the I2C bus further comprises a signal state of SDA, and the device further comprises an unlocking module (not shown in the figure), which can execute unlocking by the CPU when the signal state of SDA is in a lock state, and execute the step of skipping, by the CPU, the current optical module to access the next optical module when the unlocking is unsuccessful.

[0144] In one embodiment, the sending module 11 can further send, by the CPU, the access instruction to the current optical module again when the access fails and the signal state of the I2C bus is not in a lock state, and execute the step of skipping, by the CPU, the current optical module to access the next optical module when the access fails and the access times reach a preset number.

[0145] In one embodiment, the optical module I2C circuit further comprises a Switch connected with each optical module, the Switch is connected with the CPU through the I2C bus, and the device further comprises a reset module (not shown in the figure) before the CPU skips the current optical module to access the next optical module and performs the alarm prompt on the current optical module, the reset module can reset and de-reset the Switch by the CPU to release the I2C bus between the Switch and the CPU, the CPU creates an abnormality mark for the current optical module, and skips the current optical module to access the next optical module according to the abnormality mark.

[0146] In one of the embodiments, the device further comprises an alarm module (not shown in the figure), which can control the CPU to light up the indicator corresponding to the current optical module, and / or the CPU generates a prompt message according to the abnormal flag and the SCL state of the I2C bus signal state being locked, prints the prompt message through the serial port, and / or the CPU stores the prompt message in the form of a log locally.

[0147] In one of the embodiments, the Switches include a plurality of Switches, each of which is connected to an isolation circuit, a power supply and a plurality of optical modules, and the device further comprises an isolation module (not shown in the figure), which can isolate the power supply domain of the target Switch from the power supply domains of other Switches through the isolation circuit connected to the target Switch when a short circuit occurs in the power supply domain to which the target Switch and the corresponding optical modules belong, so that the CPU skips the optical modules in the power supply domain of the target Switch and accesses the optical modules connected to other Switches.

[0148] In one embodiment, a computer device, which can be a server, is provided, and an internal structure diagram of the computer device can be as shown in Figure 6 The computer device includes a processor, a memory, a network interface and a database connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is configured to store running data of smart home devices and other data. The network interface of the computer device is configured to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement the abnormal processing method of the optical module I2C circuit.

[0149] In one embodiment, a computer device is provided, which includes a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented: the CPU sends an access instruction to a current optical module; when the access fails, the CPU acquires the signal state of the I2C bus; when the SCL of the I2C bus signal state is locked, the CPU skips the current optical module to access the next optical module and alarms the current optical module.

[0150] In one embodiment, the optical module I2C circuit further comprises a CPLD connected to the CPU, and the CPLD is further connected to the I2C bus. When the processor executes the computer program to implement the step of the CPU acquiring the signal state of the I2C bus, the following steps are implemented:

[0151] The CPLD monitors the signal state of the I2C bus in real time and stores the signal state of the I2C bus into an I2C state register;

[0152] The CPU reads the I2C state register to obtain the signal state of the I2C bus; or

[0153] When the CPLD monitors that the signal state of the I2C bus is a lock state, the CPLD reports an exception information to the CPU.

[0154] In an embodiment, the signal state of the I2C bus further includes a signal state of SDA, and when the processor executes the computer program, the following steps are further implemented:

[0155] When the signal state of SDA is a lock state, the CPU performs unlocking, and when the unlocking is unsuccessful, the CPU performs a step of skipping the current optical module to access a next optical module.

[0156] In an embodiment, when the processor executes the computer program, the following steps are further implemented:

[0157] When the access fails and the signal state of the I2C bus is not locked, the CPU re-sends an access instruction to the current optical module;

[0158] When the access fails and the access times reach a preset number of times, the CPU performs a step of skipping the current optical module to access a next optical module.

[0159] In an embodiment, the optical module I2C circuit further includes a Switch connected with each optical module, and the Switch is connected with the CPU through the I2C bus, and when the processor executes the computer program to implement the step of the CPU skipping the current optical module to access a next optical module and the step of the CPU alarming and prompting the current optical module, the following steps are further implemented:

[0160] The CPU controls the Switch to reset and un-reset to release the I2C bus between the Switch and the CPU;

[0161] The CPU creates an exception mark for the current optical module and skips the current optical module to access a next optical module according to the exception mark.

[0162] In an embodiment, when the processor executes the computer program, the following steps are further implemented:

[0163] The CPU controls an indicator light corresponding to the current optical module to be lighted; and / or

[0164] The CPU generates a prompt information according to the exception mark and the signal state of the I2C bus, and prints the prompt information through a serial port; and / or

[0165] The CPU stores the prompt information in the form of a log in the local.

[0166] In one embodiment, the above-mentioned Switches include a plurality of Switches, each of which is connected to an isolation circuit, a power supply and a plurality of optical modules, and when the processor executes the computer program, the following steps are further implemented:

[0167] When a short circuit occurs in the power supply domain to which one of the target Switches and the corresponding optical modules belong, the isolation circuit connected to the target Switch isolates the power supply domain to which the target Switch belongs from the power supply domains to which the other Switches belong, so that the CPU skips the optical modules in the power supply domain to which the target Switch belongs and accesses the optical modules connected to the other Switches.

[0168] In one embodiment, a computer-readable storage medium is provided, and the computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the following steps are implemented: the CPU sends an access instruction to a current optical module; when the access fails, the CPU obtains a signal state of an I2C bus; when the SCL in the signal state of the I2C bus is in a lock state, the CPU skips the current optical module and accesses a next optical module, and the CPU prompts an alarm to the current optical module.

[0169] In one embodiment, the above-mentioned optical module I2C circuit further includes a CPLD connected to the CPU, and the above-mentioned CPLD is further connected to the I2C bus. When the computer program is executed by the processor to implement the step of obtaining the signal state of the I2C bus by the CPU, the following steps are further implemented:

[0170] The CPLD monitors the signal state of the I2C bus in real time and stores the signal state of the I2C bus in an I2C state register;

[0171] The CPU reads the I2C state register to obtain the signal state of the I2C bus; or

[0172] When the CPLD monitors that the signal state of the I2C bus is in a lock state, the CPLD reports abnormal information to the CPU.

[0173] In one embodiment, the signal state of the above-mentioned I2C bus further includes a signal state of SDA, and when the computer program is executed by the processor, the following steps are further implemented:

[0174] When the signal state of SDA is in a lock state, the CPU performs unlocking, and when the unlocking is unsuccessful, the CPU performs the step of skipping the current optical module and accessing the next optical module.

[0175] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0176] When the access fails and the signal state of the I2C bus is not locked, the CPU re-sends an access instruction to the current optical module;

[0177] When the access fails and the number of access reaches a preset number, the CPU executes a step of skipping the current optical module to access the next optical module.

[0178] In an embodiment, the optical module I2C circuit further comprises a Switch connected with each optical module, and the Switch is connected with the CPU through the I2C bus. Before the CPU skips the current optical module to access the next optical module and the CPU gives an alarm prompt to the current optical module, the computer program executed by the processor further implements the following steps:

[0179] The CPU controls the Switch to reset and un-reset, so as to release the I2C bus between the Switch and the CPU;

[0180] The CPU creates an exception mark for the current optical module, and skips the current optical module to access the next optical module according to the exception mark.

[0181] In an embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0182] The CPU controls an indicator corresponding to the current optical module to light up; and / or

[0183] The CPU generates a prompt information according to the exception mark and the SCL state being the locked state in the signal state of the I2C bus, and prints the prompt information through the serial port; and / or

[0184] The CPU stores the prompt information in the form of a log in the local.

[0185] In an embodiment, the Switches include a plurality of Switches, each Switch is connected with an isolation circuit, a power supply and a plurality of optical modules. When the computer program is executed by the processor, the following steps are further implemented:

[0186] When short circuit occurs in a target Switch and the corresponding power supply domain of each optical module, the isolation circuit connected with the target Switch isolates the power supply domain of the target Switch from the power supply domains of other Switches, so that the CPU skips each optical module in the power supply domain of the target Switch to access each optical module connected with other Switches.

[0187] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0188] Any combination of the technical features of the above embodiments can be made, and in order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the description.

[0189] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A method for handling anomalies in an optical module I2C circuit, characterized in that, The optical module I2C circuit includes a CPU and at least one optical module. The CPU is connected to each optical module via an I2C bus. The optical module I2C circuit also includes multiple switches and multiple isolation circuits. The CPU is connected to the isolation circuits, each isolation circuit is connected to a corresponding switch, and each switch is also connected to a corresponding power supply and multiple optical modules. The isolation circuits are composed of MOSFETs. The method includes: The CPU sends an access command to the current optical module; When an access fails, the CPU acquires the signal status of the I2C bus; When the SCL signal state of the I2C bus is locked, the CPU skips the current optical module and accesses the next optical module, and issues an alarm to the current optical module. When a short circuit occurs in the power domain of one of the target switches and the corresponding optical module, the power domain of the target switch is isolated from the power domain of other switches through the isolation circuit connected to the target switch, so that the CPU can skip the optical module in the power domain of the target switch and access the optical module connected to other switches. The signal states of the I2C bus also include the signal states of SDA, and the method further includes: When the signal state of the SDA is locked, the CPU performs unlocking. If unlocking fails, the CPU performs the step of skipping the current optical module and accessing the next optical module.

2. The method according to claim 1, characterized in that, The optical module I2C circuit also includes a CPLD connected to the CPU, and the CPLD is also connected to the I2C bus. The CPU acquires the signal status of the I2C bus, including: The CPLD monitors the signal status of the I2C bus in real time and stores the signal status of the I2C bus in the I2C status register; The CPU reads the I2C status register to obtain the signal status of the I2C bus; or When the CPLD detects that the I2C bus signal status is locked, it reports the abnormal information to the CPU.

3. The method according to claim 1, characterized in that, The method further includes: When the access fails and the signal state of the I2C bus is not locked, the CPU resends the access command to the current optical module. When an access fails and the number of access attempts reaches a preset number, the CPU executes the step of skipping the current optical module and accessing the next optical module.

4. The method according to claim 1, characterized in that, Before the CPU skips the current optical module and accesses the next optical module, the method further includes: The CPU controls the Switch to reset and de-reset in order to release the I2C bus between the Switch and the CPU; The CPU creates an anomaly flag for the current optical module and skips the current optical module to access the next optical module based on the anomaly flag.

5. The method according to claim 4, characterized in that, The CPU provides an alarm notification to the current optical module, including: The CPU controls the indicator light corresponding to the current optical module to illuminate; and / or The CPU generates a prompt message based on the exception flag and the SCL state being locked in the I2C bus signal status, and prints the prompt message via the serial port; and / or The CPU stores the prompt information locally in the form of a log.

6. An anomaly handling device for an optical module I2C circuit, characterized in that, The optical module I2C circuit includes a CPU and at least one optical module. The CPU is connected to each optical module via an I2C bus. The optical module I2C circuit also includes multiple switches and multiple isolation circuits. The CPU is connected to the isolation circuits, each isolation circuit is connected to a corresponding switch, and each switch is also connected to a corresponding power supply and multiple optical modules. The isolation circuits are composed of MOSFETs. The device includes: The transmitting module is used by the CPU to send an access command to the current optical module; An acquisition module is used for the CPU to acquire the signal status of the I2C bus when an access failure occurs; The processing module is configured to, when the clock signal line of the I2C bus is locked, allow the CPU to skip the current optical module and access the next optical module, and issue an alarm to the current optical module. When a short circuit occurs in the power domain of a target switch and its corresponding optical module, the CPU isolates the power domain of the target switch from other switches via an isolation circuit connected to the target switch, allowing the CPU to skip optical modules within the target switch's power domain and access optical modules connected to other switches. The I2C bus signal state also includes the SDA signal state. The processing module is further configured to... When the signal state of the SDA is locked, the CPU performs unlocking. If unlocking fails, the CPU performs the step of skipping the current optical module and accessing the next optical module.

7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

Images