Logical address allocation method and device, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure provide a logical address allocation method and device, electronic equipment and storage medium. A first request is received from a target virtual machine unit, the first request being used to register a logical address of a submission queue item of the target virtual machine unit. A first hash value is obtained by performing a hash operation based on the first request, the first hash value being used to indicate the submission queue item. A target hash table corresponding to the target virtual machine unit is obtained, and the target hash table is queried based on the first hash value to obtain a target hash bucket to which the first hash value belongs. A target logical address corresponding to a hash bucket identifier of the target hash bucket is obtained from currently available logical addresses based on the hash bucket identifier. The target logical address is registered as a logical address corresponding to the generated submission queue item. The method achieves fast registration of the logical address of the submission queue item, improves the allocation efficiency of the logical address, and reduces resource occupation in the logical address allocation process.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of data storage, and particularly relate to a logical address allocation method and device, an electronic device, and a storage medium. BACKGROUND

[0002] Device virtualization plays a very important role in the development of cloud computing. In the prior art, when one or more non-volatile memory host controller interface specification (NVM Express, NVMe) storage media provide storage space for virtual machine units, a central processing unit (DPU) based on a linked list uniformly manages the logical addresses of multiple virtual machine units, thereby realizing logical mapping of virtual machines to storage media.

[0003] However, the prior art scheme of allocating logical addresses of virtual machine units through a linked list has the problems of low efficiency and high resource occupation. SUMMARY

[0004] Embodiments of the present disclosure provide a logical address allocation method and device, an electronic device, and a storage medium to overcome the problems of low efficiency and high resource occupation in the logical address allocation process.

[0005] In a first aspect, embodiments of the present disclosure provide a logical address allocation method, comprising:

[0006] receiving a first request sent by a target virtual machine unit, the first request being used to register a logical address of a submission queue item of the target virtual machine unit; performing a hash operation based on the first request to obtain a first hash value, the first hash value being used to indicate the submission queue item; obtaining a target hash table corresponding to the target virtual machine unit, and querying the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs; based on a hash bucket identifier of the target hash bucket, obtaining a target logical address corresponding to the hash bucket identifier from currently available logical addresses; and registering the target logical address as a logical address corresponding to the submission queue item.

[0007] In a second aspect, embodiments of the present disclosure provide a logical address allocation device, comprising:

[0008] a receiving module configured to receive a first request sent by a target virtual machine unit, the first request being used to register a logical address of a submission queue item of the target virtual machine unit;

[0009] a computing module configured to perform a hash operation based on the first request to obtain a first hash value;

[0010] The first distribution module is configured to obtain a target hash table corresponding to the target virtual machine unit, and query the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs;

[0011] The second distribution module is configured to obtain a target logical address corresponding to a hash bucket identifier of the target hash bucket from currently available logical addresses based on the hash bucket identifier, and register the target logical address as a logical address corresponding to the submission queue entry.

[0012] In a third aspect, an electronic device is provided, and the electronic device comprises:

[0013] a processor, and a memory connected with the processor in communication;

[0014] The memory stores computer-executed instructions.

[0015] The processor executes the computer-executed instructions stored in the memory to implement the logical address distribution method as described in the first aspect and various possible designs of the first aspect.

[0016] In a fourth aspect, a computer-readable storage medium is provided, and the computer-readable storage medium stores computer-executed instructions. When a processor executes the computer-executed instructions, the logical address distribution method as described in the first aspect and various possible designs of the first aspect is implemented.

[0017] In a fifth aspect, a computer program product is provided, and the computer program product comprises a computer program. When a processor executes the computer program, the logical address distribution method as described in the first aspect and various possible designs of the first aspect is implemented.

[0018] The logical address allocation method, apparatus, electronic device, and storage medium provided in this embodiment receive a first request sent by a target virtual machine unit, the first request being used to register the logical address of a submission queue entry of the target virtual machine unit; perform a hash operation based on the first request to obtain a first hash value, the first hash value being used to indicate the submission queue entry; obtain a target hash table corresponding to the target virtual machine unit, and query the target hash table based on the first hash value to obtain the target hash bucket to which the first hash value belongs; based on the hash bucket identifier of the target hash bucket, obtain the target logical address corresponding to the hash bucket identifier from the currently available logical addresses; and register the target logical address as the logical address corresponding to the submission queue entry. By performing hash calculation in response to the first request to obtain a first hash value representing the submission queue entry, and then sequentially mapping the first hash value to the target hash bucket, and from the target hash bucket to the target logical address corresponding to the submission queue entry, the table lookup method based on hash mapping is more efficient than the linked list lookup method, and does not require additional storage space to store linked list data. Therefore, it achieves fast registration of the logical address of the submission queue entry, improves the allocation efficiency of logical addresses, and reduces the resource consumption in the logical address allocation process. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 An application scenario diagram of the logical address allocation method provided in the embodiments of this disclosure;

[0021] Figure 2 A flowchart illustrating the logical address allocation method provided in the embodiments of this disclosure. Figure 1 ;

[0022] Figure 3 for Figure 2 A flowchart illustrating the specific implementation of step S102 in the illustrated embodiment;

[0023] Figure 4 A schematic diagram of a data structure for a first request provided in an embodiment of this disclosure;

[0024] Figure 5 A flowchart illustrating the logical address allocation method provided in the embodiments of this disclosure. Figure 2 ;

[0025] Figure 6This is a schematic diagram illustrating a process for determining a hash bucket identifier provided in this disclosure;

[0026] Figure 7 A schematic diagram of bitmap data provided in an embodiment of this disclosure;

[0027] Figure 8 A schematic diagram illustrating a process for processing submission queue entries provided in an embodiment of this disclosure;

[0028] Figure 9 A flowchart illustrating the logical address allocation method provided in the embodiments of this disclosure. Figure 3 ;

[0029] Figure 10 for Figure 9 A flowchart illustrating the specific implementation of step S306 in the illustrated embodiment;

[0030] Figure 11 for Figure 10 A flowchart illustrating the specific implementation of step S3063 in the illustrated embodiment;

[0031] Figure 12 A schematic diagram illustrating a process for processing completed queue entries provided in an embodiment of this disclosure;

[0032] Figure 13 A structural block diagram of the logical address allocation device provided in the embodiments of this disclosure;

[0033] Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure;

[0034] Figure 15 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0036] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present disclosure are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of countries and regions, and provide corresponding operation portal for user to choose authorization or refusal.

[0037] The application scenarios of the embodiments of the present disclosure are explained as follows:

[0038] Figure 1 An application scenario diagram of the logical address allocation method provided by the embodiments of the present disclosure, the logical address allocation method provided by the embodiments of the present disclosure can be applied to distributed computing, virtual machine management, running and other application scenarios. Specifically, the method provided by the embodiments of the present disclosure can be applied to a central processing unit distributed processing unit (DPU, hereinafter referred to as distributed processing unit) or an electronic device including a distributed processing unit, such as a virtual machine server. Referring to Figure 1 As shown in the figure, the electronic device is provided with a distributed processing unit and a solid state disk (SSD), wherein one end of the distributed processing unit communicates with a plurality of virtual machine units (software units) through a peripheral component interconnect express (PCIe) interface, and the other end communicates with a solid state disk based on an NVMe protocol, wherein the distributed processing unit includes an NVMe controller, and the logical address management and allocation of the virtual machine unit are realized through the NVMe controller, thereby realizing the mapping between the virtual machine unit and the solid state disk, providing independent storage media for the plurality of virtual machine units by the solid state disk, and realizing the flexible configuration of the virtual machine unit.

[0039] In the prior art, for each virtual machine unit, the NVMe controller allocates a corresponding logical address, and specifically, each virtual machine unit corresponds to a namespace, and each namespace can apply for a preset number of logical addresses. When there are N virtual machine units running, the NVMe controller needs to maintain N linked lists to save the address information in the corresponding namespaces. Then, when the NVMe controller receives a submission queue entry (SQE) for a read or write instruction, the NVMe controller allocates a logical address for the submission queue entry, through which the mapping with the physical storage medium can be realized, thereby realizing the execution of the corresponding read or write instruction. However, in actual application, the scheme of allocating addresses for submission queue entries through linked lists is inefficient in searching for corresponding logical addresses through linked lists due to the characteristics of linked lists, and the maintenance of linked lists consumes a large amount of storage resources, thus resulting in the problems of low allocation efficiency and high resource occupation. The present embodiment provides a logical address allocation method to solve the above problems.

[0040] Reference Figure 2 , Figure 2 The flowchart of the logical address allocation method provided by the present embodiment Figure 1 The method of the present embodiment can be applied to a distributed processing unit or an electronic device comprising a distributed processing unit, and the logical address allocation method comprises:

[0041] Step S101: receiving a first request sent by a target virtual machine unit, the first request being used to register the logical address of the submission queue entry of the target virtual machine unit.

[0042] Exemplarily, the execution subject of the method provided by the present embodiment can be a distributed processing unit chip or a device comprising the same, such as a network card device, which is referred to as a distributed processing unit in the embodiment. Referring to the application scenario diagram shown in Figure 1 The target virtual machine unit is one of a plurality of virtual machine units communicatively connected to the distributed processing unit, wherein the virtual machine unit refers to a virtual machine program, a computing thread, a computing unit, etc. running in the same electronic device or a plurality of electronic devices, and the virtual machine unit can independently execute operation instructions through the computing core, thread, memory and storage space allocated thereto.

[0043] Further, when a read-write instruction needs to be executed in the target virtual machine, a corresponding logical address needs to be created and registered for the instruction, so as to realize the mapping from the application layer instruction to the physical layer. The execution of the read-write instruction is realized through a submission queue (SQ) and a completion queue (CQ). The submission queue and the completion queue are created in the memory by the distributed processing unit through the NVMe controller. The read-write instruction sent by the virtual machine unit to the storage medium is stored in the submission queue, and then the read-write instruction is obtained from the submission queue by the storage medium. After the storage medium executes the read-write instruction, the executed read-write instruction is stored in the completion queue. The virtual machine unit can determine that the previously sent read-write instruction has been executed by reading the information in the completion queue. The element (instruction information) in the submission queue is a submission queue entry. The element (instruction information) in the completion queue is a completion queue entry. The specific implementation of the submission queue, the completion queue, the submission queue element, and the completion queue element is known to those skilled in the art and will not be described here.

[0044] Further, when the virtual machine unit needs to execute a read-write instruction, it sends a first request to the distributed processing unit to request the distributed processing unit to register a corresponding logical address for the submission queue entry for executing the read-write instruction. For each virtual machine unit, the logical address it has is limited. For example, the logical address corresponding to the virtual machine unit A includes addr_0 to adrr_255. That is, the virtual machine unit A has a maximum of 256 available logical addresses. When the virtual machine unit executes a read-write instruction, it can register one of the 256 available logical addresses as the logical address of the submission queue entry. Then, based on the logical address and the information in the submission queue entry, the corresponding disk physical address can be obtained, so as to complete the execution of the read-write instruction. The process is described in detail in the subsequent steps.

[0045] Step S102: Hash operation is performed based on the first request to obtain a first hash value, which is used to indicate the submission queue entry.

[0046] For example, after the distributed processing unit obtains the first request, a hash operation is performed according to the identification information in the first request, which represents the submission queue entry of the target virtual machine unit, to obtain a hash value indicating the submission queue entry, i.e. a first hash value. In one possible implementation, the first request includes the unit identifier of the target virtual machine unit and the entry identifier of the submission queue entry, such as Figure 3As shown, exemplarily, the specific implementation steps of step S102 include:

[0047] Step S1021: Combine the unit identifier and the entry identifier to obtain the first position identifier.

[0048] Step S1022: Based on the target hash algorithm, process the first position identifier to obtain the first hash value.

[0049] Figure 4 This is a schematic diagram of a data structure for a first request provided in an embodiment of this disclosure, such as... Figure 4 As shown, the d1 field of the first request stores the unit identifier dev_1 of the virtual machine unit (shown as dev_1 in the figure), while the d2 field of the first request stores the entry identifier info_1 of the submission queue entry (shown as info_1 in the figure). Further, exemplaryly, the entry identifier info_1 can be a unique identifier generated based on the system time for the submission queue entry, or it can be a set of information such as the operation type, data length, and starting disk address corresponding to the aforementioned submission queue entry. By combining the unit identifier dev_1 in the d1 field and the entry identifier info_1 in the d2 field, for example, by concatenating the characters corresponding to dev_1 and info_1, the first position identifier [dev_1, info_1] is obtained. Of course, in other possible implementations, the first position identifier can be generated by further combining other information, for example, by further combining the reference information info_2 in the d3 field (not shown in the figure) to generate the first position identifier [dev_1, info_1, info_2], thereby achieving a more accurate representation of the submission queue entry. Then, the first position identifier is used as the hash input value (i.e., the key value), and a hash operation is performed (shown as hash(pos_1) in the figure). The hash operation result is the first hash value.

[0050] Step S103: Obtain the target hash table corresponding to the target virtual machine unit, and query the target hash table based on the first hash value to obtain the target hash bucket to which the first hash value belongs.

[0051] Step S104: Based on the hash bucket identifier of the target hash bucket, obtain the target logical address corresponding to the hash bucket identifier from the currently available logical addresses.

[0052] Exemplarily, after receiving the first request sent by the target virtual machine unit, a hash value is obtained based on the identification information in the first request, and the position of the first hash value is determined by querying the target hash table. Specifically, first, the unit identifier representing the target virtual machine unit in the first request is used to determine the target hash table corresponding to the target virtual machine unit, wherein each virtual machine unit corresponds to a hash table. Through the unit identifier and the preset mapping relationship, a unique hash table, i.e., the target hash table, can be obtained. The target hash table represents the mapping relationship between the virtual machine unit and the corresponding hash bucket, i.e., the mapping relationship between the unit identifier of the virtual machine unit and the hash bucket identifier of the target hash bucket. The hash bucket identifier represents the target hash bucket to which the first hash value belongs. The hash bucket is a set of hash values, and the target hash bucket includes the first hash value. Further, the hash bucket is a data structure composed of multiple hash slots, and the hash values are stored in the hash slots in the hash bucket, thereby realizing a many-to-one hash mapping relationship and mapping multiple hash values to the same logical address.

[0053] Further, after querying the target hash table by the first hash value, the target hash bucket is obtained, and then, based on the hash bucket identifier of the target hash bucket, an available logical address, i.e., a target logical address, is allocated to the target hash bucket from the currently available logical addresses.

[0054] Step S105: Register the target logical address as the logical address corresponding to the generated commit queue entry.

[0055] Exemplarily, further, after obtaining the target logical address, the target logical address is registered as the target logical address of the commit queue entry, thereby realizing the logical address allocation of the commit queue entry corresponding to the first request. On the one hand, after obtaining the first hash value through hash calculation, the uniqueness of the target logical address corresponding to the commit queue entry can be guaranteed based on the first hash value (in the case of no hash conflict), thereby ensuring the effectiveness of the target logical address. On the other hand, the processing unit can quickly obtain the logical address corresponding to the first hash value by querying the hash table, thereby realizing the purpose of quickly and efficiently allocating the target logical address to the commit queue entry. Compared with the scheme of using a linked list to allocate logical addresses in the prior art, the address allocation efficiency can be effectively improved and the storage space occupation can be reduced.

[0056] In the embodiment, a first request sent by a target virtual machine unit is received, the first request being used for registering a logical address of a submission queue item of the target virtual machine unit; a first hash value is obtained by performing a hash operation based on the first request, the first hash value being used for indicating the submission queue item; and a target logical address corresponding to the submission queue item is generated based on the first hash value. The first hash value representing the submission queue item is obtained by performing the hash calculation in response to the first request, and the target logical address corresponding to the submission queue item is mapped based on the first hash value. Since the hash table lookup method is more efficient than the linked list query method, and no additional storage space is required to store the linked list data, the logical address of the submission queue item is quickly registered, the allocation efficiency of the logical address is improved, and the resource occupation in the logical address allocation process is reduced.

[0057] Reference Figure 5 , Figure 5 Flowchart of a logical address allocation method provided by an embodiment of the present disclosure Figure 2 The embodiment is based on the embodiment shown in Figure 2 On the basis of the embodiment shown in

[0058] Step S201: receiving a first request sent by a target virtual machine unit, the first request being used for registering a logical address of a submission queue item of the target virtual machine unit.

[0059] Step S202: obtaining a target hash table corresponding to the target virtual machine unit.

[0060] Step S203: obtaining a first hash value according to the first request, and determining a corresponding hash bucket identifier according to the first hash value and the target hash table, the hash bucket identifier representing a target hash bucket to which the first hash value belongs.

[0061] Exemplarily, reference is made to Figure 2In the embodiment shown, after receiving the first request sent by the target virtual machine unit, the relevant step is to perform hash calculation and table lookup based on the identification information in the first request. Specifically, first, the unit identifier representing the target virtual machine unit in the first request is used to determine the target hash table corresponding to the target virtual machine unit, wherein each virtual machine unit corresponds to a hash table. Through the unit identifier and a preset mapping relationship, a unique hash table, i.e., the target hash table, can be obtained. The target hash table represents the mapping relationship between the virtual machine unit and the corresponding hash bucket, i.e., the mapping relationship between the unit identifier of the virtual machine unit and the hash bucket identifier of the target hash bucket. The hash bucket identifier represents the target hash bucket to which the first hash value belongs. The hash bucket is a collection of hash values, and the target hash bucket is the hash bucket containing the first hash value. The hash bucket is a data structure composed of multiple hash slots, and each hash value is mapped to a logical address through the hash values stored in the multiple hash slots in the hash bucket.

[0062] In a possible implementation, the target hash table is a multi-level hash table, which at least includes a first-level hash table and a second-level hash table. According to the first hash value corresponding to the first request, the target hash table is queried, and then at least twice hash mapping is performed, so as to obtain the corresponding hash bucket identifier, thereby further reducing hash conflicts. Figure 6 A process for determining a hash bucket identifier provided by the present disclosure is shown in the schematic diagram Figure 6 As shown, the target hash table includes a first-level hash table hash_0 and a second-level hash table hash_1. The first hash value is used to first query the first-level hash table hash_0, and then the corresponding second-level hash table hash_1 of the first-level hash table hash_0 is used to obtain the corresponding hash bucket identifier target_hash. Then, the corresponding target logical address is obtained from the bitmap data through the hash bucket identifier target_hash. The concept and implementation of the multi-level hash table are prior art, and will not be described here.

[0063] Step S204: Obtain the target logical address corresponding to the submission queue entry according to the hash bucket identifier and the bitmap data, wherein the bitmap data represents a set of currently available logical addresses.

[0064] Exemplarily, further, according to the hash bucket identifier, read bitmap data corresponding to the hash bucket identifier, the bitmap data is a sequence composed of binary numbers (0 and 1) or Boolean values (True and False). Through the bitmap data, the description of the set of currently available logical addresses can be realized. For example, the preset logical address represented by the binary number 0 is occupied, that is, the logical address corresponding to the 0 position is an unusable address; the preset logical address represented by the binary number 1 is not occupied, that is, the logical address corresponding to the 1 position is an available address, more specifically, for example. An 8-bit bitmap data is [00000111]. According to the bitmap data, it can be known that the 5 logical addresses corresponding to the second binary number 0 are occupied, and the 3 logical addresses corresponding to the second binary number 1 are not occupied. Therefore, the bitmap data realizes the function of recording the index of the available logical address. Then, an available logical address, that is, a target logical address, is obtained from the bitmap data corresponding to the hash bucket identifier, as a query response to the first hash value (corresponding to the first request), so as to realize the allocation of the logical address of the submission queue item of the target virtual machine unit.

[0065] Exemplarily, the bitmap data is composed of binary numbers of a target bit number, and the specific implementation manner of step S204 includes:

[0066] Step S2041: detecting a target sequence number of a first target binary number in the bitmap data.

[0067] Step S2042: obtaining a target logical address according to the target sequence number and the hash bucket identifier.

[0068] Exemplarily, the target sequence number is the first target binary number in the bitmap data. Figure 7 A schematic diagram of bitmap data provided by an embodiment of the present disclosure is as follows: Figure 7 The above process is described in detail as follows: Figure 7As shown, the storage unit in the distributed processor stores N hash buckets, and the corresponding hash bucket identifiers are hash_1 to hash_N. Each hash bucket (or hash bucket identifier) corresponds to a bitmap data also stored in the storage unit in the distributed processor, i.e., bitmap data D_1 to bitmap data D_N. After obtaining the hash bucket identifier hash_1 according to the first hash value, the corresponding bitmap data D_1 is obtained based on the hash bucket identifier hash_1. The content in the bitmap data D_1 is [000111], where the binary number "1" represents an occupied logical address, and the binary number "0" represents an unoccupied logical address. In this embodiment, the target binary number is 0. Then, the target sequence number index of the first target binary number is detected from right to left, i.e., index = 4. Further, the first address addr_1 of a logical address is determined according to the hash bucket identifier hash_1, and the final target logical address addr_2 = addr_1 + index is obtained according to the target sequence number index as an address offset. Of course, it can be understood that the above specific implementation manner of obtaining the target logical address according to the target sequence number and the hash bucket identifier is only exemplary, and the specific implementation manner can be set as needed based on the obtained target sequence number and hash bucket identifier, which will not be described herein.

[0069] In this embodiment, since the bitmap data has a smaller volume, the target logical address is obtained by twice calculation based on the index corresponding to the target binary number provided by the bitmap data. Therefore, the position information of the logical address does not need to be stored in the bitmap data, further reducing the storage space occupation and improving the query efficiency and reducing the storage space occupation.

[0070] Optionally, in another possible implementation, after step S203, the method further includes:

[0071] Step S205: detecting a conflict state of the first hash value in the target hash bucket.

[0072] Step S206: when the conflict state is the first state, writing the target sequence number into the hash slot corresponding to the first hash value in the target hash bucket, so as to establish a mapping relationship between the first hash value and the target logical address.

[0073] Step S207: when the conflict state is the second state, buffering the first hash value, so as to establish a mapping relationship between the first hash value and the target logical address after the target time length.

[0074] Exemplarily, after obtaining the first hash value, it is judged whether the first hash value corresponds to a conflict state, i.e., whether the first hash value is already contained in the target hash bucket. Specifically, if the first hash value is not contained in the target hash bucket, the first hash value is not in conflict, i.e., the conflict state is the first state; on the contrary, if the first hash value is already contained in the target hash bucket, the first hash value is in conflict, i.e., the conflict state is the second state.

[0075] Further, the hash bucket is composed of hash slots, i.e., a data structure for storing the first hash value. When the conflict state is the first state, i.e., the hash slot does not store the first hash value, the target logical address obtained by the above step S204 is written into the hash slot corresponding to the first hash value, so as to complete the record of the mapping relationship between the first hash value and the target logical address, i.e., to allocate the corresponding target logical address to the submission queue entry. Then, when the submission queue entry is actually executed, the corresponding target logical address can be obtained by querying the target hash bucket, so as to implement the read-write instruction corresponding to the submission queue entry. On the other hand, when the conflict state is the second state, i.e., the hash slot already stores the first hash value, it is indicated that the target logical address indexed by the first hash value has been stored in the target hash bucket. In this case, since the logical address corresponding to the first hash value is occupied, the target logical address cannot be immediately allocated to the submission queue entry corresponding to the first request. At this time, the first hash value is buffered to the memory, which is equivalent to suspending the first request. After a preset time length or after receiving a trigger instruction, when the occupied logical address is released, the first request is responded again, and the above steps of the embodiment are re-executed until the target logical address is written into the target hash bucket, and the logical address allocation of the submission queue entry corresponding to the first request is completed.

[0076] Figure 8 A process diagram for processing the submission queue entry provided by the embodiment of the present disclosure can be referred to Figure 8 for understanding the above steps. As shown in Figure 8 , first, the submission queue entry (shown as sqe in the figure) is scheduled, and then the hash calculation is performed based on the nsid and sqeid of the submission queue entry, where the nsid is an identifier for the controller to access the namespace (equivalent to the unit identifier of the target virtual machine unit in the embodiment), and the sqeid is a send queue element id, which is globally unique (equivalent to the entry identifier of the submission queue entry in the embodiment). Then, the hash bucket of the corresponding hash table is read, and the hash slot corresponding to the difference value is read. Then, it is judged whether the hash bucket is full. If yes, the submission queue entry is temporarily stored in the bucket, and will be applied later. If not, the position of the corresponding bitmap data is read, the empty position is found, and the position of the bitmap data and the corresponding key are filled into the hash slot of the hash bucket of the hash table.

[0077] In the step of the embodiment, the target logical address is determined by combining the bitmap data, and the target logical address is stored in the corresponding hash slot in the hash bucket, so as to realize the mapping construction of the first hash value and the target logical address, and further realize the logical address allocation of the submission queue item corresponding to the first request. Since the volume of the bitmap data is smaller, and the target logical address is obtained by twice calculation based on the index corresponding to the target binary number provided by the bitmap data, it is not necessary to store the position information of the logical address in the bitmap data, so as to further reduce the occupation of the storage space and improve the allocation efficiency of the logical address.

[0078] Figure 9 Flowchart of the logical address allocation method provided by the embodiment of the present disclosure Figure 3 On the basis of the embodiment shown in Figure 2 On the basis of the embodiment shown in

[0079] Step S301: receiving the first request sent by the target virtual machine unit, the first request being used for registering the logical address of the submission queue item of the target virtual machine unit.

[0080] Step S302: performing hash operation based on the first request to obtain a first hash value, the first hash value being used for indicating the submission queue item.

[0081] Step S303: generating the target logical address corresponding to the submission queue item based on the first hash value.

[0082] Step S304: receiving the second request sent by the virtual machine unit, the second request being used for releasing the logical address of the completion queue item of the virtual machine unit.

[0083] Step S305: performing hash operation based on the second request to obtain a second hash value, the second hash value being used for indicating the completion queue item.

[0084] Step S306: releasing the target logical address corresponding to the completion queue item based on the second hash value.

[0085] By way of example, based on the introduction of the submission queue and the completion queue, the submission queue item in the submission queue and the completion queue item in the completion queue usually appear in pairs, therefore, with reference to the above description, the target logical address corresponding to the submission queue item is released based on the second hash value, and the target logical address corresponding to the completion queue item is released based on the second hash value. Figure 2The receiving target virtual machine unit sends a first request, and the processing unit processes the first request. Similarly, in response to the first request, the processing unit allocates an address for a submission queue entry, and after the read-write instruction corresponding to the submission queue entry is executed, the processing unit needs to generate a corresponding completion queue entry. Accordingly, the processing unit needs to continue processing the completion queue entry, thereby releasing the address corresponding to the completion queue entry. In an example, the completion queue entry in the step and the submission queue entry in the previous step are for the same read-write instruction.

[0086] Further, similarly, after the read-write instruction corresponding to the submission queue entry is executed, the virtual machine unit sends a second request to release the logical address of the completion queue entry. After the processing unit receives the second request, the processing unit performs a hash operation on the second request to obtain a second hash value indicating the completion queue entry. The specific implementation process is similar to the process of calculating the first hash value in the above embodiment, and will not be described here. Then, the second hash value is used to query the target hash table to obtain a target hash bucket storing the target logical address, and the content in the target hash bucket is processed, thereby completing the address release of the corresponding target logical address.

[0087] As shown in an example, Figure 10 The specific implementation of step S306 includes the following steps.

[0088] Step S3061: According to the second hash value and the target hash table corresponding to the target virtual machine unit, a corresponding hash bucket identifier is determined, which represents the target hash bucket to which the first hash value belongs.

[0089] Step S3062: The target hash bucket is searched based on the second hash value to obtain a hit result.

[0090] Step S3063: According to the hit result, the target logical address is obtained, and the target logical address is released.

[0091] Exemplarily, first, a target hash table corresponding to a target virtual machine unit is acquired, and a target hash bucket corresponding to the second hash value is obtained by querying the target hash table and the second hash value; in this embodiment, since the completion queue entry and the submission queue entry in the previous step are directed to the same read-write instruction, the second hash value corresponding to the completion queue entry is the same as the first hash value corresponding to the submission queue entry, and the calculation method of the second hash value corresponding to the queue entry can refer to the calculation method of the first hash value in the previous embodiment, which will not be described here. Then, the target hash bucket is searched based on the second hash value, and a hit result indicating whether the second hash value is stored in the target hash bucket is obtained according to the search result. If the hit result is that the second hash value is stored in the hash slot corresponding to the target hash bucket, the target logical address is obtained by reading the information in the hash slot. Then, on the one hand, the hash slot is emptied and the second hash value (i.e. the first hash value) stored in the hash slot is deleted, and on the other hand, the binary number representing the target logical position in the bitmap data is restored, so as to realize the target logical address.

[0092] Exemplarily, the hit result includes a hash slot identifier, such as Figure 11 As shown in FIG. 13, the specific implementation steps of step S3063 include:

[0093] Step S3063A: obtaining a target sequence number according to the hash slot identifier, the target sequence number representing the position of the logical address corresponding to the completion queue entry in the bitmap data.

[0094] Step S3063B: performing a non-operation on the binary number corresponding to the target sequence number in the bitmap data, and deleting the second hash value stored in the target hash slot corresponding to the hash slot identifier, so as to release the target logical address.

[0095] Exemplarily, when the second hash value hits the corresponding target hash slot (i.e. the second hash value has been stored in the target hash slot), the hash slot identifier of the target hash slot is returned as the hit result. Then, the information in the target hash slot is read based on the hash slot identifier, and the target sequence number can be obtained, that is, the hash value stored in the hash slot and the sequence number representing the position of the logical address corresponding to the hash value in the bitmap data, that is, the target sequence number. The hash value and the sequence number stored in the target hash slot hit by the second hash value are the first hash value and the corresponding target sequence number written in the target hash slot in response to the first request in the above embodiment. For details, please refer to the introduction of the related steps in the embodiments shown in Figure 2 , Figure 5 here.

[0096] Afterwards, on one hand, the target sequence number is taken as a bit number coordinate (for example, 5), and the position of the binary number in the bitmap data corresponding to the target virtual machine unit is reversely located, and the binary number at the position is set to the target binary number (for example, 1) in the previous step due to the allocation of the address for the submission queue entry. At this time, the binary number at the position is taken as a non-operation (namely, 0 is set to 1, and 1 is set to 0), so as to release the logical address previously occupied by the submission queue entry. On the other hand, the target hash slot hit by the second hash value is cleared, namely, the first hash value filled in the hash slot when the logical address is allocated for the submission queue entry is deleted, so as to realize the release of the target logical address.

[0097] Figure 12 A process diagram for processing a completion queue entry provided by an embodiment of the present disclosure is shown in FIG. 4, and the above steps can be understood with reference to the processing process shown in FIG. 5. Figure 12 Figure 12 Figure 12 As shown in FIG. 6, the hash calculation is performed based on the Nsid and Sqeid of the completion queue entry (shown as cqe in the figure), wherein the Nsid is an identifier of the controller for accessing the namespace (equivalent to the unit identifier of the target virtual machine unit in the embodiment); and the Sqeid is a send queue element id, which is globally unique (equivalent to the entry identifier of the completion queue entry in the embodiment). Afterwards, it is judged whether the corresponding hash slot is hit. If hit, the corresponding hash slot is set to 0, and the corresponding position of the bitmap data is set to 0. If not hit, no processing is performed.

[0098] In the embodiment, the steps S301 to S303 are consistent with the implementation manners of the steps S101 to S103 in the above embodiment, and the detailed discussion can be referred to the discussion in the corresponding steps in the embodiments shown in FIG. 7 and FIG. 8, which will not be repeated here. Figure 2 Figure 5

[0099] The logical address allocation method corresponding to the above embodiment, Figure 13 A structural block diagram of a logical address allocation apparatus provided by an embodiment of the present disclosure is shown in FIG. 9. For the convenience of description, only the parts related to the embodiment of the present disclosure are shown. Referring to FIG. 9, the logical address allocation apparatus 4 comprises: Figure 13 A receiving module 41, configured to receive a first request sent by a target virtual machine unit, the first request being used for registering a logical address of a submission queue entry of the target virtual machine unit;

[0100] A calculating module 42, configured to perform hash operation based on the first request to obtain a first hash value;

[0101]

[0102] ​​​​​The first distribution module 43 is configured to obtain a target hash table corresponding to the target virtual machine unit, and query the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs;

[0103] The second distribution module 44 is configured to obtain a target logical address corresponding to the hash bucket identifier from the currently available logical addresses based on the hash bucket identifier of the target hash bucket, and register the target logical address as a logical address generated by the submission queue entry.

[0104] In an embodiment of the present disclosure, the first request includes a unit identifier of the target virtual machine unit and a queue entry identifier of the submission queue entry; the calculation module 42 is specifically configured to: combine the unit identifier and the queue entry identifier to obtain a first location identifier; and process the first location identifier based on a target hash algorithm to obtain a first hash value.

[0105] In an embodiment of the present disclosure, the second distribution module 44 is specifically configured to: obtain bitmap data corresponding to the target virtual machine unit, where the bitmap data is composed of at least two binary numbers arranged in order, and the bitmap data represents a set of currently available logical addresses; and obtain a target logical address corresponding to the hash bucket identifier according to the hash bucket identifier and the bitmap data.

[0106] In an embodiment of the present disclosure, when the second distribution module 44 obtains the target logical address corresponding to the hash bucket identifier according to the hash bucket identifier and the bitmap data, the second distribution module 44 is specifically configured to: detect a target sequence number of a first target binary number in the bitmap data, where the target binary number is used to indicate availability of a logical address; and obtain the target logical address according to the target sequence number and the hash bucket identifier.

[0107] In an embodiment of the present disclosure, the second distribution module 44 is further configured to: detect a conflict state of the first hash value in the target hash bucket; when the conflict state is a first state, write the target sequence number into a hash slot corresponding to the first hash value in the target hash bucket, so as to establish a mapping relationship between the first hash value and the target logical address; and perform a non-operation on a binary number corresponding to the target sequence number in the bitmap data.

[0108] In an embodiment of the present disclosure, the second distribution module 44 is further configured to: detect a conflict state of the first hash value in the target hash bucket; when the conflict state is a second state, buffer the first hash value, so as to establish a mapping relationship between the first hash value and the target logical address after a target time length.

[0109] In an embodiment of the present disclosure, the receiving module 41 is further configured to receive a second request sent by the virtual machine unit, the second request being used to release a logical address of a completion queue entry of the virtual machine unit; the computing module 42 is further configured to perform a hash operation based on the second request to obtain a second hash value, the second hash value being used to indicate the completion queue entry; and the second allocating module 44 is further configured to release a target logical address corresponding to the completion queue entry based on the second hash value.

[0110] In an embodiment of the present disclosure, when the second allocating module 44 releases the target logical address corresponding to the completion queue entry based on the second hash value, the second allocating module 44 is specifically configured to determine a corresponding hash bucket identifier according to the second hash value and a target hash table corresponding to the target virtual machine unit, the hash bucket identifier representing a target hash bucket to which the first hash value belongs; perform a search on the target hash bucket based on the second hash value to obtain a hit result; and obtain the target logical address according to the hit result and release the target logical address.

[0111] In an embodiment of the present disclosure, the hit result includes a hash slot identifier; when the allocating module 43 obtains the target logical address according to the hit result and releases the target logical address, the allocating module 43 is specifically configured to obtain a target sequence number according to the hash slot identifier, the target sequence number representing a position of the logical address corresponding to the completion queue entry in bitmap data; perform a NOT operation on a binary number corresponding to the target sequence number in the bitmap data, and delete the second hash value stored in a target hash slot corresponding to the hash slot identifier, so as to release the target logical address.

[0112] The receiving module 41, the computing module 42, the first allocating module 43 and the second allocating module 44 are sequentially connected. The logical address allocation apparatus 4 provided in the embodiment can execute the technical solutions of the above method embodiments, and has similar implementation principles and technical effects, which will not be described here again.

[0113] Figure 14 A structural schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown in FIG. 5, which includes: Figure 14

[0114] a processor 51 and a memory 52 connected with the processor 51 in communication;

[0115] The memory 52 stores computer execution instructions.

[0116] The processor 51 executes the computer execution instructions stored in the memory 52 to implement the logical address allocation method in the embodiment shown in FIG. 4. Figures 2-12

[0117] Optionally, the processor 51 and the memory 52 are connected through a bus 53. ​​

[0118] The relevant description can be referred to Figures 2-12 The steps in the corresponding embodiments correspond to the relevant description and effects, which will not be described in detail here.

[0119] The embodiments of the present disclosure provide a computer readable storage medium, the computer readable storage medium stores computer execution instructions, and the computer execution instructions are used to implement the present disclosure Figures 2-12 The logical address allocation method provided by any of the embodiments.

[0120] The embodiments of the present disclosure provide a computer program product, including a computer program, which is executed by a processor to implement the logical address allocation method as Figures 2-12 The logical address allocation method in the embodiments.

[0121] Reference Figure 15 , which shows a structural schematic diagram of an electronic device 900 suitable for implementing the embodiments of the present disclosure. The electronic device 900 can be a terminal device or a server. The terminal device can include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, personal digital assistants (PDA), tablet computers (PAD), portable multimedia players (PMP), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. Figure 15 The electronic device shown is only an example and should not limit the functions and use range of the embodiments of the present disclosure.

[0122] As shown in Figure 15 , the electronic device 900 can include a processing device (such as a central processor, a graphics processor, etc.) 901, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 902 or programs loaded from a storage device 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the electronic device 900 are also stored. The processing device 901, the ROM 902, and the RAM 903 are connected to each other through a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0123] In general, the following devices can be connected to the I / O interface 905: input devices 906, including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; output devices 907, including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage devices 908, including, for example, a magnetic tape, a hard disk, and the like; and communication devices 909. The communication devices 909 can allow the electronic device 900 to communicate wirelessly or via a wire with other devices to exchange data. Although Figure 15 The electronic device 900 is shown with various devices, but it is understood that all of the illustrated devices are not required to implement or be present. More or fewer devices can alternatively be implemented or present.

[0124] In particular, the processes described above with reference to the flowcharts can be implemented as a computer software program according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program code for executing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via the communication devices 909, or installed from the storage devices 908, or installed from the ROM 902. When the computer program is executed by the processing devices 901, the above-mentioned functions defined in the methods of the embodiments of the present disclosure are performed.

[0125] It should be noted that the computer-readable medium in the above disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the present disclosure, the computer-readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take many forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus. The program code contained in the computer-readable medium can be transmitted by any suitable medium, including but not limited to a wire, a cable, an RF (radio frequency) or the like, or any suitable combination of the above.

[0126] The computer-readable medium described above can be contained in the electronic device described above; or can exist separately and not be assembled into the electronic device.

[0127] The computer-readable medium described above carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods shown in the above embodiments.

[0128] Computer program code for carrying out operations of the present disclosure can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0129] The flow diagrams and the block diagrams in the drawings are meant as possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

[0130] The units described in the embodiments of the present disclosure can be implemented by software, or by hardware. In some cases, the name of the unit does not constitute a limitation on the unit itself. For example, the first obtaining unit can also be described as a unit for obtaining at least two Internet protocol addresses.

[0131] The functions described above in the specification of the present disclosure can be performed by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Program-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc.

[0132] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium can include, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more of an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0133] In a first aspect, according to one or more embodiments of the present disclosure, a logical address allocation method is provided, comprising:

[0134] receiving a first request sent by a target virtual machine unit, the first request being used to register a logical address of a submission queue item of the target virtual machine unit; performing a hash operation based on the first request to obtain a first hash value, the first hash value being used to indicate the submission queue item; obtaining a target hash table corresponding to the target virtual machine unit, and querying the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs; based on a hash bucket identifier of the target hash bucket, obtaining a target logical address corresponding to the hash bucket identifier from currently available logical addresses; and registering the target logical address as a logical address generated for the submission queue item.

[0135] According to one or more embodiments of the present disclosure, the first request includes a unit identifier of the target virtual machine unit and an item identifier of the submission queue item; the hash operation based on the first request to obtain a first hash value includes: combining the unit identifier and the item identifier to obtain a first position identifier; and processing the first position identifier based on a target hash algorithm to obtain the first hash value.

[0136] According to one or more embodiments of the present disclosure, the obtaining of the target logical address corresponding to the hash bucket identifier from the currently available logical addresses based on the hash bucket identifier of the target hash bucket includes: obtaining bitmap data corresponding to the target virtual machine unit, wherein the bitmap data is composed of at least two ordered binary numbers, and the bitmap data represents a set of currently available logical addresses; and obtaining the target logical address corresponding to the hash bucket identifier according to the hash bucket identifier and the bitmap data.

[0137] According to one or more embodiments of the present disclosure, the obtaining, according to the hash bucket identifier and the bitmap data, of the target logical address corresponding to the hash bucket identifier comprises: detecting a target sequence number of a first target binary number in the bitmap data, the target binary number being used to indicate availability of a logical address; and obtaining the target logical address according to the target sequence number and the hash bucket identifier.

[0138] According to one or more embodiments of the present disclosure, the method further comprises: detecting a conflict state of the first hash value in the target hash bucket; when the conflict state is a first state, writing the target sequence number into a hash slot corresponding to the first hash value in the target hash bucket, so as to establish a mapping relationship between the first hash value and the target logical address; and performing a non-operation on a binary number corresponding to the target sequence number in the bitmap data.

[0139] According to one or more embodiments of the present disclosure, the method further comprises: detecting a conflict state of the first hash value in the target hash bucket; and when the conflict state is a second state, buffering the first hash value, so as to establish a mapping relationship between the first hash value and the target logical address after a target time length.

[0140] According to one or more embodiments of the present disclosure, the method further comprises: receiving a second request sent by the virtual machine unit, the second request being used to release a logical address of a completion queue item of the virtual machine unit; performing a hash operation based on the second request to obtain a second hash value, the second hash value being used to indicate the completion queue item; and releasing a target logical address corresponding to the completion queue item based on the second hash value.

[0141] According to one or more embodiments of the present disclosure, the releasing, based on the second hash value, of the target logical address corresponding to the completion queue item comprises: determining a hash bucket identifier corresponding to the second hash value and a target hash table corresponding to the target virtual machine unit, the hash bucket identifier representing a target hash bucket to which the first hash value belongs; performing a search on the target hash bucket based on the second hash value to obtain a hit result; and obtaining the target logical address according to the hit result and releasing the target logical address.

[0142] According to one or more embodiments of the present disclosure, the hit result comprises a hash slot identifier; and according to the hit result, the target logical address is obtained and released, comprising: according to the hash slot identifier, a target sequence number is obtained, the target sequence number representing a position of the logical address corresponding to the completion queue entry in bitmap data; performing a NOT operation on a binary number corresponding to the target sequence number in the bitmap data, and deleting a second hash value stored in a target hash slot corresponding to the hash slot identifier, so as to release the target logical address.

[0143] In a second aspect, according to one or more embodiments of the present disclosure, a logical address allocation apparatus is provided, comprising:

[0144] A receiving module is configured to receive a first request sent by a target virtual machine unit, the first request being used to register a logical address of a submission queue entry of the target virtual machine unit;

[0145] A computing module is configured to perform a hash operation based on the first request to obtain a first hash value;

[0146] A first allocation module is configured to obtain a target hash table corresponding to the target virtual machine unit, and query the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs;

[0147] A second allocation module is configured to obtain, based on a hash bucket identifier of the target hash bucket, a target logical address corresponding to the hash bucket identifier from currently available logical addresses, and register the target logical address as a logical address corresponding to the submission queue entry.

[0148] According to one or more embodiments of the present disclosure, the first request comprises a unit identifier of the target virtual machine unit and a queue entry identifier of the submission queue entry; and the computing module is specifically configured to: combine the unit identifier and the queue entry identifier to obtain a first position identifier; and perform processing on the first position identifier based on a target hash algorithm to obtain the first hash value.

[0149] According to one or more embodiments of the present disclosure, the second allocation module is specifically configured to: obtain bitmap data corresponding to the target virtual machine unit, wherein the bitmap data is composed of at least two sequentially arranged binary numbers, and the bitmap data represents a set of currently available logical addresses; and obtain, according to the hash bucket identifier and the bitmap data, a target logical address corresponding to the hash bucket identifier.

[0150] According to one or more embodiments of the present disclosure, the second allocation module is specifically configured to: detect a target sequence number of a first target binary number in the bitmap data, the target binary number being used to indicate availability of a logical address; and obtain the target logical address according to the target sequence number and the hash bucket identifier.

[0151] According to one or more embodiments of the present disclosure, the second allocation module is further configured to: detect a conflict state of the first hash value in the target hash bucket; when the conflict state is a first state, write the target sequence number into a hash slot corresponding to the first hash value in the target hash bucket, so as to establish a mapping relationship between the first hash value and the target logical address; and perform a non-operation on a binary number corresponding to the target sequence number in the bitmap data.

[0152] According to one or more embodiments of the present disclosure, the second allocation module is further configured to: detect a conflict state of the first hash value in the target hash bucket; and when the conflict state is a second state, buffer the first hash value, so as to establish a mapping relationship between the first hash value and the target logical address after a target time length.

[0153] According to one or more embodiments of the present disclosure, the receiving module is further configured to: receive a second request sent by the virtual machine unit, the second request being used to release a logical address of a completion queue entry of the virtual machine unit; the computing module is further configured to: perform a hash operation based on the second request to obtain a second hash value, the second hash value being used to indicate the completion queue entry; and the second allocation module is further configured to: release a target logical address corresponding to the completion queue entry based on the second hash value.

[0154] According to one or more embodiments of the present disclosure, the second allocation module is specifically configured to: determine a hash bucket identifier corresponding to the second hash value and a target hash table corresponding to the target virtual machine unit, the hash bucket identifier representing a target hash bucket to which the first hash value belongs; perform a search on the target hash bucket based on the second hash value to obtain a hit result; and obtain the target logical address according to the hit result and release the target logical address.

[0155] According to one or more embodiments of the present disclosure, the hit result includes a hash slot identifier; and the allocation module is specifically configured to: obtain a target sequence number according to the hash slot identifier, the target sequence number representing a position of the logical address corresponding to the completion queue entry in the bitmap data; perform a non-operation on a binary number corresponding to the target sequence number in the bitmap data, and delete the second hash value stored in a target hash slot corresponding to the hash slot identifier, so as to release the target logical address.

[0156] In a third aspect, an electronic device is provided, including: a processor, and a memory connected with the processor in communication;

[0157] The memory stores computer-executable instructions;

[0158] The processor executes the computer-executable instructions stored in the memory to implement the logical address allocation method according to the first aspect and various possible designs of the first aspect.

[0159] In a fourth aspect, a computer-readable storage medium is provided, which stores computer-executable instructions, and when a processor executes the computer-executable instructions, the logical address allocation method according to the first aspect and various possible designs of the first aspect is implemented.

[0160] In a fifth aspect, a computer program product is provided, which includes a computer program, and when a processor executes the computer program, the logical address allocation method according to the first aspect and various possible designs of the first aspect is implemented.

[0161] The above description is merely preferred embodiments of the present disclosure and a description of principles of applied technologies. It should be understood by those skilled in the art that the disclosed scope of the present disclosure is not limited to the technical solutions formed by the specific combinations of the above technical features, and also covers other technical solutions formed by any combinations of the above technical features or equivalent features without departing from the disclosed concept. For example, the technical solutions formed by replacing the above features with the technical features disclosed in the present disclosure (but not limited to) having similar functions.

[0162] In addition, although each operation is described in a particular order, this should not be understood as requiring the operations to be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing can be advantageous. Similarly, although several implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Certain features described in the context of separate embodiments can also be combined in a single embodiment. Conversely, various features described in the context of a single embodiment can also be separated and implemented in multiple embodiments.

[0163] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A method of allocating logical addresses, characterized by, The method comprises: receiving a first request sent by a target virtual machine unit, the first request being used for registering a logical address of a submission queue item of the target virtual machine unit; performing hash operation based on the first request to obtain a first hash value, the first hash value being used for indicating the submission queue item; obtaining a target hash table corresponding to the target virtual machine unit, and querying the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs; based on a hash bucket identifier of the target hash bucket, obtaining a target logical address corresponding to the hash bucket identifier from currently available logical addresses; registering the target logical address as a logical address generated by the submission queue item, wherein the first request comprises a unit identifier of the target virtual machine unit and an item identifier of the submission queue item, and the hash operation based on the first request to obtain the first hash value comprises: combining the unit identifier and the item identifier to obtain a first position identifier; processing the first position identifier based on a target hash algorithm to obtain the first hash value.

2. The method of claim 1, wherein, The obtaining of the target logical address corresponding to the hash bucket identifier of the target hash bucket from the currently available logical addresses comprises: obtaining bitmap data corresponding to the target virtual machine unit, wherein the bitmap data is composed of at least two ordered binary numbers, and the bitmap data represents a set of currently available logical addresses; obtaining the target logical address corresponding to the hash bucket identifier according to the hash bucket identifier and the bitmap data.

3. The method of claim 2, wherein, The obtaining of the target logical address corresponding to the hash bucket identifier according to the hash bucket identifier and the bitmap data comprises: detecting a target sequence number of a first target binary number in the bitmap data, the target binary number being used for indicating availability of a logical address; obtaining the target logical address according to the target sequence number and the hash bucket identifier.

4. The method of claim 3, wherein, The method further comprises: detecting a conflict state of the first hash value in the target hash bucket; when the conflict state is a first state, writing the target sequence number into a hash slot corresponding to the first hash value in the target hash bucket, so as to establish a mapping relationship between the first hash value and the target logical address; performing non-operation on a binary number corresponding to the target sequence number in the bitmap data.

5. The method of claim 3, wherein, The method further comprises: detecting a conflict state of the first hash value in the target hash bucket; when the conflict state is a second state, buffering the first hash value, so as to establish a mapping relationship between the first hash value and the target logical address after a target time length.

6. The method of claim 1, wherein, The method further comprises: receiving a second request sent by the virtual machine unit, the second request being used for releasing a logical address of a completion queue item of the virtual machine unit; performing hash operation based on the second request to obtain a second hash value, the second hash value being used for indicating the completion queue item; releasing a target logical address corresponding to the completion queue item based on the second hash value.

7. The method of claim 6, wherein, Releasing, based on the second hash value, the target logical address corresponding to the completion queue entry, includes: According to the second hash value and the target hash table corresponding to the target virtual machine unit, a corresponding hash bucket identifier is determined, which represents the target hash bucket to which the first hash value belongs; Based on the second hash value, the target hash bucket is searched to obtain a hit result; According to the hit result, the target logical address is obtained and released.

8. The method of claim 7, wherein, The hit result includes a hash slot identifier; according to the hit result, the target logical address is obtained and released, including: According to the hash slot identifier, a target sequence number is obtained, which represents the position of the logical address corresponding to the completion queue entry in the bitmap data; The binary number corresponding to the target sequence number in the bitmap data is not operated, and the second hash value stored in the target hash slot corresponding to the hash slot identifier is deleted to release the target logical address.

9. A logical address allocation apparatus characterized by comprising: Including: The receiving module is configured to receive a first request sent by a target virtual machine unit, the first request being used to register a logical address of a submission queue entry of the target virtual machine unit; The computing module is configured to perform hash operation based on the first request to obtain a first hash value; The first allocation module is configured to obtain a target hash table corresponding to the target virtual machine unit, and query the target hash table based on the first hash value to obtain a target hash bucket to which the first hash value belongs; The second allocation module is configured to obtain, based on a hash bucket identifier of the target hash bucket, a target logical address corresponding to the hash bucket identifier from currently available logical addresses, and register the target logical address as a logical address corresponding to the submission queue entry, Wherein, the first request includes a unit identifier of the target virtual machine unit and an entry identifier of the submission queue entry, and the hash operation based on the first request to obtain a first hash value includes: Combining the unit identifier and the entry identifier to obtain a first position identifier; Based on a target hash algorithm, the first position identifier is processed to obtain the first hash value.

10. An electronic device, comprising: Including: A processor, and a memory in communication connection with the processor; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory to implement the logical address allocation method in any one of claims 1 to 8.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer execution instructions, and when the processor executes the computer execution instructions, the logical address allocation method in any one of claims 1 to 8 is implemented.

12. A computer program product, characterised in that, Including a computer program, which is executed by a processor to implement the logical address allocation method in any one of claims 1 to 8.

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