Array substrate, display substrate and display device

Abstract

The application provides an array substrate, a display substrate and a display device. The array substrate comprises a driving area and a first frame area extending along a first direction on one side of the driving area and the bit driving area. The array substrate comprises a substrate and a driving circuit layer on one side of the substrate. The driving circuit layer comprises a plurality of gate driving circuits in the first frame area, a first signal line, a second signal line and a third signal line. The first signal line and the second signal line extend along the first direction, and the third signal line extends along a second direction. The first signal line is on one side of the second signal line away from the driving area. The plurality of gate driving circuits comprise a dummy gate driving circuit and a starting row gate driving circuit; one end of the first signal line is electrically connected with the third signal line, and the other end is used for electrically connecting with a driving chip, and the driving chip provides a driving signal to the starting row gate driving circuit. The third signal line is electrically connected with the dummy gate driving circuit and the starting row gate driving circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display substrate, and a display device. Background Technology

[0002] The display panel includes a driving circuit layer and a light-emitting structure layer located on the driving circuit layer. The driving circuit layer includes gate driving circuits and pixel circuits. The starting row gate driving circuit receives driving signals provided by the driving chip, outputs driving signals to the pixel circuits, and outputs cascaded signals to the cascaded gate driving circuits. Summary of the Invention

[0003] This application provides an array substrate, a display substrate, and a display device.

[0004] According to a first aspect of the present application, an array substrate is provided. The array substrate is used as a display substrate, the array substrate includes a driving region corresponding to a display area of ​​the display substrate and a first border region located on one side of the driving region and extending along a first direction, the array substrate includes a substrate and a driving circuit layer located on one side of the substrate;

[0005] The driving circuit layer includes a plurality of gate driving circuits, a first signal line, a second signal line, and a third signal line located in the first border area; the first signal line and the second signal line extend along the first direction, and the third signal line extends along the second direction, which intersects with the first direction; the first signal line is located on the side of the second signal line away from the driving area; the plurality of gate driving circuits include a dummy gate driving circuit and a starting row gate driving circuit; one end of the first signal line is electrically connected to the third signal line, and the other end is used to be electrically connected to the driving chip, and the driving chip provides a driving signal to the starting row gate driving circuit; the third signal line is electrically connected to the dummy gate driving circuit and also electrically connected to the starting row gate driving circuit.

[0006] In one embodiment, the driving circuit layer further includes a fourth signal line and a connecting portion. The fourth signal line is adjacent to the first signal line, disposed on the same layer and extending in the same direction. The fourth signal line is connected to the third signal line. The connecting portion connects to the first signal line and the fourth signal line respectively.

[0007] In one embodiment, the driving circuit layer includes a first conductive layer, a first insulating layer located on the side of the first conductive layer away from the substrate, a second conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the second conductive layer away from the substrate; the first signal line and the fourth signal line are located on the first conductive layer, and the overlapping portion is located on the side of the first insulating layer facing the substrate.

[0008] In one embodiment, the driving circuit layer includes a first conductive layer, a first insulating layer located on the side of the first conductive layer away from the substrate, a second conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the second conductive layer away from the substrate; the first signal line and the fourth signal line are located on the first conductive layer, the first insulating layer is provided with a first through hole, and the overlapping portion is located on the side of the second insulating layer facing the substrate and is located in the first through hole.

[0009] In one embodiment, the driving circuit layer includes a first conductive layer, a first insulating layer located on the side of the first conductive layer away from the substrate, a second conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the second conductive layer away from the substrate; the first signal line and the fourth signal line are located on the first conductive layer, and the driving circuit layer is provided with a second through hole penetrating the first insulating layer and the second insulating layer, and the overlapping portion is located in the second through hole.

[0010] In one embodiment, the fourth signal line includes a first sub-signal line, a second sub-signal line, and a third sub-signal line arranged in the first direction. A first gap exists between the second sub-signal line and the first and third sub-signal lines, and the second sub-signal line overlaps with the overlapping portion and is connected to the third signal line.

[0011] In one embodiment, the third signal line includes a fourth sub-signal line and a fifth sub-signal line located on the side of the fourth sub-signal line away from the first signal line. A second gap exists between the fourth sub-signal line and the fifth sub-signal line. The end of the fourth sub-signal line away from the second gap is electrically connected to the first signal line, and the end of the fourth sub-signal line adjacent to the second gap is electrically connected to the starting row gate driving circuit.

[0012] In one embodiment, the driving circuit layer further includes a first conductor, one end of which is connected to the third signal line and the other end of which is electrically connected to the starting row gate driving circuit; the array substrate further includes an insulating layer located between the first conductor and the third signal line, the first conductor being electrically connected to the third signal line through an opening in the insulating layer; the orthographic projection of the first conductor on the substrate overlaps with the orthographic projection of the third signal line on the substrate.

[0013] In one embodiment, the driving circuit layer further includes a first wire, which includes a first sub-wire and a second sub-wire. One end of the first sub-wire is connected to the third signal line, and the other end is electrically connected to the starting row gate driving circuit. The second sub-wire is located on the side of the first sub-wire away from the starting row gate driving circuit. There is a third gap between the first sub-wire and the second sub-wire.

[0014] In one embodiment, the driving circuit layer further includes a first conductor and at least one fifth signal line; one end of the first conductor is connected to the third signal line, and the other end is electrically connected to the starting row gate driving circuit; the first conductor extends at least partially along the first direction; the fifth signal line extends along the second direction and is electrically connected to the dummy gate driving circuit; the fifth signal line includes a sixth sub-signal line, a seventh sub-signal line, and an eighth sub-signal line arranged in the second direction, and a fourth gap exists between the seventh sub-signal line and the sixth and eighth sub-signal lines, and the orthographic projections of the two fourth gaps on the substrate are located on opposite sides of the orthographic projection of the first conductor on the substrate.

[0015] In one embodiment, the gate driving circuit includes a startup transistor, a pull-down transistor, and a connection node. The output terminal of the startup transistor and the input terminal of the pull-down transistor are respectively connected to the connection node. The third signal line is electrically connected to the gate of the startup transistor of the starting row gate driving circuit. The second signal line transmits the same signal as the first signal line. The driving circuit layer also includes a plurality of second wires. One end of each second wire is connected to the second signal line, and the other end is connected to the gate of the pull-down transistor of the gate driving circuit.

[0016] The second conductor corresponding to the starting row gate drive circuit includes a third sub-wire and a fourth sub-wire. There is a fifth gap between the third sub-wire and the fourth sub-wire. The end of the third sub-wire away from the fifth gap is connected to the gate drive circuit, and the end of the fourth sub-wire away from the fifth gap is connected to the gate of the pull-down transistor.

[0017] In one embodiment, the width of the first signal line is greater than the width of the second signal line.

[0018] In one embodiment, the driving circuit layer further includes a plurality of sixth signal lines located between the first signal line and the second signal line.

[0019] According to a second aspect of the present application, a display substrate is provided, the display substrate including the above-described array substrate and a light-emitting structure layer located on the side of the array substrate opposite to the substrate; the display substrate includes a display area, and the light-emitting structure layer includes a plurality of sub-pixels located in the display area.

[0020] In one embodiment, the display substrate further includes a color filter layer located on the side of the light-emitting structure layer opposite to the substrate, and the light-emitting structure layer includes liquid crystal molecules.

[0021] According to a third aspect of the embodiments of this application, a display device is provided, the display device including the display substrate described above.

[0022] The array substrate, display substrate, and display device provided in this application embodiment have a starting row gate driving circuit electrically connected to a driving chip via a third signal line. The driving chip can provide a driving signal to the starting row driving circuit via the third signal line, so that the starting row gate driving circuit can work normally and ensure the normal display of the display substrate. The use of a third signal line electrically connected to a dummy gate driving circuit to realize the electrical connection between the driving chip and the starting row gate driving circuit eliminates the need for additional connection lines, which helps to simplify the manufacturing process of the display substrate. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of this application;

[0024] Figure 2 This is a schematic diagram of the structure of the driving circuit layer of the display substrate located in the first frame area according to an exemplary embodiment of this application;

[0025] Figure 3 This is a circuit diagram of a gate driving circuit provided in an exemplary embodiment of this application;

[0026] Figure 4 This is a partial cross-sectional view of a gate driving circuit provided in an exemplary embodiment of this application;

[0027] Figure 5 This is a partial cross-sectional view of a gate driving circuit provided in another exemplary embodiment of this application;

[0028] Figure 6 This is a partial cross-sectional view of a gate driving circuit provided in another exemplary embodiment of this application;

[0029] Figure 7 yes Figure 2 A partial structural schematic diagram of the driving circuit layer of the display substrate is shown.

[0030] Figure 8 yes Figure 2The diagram shows a partial structural schematic of the driving circuit layer of the display substrate. Detailed Implementation

[0031] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0032] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0033] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0034] This application provides an array substrate, a display substrate, and a display device. The array substrate, display substrate, and display device of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can complement or combine with each other.

[0035] To save on display panel manufacturing costs, smaller display panels can share the same mask for fabricating the driving circuit layer as larger display panels. For example, a 58.5-inch display panel and a 65-inch display panel can share the same mask for fabricating the driving circuit layer. After the driving circuit layer of the smaller display panel is fabricated, the excess portion of the driving circuit layer needs to be cut off. This results in the removal of the starting row gate driving circuit. Consequently, the starting row gate driving circuit in the resulting display substrate cannot be electrically connected to the driving chip, causing the starting row gate driving circuit to malfunction and affecting the normal display of the display panel.

[0036] This application provides an array substrate. The array substrate is used as a display substrate, and the display substrate includes a display area. For example... Figure 1As shown, the array substrate includes a driving region 111 corresponding to the display area of ​​the display substrate and a first border region 112 located on one side of the driving region 111 and extending along a first direction X. The array substrate includes a substrate and a driving circuit layer 10 located on one side of the substrate; the driving circuit layer 10 includes a plurality of gate driving circuits 20 located in the first border region 112 and a plurality of pixel circuits 30 located in the driving region 111.

[0037] like Figure 2 As shown, the driving circuit layer 10 further includes a first signal line 11, a second signal line 12, and a third signal line 13 located in the first border area 112; the first signal line 11 and the second signal line 12 extend along the first direction X, and the third signal line 13 extends along the second direction Y, which intersects with the first direction X; the first signal line 11 is located on the side of the second signal line 12 away from the driving area 111; the plurality of gate driving circuits 20 include a dummy gate driving circuit 21 and a starting row gate driving circuit 22; one end of the first signal line 11 is electrically connected to the third signal line 13, and the other end is used to be electrically connected to the driving chip, and the driving chip provides a driving signal to the starting row gate driving circuit 22; the third signal line 13 is electrically connected to the dummy gate driving circuit 21 and to the starting row gate driving circuit 22.

[0038] The array substrate provided in this application embodiment has a starting row gate driving circuit electrically connected to a driving chip via a third signal line. The driving chip can provide a driving signal to the starting row driving circuit via the third signal line, so that the starting row gate driving circuit can work normally and ensure the normal display of the display substrate. The use of a third signal line electrically connected to a dummy gate driving circuit to realize the electrical connection between the driving chip and the starting row gate driving circuit eliminates the need for additional connection lines, which helps to simplify the manufacturing process of the display substrate.

[0039] In one embodiment, such as Figure 1 As shown, the bezel area of ​​the display substrate may include two first bezel areas 112 arranged opposite to each other. The display substrate also includes a second bezel area 113 and a third bezel area 114 arranged opposite to each other and extending in the same direction. The second bezel area 113 and the third bezel area 114 extend along a second direction Y. The first direction X and the second direction Y may be perpendicular to each other. For example, the first direction X is the column direction and the second direction Y is the row direction. The two first bezel areas 112 may each be provided with a gate driving circuit 20. The driving circuit layer may also include a plurality of dummy pixel circuits 40 located in the second bezel area 113. The third bezel area 114 may be provided with fan-out lines, flexible circuit boards, etc. The flexible circuit board can be electrically connected to the driving chip, and the third signal line 13 can be electrically connected to the driving chip by being electrically connected to the flexible circuit board.

[0040] In one embodiment, such as Figure 1 As shown, the plurality of gate driving circuits 20 on the array substrate can be arranged in the first direction X. The plurality of gate driving circuits 20 also include a non-starting row gate driving circuit 23, which can be located on the side of the starting row gate driving circuit 22 opposite to the dummy gate driving circuit 21. The dummy gate driving circuit 21 refers to a gate driving circuit that does not provide gate driving signals to the pixel circuit, and the dummy gate driving circuit 21 can be electrically connected to the dummy pixel circuit 40. The starting row gate driving circuit 22 operates after receiving the driving signal provided by the driving chip and outputs a cascaded signal to the non-starting row gate driving circuit 23 cascaded with it. The number of starting row gate driving circuits 22 can be one or more, for example, three.

[0041] In one embodiment, the driving circuit layer 10 includes a first conductive layer and a second conductive layer located on the side of the first conductive layer facing away from the substrate. Both the pixel circuit and the gate driving circuit may include a thin-film transistor (TFT), which includes an active layer, a gate electrode, a source electrode, and a drain electrode. The gate electrode may be located on the side of the active layer facing the substrate, and the source electrode and drain electrode may be located on the side of the active layer facing away from the substrate. For example, the gate electrode may be located on the first conductive layer, and the source electrode and drain electrode may be located on the second conductive layer.

[0042] like Figure 2 As shown, the driving circuit layer 10 may further include a plurality of signal lines located in the first border region 112 and extending along the first direction X. In the direction near the gate driving circuit 20, the plurality of signal lines extending along the first direction X are arranged sequentially as a start control signal STV1, a plurality of clock signal lines 31-36, a high-level power supply signal line 371, a high-level power supply signal line 372, a low-level power supply signal line 38, and a start control signal STV2. The start control signal line STV1 and the start control signal line STV2 can transmit the same signal.

[0043] In one embodiment, such as Figure 3 As shown, the gate drive circuit includes capacitor C1 and transistors M1, M2, M3, M5, M5', M6, M6', M7, M8, M8', M9, M9', M10, M10', M11, M11', M12, M12', M13, M16, and M16'. The gate drive circuit also includes input ports INPUT, RST_PU, STV, VGL, LVGL, VDDO, VDDE, and CLK, and output ports GOUT and OUTC. The connection relationships of capacitor C1, the aforementioned transistors, the input ports, and the output ports are as follows: Figure 3As shown. The gate drive circuit also includes a connection node PU, transistor M1 is a startup transistor, and transistor M7 is a pull-down transistor. The input terminal and gate of the startup transistor M1 are connected to the input port INPUT, and the output terminal of the startup transistor M1 is connected to the connection node PU. The input terminal of the pull-down transistor M7 is connected to the connection node PU, the gate of the pull-down transistor M7 is connected to the input port STV, and the output terminal of the pull-down transistor M7 is connected to the low-level power signal input port LVGL.

[0044] In one embodiment, the startup transistor M1 of the starting row gate driving circuit 22 is connected to the first signal line 11. Specifically, the first signal line 11 can be electrically connected to the gate of the startup transistor M1 of the starting row gate driving circuit 22, providing a driving signal to the gate of the startup transistor M1. In some embodiments, the first signal line 11 can be a start control signal line STV1, providing a start control signal to the gate of the startup transistor M1 of the starting row gate driving circuit 22 to turn on the startup transistor M1.

[0045] In one embodiment, the pull-down transistor M7 of the gate drive circuit is connected to the first signal line 12. Specifically, the second signal line 12 can be electrically connected to the gate of the start-up transistor M7 of the gate drive circuit 22, providing a start control signal to the gate of the pull-down transistor M7, causing the pull-down transistor M7 to conduct, thereby pulling the level of the connection node PU low. In some embodiments, the second signal line 12 can be the start control signal line STV2.

[0046] In one embodiment, the third signal line 13 is a clock signal line connected to the input port CLK of the dummy gate driving circuit. Since the startup transistor M1 of the dummy gate driving circuit is not connected to the third signal line 13, it cannot receive the driving signal provided by the driving chip. Therefore, the dummy gate driving circuit cannot be started and cannot drive the pixel circuit to work.

[0047] In one embodiment, the first signal line 11 and the second signal line 12 transmit the same signal. For example... Figure 1 As shown, the width of the first signal line 11 is greater than the width of the second signal line 12. If the third signal line 13 is melted and electrically connected to the second signal line 12 using a laser process, the smaller width of the second signal line 12 could easily lead to a short circuit due to the third signal line 13 shortly connecting to the adjacent signal line after melting. The larger width of the first signal line 11 avoids this short circuit when connecting to the fourth signal line 14.

[0048] In one embodiment, such as Figure 2 , Figures 4 to 6As shown, the driving circuit layer 10 further includes a fourth signal line 14 and a connecting portion 50. The fourth signal line 14 is adjacent to the first signal line 11, disposed on the same layer, and extends in the same direction. The fourth signal line 14 is connected to the third signal line 13. The connecting portion 50 connects to both the first signal line 11 and the fourth signal line 14. Thus, the first signal line 11 is electrically connected to the third signal line 13 sequentially through the connecting portion 50, the fourth signal line 14, and so on.

[0049] In one embodiment, such as Figures 4 to 6 As shown, the driving circuit layer includes a first conductive layer 53, a first insulating layer 51 located on the side of the first conductive layer 53 facing away from the substrate 115, a second conductive layer (not shown) located on the side of the first insulating layer 51 facing away from the substrate 115, and a second insulating layer 52 located on the side of the second conductive layer facing away from the substrate 115. The start control signal STV1, multiple clock signal lines 31-36, high-level power signal line 371, high-level power signal line 372, low-level power signal line 38, and start control signal STV2 can all be located on the first conductive layer 53, and the third signal line 13 can be located on the second conductive layer.

[0050] In one embodiment, the overlap portion 50 can be made of tungsten, and can be formed by depositing conductive tungsten. Tungsten has high stability and is not easily oxidized, which can prevent the overlap portion 50 from being oxidized and affecting its electrical connection with the first signal line 11 and the second signal line 14. Alternatively, the overlap portion 50 can be formed by coating with silver.

[0051] In one embodiment, such as Figure 4 As shown, the first signal line 11 and the fourth signal line 14 are located in the first conductive layer 53, and the overlap portion 50 is located on the side of the first insulating layer 51 facing the substrate 115. The overlap portion 50 is partially located between the first signal line 11 and the fourth signal line 14, and partially located on the side of the first conductive layer 53 away from the substrate 115. In this embodiment, the overlap portion 50 is formed after the first conductive layer 53 is formed and before the first insulating layer 51 is formed. Both the first insulating layer 51 and the second insulating layer 52 cover the overlap portion 50, effectively preventing water and oxygen intrusion into the overlap portion 50, thus helping to improve the reliability of the array substrate.

[0052] In another embodiment, such as Figure 5As shown, the first signal line 11 and the fourth signal line 14 are located in the first conductive layer 53. The first insulating layer 51 has a first through-hole 511. The overlapping portion 50 is located on the side of the second insulating layer 52 facing the substrate 115 and is located within the first through-hole 511. The overlapping portion 50 is partially located between the first signal line 11 and the fourth signal line 14, and partially located on the side of the first conductive layer 53 away from the substrate 115. In this embodiment, the overlapping portion 50 is formed after the first insulating layer 51 is formed and before the second insulating layer 52 is formed. The second insulating layer 52 covers the overlapping portion 50, which can effectively prevent water and oxygen from intruding into the overlapping portion 50, thus helping to improve the reliability of the array substrate.

[0053] In yet another embodiment, such as Figure 6 As shown, the first signal line 11 and the fourth signal line 14 are located in the first conductive layer 53. The driving circuit layer has a second through-hole 512 penetrating the first insulating layer 51 and the second insulating layer 52. The overlapping portion 50 is located within the second through-hole 512. The overlapping portion 50 is partially located between the first signal line 11 and the fourth signal line 14, and partially located on the side of the first conductive layer 53 facing away from the substrate 115. In this embodiment, the overlapping portion 50 is formed after the second insulating layer 52 is formed.

[0054] In one embodiment, such as Figure 7 As shown, the fourth signal line 14 includes a first sub-signal line 141, a second sub-signal line 142, and a third sub-signal line 143 arranged in the first direction X. A first gap 101 exists between the second sub-signal line 142 and the first sub-signal line 141 and the third sub-signal line 143, respectively. The second sub-signal line 142 overlaps with the overlapping portion 50 and is connected to the third signal line 13. This arrangement separates the second sub-signal line 142 from both the first sub-signal line 141 and the third sub-signal line 143, preventing signals from the first sub-signal line 141 and the third sub-signal line 143 from being transmitted to the second sub-signal line 142. This reduces interference with the signal provided by the first signal line 11 to the starting row gate driving circuit 22 via the second sub-signal line 142. In some embodiments, the fourth signal line 14 can be cut using a laser etching process after its formation.

[0055] In one embodiment, such as Figure 8As shown, the third signal line 13 includes a fourth sub-signal line 131 and a fifth sub-signal line 132 located on the side of the fourth sub-signal line 131 away from the first signal line 11. A second gap 102 exists between the fourth sub-signal line 131 and the fifth sub-signal line 132. The end of the fourth sub-signal line 131 adjacent to the second gap 102 is electrically connected to the starting row gate driving circuit 22. This configuration prevents the third signal line 13 from receiving signals from the driving chip and interfering with the driving signal provided by the first signal line 11 to the starting row gate driving circuit 22 through the third signal line 13. In some embodiments, the third signal line 13 can be cut using a laser etching process after its formation.

[0056] In some embodiments, the third signal line 13 is located in the second conductive layer, and the orthographic projection of the second gap 102 on the substrate does not overlap with the orthographic projection of the first conductive layer on the substrate. This configuration prevents the laser energy from acting on the first conductive layer during laser etching, thus avoiding melting the first conductive layer and causing it to electrically connect with the third signal line 13, or electrically connecting two adjacent conductive structures in the first conductive layer, which would affect the performance of the display substrate.

[0057] In one embodiment, such as Figure 8 As shown, the driving circuit layer further includes a first conductive line 60, one end of which is connected to the third signal line 13, and the other end is electrically connected to the starting row gate driving circuit 22, specifically, to the gate of the starting transistor M1 of the starting row gate driving circuit 22. The array substrate also includes an insulating layer located between the first conductive line 60 and the third signal line 13. The first conductive line 60 is electrically connected to the third signal line 13 through an opening in the insulating layer; the orthographic projection of the first conductive line 60 on the substrate overlaps with the orthographic projection of the third signal line 13 on the substrate. This configuration allows the third signal line 13 to be directly connected to the first conductive line 60 through the opening, without the need for other transition structures, thus simplifying the structure of the display substrate. The first conductive line 60 may be located in a first conductive layer, the third signal line 13 in a second conductive layer, and the insulating layer may be the first insulating layer.

[0058] In one embodiment, such as Figure 8 As shown, when there are multiple starting row gate drive circuits 22, the first wires 60 correspond one-to-one with the starting row gate drive circuits 22. One end of each first wire 60 is electrically connected to the third signal line 13, and the other end is electrically connected to the start transistor M1 of the corresponding starting row gate drive circuit 22.

[0059] In some embodiments, after the third signal line 13 is formed, a laser etching process can be used to form an opening in the insulating layer between the first conductor 60 and the third signal line 13, exposing a portion of the first conductor 60. During laser etching, the third signal line 13 melts and enters the opening to form a conductive portion, thereby connecting the third signal line 13 to the first conductor 60 through the conductive portion located in the opening.

[0060] In one embodiment, such as Figure 8 As shown, the first conductor 60 includes a first sub-conductor 61 and a second sub-conductor 62. One end of the first sub-conductor 61 is connected to the third signal line 13, and the other end is electrically connected to the starting row gate driving circuit 22. The second sub-conductor 62 is located on the side of the first sub-conductor 61 away from the starting row gate driving circuit 22. A third gap 103 exists between the first sub-conductor 61 and the second sub-conductor 62. This configuration can further reduce interference to the signal transmitted from the third signal line 13 to the starting row gate driving circuit 22.

[0061] In one embodiment, the driving circuit layer further includes at least one fifth signal line 70; the fifth signal line 70 extends along the second direction and is electrically connected to the dummy gate driving circuit 21. The fifth signal line 70 includes a sixth sub-signal line 71, a seventh sub-signal line 72, and an eighth sub-signal line 73 arranged in the second direction Y. A fourth gap 104 exists between the seventh sub-signal line 72 and each of the sixth and eighth sub-signal lines 71 and 73. The orthographic projections of the two fourth gaps 104 on the substrate are located on opposite sides of the orthographic projection of the first conductor 60 on the substrate. This arrangement prevents the signal from the fifth signal line 70 from interfering with the signal transmitted from the first conductor 60 to the starting row gate driving circuit 22. The fifth signal line 70 is located in the second conductive layer, and the first conductor 60 is located in the first conductive layer. The orthographic projections of the two fourth gaps 104 on the substrate are located on opposite sides of the orthographic projections of the first conductor 60 on the substrate. This avoids the laser acting on the first conductor 60 when the fifth signal line 70 is cut using a laser etching process, which would cause the first conductor 60 to be electrically connected to the adjacent signal line or to the fifth signal line 70.

[0062] In one embodiment, such as Figure 8 As shown, the driving circuit layer further includes a plurality of second wires 80, one end of each second wire 80 being connected to the second signal line 12, and the other end being connected to the gate of the pull-down transistor film M7 of the gate driving circuit. That is, the second signal line 12 provides a signal to the gate of the pull-down transistor film M7 through the second wires 80.

[0063] In one embodiment, such as Figure 8As shown, the second conductor 80 corresponding to the starting row gate driving circuit 22 includes a third sub-conductor 81 and a fourth sub-conductor 82. A fifth gap 105 exists between the third sub-conductor 81 and the fourth sub-conductor 82. The end of the third sub-conductor 81 away from the fifth gap 105 is connected to the second signal line 12, and the end of the fourth sub-conductor 82 away from the fifth gap 105 is connected to the gate of the pull-down transistor M7. Since the array substrate provided in this embodiment shares a mask for fabricating the driving circuit layer with an array substrate larger than itself, the starting row gate driving circuit 22 of the array substrate provided in this embodiment corresponds to the non-starting row driving circuit of the large-size array substrate, resulting in the gate of the pull-down transistor M7 of the starting row gate driving circuit of the array substrate provided in this embodiment being electrically connected to the second signal line 12. By dividing the second conductor 80 into the third sub-conductor 81 and the fourth sub-conductor 82, the gate of the pull-down transistor M7 of the starting row gate driving circuit of the small-size array substrate does not receive the signal transmitted by the second signal line 12, and the pull-down transistor M7 is not turned on, thus ensuring the normal operation of the starting row gate driving circuit.

[0064] In one embodiment, such as Figure 8 As shown, the driving circuit layer also includes multiple third wires 90. These third wires 90 are electrically connected to the gate of the startup transistor M1 in the non-starting row gate driving circuit, and are used to transmit cascaded signals to the gate of the startup transistor M1. Since the array substrate provided in this embodiment shares a mask for fabricating the driving circuit layer with array substrates larger than itself, in the large-size array substrate, the end of the third wire 90 furthest from the corresponding startup transistor M1 is connected to the output terminal OUTC of the previous stage gate driving circuit. After the array substrate provided in this embodiment is fabricated, a portion of the gate driving circuit needs to be cut off. The end of the third wire 90 furthest from the corresponding startup transistor M1 is cut off, and the gate driving circuit corresponding to the third wire 90 needs to be electrically connected to the previous stage gate driving circuit using a new wire.

[0065] In one embodiment, such as Figure 8 As shown, the third conductor 90 includes a fifth sub-conductor 91 and a sixth sub-conductor 92, with a sixth gap 106 between the fifth sub-conductor 91 and the sixth sub-conductor 92. This arrangement further reduces interference to the signal transmitted from the third signal line 13 to the starting row gate drive circuit 22.

[0066] In one embodiment, such as Figure 8As shown, the driving circuit layer further includes a fourth conductor 930, which includes a seventh sub-conductor 931 and an eighth sub-conductor 932. A seventh gap 107 exists between the seventh sub-conductor 931 and the eighth sub-conductor 932. The end of the eighth sub-conductor 932 facing away from the seventh gap 107 is electrically connected to the dummy gate driving circuit 21. In a large-size array substrate, the dummy gate driving circuit is a non-starting row gate driving circuit. The fourth conductor 930 is used to connect this non-starting row gate driving circuit to the output terminal OUTC of the previous stage gate driving circuit, thereby transmitting a cascaded signal to the non-starting row gate driving circuit. In this embodiment, the fourth conductor 930 does not need to provide a cascaded signal to the dummy gate driving circuit. Cutting the fourth conductor 930 into two parts can further reduce the interference received by the signal transmitted from the third signal line 13 to the starting row gate driving circuit 22.

[0067] In one embodiment, such as Figure 2 As shown, the driving circuit layer also includes a plurality of sixth signal lines located between the first signal line 11 and the second signal line 12. When the first signal line 11 is the start control signal STV1 and the second signal line 12 is the start control signal STV2, the plurality of sixth signal lines include a plurality of clock signal lines 31-36, a high-level power supply signal line 371, a high-level power supply signal line 372 and a low-level power supply signal line 38.

[0068] This application also provides a display substrate, which includes an array substrate as described in any of the above embodiments and a light-emitting structure layer located on the side of the array substrate facing away from the substrate; the display substrate includes a display area, and the light-emitting structure layer includes a plurality of sub-pixels located in the display area and is electrically connected to a pixel circuit located in the driving area.

[0069] In one embodiment, the light-emitting structure layer further includes a plurality of sub-pixels located in the second border region, and the plurality of sub-pixels are electrically connected to a dummy gate driver. When the display substrate is in display mode, these sub-pixels do not emit light.

[0070] In one embodiment, the display substrate further includes a color filter layer located on the side of the light-emitting structure layer opposite to the substrate, and the light-emitting structure layer includes liquid crystal molecules. That is, the display substrate is a liquid crystal display substrate.

[0071] In one embodiment, the display substrate further includes a sealant located between the array substrate and the color filter layer, the sealant surrounding the liquid crystal molecules. The sealant prevents liquid crystal molecules from flowing out of the display area and also helps improve the encapsulation performance of the display substrate.

[0072] This application also provides a display device, which includes the display substrate described in any of the above embodiments.

[0073] In some embodiments, the display device further includes a housing, in which a display substrate is embedded.

[0074] The display device provided in this application embodiment can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0075] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0076] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0077] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate is used as a display substrate. The array substrate includes a driving area corresponding to the display area of ​​the display substrate and a first border area located on one side of the driving area and extending along a first direction. The array substrate includes a substrate and a driving circuit layer located on one side of the substrate. The driving circuit layer includes multiple gate driving circuits, a first signal line, a second signal line, a third signal line, and multiple clock signal lines located in the first border area. The first signal line, the second signal line, and the multiple clock signal lines all extend along the first direction, and the third signal line extends along the second direction, which intersects with the first direction. The first signal line is located on the side of the second signal line away from the driving area and on the side of the multiple clock signal lines away from the driving area. The multiple gate driving circuits include a dummy gate driving circuit and a starting row gate driving circuit. One end of the first signal line is electrically connected to the third signal line, and the other end is used to electrically connect to the driving chip, which provides a driving signal to the starting row gate driving circuit. The third signal line is electrically connected to the dummy gate driving circuit and also to the starting row gate driving circuit. The width of the first signal line is greater than the width of the second signal line.

2. The array substrate according to claim 1, characterized in that, The driving circuit layer further includes a fourth signal line and an overlap portion. The fourth signal line is adjacent to the first signal line, disposed on the same layer and extending in the same direction. The fourth signal line is connected to the third signal line. The overlap portion overlaps with the first signal line and the fourth signal line respectively.

3. The array substrate according to claim 2, characterized in that, The driving circuit layer includes a first conductive layer, a first insulating layer located on the side of the first conductive layer away from the substrate, a second conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the second conductive layer away from the substrate; the first signal line and the fourth signal line are located on the first conductive layer, and the overlapping portion is located on the side of the first insulating layer facing the substrate.

4. The array substrate according to claim 2, characterized in that, The driving circuit layer includes a first conductive layer, a first insulating layer located on the side of the first conductive layer away from the substrate, a second conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the second conductive layer away from the substrate; the first signal line and the fourth signal line are located on the first conductive layer, the first insulating layer is provided with a first through hole, and the overlapping portion is located on the side of the second insulating layer facing the substrate and is located in the first through hole.

5. The array substrate according to claim 2, characterized in that, The driving circuit layer includes a first conductive layer, a first insulating layer located on the side of the first conductive layer away from the substrate, a second conductive layer located on the side of the first insulating layer away from the substrate, and a second insulating layer located on the side of the second conductive layer away from the substrate; the first signal line and the fourth signal line are located on the first conductive layer, and the driving circuit layer is provided with a second through hole penetrating the first insulating layer and the second insulating layer, and the overlapping portion is located in the second through hole.

6. The array substrate according to claim 2, characterized in that, The fourth signal line includes a first sub-signal line, a second sub-signal line, and a third sub-signal line arranged in the first direction. There is a first gap between the second sub-signal line and the first sub-signal line and the third sub-signal line, respectively. The second sub-signal line overlaps with the overlapping portion and is connected to the third signal line.

7. The array substrate according to claim 1, characterized in that, The third signal line includes a fourth sub-signal line and a fifth sub-signal line located on the side of the fourth sub-signal line away from the first signal line. There is a second gap between the fourth sub-signal line and the fifth sub-signal line. The end of the fourth sub-signal line away from the second gap is electrically connected to the first signal line. The end of the fourth sub-signal line adjacent to the second gap is electrically connected to the starting row gate driving circuit.

8. The array substrate according to claim 1, characterized in that, The driving circuit layer further includes a first conductor, one end of which is connected to the third signal line and the other end of which is electrically connected to the starting row gate driving circuit; the array substrate further includes an insulating layer located between the first conductor and the third signal line, and the first conductor is electrically connected to the third signal line through an opening in the insulating layer; the orthographic projection of the first conductor on the substrate overlaps with the orthographic projection of the third signal line on the substrate.

9. The array substrate according to claim 1, characterized in that, The driving circuit layer further includes a first conductor, which includes a first sub-conductor and a second sub-conductor. One end of the first sub-conductor is connected to the third signal line, and the other end is electrically connected to the starting row gate driving circuit. The second sub-conductor is located on the side of the first sub-conductor away from the starting row gate driving circuit. There is a third gap between the first sub-conductor and the second sub-conductor.

10. The array substrate according to claim 1, characterized in that, The driving circuit layer further includes a first conductor and at least one fifth signal line; one end of the first conductor is connected to the third signal line, and the other end is electrically connected to the starting row gate driving circuit; the first conductor extends at least partially along the first direction; the fifth signal line extends along the second direction and is electrically connected to the dummy gate driving circuit; the fifth signal line includes a sixth sub-signal line, a seventh sub-signal line, and an eighth sub-signal line arranged in the second direction, and a fourth gap exists between the seventh sub-signal line and the sixth and eighth sub-signal lines, and the orthographic projections of the two fourth gaps on the substrate are located on opposite sides of the orthographic projection of the first conductor on the substrate.

11. The array substrate according to claim 1, characterized in that, The gate driving circuit includes a startup transistor, a pull-down transistor, and a connection node. The output terminal of the startup transistor and the input terminal of the pull-down transistor are respectively connected to the connection node. The third signal line is electrically connected to the gate of the startup transistor of the starting row gate driving circuit. The second signal line transmits the same signal as the first signal line. The driving circuit layer also includes a plurality of second wires. One end of each second wire is connected to the second signal line, and the other end is connected to the gate of the pull-down transistor of the gate driving circuit. The second conductor corresponding to the starting row gate drive circuit includes a third sub-conductor and a fourth sub-conductor. There is a fifth gap between the third sub-conductor and the fourth sub-conductor. The end of the third sub-conductor away from the fifth gap is connected to the gate drive circuit, and the end of the fourth sub-conductor away from the fifth gap is connected to the gate of the pull-down transistor.

12. The array substrate according to claim 11, characterized in that, The driving circuit layer also includes a plurality of sixth signal lines located between the first signal line and the second signal line.

13. A display substrate, characterized in that, The display substrate includes an array substrate as described in any one of claims 1 to 12 and a light-emitting structure layer located on the side of the array substrate facing away from the substrate; the display substrate includes a display area, and the light-emitting structure layer includes a plurality of sub-pixels located in the display area.

14. The display substrate according to claim 13, characterized in that, The display substrate further includes a color filter layer located on the side of the light-emitting structure layer opposite to the substrate, and the light-emitting structure layer includes liquid crystal molecules.

15. A display device, characterized in that, The display device includes the display substrate as described in claim 13 or 14.

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