Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate, a plurality of active regions, a plurality of first conductive lines, and at least one first plug. The active regions extend parallel to each other along a first direction, and the first conductive lines cross the active regions. Each of the first conductive lines has opposite first and second ends. The first plug is disposed on the first end of the first conductive line and electrically connected to the first conductive line. The first plug entirely covers the first end of the first conductive line and directly contacts a top surface, a sidewall, and an end surface of the first end. Thus, the contact area between the plug and the first conductive line is increased, the contact resistance of the plug is reduced, and the reliability of the electrical connection between the plug and the first conductive line is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage, and more particularly to a semiconductor storage device. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, since it can obtain a longer carrier channel length within the same semiconductor substrate, thereby reducing leakage current caused by the capacitor structure, it has gradually replaced DRAM cells with only a planar gate structure under the current mainstream development trend.

[0003] Generally, a DRAM cell with a recessed gate structure includes a transistor assembly and a charge storage device to receive voltage signals from the bit line and word line. However, due to limitations in process technology, existing DRAM cells with recessed gate structures still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Summary of the Invention

[0004] One object of the present invention is to provide a semiconductor memory device in which a plug is disposed on two opposite ends of a bit line or word line and completely covers the end of the bit line or word line. In this way, the plug can directly contact the top surface, sidewall, and end face of the end, increasing the contact area between the plug and the bit line or word line, reducing the contact resistance of the plug, and thereby improving the reliability of the electrical connection between the plug and the bit line or word line.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor memory device comprising a substrate, a plurality of active regions, a plurality of first conductive lines, and at least one first plug. The active regions extend parallel to each other along a first direction, and the first conductive lines cross the active regions, wherein each first conductive line has a first end and a second end opposite to each other. The first plug is disposed on the first end of the first conductive line and electrically connected to the first conductive line, wherein the first plug completely covers the first end of the first conductive line and directly contacts the top surface, sidewall, and end face of the first end.

[0006] The semiconductor memory device of the present invention places plugs at both opposite ends of a conductor (bit line or word line, etc.) and completely covers the end of the conductor. Thus, the plug can directly contact at least the top surface, sidewall, and end face of the end of the conductor, increasing the contact area between the plug and the conductor and reducing the contact resistance of the plug. Furthermore, the end of the conductor may optionally have an additional protrusion to further increase the contact area between the plug and the conductor, wherein the protrusion may have various shapes (straight, L-shaped, arc-shaped, or hook-shaped) or sizes. Therefore, the semiconductor memory device of the present invention helps to improve the reliability of the electrical connection between the plug and the conductor.

[0007] Optionally, the thickness of the sidewall covered by the first plug at the first end is less than the thickness of the end face covered by the first plug at the first end.

[0008] Optionally, the portion of the first plug covering the sidewall and end face of the first end has a different depth in a direction perpendicular to the base.

[0009] Optionally, the distances from different sidewalls of the first plug to different surfaces of the first end are different, and the portion of the first plug with a greater distance from the first end has a deeper depth in the direction perpendicular to the base.

[0010] Optionally, the bottom surface of the first plug is lower than the bottom surface of the first wire.

[0011] Optionally, the semiconductor memory device further includes: a plurality of second wires extending parallel to each other along a first direction and across the active region, wherein each second wire is sequentially alternately arranged with each first wire in a second direction perpendicular to the first direction, and each second wire has a first end and a second end opposite to each other; and at least one second plug disposed on the second end of the second wire and electrically connected to the second wire, wherein the second plug completely covers the second end of the second wire.

[0012] Optionally, the first end of the first wire and the first end of the second wire are misaligned with each other in the second direction.

[0013] Optionally, the first plug includes a plurality of first plugs, which are alternately disposed on the first end of the first wire and are aligned with each other.

[0014] Optionally, the first end of each of the first wires includes a first protrusion, and the first protrusion extends toward a third direction.

[0015] Optionally, the second end of each of the first conductors includes a second protrusion, the second protrusion extending in the opposite direction to the third direction.

[0016] Optionally, each of the first protrusions and each of the second protrusions is in a straight line or an L-shape.

[0017] Optionally, the first plug also covers the first protrusion on the first end of the first wire.

[0018] Optionally, the first plug completely covers the end face of the first protrusion.

[0019] Optionally, the first wire is disposed within the substrate.

[0020] Optionally, the substrate further includes a shallow trench isolation surrounding the active area, wherein the first end of the first conductor is disposed within the shallow trench isolation.

[0021] Optionally, the first wire is disposed on the substrate.

[0022] Optionally, the substrate further includes a shallow trench isolation surrounding the active region, wherein the first end of the first conductor is disposed on the shallow trench isolation.

[0023] Optionally, it further includes: a plurality of third conductors extending parallel to each other along a first direction, wherein the third conductors are disposed on one side of the first conductor, and each of the third conductors has a first end and a second end opposite to each other; and

[0024] At least one third plug is disposed on the third conductor, near the first end of the third conductor, and electrically connected to the third conductor, wherein the third plug does not cover the first end of the third conductor.

[0025] Optionally, the third plug covers the two opposite sidewalls and the top surface of the third conductor.

[0026] Optionally, it further includes: an insulating layer covering the active area and the first wire, the first plug being disposed within the insulating layer, and the top surface of the first plug being flush with the top surface of the insulating layer. Attached Figure Description

[0027] Figures 1 to 8 A schematic diagram of a semiconductor memory device according to a first preferred embodiment of the present invention is shown; wherein

[0028] Figure 1 This is a top view schematic diagram of the semiconductor memory device of the present invention;

[0029] Figure 2 for Figure 1 A cross-sectional view along the tangent line A-A';

[0030] Figure 3 for Figure 1 A schematic cross-sectional view along the tangent line B-B'.

[0031] Figure 4 for Figure 1 Another cross-sectional view along the tangent B-B';

[0032] Figure 5 for Figure 1 A schematic cross-sectional view along the tangent C-C'.

[0033] Figure 6 for Figure 1 A schematic cross-sectional view along the tangent line D-D'.

[0034] Figure 7 for Figure 1 Another cross-sectional view along the tangent line D-D';

[0035] Figure 8 for Figure 1 Another cross-sectional view along the tangent line D-D';

[0036] Figure 9 A top view schematic diagram of a semiconductor memory device according to a second preferred embodiment of the present invention is shown;

[0037] Figure 10 A top view schematic diagram of a semiconductor memory device according to a third preferred embodiment of the present invention is shown.

[0038] The reference numerals in the attached figures are explained as follows:

[0039] 100, First semiconductor memory device; 200, Second semiconductor memory device; 300, Third semiconductor memory device; 101, First region; 102, Second region; 110, Substrate; 112, Shallow trench isolation; 113, Active region; 130, First word line; 130a, First bottom surface; 131, Dielectric layer; 133, Gate dielectric layer; 135, Gate; 137, Third insulating layer; 140, Second insulating layer; 142, First insulating layer Layer; 150, First bit line; 150a, Second bottom surface; 151, Semiconductor layer; 153, First barrier layer; 155, First metal layer; 157, Shielding layer; 160, Bit line contact plug; 170, First plug; 190, Second plug; 171, First barrier layer; 191, Second barrier layer; 173, Second metal layer; 193, Third metal layer; 170a, Third bottom surface; 190a, Fifth bottom surface; 170b, Fourth bottom surface; 1 90b, Sixth bottom surface; 230, Second letter line; 231, Second protrusion; 233, First protrusion; 231a, Third protrusion; 233a, Fourth protrusion; 250, Second position line; 251, Fifth protrusion; 253, Sixth protrusion; 251a, Seventh protrusion; 253a, Eighth protrusion; 270, Third plug; 290, Fourth plug; 330, Third letter line; 331, Ninth protrusion; 333, Tenth protrusion ; 331a, Eleventh protrusion; 333a, Twelfth protrusion; 350, Third position line; 351, Thirteenth protrusion; 353, Fourteenth protrusion; 351a, Fifteenth protrusion; 353a, Sixteenth protrusion; 370, Fifth plug; 390, Sixth plug; D1, First direction; D2, Second direction; D3, Third direction; E1, First dashed frame; E2, Second dashed frame; E3, Third dashed frame; E4, Fourth dashed frame. Detailed Implementation

[0040] To enable those skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings.

[0041] Please refer to the following first. Figures 1 to 8 The illustration is a schematic diagram of a semiconductor memory device, namely a first semiconductor memory device 100, according to a first preferred embodiment of the present invention. Figure 1 This is a top view schematic diagram of the first semiconductor memory device 100. Figures 2 to 8This is a cross-sectional schematic diagram of the first semiconductor memory device 100. The first semiconductor memory device 100 is, for example, a dynamic random access memory (DRAM), which includes at least one transistor assembly (not shown) and at least one capacitor structure (not shown) to serve as the smallest unit in a DRAM array and to receive voltage signals from a first wire and a second wire, wherein the first wire is, for example, a first word line 130 and the second wire is, for example, a first bit line 150.

[0042] First, please refer to Figure 1 and Figure 2 As shown, the first semiconductor memory device 100 includes a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate. At least one shallow trench isolation (STI) is formed within the substrate 110 to define a plurality of active areas 113. The active areas 113 extend parallel to each other and spaced apart from each other along a first direction D1, and are alternately arranged along the first direction D1. Thus, the active areas 113 can present a specific arrangement, such as... Figure 1 The array arrangement shown is an example, but not limited to. In one embodiment, each active region 113 is formed, for example, by patterning the substrate 110. For example, a mask layer (not shown) is first formed on the substrate 110. The mask layer includes multiple patterns (not shown) that can be used to define the active regions 113 and exposes a portion of the substrate 110. An etching process is then performed using the mask layer to remove the portion of the substrate 110 to form at least one trench (not shown). A dielectric layer (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, is then formed within the at least one trench. This forms a shallow trench isolation 112 with its top surface flush with the surface of the substrate 110, thus defining the active regions 113. In this way, the shallow trench isolation 112 can be disposed around the active regions 113, and the specific fabrication process of the active regions 113 is not limited to the aforementioned fabrication process. In another embodiment, the active region can also be formed using a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse patterning (SARP) fabrication process, etc.

[0043] Please refer to Figure 1 as well as Figure 2As shown, multiple buried gates 135 are also formed within the substrate 110, which can serve as buried first word lines 130 (BWL). Each first word line 130 extends parallel to each other along the second direction D2 and crosses below each active region 113 (in the first direction D1), as shown. Figure 1 As shown. In one embodiment, the first word line 130 is formed, for example, by means of the following manufacturing process, but not limited thereto. First, a plurality of trenches (not shown) are formed in the substrate 110, the trenches being parallel to each other and extending toward the second direction D2. Then, a dielectric layer 131 covering the entire surface of each of the trenches, a gate dielectric layer 133 and a gate 135 filling the lower half of each of the trenches, and a third insulating layer 137 filling the upper half of each of the trenches are formed sequentially, wherein the top surface of the third insulating layer 137 is flush with the surface of the substrate 110, as shown. Figure 2 As shown. Therefore, the gate poles 135 located within each of the aforementioned ditches can also extend parallel to each other towards the second direction D2, forming as shown. Figure 1 The first character line shown is 130.

[0044] A second insulating layer 140 is formed on the substrate 110. The second insulating layer 140, for example, comprises a silicon monoxide-silicon nitride-oxide (ONO) structure to cover the surface of the substrate 110 and the first word line 130 embedded within the substrate 110. Please refer to... Figure 1 as well as Figure 5 As shown, a plurality of first bit lines 150 are also formed on the substrate 110. Each first bit line 150 extends parallel to each other along a third direction D3 and simultaneously crosses the active region 113 in the first direction D1 and the first word line 130 in the second direction D2. That is, the third direction D3 is different from the first direction D1 and the second direction D2, and is preferably perpendicular to the second direction D2 but not perpendicular to the first direction D1. Furthermore, a plurality of bit line contact plugs 160 (BLC) are formed below a portion of the first bit lines 150, between two adjacent first word lines 130. In this way, the first bit lines 150 and the first word lines 130 can be isolated from each other by the second insulating layer 140, and can be further electrically connected to a source / drain region (not shown) of the transistor component of the first semiconductor memory device 100 through the bit line contact plugs 160.

[0045] In one embodiment, the first bit line 150 and the bit line contact plug 160 are formed, for example, by means of the following fabrication process, but not limited thereto. First, another mask layer (not shown) is formed on the substrate 110. This other mask layer can be used to define the location (not shown) where the bit line contact plug 160 is formed. An etching process is performed using the other mask layer to remove the second insulating layer 140 and the portion of the substrate 110 below it at the location, so as to form a plurality of openings (not shown) on the surface of the substrate 110 between adjacent word lines. Then, the other mask layer is completely removed. During the formation of these openings, an ion implantation process, such as an anti-punch-through ion implantation process, can also be performed simultaneously to further form a doped region (not shown) within the substrate 110 exposed by the openings, thereby preventing current leakage. Subsequently, a semiconductor layer (not shown, for example, a polysilicon layer) is formed on the substrate 110, filling the openings and further covering the substrate 110. Then, a barrier layer (not shown, for example, comprising a titanium layer and / or a titanium nitride layer), a metal layer (not shown, for example, a low-resistivity metal comprising tungsten, aluminum, or copper), and a shielding layer (not shown, for example, comprising silicon nitride or silicon carbonitride) are sequentially formed on the semiconductor layer, but are not limited thereto. Then, a patterning process is performed on the stacked semiconductor layer, the barrier layer, the metal layer, and the shielding layer, such that the semiconductor layer filling the openings can form bit line contact plugs 160, and the stacked semiconductor layer 151, the first barrier layer 153, the first metal layer 155, and the shielding layer 157 on the substrate 110 can form a first bit line 150, such as... Figure 5 As shown. Through the aforementioned manufacturing process, the bit line contact plug 160 is integrally formed with the semiconductor layer 151 of the first bit line 150, such that the bit line contact plug 160 and the semiconductor layer 151 of the first bit line 150 may include the same material (e.g., polysilicon), but are not limited thereto. In another embodiment, the bit line contact plugs and the bit lines may also be selected to include different materials. Furthermore, in another embodiment, to simplify the manufacturing process of the first semiconductor memory device 100, the word lines or the bit lines may be formed by means of the aforementioned self-aligned dual patterning process or the aforementioned self-aligned reverse patterning process.

[0046] It should be noted that the first semiconductor memory device 100 further includes a first region 101 and a second region 102. The first region 101 is, for example, a region with relatively high component density, such as a memory cell region, while the second region 102 is a region with relatively low component density, such as a peripheral region, but is not limited thereto. In this embodiment, the second region 102 is disposed outside and surrounds the first region 101. The aforementioned active region 113, first word line 130, and first bit line 150 are mainly disposed within the first region 101. Furthermore, the first word line 130 and the first bit line 150 further extend into the second region 102 and are electrically connected to an external circuit (not shown) through a plurality of first plugs 170 and a plurality of second plugs 190 disposed within the second region 102. Figure 1 As shown. However, those skilled in the art will readily understand that the relative positions of the first region and the second region are not based on... Figure 1 The examples shown are limited; at the same time, Figure 1 In order to clearly show the connection relationship between the first plug 170 and the first word line 130 or the second plug 190 and the first word line 150, only a portion of the first area 101 is drawn. Therefore, the specific number of active areas 113, the first word line 130, and the first word line 150 is not specified. Figure 1 The examples shown are limited to those shown.

[0047] Specifically, the first plug 170 and the second plug 190 are preferably disposed at two opposite ends of the first letter 130 or the first first letter 150, and completely cover the aforementioned ends. Here, the aforementioned ends of the first letter 130 refer, for example, to the two opposite ends of each first letter 130 in the second direction D2 at approximately 1% to 5% of the overall length, meaning that each first letter 130 is located at... Figure 1 The first end within the first dashed box E1, and the position located in Figure 1 The second end within the second dashed box E2, wherein either the first end or the second end is located within the shallow ditch isolation 112, such as Figure 1 and Figure 2 As shown. Please refer to the following: Figure 1 As shown, the plurality of first plugs 170 electrically connected to each first word line 130 are alternately disposed on the first end or the second end of adjacent first word lines 130, that is, the first plugs 170 are sequentially disposed on each first word line 130. Figure 1Counting from right to left, the first end of the first character line 130, the second end of the second character line 130, the first end of the third character line 130, and so on; and each of the first plugs 170 can be aligned with each other in a third direction D3 perpendicular to the second direction D2, but is not limited thereto. In this embodiment, the first plug 170 can be directly disposed on the first end or the second end of the first character line 130, and completely cover the first end or the second end. That is, each first plug 170 can directly contact at least four surfaces of the first end or the second end, including the top surface of the first end or the second end, the two opposite sidewalls of the first end or the second end in the second direction D2, and the end face of the first end or the second end in the direction perpendicular to the second direction D2 (i.e., the third direction D3), such as... Figure 1 As shown, but not limited to. In another embodiment, at least a portion of the first plug 170 (as shown) Figure 1 (As shown on the left) Alternatively, it can be positioned outside the aforementioned first end or second end of the first character line 130, without covering the aforementioned first end or second end. For example, at least a portion of the first character line 130 (such as...) Figure 1 (As shown on the left) can have a relatively long length. Thus, assuming each of the first plugs 170 is aligned with each other in the third direction D3, the first plugs 170 disposed on at least a portion of the first letter 130 cannot cover the two opposite ends (the first end or the second end) of the first letter 130, particularly the end faces of the first end or the second end in the third direction D3. In this case, the aforementioned portion of the first plug 170 can only directly contact three surfaces of the first letter 130, including the top surface of the first letter 130 and the two opposite sidewalls of the first letter 130 in the second direction D2, such as... Figure 1 As shown on the left. In the aforementioned embodiment, the first word line 130 (e.g., at least a portion of the above-mentioned first word line 130) Figure 1 (As shown on the left) Preferably, it is located at the edge of the first region 101 or within the second region 102, but is not limited thereto.

[0048] Similarly, the aforementioned ends of the first line 150 refer, for example, to the two opposite ends of each first line 150 in the third direction D3, approximately 1% to 5% of the total length, meaning that each first line 150 is located at... Figure 1 The first end within the third dashed box E3, and the position located in Figure 1 The second end within the fourth dashed box E4, the first end or the second end is located on the shallow ditch isolation 112, such as Figure 1 and Figure 5 As shown. Please refer to the following: Figure 1As shown, the plurality of second plugs 190 electrically connecting each first line 150 are alternately disposed on the first end or the second end of adjacent first lines 150, that is, the second plugs 190 are sequentially disposed on... Figure 1 Counting from bottom to top, the second end of the first first line 150, the first end of the second first line 150, the second end of the third first line 150, and so on; and each second plug 190 can be aligned with each other in the second direction D2 perpendicular to the third third direction D3. In this embodiment, the second plug 190 can be directly disposed on the first end or the second end of the first line 150, and completely cover the first end or the second end. That is, each second plug 190 can directly contact at least four surfaces of the first end or the second end, including the top surface of the first end or the second end, the two opposite sidewalls of the first end or the second end in the third third direction D3, and the end face of the first end or the second end in the direction perpendicular to the third third direction D3 (i.e., the second direction D2), such as... Figure 1 As shown, but not limited to. In another embodiment, at least a portion of the second plug 190 (as shown) Figure 1 (As shown above) It can also be optionally positioned outside the aforementioned first end or second end of the first line 150, without covering the aforementioned first end or second end. For example, at least a portion of the first line 150 (such as...) Figure 1 As shown above, the second plugs 190 may have a relatively long length. Therefore, assuming each second plug 190 is aligned with the other in the second direction D2, the second plugs 190 located on at least a portion of the first line 150 cannot cover the two opposite ends (the first end or the second end) of the first line 150, particularly not the end faces of the first or second ends in the second direction D2. In this case, the second plugs 190 can only directly contact three surfaces of the first line 150, including the top surface of the first line 150 and the two opposite sidewalls of the first line 150 in the third direction D3. Figure 1 As shown above. In the foregoing embodiment, at least a portion of the first line 150 (as shown above) Figure 1 (As shown above) Preferably located at the edge of the first region 101 or within the second region 102, but not limited thereto.

[0049] On the other hand, the portions of each first plug 170 and each second plug 190 covering the surfaces (including top surface, sidewall surface, and / or end face) of the first first letter line 130 (the aforementioned first end or the aforementioned second end) or the first first letter line 150 (the aforementioned first end or the aforementioned second end) may have the same or different thicknesses. Correspondingly, the portions of the first plug 170 or the second plug 190 may also have the same or different depths in the direction perpendicular to the substrate 110. In one embodiment, the first plug 170 or the second plug 190 is formed, for example, by means of the following manufacturing process, but is not limited thereto; and the manufacturing process of the first plug 170 may be performed together with the manufacturing process of the second plug 190 or separately. First, a first insulating layer 142 is formed, the first insulating layer 142 comprising, for example, silicon oxide, silicon oxynitride, or silicon nitride, and integrally covers the substrate 110 as an interlayer dielectric layer (ILD). Then, a second mask layer (not shown) is formed on the first insulating layer 142. This second mask layer can be used to define the formation sites (not shown) of the first plug 170 or the second plug 190. An etching process is performed using the second mask layer to remove the first insulating layer 142 and the second insulating layer 140 below it at the aforementioned sites, or only to remove the first insulating layer 142 at the aforementioned sites, forming a plurality of plug holes (not shown) to expose the first end or the second end of the first word line 130, or to expose the first end or the second end of the first word line 150, respectively. Then, the second mask layer is completely removed. Afterward, a barrier layer (not shown, such as titanium, titanium nitride, tantalum, or tantalum oxide) and a metal layer (not shown, such as aluminum, tungsten, copper, or other low-resistivity metal) are sequentially deposited to fill each of the aforementioned plug holes. The first plug 170 or the second plug 190 is then formed through an etching process. Thus, the top surface of the first plug 170 or the second plug 190 can be flush with the top surface of the first insulating layer 142; and each first plug 170 may include a first barrier layer 171 covering the surface of each plug hole and a second metal layer 173 filling each plug hole, such as Figure 2 as well as Figure 3 As shown; and each second plug 190 may include a second barrier layer 191 covering the surface of each plug hole and a third metal layer 193 filling each plug hole, such as Figure 5 as well as Figure 6 As shown.

[0050] It should be noted that during the etching process of the aforementioned plug hole, the etchant or etching gas introduced may be blocked by the lower first letter line 130 (the aforementioned first end or the aforementioned second end) or the first first line 150 (the aforementioned first end or the aforementioned second end). Therefore, when the sidewall of the aforementioned plug hole is too close to the sidewall of the first letter line 130 (the aforementioned first end or the aforementioned second end) or the first first line 150 (the aforementioned first end or the aforementioned second end), the aforementioned etchant or the aforementioned etching gas may not be able to pass through smoothly, thus affecting the etching rate of the aforementioned etching process. Therefore, the first plug 170 (such as...) Figure 2 The sidewall of the first plug 170 (as shown on the right) may gradually slope towards the first letter 130 (the aforementioned first end or the aforementioned second end) until it directly contacts the sidewall surface of the first letter 130 (the aforementioned first end or the aforementioned second end), so that the first plug 170 (as shown on the right) Figure 2 As shown on the right, the portions covering the two opposite sidewalls of the first letter 130 (the aforementioned first end or the aforementioned second end) may have different depths d1 and d2 within the base 110, respectively. Figure 2 As shown. Furthermore, the first plug 170 (as shown) Figure 2 (As shown on the right) The maximum distance L1 between the sidewall of the aforementioned sidewall with a smaller depth d1 and the sidewall surface of the first letter 130 (the aforementioned first end or the aforementioned second end) is less than that of the first plug 170 (as shown on the right). Figure 2 As shown on the right, the maximum distance L2 between the aforementioned sidewall with a greater depth d2 and the sidewall surface of the first letter 130 (the aforementioned first end or the aforementioned second end), that is, the first plug 170 (as shown on the right) Figure 2 As shown on the right, the portions covering the two opposite sidewalls of the first character line 130 (the aforementioned first end or the aforementioned second end) may have different thicknesses L1 and L2, such as... Figure 2 As shown on the right. In another embodiment, the first plug 170 (as shown on the right) Figure 2 The portions covering the two opposite sidewalls of the first letter 130 (the aforementioned first end or the aforementioned second end) may also have the same depth d2 within the base 110, and also the same thickness L2, as shown on the left. Figure 2 As shown on the left. Preferably, the portion of the first plug 170 covering the end face of the first letter 130 (the aforementioned first end or the aforementioned second end) may have a relatively maximum thickness L3 (thickness L3 > thickness L1). Figure 2 (as shown) or thickness L2 (as shown) Figure 2 As shown), to ensure that the first plug 170 can completely cover the end face of the first end or the second end, as shown. Figure 3As shown. Furthermore, in the aforementioned embodiments, although the maximum depth d2 of each portion of the first plug 170 covering each of the aforementioned surfaces of the first letter 130 (the aforementioned first end or the aforementioned second end) within the base 110 is described as not exceeding the depth of the first letter 130 (the aforementioned first end or the aforementioned second end) within the base 110, the third bottom surface 170a of each portion of the first plug 170 covering each of the aforementioned surfaces of the first letter 130 (the aforementioned first end or the aforementioned second end) can be coplanar with the first bottom surface 130a of the first letter 130 (the aforementioned first end or the aforementioned second end), such as... Figure 2 and Figure 3 As shown, but not limited to this. Those skilled in the art will readily understand that in other embodiments, the depth of the first plug 170 formed within the substrate 110 can be adjusted according to actual process requirements, selectively causing the first plug 170 to cover at least one bottom surface of each of the aforementioned portions of the aforementioned surfaces of the first letter line 130 (the aforementioned first end or the aforementioned second end) to be lower than the first bottom surface 130a of the first letter line 130. For example… Figure 4 The diagram shows the fourth bottom surface 170b of the portion of the first plug 170 covering the end face of the first letter line 130 (the aforementioned first end or the aforementioned second end) being lower than the first bottom surface 130a of the first letter line 130. Thus, this portion can also have a relatively large depth d3 within the base 110. In simple terms, the distances between each sidewall of the first plug 170 and each surface of the first letter line 130 can be the same or different, so that the thickness of the first plug 170 covering each surface of the first letter line 130 can also be the same or different. In a preferred embodiment, the greater the distance between the sidewall of the first plug 170 and the surface of the first letter line 130, the deeper this portion is in the direction perpendicular to the base 110, such as the portion of the first plug 170 covering the end face of the first letter line 130, but this is not a limitation.

[0051] Similarly, the second plug 190 (as Figure 5 The sidewall of the second plug 190 (as shown on the left) may gradually slope towards the first line 150 (the first end or the second end) until it directly contacts the sidewall surface of the first line 150 (the first end or the second end), so that the second plug 190 (as shown on the left) Figure 5 The portions covering the two opposite sidewalls of the first line 150 (the aforementioned first end or the aforementioned second end) as shown on the left can have different depths d4 and d5 within the first insulating layer 142, respectively. Figure 5 As shown. Furthermore, the second plug 190 (as shown) Figure 5(As shown on the left) The maximum distance L4 between the aforementioned sidewall with a smaller depth d4 and the sidewall surface of the first line 150 (the aforementioned first end or the aforementioned second end) is less than that of the second plug 190 (as shown on the left). Figure 5 (As shown on the left) The maximum distance L5 between the aforementioned sidewall with a greater depth d5 ​​and the sidewall surface of the first line 150 (the aforementioned first end or the aforementioned second end), that is, the second plug 190 (as shown on the left) Figure 5 The portions covering the two opposite sidewalls of the first line 150 (the aforementioned first end or the aforementioned second end) have different thicknesses L4 and L5, as shown on the left. Figure 5 As shown on the left. In another embodiment, the second plug 190 (as shown on the left) Figure 5 The portions covering the two opposite sidewalls of the first line 150 (the aforementioned first end or the aforementioned second end) as shown on the right can also have the same depth d5 ​​within the first insulating layer 142, and also have the same thickness L5, as... Figure 5 As shown on the right. Preferably, the portion of the second plug 190 covering the end face of the first line 150 (the aforementioned first end or the aforementioned second end) may have a relatively maximum thickness L6 (thickness L6 > thickness L3). Figure 3 and Figure 4 (as shown) or thickness L4 (as shown) Figure 3 and Figure 4 As shown), to ensure that the second plug 190 can completely cover the end face of the first end or the second end, as shown. Figure 6 As shown. Furthermore, in the aforementioned embodiments, although the maximum depth d5 ​​of each portion of the second plug 190 covering each of the surfaces of the first line 150 (the aforementioned first end or the aforementioned second end) within the first insulating layer 142 is described as not exceeding the depth of the first line 150 (the aforementioned first end or the aforementioned second end) within the first insulating layer 142, the fifth bottom surface 190a of the second plug 190 covering each of the aforementioned portions of each of the surfaces of the first line 150 (the aforementioned first end or the aforementioned second end) can be coplanar with the second bottom surface 150a of the first line 150 (the aforementioned first end or the aforementioned second end), that is, located on the second insulating layer 140, as shown. Figure 5 and Figure 6 As shown, but not limited to this. Those skilled in the art will readily understand that in other embodiments, the depth of the second plug 190 formed within the first insulating layer 142 can be adjusted according to actual process requirements. Selectively, the second plug 190 may cover at least one bottom surface of each of the aforementioned portions of the aforementioned surfaces of the first line 150 (the aforementioned first end or the aforementioned second end) that is lower than the second bottom surface 150a of the first line 150. For example… Figure 7The diagram shows the second plug 190 covering the end face portion of the first line 150 (the first end or the second end), with its sixth bottom surface 190b lower than the second bottom surface 150a of the first line 150. This allows the portion to penetrate the second insulating layer 140 and have a relatively large depth d6. In simple terms, the distances between each sidewall of the second plug 190 and each surface of the end of the first line 150 (the first end or the second end) can be the same or different, so that the thickness of the second plug 190 covering each surface of the first line 150 can also be the same or different. In a preferred embodiment, the greater the distance between the sidewall of the second plug 190 and the surface of the first line 150, the deeper the portion in the direction perpendicular to the base 110, such as the portion of the second plug 190 covering the end face of the first line 150, but this is not a limitation.

[0052] Furthermore, in the case where the second plug 190 can further penetrate the second insulating layer 140, after the plug hole has been etched downwards to remove the second insulating layer 140, a lateral etching process can be performed to partially remove the shallow trench isolation 112 below the first line 150 (the first end or the second end). Thus, the formed second plug 190 can further cover a portion of the second bottom surface 150a of the first line 150. Figure 8 As shown, the second plug 190 can directly contact the five surfaces of the first line 150 (the first end or the second end), including the top and bottom surfaces of the first end or the second end, the two opposite sidewalls, and the end face, thereby increasing the contact area between the second plug 190 and the first line 150.

[0053] Therefore, as Figures 1 to 8As shown, in the first preferred embodiment of the present invention, the first semiconductor memory device 100 has a first plug 170 electrically connected to a first word line 130 and / or a second plug 190 electrically connected to a first word line 150 disposed at two opposite ends of the first word line 130 or the first word line 150, and the entire end is covered thereunder. Thereby, the first plug 170 and / or the second plug 190 can directly contact at least four surfaces of the first word line 130 (the first end or the second end) or the first word line 150 (the first end or the second end), including the top surface of the first end or the second end, the two opposite sidewalls, and the end face, thereby increasing the contact area between the first plug 170 and the first word line 130 and / or the second plug 190 and the first word line 150, so that the first plug 170 electrically connected to the first word line 130 and / or the second plug 190 electrically connected to the first word line 150 can have a relatively low contact resistance (Rc). Furthermore, the portions of the first plug 170 covering the first letter 130 and / or the second plug 190 covering the first letter 150 (including the top surface, side wall surface and / or end surface, and even the bottom surface) may have the same or different thicknesses. Correspondingly, the portions of the first plug 170 and / or the second plug 190 may also have the same or different depths in the direction perpendicular to the base 110, and the portions with relatively thicker thicknesses have relatively deeper depths. Preferably, the portion of the first plug 170 covering the end face of the first letter 130 and / or the portion of the second plug 190 covering the end face of the first letter 150 may have a relatively maximum thickness L3 / L6 and a depth d2 / d5 (or depth d3 / d6) relative to the portions of the first plug 170 and / or the second plug 190 covering other portions of the first letter 130 and the first letter 150, to ensure that the first plug 170 and / or the second plug 190 can completely cover the end faces of the ends (the first end or the second end) of the first letter 130 and / or the first letter 150.

[0054] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor memory device of this invention may have other forms or be formed through other manufacturing processes, and is not limited to the foregoing description. For example, in the foregoing embodiments, although the configuration of the first plug 170 electrically connected to the first word line 130 and / or the second plug 190 electrically connected to the first word line 150 is described as an example, it is not limited thereto. In another embodiment, the configuration of the first plug 170 and / or the second plug 190 may also be used to electrically connect other wires of the aforementioned semiconductor memory device, or the first plug 170 and / or the second plug 190 may also have varying configurations. Therefore, other embodiments or variations of the semiconductor memory device and its forming method will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same points. In addition, the same components in the various embodiments of this invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0055] Please refer to Figure 9 The illustration shows a schematic diagram of the second semiconductor memory device 200 in the second preferred embodiment of the present invention. The second semiconductor memory device 200 of this embodiment is generally the same as the first semiconductor memory device 100 in the first preferred embodiment described above, also including a substrate 110, a shallow trench isolation 112, and an active region 113, etc. The similarities will not be repeated here. The main difference between this embodiment and the previous embodiment is that the two opposite ends of the second word line 230 or the second bit line 250 in this embodiment are additionally provided with protrusions. These protrusions extend in a direction perpendicular to the second word line 230 or the second bit line 250. The third plug 270 electrically connected to the second word line 230 and / or the fourth plug 290 electrically connected to the second bit line 250 are still provided at the two opposite ends of the second word line 230 or the second bit line 250, and can optionally completely cover the ends and the protrusions, or partially cover the ends and the protrusions.

[0056] In detail, each of the two adjacent second character lines 230 has a second protrusion 231 and a first protrusion 233 at its first and second ends, respectively. Both the second protrusion 231 and the first protrusion 233 extend in a direction perpendicular to the second character line 230 (i.e., perpendicular to the second direction D2), allowing each second character line 230 to form an L-shape or an inverted L-shape in the second direction D2, but not limited to this. Specifically, the first protrusion 233 at the second end of the second character line 230 extends in a third direction D3, while the second protrusion 231 at the first end of the second character line 230 extends in the opposite direction to the third direction D3. Figure 9As shown. In one embodiment, the second protrusion 231 and the first protrusion 233 may have the same length, so that two adjacent second digit lines 230 may be rotationally symmetrical about a geometric axis (not shown), but this is not a limitation. In another embodiment, the protrusions provided at the first end or the second end may also be selected to have different lengths. Therefore, the third plugs 270 provided at the two opposite ends of the second digit line 230 for electrical connection can directly contact more of the surface of the first end or the second end, while completely covering the first end or the second end and the second protrusions 231 or 233 provided on the first end or the second end, thereby further increasing the contact area between the third plug 270 and the second digit line 230, and effectively reducing the resistance of the third plug 270. The distances between each sidewall of the third plug 270 and each surface of the second protrusion 231 or the first protrusion 233 may be the same or different, so that the thickness of the third plug 270 covering each surface of the second protrusion 231 or the first protrusion 233 may also be the same or different. In a preferred embodiment, the greater the distance between the sidewall of the third plug 270 and the surface of the second protrusion 231 or the first protrusion 233, the deeper the depth of the portion in the direction perpendicular to the base 110. The portion is preferably the portion of the third plug 270 covering the end face of the second protrusion 231 or the first protrusion 233 in the second direction D2, but it is not limited thereto.

[0057] Similarly, a fifth protrusion 251 and a sixth protrusion 253 are respectively provided at the first and second ends of two adjacent second position lines 250. Both the fifth protrusion 251 and the sixth protrusion 253 extend in a direction perpendicular to the second position line 250 (i.e., perpendicular to the third direction D3), so that each second position line 250 can be L-shaped or inverted L-shaped in the third direction D3, but is not limited to this. Specifically, the sixth protrusion 253 at the second end of the second position line 250 extends in the second direction D2, while the fifth protrusion 251 at the first end of the second position line 250 extends in the opposite direction to the second direction D2. Figure 9As shown. In one embodiment, the fifth protrusion 251 and the sixth protrusion 253 may have the same length, so that two adjacent second position lines 250 may be rotationally symmetrical about a geometric axis (not shown), but this is not a limitation. In another embodiment, the protrusions provided at the first end or the second end may also be selected to have different lengths. Therefore, the fourth plug 290 provided at the two opposite ends of the second position line 250 for electrical connection can, while completely covering the first end or the second end and the fifth protrusion 251 or the sixth protrusion 253 provided on the first end or the second end, also directly contact more of the surface of the first end or the second end, thereby further increasing the contact area between the fourth plug 290 and the second position line 250, and effectively reducing the resistance of the fourth plug 290. The distances between each sidewall of the fourth plug 290 and each surface of the fifth protrusion 251 or the sixth protrusion 253 may be the same or different, so that the thickness of the fourth plug 290 covering each surface of the fifth protrusion 251 or the sixth protrusion 253 may also be the same or different. In a preferred embodiment, the greater the distance between the sidewall of the fourth plug 290 and the surface of the fifth protrusion 251 or the sixth protrusion 253, the deeper the depth of the portion in the direction perpendicular to the base 110. The portion is preferably the portion of the fourth plug 290 covering the end face of the fifth protrusion 251 or the sixth protrusion 253 in the third direction D3, but it is not limited thereto.

[0058] On the other hand, in one embodiment, two adjacent second word lines 230 may be selectively aligned and side-by-side with each other on a third direction D3 (e.g. Figure 9 As shown on the left), they can also be arranged in a staggered manner (as shown on the left). Figure 9 (As shown on the right). That is to say, the first end or the second end of two adjacent second characters 230 can be staggered by a distance g1 in the second direction D2, so that the second protrusion 231 and the third protrusion 231a provided on the first end, or the first protrusion 233 and the fourth protrusion 233a provided on the second end, can also be staggered by a distance g1 accordingly, such as... Figure 9 As shown on the right. Alternatively, two adjacent second position lines 250 can also be selectively aligned side-by-side in the second direction D2 (e.g. Figure 9 As shown above), they can also be arranged in a staggered manner (as shown above). Figure 9 (As shown below). That is to say, the first end or the second end of two adjacent second position lines 250 can be staggered by a distance g1 in the third direction D3, so that the fifth protrusion 251 and the seventh protrusion 251a provided on the first end, or the sixth protrusion 253 and the eighth protrusion 253a provided on the second end, can also be staggered by a distance g1 accordingly, such as... Figure 9As shown below. In this way, when setting the third plug 270 that is electrically connected to the second bit line 230 or the fourth plug 290 that is electrically connected to the second bit line 250, the adjacent third plug 270 or the adjacent fourth plug 290 can have a relatively large manufacturing space, thereby avoiding short circuits. Furthermore, in another embodiment, the third plug 270 electrically connected to the second bit line 230 or the fourth plug 290 electrically connected to the second bit line 250 may optionally completely cover the first end or the second end, but only partially cover the second protrusion 231 / fifth protrusion 251 or the first protrusion 233 / sixth protrusion 253 disposed on the first end or the second end, such that at least one surface of the second protrusion 231 / fifth protrusion 251 or the first protrusion 233 / sixth protrusion 253 (such as the aforementioned end face of the second protrusion 231 / fifth protrusion 251 or the first protrusion 233 / sixth protrusion 253) is not covered by the third plug 270 / fourth plug 290. Thus, adjacent third plugs 270 (such as...) Figure 9 (as shown on the left) or the adjacent fourth plug 290 (as shown on the left) Figure 9 There is relatively more production space between them (as shown above).

[0059] Therefore, in the second preferred embodiment of the present invention, the semiconductor memory device 200 is further improved by the protrusions added to the two opposite ends of the second word line 230 and / or the second bit line 250, thereby increasing the contact area of ​​the third plug 270 electrically connected to the second word line 230 and / or the fourth plug 290 electrically connected to the second bit line 250, and more effectively reducing the resistance of the third plug 270 and / or the fourth plug 290. Those skilled in the art will readily understand that although the shapes of the protrusions described in the foregoing embodiments are all described as straight lines, this is not a limitation. While increasing the contact area between the plugs and the wires, the protrusions can be further varied or configured according to actual component requirements. For example, in other embodiments, the protrusions may also have other shapes, such as L-shapes, or different sizes or lengths.

[0060] Please refer to Figure 10As shown, the illustration is a schematic diagram of a third semiconductor memory device 300 in the third preferred embodiment of the present invention. The third semiconductor memory device 300 in this embodiment is generally the same as the second semiconductor memory device 200 in the aforementioned second preferred embodiment, and the similarities will not be repeated. The main difference between this embodiment and the aforementioned embodiments lies only in the shape of the protrusion. The fifth plug 370 electrically connected to the third word line 330 and / or the sixth plug 390 electrically connected to the third bit line 350 are still provided at the two opposite ends of the third word line 330 or the third bit line 350, and can selectively completely cover the ends and the protrusion, or partially cover the ends and the protrusion.

[0061] In detail, the ninth protrusion 331 and tenth protrusion 333 located at the first or second end of the third letter line 330 are, for example, L-shaped or inverted L-shaped. Preferably, each tenth protrusion 333 located at the first end and each ninth protrusion 331 located at the second end may have the same size and shape. In this way, two adjacent third letter lines 330 may be rotationally symmetrical about a geometric axis (not shown), but this is not a limitation. However, in another embodiment, the protrusions located at the first or second end of the third letter line 330 may also be selected to have different sizes or shapes. Therefore, the fifth plug 370, which is provided at both opposite ends of the third digit line 330 for electrical connection, can directly contact more of the surface of the first or second end while completely covering the first or second end and the ninth or tenth protrusion 331 or 333 provided on the first or second end, thereby further increasing the contact area between the fifth plug 370 and the third digit line 330 and effectively reducing the resistance of the fifth plug 370. Similarly, the thirteenth protrusion 351 and fourteenth protrusion 353 provided at the first or second end of the third digit line 350 can also be L-shaped or inverted L-shaped, and the fourteenth protrusion 353 provided at the first end and the thirteenth protrusion 351 provided at the second end preferably have the same size and shape. In this way, two adjacent third digit lines 350 can be rotationally symmetrical about a geometric axis (not shown), but this is not a limitation. However, in another embodiment, the protrusions at the first or second end of the third bit line 350 may also be selected to have different sizes or shapes. In this way, the sixth plug 390, which is provided at both opposite ends of the third bit line 350 for electrical connection, can directly contact more of the surface of the first or second end while completely covering the first or second end and the thirteenth or fourteenth protrusion 351 or fourteenth protrusion 353 provided on the first or second end. This further increases the contact area between the sixth plug 390 and the third bit line 350, thereby effectively reducing the resistance of the sixth plug 390. It should be noted that the distances between the sidewalls of the fifth plug 370 or the sixth plug 390 and the surfaces of the protrusions may be the same or different, so that the thickness of the plug 370 or the sixth plug 390 covering the different surfaces of the protrusions may also be the same or different. In a preferred embodiment, the greater the distance between the sidewall of the fifth plug 370 or the sixth plug 390 and the surface of the protrusion, the deeper the depth of the portion in the direction perpendicular to the base 110. The portion is preferably the portion of the fifth plug 370 or the sixth plug 390 covering the end face of the protrusion, but is not limited thereto.

[0062] On the other hand, in one embodiment, two adjacent third word lines 330 may also be selectively aligned and arranged side by side on the third direction D3 (e.g. Figure 10 As shown on the left), they can also be arranged in a staggered manner (as shown on the left). Figure 10 (As shown on the right). That is to say, the first end or the second end of two adjacent third characters 330 can be staggered by a distance g1 in the second direction D2, so that the ninth protrusion 331 and the eleventh protrusion 331a provided on the first end, or the tenth protrusion 333a and the twelfth protrusion 333a provided on the second end, can also be staggered by a distance g1 accordingly, such as... Figure 10 As shown on the right. Alternatively, two adjacent third position lines 350 can also be selectively aligned side-by-side in the second direction D2 (e.g. Figure 10 As shown above), they can also be arranged in a staggered manner (as shown above). Figure 10 (As shown below). That is to say, the first end or the second end of two adjacent third position lines 350 can be staggered by a distance g1 in the third direction D3, so that the thirteenth protrusion 351 and the fifteenth protrusion 351a provided on the first end, or the fourteenth protrusion 353 and the sixteenth protrusion 353a provided on the second end, can also be staggered by a distance g1 accordingly, such as... Figure 10 As shown below. Thus, when setting the fifth plug 370 for electrical connection of the third bit line 330 or the sixth plug 390 for electrical connection of the third bit line 350, the adjacent fifth plug 370 or the adjacent sixth plug 390 can also have relatively large manufacturing space, thereby avoiding short circuits. Furthermore, in another embodiment, the fifth plug 370 electrically connected to the third bit line 330 or the sixth plug 390 electrically connected to the third bit line 350 may optionally completely cover the first end or the second end, but only partially cover the ninth protrusion 331 / thirteenth protrusion 351 or tenth protrusion 333 / fourteenth protrusion 353 disposed on the first end or the second end, such that at least one surface of the ninth protrusion 331 / thirteenth protrusion 351 or tenth protrusion 333 / fourteenth protrusion 353 (such as the aforementioned end face of the ninth protrusion 331 / thirteenth protrusion 351 or tenth protrusion 333 / fourteenth protrusion 353) is not covered by the fifth plug 370 / sixth plug 390, thus, adjacent fifth plugs 370 (such as Figure 10 (as shown on the left) or the adjacent sixth plug 390 (as shown on the left) Figure 10 There is relatively more production space between them (as shown above).

[0063] Therefore, the third semiconductor memory device 300 of the third preferred embodiment of the present invention further increases the contact area of ​​the fifth plug 370 electrically connected to the third word line 330 and / or the sixth plug 390 electrically connected to the third bit line 350 by changing the shape of the protrusions provided at the ends of the third word line 330 and / or the third bit line 350, and can more effectively reduce the resistance of the fifth plug 370 and / or the sixth plug 390. Furthermore, those skilled in the art should readily understand that the specific shape changes of the protrusions are not limited to those described above. For example, when forming the third word line 330 and / or the third bit line 350, the etching process conditions can be adjusted so that the formed protrusions are partially rounded and can generally present an arc shape (not shown) or a hook shape (not shown), which also helps to increase the contact area between the protrusions and the plugs.

[0064] In general, the semiconductor memory device of the present invention places plugs at both opposite ends of a conductor (bit line or word line, etc.) and completely covers the ends of the conductor. Thus, the plugs can at least directly contact the top surface, sidewalls, and end faces of the ends of the conductor, increasing the contact area between the plugs and the conductor and reducing the contact resistance of the plugs. Furthermore, the ends of the conductors may optionally have an additional protrusion to further increase the contact area between the plugs and the conductors, wherein the protrusion may have various shapes (straight, L-shaped, arc-shaped, or hook-shaped) or sizes. Therefore, the semiconductor memory device of the present invention helps to improve the reliability of the electrical connection between the plugs and the conductors.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that, Include: One base; Multiple active regions are defined on the substrate; A plurality of first wires extend parallel to each other along a first direction, the first wires traversing the active region, wherein each first wire has a first end and a second end opposite to each other; and At least one first plug is disposed on the first end of the first wire and electrically connected to the first wire, wherein the first plug completely covers the first end of the first wire and directly contacts the top surface, side wall, bottom surface and end face of the first end.

2. The semiconductor memory device according to claim 1, characterized in that, The thickness of the sidewall covered by the first plug at the first end is less than the thickness of the end face covered by the first plug at the first end.

3. The semiconductor memory device according to claim 1, characterized in that, The portion of the first plug covering the sidewall and end face of the first end has a different depth in a direction perpendicular to the base.

4. The semiconductor memory device according to claim 1, characterized in that, The distances from different sidewalls of the first plug to different surfaces of the first end are different, and the greater the distance from the first plug to the first end, the deeper it is in the direction perpendicular to the base.

5. The semiconductor memory device according to claim 1, characterized in that, The semiconductor memory device further includes: A plurality of second conductors extend parallel to each other along the first direction and across the active region, wherein each second conductor is sequentially alternated with each first conductor in a second direction perpendicular to the first direction, and each second conductor has opposing first and second ends; and At least one second plug is disposed on the second end of the second wire and electrically connected to the second wire, wherein the second plug completely covers the second end of the second wire.

6. The semiconductor memory device according to claim 1, characterized in that, Each of the first wires has a first protrusion at its first end, and adjacent first protrusions are staggered by a predetermined distance in the first direction, with the first protrusions extending in a second direction perpendicular to the first direction.

7. The semiconductor memory device according to claim 6, characterized in that, Each of the first plugs corresponds to one of the first wires, and the first plug completely covers the first end and the first protrusion of the first wire.

8. The semiconductor memory device according to claim 6, characterized in that, Each of the first conductors has a second protrusion at its second end, and adjacent second protrusions are staggered by a predetermined distance in the first direction, with each second protrusion extending in the opposite direction to the second direction.

9. The semiconductor memory device according to claim 1, characterized in that, It also includes: a plurality of third conductors extending parallel to each other along a first direction, wherein the third conductors are disposed on one side of the first conductor, and each of the third conductors has a first end and a second end opposite to each other; and At least one third plug is disposed on the third conductor, near the first end of the third conductor, and electrically connected to the third conductor, wherein the third plug does not cover the first end of the third conductor.

10. The semiconductor memory device according to claim 1, characterized in that, The semiconductor memory device further includes: A plurality of second conductors extend parallel to each other along the first direction and across the active region, wherein each second conductor is sequentially alternated with each first conductor in a second direction perpendicular to the first direction, and each second conductor has opposing first and second ends; and At least one second plug is disposed on the second end of the second wire and electrically connected to the second wire, wherein the bottom surface of the second plug is lower than the bottom surface of the second wire.

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