A reusable multi-system FPGA test system

Abstract

This invention discloses a reusable multi-system FPGA test system. The FPGA test equipment includes a chassis, a main control module, at least one data transceiver module, and a clock module within the chassis, as well as adapter modules connected to each data transceiver module. Each adapter module of the FPGA test equipment is connected to the pins of the FPGA under test (DUT) via a dedicated connector, transmitting data to be sent from the data transceiver module to the DUT, and transmitting the data output from the DUT to the data transceiver module for verification. The clock module is connected to the DUT via a dedicated clock interface, transmitting the generated clock signal to the DUT through the dedicated interface. The DUT then processes the data received from the dedicated connector and the clock signal received from the clock module, generating and outputting the output data. This invention solves the problem of limited airworthiness confidence caused by the limited number of FPGAs that can be tested on the target board in existing FPGA test environments.

Description

Technical Field

[0001] This invention relates to, but is not limited to, the field of civil aviation FPGA verification technology, and particularly to a reusable multi-system FPGA test system. Background Technology

[0002] In civil aviation, FPGA verification follows the DO-254 standard, employing review, analysis, and testing as verification methods. Testing offers the highest airworthiness confidence, therefore, FPGA requirements should be covered by testing as extensively as possible. The use of testing methods necessitates a physical testing environment; the quality of the testing environment design and the speed of production directly impact the efficiency of the entire testing process.

[0003] FPGA (Field-Programmable Gate Array) is a programmable logic device that can be repeatedly programmed, offering excellent flexibility. It is primarily used to implement complex functions and is widely used in the aerospace industry. Aircraft have multiple systems, each performing different functions, and the FPGAs used in each system also have different functionalities. For aircraft manufacturers, building separate testing environments for different systems or subsystems would be prohibitively costly and time-consuming.

[0004] The existing FPGA testing environment consists of the circuit board containing the FPGA (i.e., the target board) and the testing software. The existing FPGA testing environment has the following problems: Firstly, because the target board is designed primarily to meet design requirements, the number of pins available for FPGA measurement is limited. While logic analyzers and other instruments are used for better testing of FPGA functionality and performance, the target board does not have connectors for measurement, making it difficult to measure many FPGA signals. Secondly, the testing software is developed based on the product software, and some abnormal stimuli cannot be generated during FPGA testing. Therefore, it can be seen that the number of FPGAs that can be tested on the target board is limited, resulting in limited airworthiness confidence. Summary of the Invention

[0005] The purpose of this invention is to solve the above-mentioned technical problems. This invention provides a reusable multi-system FPGA test system to address the problem that the existing FPGA test environment has a limited number of FPGAs that can be tested on the target board, resulting in limited airworthiness confidence.

[0006] The technical solution of the present invention: The embodiments of the present invention provide a reusable multi-system FPGA test system, including: FPGA test equipment, FPGA under test and dedicated connector;

[0007] The FPGA testing equipment includes a chassis, a main control module, at least one data transceiver module and a clock module that are plugged into the chassis via chassis slots, and an adapter module that is connected to each data transceiver module respectively.

[0008] Each adapter module of the FPGA test equipment is connected to the pins of the FPGA under test via a dedicated connector. It is used to transmit the data to be sent in the data transceiver module to the FPGA under test, and also to transmit the data output by the FPGA under test to the data transceiver module for verification.

[0009] The clock module is connected to the FPGA under test via a dedicated clock interface to generate a clock at a specified frequency and transmit the clock to the FPGA under test via the dedicated clock interface. This allows the FPGA under test to process the data received from the dedicated connector and the clock received from the clock module, generate output data, and output it through the dedicated connector.

[0010] Optionally, in the reusable multi-system FPGA test system described above,

[0011] In the FPGA test equipment, each adapter module is equipped with 32 single-ended paths and 16 low-voltage differential signal paths.

[0012] The data transceiver module connected to each adapter module is used to control the data flow direction from the data transceiver module, the corresponding connected adapter module, the dedicated connector to the FPG under test, wherein the data flow direction is unidirectional transmission, unidirectional reception, or bidirectional.

[0013] Optionally, in the reusable multi-system FPGA test system described above,

[0014] The testing process of the reusable multi-system FPGA test system includes:

[0015] Step 1: The FPGA test equipment transmits the data to be sent from the main control module to the data transceiver module, which converts it into timing data and then transmits it to the corresponding dedicated connector through the general interface on the corresponding adapter module. When the timing data includes different types of timing data, the order in which the different types of data are sent can be configured as needed.

[0016] Step 2: Send a clock of a specified frequency to the clock module through the interface of the FPGA test equipment. The clock module generates a clock of the specified frequency and transmits it to the dedicated clock interface of the verification board through an RF coaxial cable. If multiple clocks are generated, the phase between the multiple clocks can be configured.

[0017] Step 3: The clock on the dedicated clock interface and the timing data on the dedicated connector form complete FPGA input data in the FPGA under test. The FPGA under test processes at least two FPGA input data channels to generate FPGA output data, which is then output through the dedicated connector.

[0018] Optionally, in the reusable multi-system FPGA test system described above, in step 3 of the test process of the reusable multi-system FPGA test system, the FPGA output data output through the dedicated connector is transmitted by the corresponding adapter module to the data transceiver module for parsing and then transmitted to the main control module.

[0019] Optionally, in the reusable multi-system FPGA test system described above,

[0020] In the FPGA testing system, the FPGA input / output interfaces are led out from the FPGA under test to a dedicated connector to form a verification board, which enables the verification board to be connected to the FPGA testing equipment and to be directly measured by a logic analyzer; the dedicated clock interface is set on the verification board.

[0021] The FPGA test equipment and verification board form the first structural component of the FPGA test system.

[0022] Optionally, the reusable multi-system FPGA test system described above further includes: a dedicated pin measurement board, which is connected to a dedicated connector for outputting FPGA output data; the FPGA test equipment, the verification board, and the dedicated pin measurement board form a second structural configuration of the FPGA test system.

[0023] In step 3 of the testing process of the reusable multi-system FPGA test system

[0024] The FPGA output data, which is output through a dedicated connector, is transmitted to external measuring instruments via a dedicated pin measurement board.

[0025] Optionally, in the reusable multi-system FPGA test system described above, the FPGA under test is located in the FPGA target board, and the FPGA test system further includes: multiple pairs of target board connectors and adapter boards, each pair of target board connectors being used to connect the FPGA target board and the adapter board respectively;

[0026] The adapter board includes a conversion circuit, dedicated connectors connected to the conversion circuit, and a dedicated clock interface. The target board connector located in the adapter board is connected to the conversion circuit.

[0027] The FPGA test equipment, FPGA target board, and conversion board form the third component structure of the FPGA test system.

[0028] Optionally, the reusable multi-system FPGA test system described above further includes: a dedicated pin measurement board, which is connected to a dedicated connector for outputting FPGA output data;

[0029] The FPGA test equipment, FPGA target board, conversion board, and dedicated pin measurement board form the fourth component structure of the FPGA test system;

[0030] In step 3 of the testing process of the reusable multi-system FPGA test system

[0031] The FPGA output data, which is output through a dedicated connector, is transmitted to external measuring instruments via a dedicated pin measurement board.

[0032] Optionally, in the reusable multi-system FPGA test system described above,

[0033] The number of dedicated clock interfaces is equal to the number of data types containing clock data sent by the data transceiver module;

[0034] Different dedicated clock interfaces are used to receive clocks generated by the same or different clock modules. Multiple clock modules are used to send clocks with different frequencies and phases. The same clock module is used to send clocks with the same frequency and phase, or clocks with the same frequency but different phases.

[0035] The beneficial effects of this invention are as follows: This invention provides a reusable multi-system FPGA test system. On one hand, it adopts a main structure of FPGA test equipment, FPGA under test (DUT), and dedicated connectors. Each adapter module in the FPGA test equipment is connected to the pins of the DUT via a dedicated connector. This allows the data to be transmitted from the data transceiver module to the DUT, and also allows the data output from the DUT to be transmitted to the data transceiver module for verification. The clock module is connected to the DUT via a dedicated clock interface. The clock module transmits a generated clock at a specified frequency to the DUT via the dedicated clock interface, enabling the DUT to process the data received from the dedicated connector and the clock received from the clock module, generate output data, and output it through the dedicated connector to verify the DUT. On the other hand, the FPGA test equipment, the DUT, the dedicated connectors, the dedicated clock interface, and the dedicated pin measurement board and external measuring instruments used in conjunction can form a test system with four different structural compositions.

[0036] The four structural components of the test system provided in this invention can all perform FPGA testing. The key is that the adapter module provides a universal interface, supporting the transmission of various signals and allowing measurement of signals on the FPGA's output pins. Therefore, the test environment design method can be used across different projects and systems. Specifically, this invention provides an FPGA test system compliant with DO-254 requirements. This FPGA test system can be reused in FPGA verification across multiple systems and projects, significantly reducing costs, improving efficiency, and shortening development time. Attached Figure Description

[0037] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions of the present invention.

[0038] Figure 1 This is a schematic diagram of configuration 1 in the reusable multi-system FPGA test system provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of configuration 2 in the reusable multi-system FPGA test system provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of configuration 3 in the reusable multi-system FPGA test system provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of configuration 4 in the reusable multi-system FPGA test system provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0043] As explained in the background section, existing FPGA testing environments have a limited number of FPGAs that can be tested on the target board, resulting in limited airworthiness confidence. Therefore, designing a testing environment that meets the airworthiness requirements for civil aviation FPGA testing while reducing time and cost is highly beneficial for FPGA verification. Furthermore, if the testing environment can be reused to some extent, the goal can be achieved.

[0044] This invention provides a method for constructing a reusable multi-system FPGA test system. The FPGA test system constructed using this method can meet the needs of testing FPGAs in real-world environments as much as possible and effectively meet airworthiness requirements. For testing between different systems, testing can be achieved in a short time by minimizing changes to the FPGA test system hardware and / or by developing only the software, thereby shortening development time and reducing costs.

[0045] The present invention provides the following specific embodiments, which can be combined with each other. For the same or similar concepts or processes, they may not be described again in some embodiments.

[0046] This invention provides a reusable FPGA test system for multiple systems. Figure 1 This is a schematic diagram of configuration 1 in the reusable multi-system FPGA test system provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of configuration 2 in the reusable multi-system FPGA test system provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of configuration 3 in the reusable multi-system FPGA test system provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of configuration 4 in the reusable multi-system FPGA test system provided in an embodiment of the present invention. Figure 1 and Figure 2 Configurations 1 and 2 shown adopt the structure of a verification plate. Figure 3 and Figure 4 Configurations 3 and 4 shown adopt the structure of an adapter plate.

[0047] Reference Figures 1 to 4 As shown, the reusable multi-system FPGA test system provided in this embodiment of the invention includes: FPGA test equipment, FPGA under test, and dedicated connector.

[0048] The FPGA test equipment in this embodiment of the invention includes a chassis (with multiple slots), a main control module, at least one data transceiver module and a high-precision clock module that are plugged into the chassis via chassis slots, and an adapter module that is connected to each data transceiver module.

[0049] In this embodiment of the invention, each adapter module of the FPGA test device is connected to the pins of the FPGA under test via a dedicated connector. It is used to transmit the data to be sent in the data transceiver module to the FPGA under test, and also to verify the data output by the FPGA under test after it has been transmitted to the data transceiver module.

[0050] In this embodiment of the invention, the clock module is connected to the FPGA under test via a dedicated clock interface to generate a clock at a specified frequency and transmit the clock to the FPGA under test via the dedicated clock interface. This allows the FPGA under test to process the data received from the dedicated connector and the clock received from the clock module, generate output data, and output it through the dedicated connector.

[0051] In this embodiment of the invention, the FPGA test equipment is a device composed of hardware and software. The software is developed according to the FPGA functions, and the hardware provides a universal path that can be reused across multiple systems. In specific implementation, each adapter module is equipped with 32 single-ended paths and 16 low-voltage differential signal paths.

[0052] The data transceiver module connected to each adapter module can control the data flow direction from the data transceiver module, the corresponding connected adapter module, the dedicated connector to the FPG under test, wherein the data flow direction is unidirectional transmission, unidirectional reception, or bidirectional.

[0053] The testing process of the reusable multi-system FPGA test system provided in this embodiment of the invention includes:

[0054] Step 1: The FPGA test equipment transmits the data to be sent from the main control module to the data transceiver module, which converts it into timing data and then transmits it to the corresponding dedicated connector through the general interface on the corresponding adapter module. When the timing data includes different types of timing data, the order in which the different types of data are sent can be configured as needed.

[0055] Step 2: Send a clock of a specified frequency to the clock module through the interface of the FPGA test equipment. The clock module generates a clock of the specified frequency and transmits it to the dedicated clock interface of the verification board through an RF coaxial cable. If multiple clocks are generated, the phase between the multiple clocks can be configured.

[0056] Step 3: The clock on the dedicated clock interface and the timing data on the dedicated connector form complete FPGA input data in the FPGA under test. The FPGA under test processes at least two FPGA input data channels to generate FPGA output data, which is then output through the dedicated connector.

[0057] In step 3, the FPGA output data output through the dedicated connector is transmitted by the corresponding adapter module to the data transceiver module for parsing, and then transmitted to the main control module.

[0058] In one implementation of this invention, such as Figure 1In the FPGA test system shown, the FPGA input / output interface is led out from the FPGA under test to a dedicated connector to form a verification board, which can be connected to the FPGA test equipment and can be directly measured by a logic analyzer; the dedicated clock interface is set on the verification board.

[0059] In this implementation, the FPGA test equipment and the verification board form the first structural component of the FPGA test system, namely... Figure 1 Configuration 1 is shown.

[0060] In one implementation of this invention, such as Figure 2 As shown, in Figure 1 Based on configuration 1 shown, the FPGA test system also includes a dedicated pin measurement board, which is connected to a dedicated connector for outputting FPGA output data.

[0061] In this implementation, the FPGA test equipment, verification board, and dedicated pin measurement board form the second structural composition of the FPGA test system, namely... Figure 2 Configuration 2 is shown.

[0062] Accordingly, in step 3 of the test process of the reusable multi-system FPGA test system shown in configuration 2, the FPGA output data output through the dedicated connector is transmitted to the external measuring instrument by the dedicated pin measurement board.

[0063] In one implementation of this invention, such as Figure 3 In the FPGA test system shown, the FPGA under test is located in the FPGA target board. The FPGA test system also includes multiple pairs of target board connectors and adapter boards. Each pair of target board connectors is used to connect the FPGA target board and the adapter board, respectively.

[0064] The adapter board includes a conversion circuit, dedicated connectors connected to the conversion circuit, and a dedicated clock interface. The target board connectors located in the adapter board are connected to the conversion circuit.

[0065] In this implementation, the FPGA test equipment, the FPGA target board, and the conversion board form the third structural component of the FPGA test system, namely... Figure 3 Configuration 3 is shown.

[0066] In one implementation of this invention, such as Figure 4 As shown, in Figure 3 Based on configuration 1 shown, the FPGA test system also includes a dedicated pin measurement board, which is connected to a dedicated connector for outputting FPGA output data.

[0067] In this implementation, the FPGA test equipment, FPGA target board, conversion board, and dedicated pin measurement board form the fourth component structure of the FPGA test system, namely... Figure 4 Configuration 4 is shown.

[0068] Accordingly, in step 3 of the test process of the reusable multi-system FPGA test system shown in configuration 4, the FPGA output data output through the dedicated connector is transmitted to the external measuring instrument by the dedicated pin measurement board.

[0069] It should be noted that in this embodiment of the invention, the number of dedicated clock interfaces is equal to the number of data types containing clock data sent by the data transceiver module;

[0070] Different dedicated clock interfaces are used to receive clocks generated by the same or different clock modules. Multiple clock modules are used to send clocks with different frequencies and phases. The same clock module is used to send clocks with the same frequency and phase, or clocks with the same frequency but different phases.

[0071] The reusable multi-system FPGA test system provided in this invention provides the above four configuration forms, mainly composed of the following structures:

[0072] (1) Composition and structure of FPGA test equipment and verification board;

[0073] (2) The structure consisting of FPGA test equipment, target board, and adapter board used to connect FPGA test equipment and target board.

[0074] Both of the above-mentioned structures can be combined with a dedicated pin measurement board and external measuring instruments.

[0075] The components in the two structural configurations described below will be explained:

[0076] 1) FPGA test equipment is a combination of hardware and software. The software is developed based on the functions of FPGA, and the hardware provides a universal path that can be reused across multiple systems.

[0077] 2) The verification board is a circuit board developed based on the target board where the FPGA is located. While keeping the original target board layout and wiring unchanged as much as possible, and ensuring that the timing of the FPGA input and output interfaces remains unchanged, the target board is modified to bring out the FPGA input and output interfaces from the FPGA under test to a dedicated connector to form the verification board. This verification board can be connected to the FPGA test equipment and can be directly measured by a logic analyzer.

[0078] 3) The adapter board is a circuit board developed based on the FPGA target board and FPGA test equipment, used to perform interface conversion between the FPGA target board and the FPGA test equipment.

[0079] 4) The FPGA test equipment hardware includes one chassis (multiple slots), one main control module, multiple data transceiver modules, multiple adapter modules corresponding to the data transceiver modules, and multiple high-precision clock templates.

[0080] The data transceiver module in the FPGA test equipment generates the timing sequence of the logic input data of the FPGA under test, parses the timing sequence of the output data, and stores the data.

[0081] In FPGA test equipment, the adapter module and clock module are key to multiplexing across multiple systems and projects. The external interfaces of the adapter module (excluding the clock) are GPIO interface (general purpose single-ended input / output interface) and LVDS differential pair interface; one clock module can be configured to generate multiple high-precision clocks and the clock frequency can be configured, and multiple clock modules can generate synchronous clocks between different data transceiver modules.

[0082] The interface between the dedicated connector and the adapter module in the FPGA test equipment is a general-purpose interface, such as a GPIO interface.

[0083] The reusable multi-system FPGA test system provided in this invention has two main components. First, it employs an FPGA test device, an FPGA under test (DUT), and dedicated connectors. Each adapter module in the FPGA test device connects to the pins of the DUT via a dedicated connector, allowing data to be transmitted from the data transceiver module to the DUT. It also allows data output from the DUT to the data transceiver module for verification. A clock module connects to the DUT via a dedicated clock interface, transmitting a generated clock signal at a specified frequency to the DUT. This enables the DUT to process the data received from the dedicated connectors and the clock signal received from the clock module, generating output data which is then output through the dedicated connectors for verification. Second, the FPGA test device, DUT, dedicated connectors, dedicated clock interface, and associated dedicated pin measurement boards and external measuring instruments can form a test system with four different configurations.

[0084] The four structural components of the test system provided in this invention can all perform FPGA testing. The key is that the adapter module provides a universal interface, supporting the transmission of various signals and allowing measurement of signals on the FPGA's output pins. Therefore, the test environment design method can be used across different projects and systems. Specifically, this invention provides an FPGA test system compliant with DO-254 requirements. This FPGA test system can be reused in FPGA verification across multiple systems and projects, significantly reducing costs, improving efficiency, and shortening development time.

[0085] The following describes the implementation of the reusable multi-system FPGA test system provided in the embodiments of the present invention through some specific implementation examples.

[0086] The reusable multi-system FPGA test system has four structural configurations, which can be divided into two categories. Figure 1 This describes the composition and structure of FPGA test equipment and verification boards. Figure 2 This describes the composition of FPGA test equipment, verification boards, and dedicated pin measurement boards. Figure 3 This describes the structure of the FPGA test equipment, adapter board, and target board. Figure 3 This describes the structure of an FPGA test device, adapter board, target board, and dedicated pin measurement board.

[0087] The FPGA test equipment in the above four components has the same structural design.

[0088] The hardware components of the FPGA test equipment include:

[0089] 1) One PIXE chassis with 9 slots, USB ports, power switch, and external power supply, monitor, etc.

[0090] 2) One main control module, containing a CPU, is used to control the entire process of sending and receiving data.

[0091] 3) Four data transceiver modules: These four data transceiver modules are of the same type of board, with FPGA and memory on the board. They can convert the data to be sent into timing data of the FPGA under test. In this process, some data, such as SPI data or RGB video data, can be buffered before being sent. The purpose of controlling the transmission interval of SPI data and RGB data can be achieved, thereby ensuring the configurability of the transmission time interval between the two. In addition, the received timing data can be converted into data without timing.

[0092] 4) Four adapter modules. These four adapter modules are of the same type. Each card has 32 single-ended channels with a maximum speed of 300Mbps and 16 low-voltage differential signal (LVDS) channels.

[0093] 5) One clock module outputs two clock frequencies or clocks with the same frequency but different phases, which can be configured.

[0094] The software on the FPGA test equipment controls the content and order of data transmission and reception according to the FPGA requirements, and determines whether configuration is required.

[0095] In the embodiments of this invention, the target board is the actual circuit board product where the FPGA is located.

[0096] The verification board in the embodiment of the present invention is developed based on the target board. While keeping the timing of the FPGA peripheral interface unchanged, it provides a dedicated clock interface 1 and a dedicated clock interface 2, and four dedicated connectors of the same type.

[0097] by Figure 2 Taking the structure shown as an example, this structure is a test system consisting of an FPGA test device, a verification board, and a dedicated pin measurement board. The data flow between the FPGA test device, the verification board, and the dedicated pin measurement board is as follows:

[0098] 1) The FPGA test equipment transmits the data to be sent (the data can be displayed on the display interface) through the main control module to the corresponding data transceiver module 1, which converts it into 28-bit RGB video timing data (2-bit horizontal and vertical synchronization data, 1-bit video data presence / absence flag, 1-bit pixel data validity flag, and 24-bit pixel data) and 4-bit SPI timing data (the presence or absence of 4-bit SPI timing data is determined according to the different paths). Then, it is transmitted to the connector 1 of the verification board through the general interface on the corresponding adapter module 1. The transmission order of the 28-bit RGB video timing data and the 4-bit SPI timing data can be configured as needed.

[0099] 2) The FPGA test equipment transmits the data to be sent from the display interface to the corresponding data transceiver module 2 through the main control module, converts it into 28-bit RGB video timing data (2-bit horizontal and vertical synchronization data, 1-bit video data presence / absence flag, 1-bit pixel data validity flag, and 24-bit pixel data), and then transmits it to the connector 2 of the verification board through the general interface on the corresponding adapter module 2.

[0100] 3) A 119MHz clock is sent to clock module 1 through the interface of the FPGA test equipment. Clock module 1 generates two 119MHz clocks and transmits them to dedicated clock interface 1 and dedicated clock interface 2 on the verification board via RF coaxial cable. The phase between the two clocks can be adjusted.

[0101] 3) The clock on the dedicated clock interface 1 on the verification board and the video timing data on the dedicated connector 1 form complete RGB video data at the receiving end of the FPGA under test.

[0102] 4) The clock on the dedicated clock interface 2 on the verification board and the video timing data on the dedicated connector 2 form complete RGB video data at the receiving end of the FPGA under test.

[0103] 5) The FPGA under test processes the two input RGB video data streams and outputs one RGB video data stream (including 28-bit RGB timing data + 1-bit 119MHz clock data) and one LVDS data stream, which are transmitted to FPGA test equipment adapter module 3 and adapter module 4 via connectors 3 and 4, respectively. The output data content of the FPGA under test is parsed in data transceiver module 3 and data transceiver module 4.

[0104] 6) The dedicated pin measurement board can be connected to the connectors (e.g., connectors 3 and 4) on the verification board for receiving output data from the FPGA under test. The signals on this board can be measured, for example, using a logic analyzer or oscilloscope.

[0105] 7) Ten dedicated test pins are designed on the verification board to bring out the test points on the verification board for measuring some special signals inside the FPGA or on the pins.

[0106] by Figure 3 Taking the illustrated structure as an example, this structure is a test system consisting of an FPGA test device, a target board, and an adapter board. This structure is similar to the one described above. Figure 2 The difference lies in the fact that the connection of the FPGA test equipment has been changed from a verification board to an adapter board. The verification board and dedicated pin measurement board are no longer used; instead, the FPGA target board is used directly. FPGA data measurements are primarily performed on the adapter board. The adapter board enables the conversion of the interface type between the FPGA test equipment and the target board.

[0107] It should be noted that the four test systems provided in this embodiment of the invention can all be used to test FPGAs. The key is that the adapter module provides a universal interface that supports the transmission of various signals and can measure the signals on the output pins of the FPGA. Therefore, the test environment design method can be used in different projects and different systems.

[0108] While the embodiments disclosed in this invention are as described above, they are merely illustrative of the embodiments to facilitate understanding of the invention and are not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and variations in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A reusable multi-system FPGA test system, characterized in that, The FPGA testing system includes: FPGA testing equipment, FPGA under test, and dedicated connectors; The FPGA testing equipment includes a chassis, a main control module, at least one data transceiver module and a clock module that are plugged into the chassis via chassis slots, and an adapter module that is connected to each data transceiver module respectively. Each adapter module of the FPGA test equipment is connected to the pins of the FPGA under test via a dedicated connector. It is used to transmit the data to be sent in the data transceiver module to the FPGA under test, and also to transmit the data output by the FPGA under test to the data transceiver module for verification. The clock module is connected to the FPGA under test via a dedicated clock interface to generate a clock at a specified frequency and transmit the clock to the FPGA under test via the dedicated clock interface. This allows the FPGA under test to process the data received from the dedicated connector and the clock received from the clock module, generate output data, and output it through the dedicated connector. The testing process of the reusable multi-system FPGA test system includes: Step 1: The FPGA test equipment transmits the data to be sent from the main control module to the data transceiver module, which converts it into timing data and then transmits it to the corresponding dedicated connector through the general interface on the corresponding adapter module. When the timing data includes different types of timing data, the order in which the different types of data are sent can be configured as needed. Step 2: Send a clock of a specified frequency to the clock module through the interface of the FPGA test equipment. The clock module generates a clock of the specified frequency and transmits it to the dedicated clock interface of the verification board through an RF coaxial cable. If multiple clocks are generated, the phase between the multiple clocks can be configured. Step 3: The clock on the dedicated clock interface and the timing data on the dedicated connector form complete FPGA input data in the FPGA under test. The FPGA under test processes at least two FPGA input data channels to generate FPGA output data, which is then output through the dedicated connector.

2. The reusable multi-system FPGA test system according to claim 1, characterized in that, In the FPGA test equipment, each adapter module is equipped with 32 single-ended paths and 16 low-voltage differential signal paths. The data transceiver module connected to each adapter module is used to control the data flow direction from the data transceiver module, the corresponding connected adapter module, the dedicated connector to the FPG under test, wherein the data flow direction is unidirectional transmission, unidirectional reception, or bidirectional.

3. The reusable multi-system FPGA test system according to claim 1, characterized in that, In step 3 of the test process of the reusable multi-system FPGA test system, the FPGA output data output through the dedicated connector is transmitted by the corresponding adapter module to the data transceiver module for parsing and then transmitted to the main control module.

4. The reusable multi-system FPGA test system according to claim 1, characterized in that, In the FPGA testing system, the FPGA input / output interfaces are led out from the FPGA under test to a dedicated connector to form a verification board, which enables the verification board to be connected to the FPGA testing equipment and to be directly measured by a logic analyzer; the dedicated clock interface is set on the verification board. The FPGA test equipment and verification board form the first structural component of the FPGA test system.

5. The reusable multi-system FPGA test system according to claim 4, characterized in that, Also includes: A dedicated pin measurement board is connected to a dedicated connector for outputting FPGA output data; the FPGA test equipment, the verification board, and the dedicated pin measurement board form a second structural component of the FPGA test system. In step 3 of the testing process of the reusable multi-system FPGA test system The FPGA output data, which is output through a dedicated connector, is transmitted to external measuring instruments via a dedicated pin measurement board.

6. The reusable multi-system FPGA test system according to claim 1, characterized in that, The FPGA under test is located in the FPGA target board. The FPGA testing system also includes: multiple pairs of target board connectors and adapter boards, each pair of target board connectors being used to connect the FPGA target board and the adapter board respectively. The adapter board includes a conversion circuit, dedicated connectors connected to the conversion circuit, and a dedicated clock interface. The target board connector located in the adapter board is connected to the conversion circuit. The FPGA test equipment, FPGA target board, and conversion board form the third component structure of the FPGA test system.

7. The reusable multi-system FPGA test system according to claim 6, characterized in that, Also includes: A dedicated pin measurement board, which is connected to a dedicated connector for outputting FPGA output data; The FPGA test equipment, FPGA target board, conversion board, and dedicated pin measurement board form the fourth component structure of the FPGA test system; In step 3 of the testing process of the reusable multi-system FPGA test system The FPGA output data, which is output through a dedicated connector, is transmitted to external measuring instruments via a dedicated pin measurement board.

8. The reusable multi-system FPGA test system according to any one of claims 1 to 7, characterized in that, The number of dedicated clock interfaces is equal to the number of data types containing clock data sent by the data transceiver module; Different dedicated clock interfaces are used to receive clocks generated by the same or different clock modules. Multiple clock modules are used to send clocks with different frequencies and phases. The same clock module is used to send clocks with the same frequency and phase, or clocks with the same frequency but different phases.

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