Image reading method, apparatus, and readable storage medium with double conversion gain

Abstract

The application provides a dual conversion gain image reading method, device and readable storage medium. The image reading method comprises the following steps: controlling a first readout circuit to perform first quantization processing on a first conversion gain reset signal and a first conversion gain image signal, and controlling a second readout circuit to perform second quantization processing on the first conversion gain reset signal and a second conversion gain image signal; wherein, when the second quantization processing is performed, the second readout circuit is subjected to quantization compensation. The dual conversion gain image reading method, device and readable storage medium provided by the application can simultaneously perform the quantization processing of the first conversion gain reset signal by the two readout circuits, effectively reduces the quantization reading time, and accelerates the reading speed.

Description

Technical Field

[0001] This application relates to the field of high dynamic range image processing technology, specifically to an image reading method, apparatus, and readable storage medium with dual conversion gain. Background Technology

[0002] Dynamic range (DR) is a key indicator characterizing the maximum range of input light signals that a CMOS image sensor (CIS) can recognize. Some applications require very high dynamic range; a higher dynamic range allows for more vivid and richer representation of bright and dark areas in an image. In the design of CMOS image sensor (CIS) imaging, achieving high dynamic range (HDR) is currently a mainstream approach by using dual conversion gain (DCG) to read multiple frames and then synthesizing them.

[0003] Traditional dual-conversion-gain HDR image sensors employ a readout quantization sequence comprising four stages: high conversion gain reset signal (HCG rst), low conversion gain reset signal (LCG rst), high conversion gain image signal (HCG sig), and low conversion gain image signal (LCG sig). This quantization sequence results in larger, slower image sensors, requiring more ADC resources and longer readout quantization times. Summary of the Invention

[0004] This application provides a dual-conversion-gain image reading method, apparatus, and readable storage medium to alleviate the problem of long image readout quantization time.

[0005] In one aspect, this application provides a dual-conversion-gain image reading method, specifically, the image reading method includes:

[0006] The system controls a first readout circuit to perform a first quantization process on a first conversion gain reset signal and a first conversion gain image signal to obtain a valid first conversion gain image signal, and controls a second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal to obtain a valid second conversion gain image signal; wherein the timing of the first readout circuit and the second readout circuit performing quantization processing on the first conversion gain reset signal overlaps at least partially; when the second readout circuit performs the second quantization process, it performs quantization compensation on the first conversion gain reset signal and / or the second conversion gain image signal to obtain the valid second conversion gain image signal.

[0007] Optionally, the first readout circuit and the second readout circuit simultaneously begin quantization processing of the first conversion gain reset signal.

[0008] Optionally, the second readout circuit performs quantization compensation on the second conversion gain image signal by adjusting the ramp voltage.

[0009] Optionally, the second readout circuit performs quantization compensation on the second conversion gain image signal by increasing the amplitude of the ramp voltage to prolong the counting process.

[0010] Optionally, the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal includes:

[0011] The first conversion gain reset signal is input to the first input terminal of the first comparator and the second comparator respectively, and the first ramp voltage is input to the second input terminal of the first comparator and the second comparator respectively, and the first counter and the second counter are controlled to count.

[0012] When the output signals of the first comparator and the second comparator are flipped, the first comparator and the second counter are controlled to stop counting.

[0013] The first conversion gain image signal is input to the first input terminal of the first comparator, the first ramp voltage is input to the second input terminal of the first comparator, and the first counter is controlled to count in the reverse direction.

[0014] When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting;

[0015] The second conversion gain image signal is input to the first input terminal of the second comparator, the second ramp voltage is input to the second input terminal of the second comparator, and the second counter is controlled to count in the reverse direction; wherein, the amplitude of the second ramp voltage is higher than that of the first ramp voltage;

[0016] When the state of the output signal of the second comparator flips, it controls the second counter to stop counting.

[0017] Optionally, the second readout circuit performs quantization compensation on the second conversion gain image signal or the first conversion gain reset signal by controlling the second conversion gain counting signal.

[0018] Optionally, the second readout circuit controls the counting of the first conversion gain reset signal by controlling the second conversion gain counting signal to stop counting in advance in order to perform quantization compensation.

[0019] Optionally, the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal includes:

[0020] The first conversion gain reset signal is input to the first input terminal of the first comparator and the second comparator respectively, and the first ramp voltage is input to the second input terminal of the first comparator and the second comparator respectively, and the first counter and the second counter are controlled to count.

[0021] When a preset condition is met, the second counter is controlled to stop counting in advance;

[0022] When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting;

[0023] The first conversion gain image signal is input to the first input terminal of the first comparator, the first ramp voltage is input to the second input terminal of the first comparator, and the first counter is controlled to count in the reverse direction.

[0024] When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting;

[0025] The second conversion gain image signal is input to the first input terminal of the second comparator, the first ramp voltage is input to the second input terminal of the second comparator, and the second counter is controlled to count in the reverse direction;

[0026] When the state of the output signal of the second comparator flips, it controls the second counter to stop counting.

[0027] Optionally, the second readout circuit controls the counting of the second conversion gain image signal by controlling the second conversion gain counting signal to extend the counting process for quantization compensation.

[0028] Optionally, the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal includes:

[0029] The first conversion gain reset signal is input to the first input terminal of the first comparator and the second comparator respectively, and the first ramp voltage is input to the second input terminal of the first comparator and the second comparator respectively, and the first counter and the second counter are controlled to count.

[0030] When the output signals of the first comparator and the second comparator flip, the first counter and the second counter are controlled to stop counting.

[0031] The first conversion gain image signal is input to the first input terminal of the first comparator, the first ramp voltage is input to the second input terminal of the first comparator, and the first counter is controlled to count in the reverse direction.

[0032] When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting;

[0033] The second conversion gain image signal is input to the first input terminal of the second comparator, the first ramp voltage is input to the second input terminal of the second comparator, and the second counter is controlled to count in the reverse direction;

[0034] When the preset conditions are met, the second counter is controlled to extend the counting.

[0035] When the state of the output signal of the second comparator flips, it controls the second counter to stop counting.

[0036] Optionally, the first conversion gain is a high conversion gain, and the second conversion gain is a low conversion gain.

[0037] Optionally, the quantization compensation is determined based on the gain difference between the first conversion gain and the second conversion gain.

[0038] Optionally, before the step of controlling the first readout circuit to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal, and controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal, the following steps are included:

[0039] The first comparator of the first readout circuit and the second comparator of the second readout circuit are cleared to zero.

[0040] Optionally, the step of clearing the second comparator of the second readout circuit includes:

[0041] Enable the first conversion gain reset mode to obtain the first conversion gain reset signal, and use the first conversion gain reset signal as a reference to clear the second comparator;

[0042] Alternatively, enable the second conversion gain reset mode to obtain the second conversion gain reset signal, and use the second conversion gain reset signal as a reference to clear the second comparator.

[0043] On the other hand, this application also provides an image reading device for performing the image reading method with dual conversion gain as described above. Specifically, the image reading device includes a pixel circuit and a first readout circuit and a second readout circuit respectively connected to the pixel circuit.

[0044] The pixel circuit is configured to output pixel signals to the first readout circuit and the second readout circuit, and the pixel signals include a first conversion gain reset signal, a first conversion gain image signal, and a second conversion gain image signal;

[0045] The first readout circuit is configured to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal;

[0046] The second readout circuit is configured to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal, the second quantization process including quantization compensation on the first conversion gain reset signal or the second conversion gain image signal.

[0047] Optionally, the first readout circuit includes a first comparator and a first counter; the second readout circuit includes a second comparator and a second counter.

[0048] The first input terminal of the first comparator receives the first conversion gain reset signal or the first conversion gain image signal, the second input terminal of the first comparator receives a ramp voltage, and the output terminal of the first comparator is connected to the first counter. The first counter is used to quantize the first conversion gain reset signal or the first conversion gain image signal according to the output result of the first comparator.

[0049] The first input terminal of the second comparator receives the first conversion gain reset signal or the second conversion gain image signal, the second input terminal of the second comparator receives the first ramp voltage or the second ramp voltage, the output terminal of the second comparator is connected to the second counter, and the second counter is configured to quantize the first conversion gain reset signal or the second conversion gain image signal according to the output result of the second comparator or according to the second conversion gain count signal.

[0050] Optionally, the second readout circuit includes a second comparator and a clearing circuit connected to each other, the clearing circuit being configured to:

[0051] The second comparator is cleared using the first conversion gain reset signal as a reference.

[0052] Alternatively, enable the second conversion gain reset mode to obtain the second conversion gain reset signal, and use the second conversion gain reset signal as a reference to clear the second comparator.

[0053] On the other hand, this application also provides a readable storage medium, specifically, the readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the image reading method described above.

[0054] As described above, the dual-conversion-gain image reading method, apparatus, and readable storage medium provided in this application can simultaneously perform the quantization process of the first conversion-gain reset signal by configuring both readout circuits to quantize the first conversion-gain reset signal, thereby effectively reducing the quantization reading time and accelerating the reading quantization speed. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0056] Figure 1 This is a basic structural block diagram of an image sensor system.

[0057] Figure 2 This is a pixel unit circuit diagram in one embodiment of this application.

[0058] Figure 3 This is a pixel circuit diagram of a two-path photosensitive pixel shared structure in one embodiment of this application.

[0059] Figure 4 This is a flowchart of a dual-conversion-gain image reading method according to an embodiment of this application.

[0060] Figures 5(a)-5(c) For this application Figure 4 Quantization processing flowchart of an example.

[0061] Figure 6 This is a block diagram of an image reading device according to an embodiment of this application.

[0062] Figure 7 This is a schematic diagram of the readout circuit in one embodiment of this application.

[0063] Figure 8 Circuit timing diagram of an image reading method according to an embodiment of this application Figure 1 .

[0064] Figure 9 Circuit timing diagram of an image reading method according to an embodiment of this application Figure 2 .

[0065] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0066] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0067] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0068] It should be noted that step designations such as S111 and S112 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S112 first and then S111, etc., but these should all be within the protection scope of this application.

[0069] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0070] The following detailed description of the contents of this application is provided in conjunction with the accompanying drawings. Figure 1 This is a basic structural block diagram of an image sensor system.

[0071] like Figure 1 As shown, the image sensor 100 includes a readout circuit 102 and a control circuit 104 connected to the pixel array 101.

[0072] Functional logic unit 103 is connected to readout circuit 102 to perform logic control on the reading of pixel circuits. Readout circuit 102 and control circuit 104 are connected to status register 105 to implement readout control of pixel array 101. Pixel array 101 includes multiple pixel units arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by pixel array 101 are output to readout circuit 102 via column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out by readout circuit 102 using the readout mode specified by status register 105, and then transmitted to functional logic unit 103. In specific applications, readout circuit 102 may include analog-to-digital converter (ADC) circuit, amplification circuit, and others. In some application embodiments, status register 105 may include a programmed selection system to determine whether the readout system reads out in rolling shutter mode or global shutter mode. Functional logic unit 103 may store only image data or image data applied or processed through image effects. In one application example, readout circuit 102 may be located along readout column lines (e.g., ...). Figure 1 As shown, image data is read out one line at a time, or various other methods may be used to read out image data. The operation of control circuit 104 can be determined by the current setting of status register 105. For example, control circuit 104 generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global exposure signal that allows all pixels of pixel array 101 to acquire their image data simultaneously through a single acquisition window. In some other applications, this shutter signal may be a rolling exposure signal, where each pixel row is read out continuously through the acquisition window.

[0073] First Embodiment

[0074] Figure 2 This is a pixel unit circuit diagram according to one embodiment of this application. The pixel array of the image sensor contains multiple pixels arranged in rows and columns, such as... Figure 2 The pixel unit shown includes a photosensitive pixel comprising a photodiode (PD) and a transfer switch (TX). The transfer switch (TX) transfers electrons generated by the photodiode (PD) through the photoelectric effect to a floating diffusion point (FD). The dual conversion gain control unit includes a conversion gain switch (DCG) and a supplementary capacitor (Cdcg), connected between a reset switch (RST) and the floating diffusion point (FD), to enable the pixel circuit to operate in either a low conversion gain or high conversion gain mode according to a control signal.

[0075] The pixel signal is amplified by the source follower switch SF and output to the column line (pixelout output) via the row selection switch RS. In another specific embodiment, the pixel unit may be a photosensitive pixel with a shared structure.

[0076] Second Embodiment

[0077] Figure 3 This is a pixel circuit diagram of a two-path photosensitive pixel shared structure in one embodiment of this application.

[0078] like Figure 3 As shown, photodiode PD1 and transmission switch TX1, along with photodiode PD2 and transmission switch TX2, constitute a shared structure photosensitive pixel, sharing and connecting to the floating diffusion point FD. Using a shared structure pixel unit reduces the number of switches in the pixel circuit, thus reducing the chip design area. Understandably, without changing the pixel circuit design area, the area of ​​the photosensitive region can be increased, thereby improving the light sensitivity of the pixel circuit and enhancing its performance. The figures and embodiments provided in this application are not limited to a two-way shared photosensitive pixel mode. In some specific embodiments, a four-way shared photosensitive pixel structure design can be adopted, such as a photosensitive pixel sharing unit consisting of PD1 and TX1, PD2 and TX2, PD3 and TX3, and PD4 and TX4 connected in a four-way shared structure and sharing the floating diffusion point FD.

[0079] Please continue to refer to this. Figure 2 The supplementary capacitor Cdcg can be the device capacitor or the parasitic capacitance to ground at the connection point of the reset switch RST and the conversion gain switch DCG. Figure 2 In one embodiment, the supplementary capacitor Cdcg is a device capacitor, with the other terminal connected to voltage VC. In another embodiment, the supplementary capacitor Cdcg is the parasitic capacitance to ground at the connection point of the reset switch RST and the switching gain switch DCG, and the other terminal of the capacitor can be grounded.

[0080] Third Embodiment

[0081] This application provides a dual-conversion-gain image reading method. Figure 4 This is a flowchart of a dual-conversion-gain image reading method according to an embodiment of this application.

[0082] Please see Figure 4 In one embodiment, the image reading method includes:

[0083] S1: Control the first readout circuit to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal to obtain an effective first conversion gain image signal, and control the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal to obtain an effective second conversion gain image signal.

[0084] The timing of the first readout circuit and the second readout circuit performing quantization processing on the first conversion gain reset signal overlaps at least partially; when the second readout circuit performs the second quantization processing, it performs quantization compensation on the first conversion gain reset signal and / or the second conversion gain image signal to obtain an effective second conversion gain image signal.

[0085] In the design of image readout imaging for image sensors, using dual conversion gain to read multiple frames of images and then synthesizing them is a mainstream approach to achieve high dynamic range in CMOS image sensors. Before activating the first conversion gain reset mode, the reset switch and conversion gain switch can be turned on to reset the floating diffusion node. Resetting the floating diffusion node before quantizing the image signal ensures the accuracy of the readout circuit's quantization.

[0086] Traditional pixel structures and control timing employing dual conversion gain to achieve high dynamic range typically switch between high and low conversion gain modes by toggling a dual conversion gain switch. In the following embodiments of this application, high conversion gain is used as the first conversion gain, and low conversion gain as the second conversion gain for specific illustration. However, this application is not limited to this; in other embodiments, low conversion gain may be used as the first conversion gain, and high conversion gain as the second conversion gain.

[0087] Optionally, the first readout circuit and the second readout circuit simultaneously begin quantization processing of the first conversion gain reset signal.

[0088] For example, after the image sensor is controlled to disconnect the reset switch and the conversion gain switch, the high conversion gain reset mode is enabled, and the first readout circuit and the second readout circuit first read the high conversion gain reset signal.

[0089] By configuring both readout circuits to quantize the first conversion gain reset signal, the quantization process of the first conversion gain reset signal by both readout circuits can be performed simultaneously, effectively reducing quantization readout time, accelerating readout speed, and improving imaging efficiency.

[0090] During the quantization reading process of the second readout circuit, since the gain conversion mode of the reset signal is different from that of the image signal, the quantization process needs to be compensated accordingly to ensure that the final quantization result is accurate and effective.

[0091] After the first and second readout circuits read the high conversion gain reset signal, they control the image sensor to turn on the transmission switch to guide the charge after photosensitive diodes are introduced into the floating diffusion node, thus entering the high conversion gain image mode, thereby enabling the first readout circuit to read the high conversion gain image signal.

[0092] Optionally, the transmission switch in the pixel circuit can be turned on; then the transmission switch can be turned off after a preset time to enable the high conversion gain image mode.

[0093] A short-time conduction transmission switch allows the charge from the photodiode to be directed to a floating diffusion node, enabling a high-conversion-gain image mode. An up-counting method can be used to perform A / D conversion on the reset level, achieving image signal quantization from the image sensor.

[0094] Optionally, the quantization compensation is determined based on the gain difference between the first conversion gain and the second conversion gain.

[0095] For example, in reading a low-conversion-gain image, since the quantization of the reset signal reads the high-conversion-gain reset signal, compensation is needed to read the counting result of the second conversion-gain counting signal to ultimately obtain the correct image information. The amount of compensation required can be determined based on the difference between the quantized values ​​of the high-conversion-gain reset signal and the low-conversion-gain reset signal in the first direction. This difference is mainly determined by the voltage difference introduced on the output bit line by the dual-conversion-gain transistor changing from the off state in high-conversion-gain mode to the on state in low-conversion-gain mode.

[0096] Figures 5(a)-5(c) For this application Figure 4 The three quantization compensation processing flowcharts of the embodiments are used as examples to illustrate the present invention.

[0097] Please refer to Figure 5(a). Optionally, the second readout circuit performs quantization compensation on the second conversion gain image signal by adjusting the ramp voltage.

[0098] During the operation of the counter in the readout circuit, the initial amplitude of the ramp voltage can be used to control the counter's counting. Taking the quantization processing of high-conversion-gain or low-conversion-gain image signals as an example, the reset signal and pixel signal can be converted from analog to digital by counting in the first direction and then in the second direction, thus realizing the quantization and reading of the pixel signal from the image circuit. For example, the counting can proceed from downward to upward, or vice versa.

[0099] For example, in a readout system that performs a counting operation during the process of the ramp voltage decreasing to the pixel voltage, increasing the initial amplitude of the ramp voltage can increase the counting duration, and decreasing the initial amplitude of the ramp voltage can decrease the counting duration. Conversely, in a readout system that performs a counting operation during the process of the ramp voltage increasing to the pixel voltage, decreasing the initial amplitude of the ramp voltage can increase the counting duration, and increasing the initial amplitude of the ramp voltage can decrease the counting duration.

[0100] Because the second readout circuit quantizes the first conversion gain reset signal, the count value is lower compared to the quantization result of the second conversion gain reset signal. Therefore, appropriate quantization compensation can be performed by extending the count to accurately read out the pixel signal.

[0101] Understandably, in a readout system that performs counting operations during the process of the ramp voltage dropping to the pixel voltage, the second readout circuit may optionally perform quantization compensation on the second conversion gain image signal by increasing the amplitude of the ramp voltage to prolong the counting process.

[0102] For example, the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal may include:

[0103] S111: Input the first conversion gain reset signal to the first input terminal of the first comparator and the second comparator respectively, input the first ramp voltage to the second input terminal of the first comparator and the second comparator respectively, and control the first counter and the second counter to count.

[0104] For example, the first comparator and the second comparator simultaneously begin quantizing and reading the first conversion gain reset signal.

[0105] S112: When the output signals of the first comparator and the second comparator are flipped, the first comparator and the second counter are controlled to stop counting.

[0106] For example, since the first comparator and the second comparator simultaneously begin quantizing and reading the first conversion gain reset signal, the first counter and the second counter also perform the same counting in the first direction under the joint control of the first ramp voltage.

[0107] S113: Input the first conversion gain image signal to the first input terminal of the first comparator, input the first ramp voltage to the second input terminal of the first comparator, and control the first counter to count in the reverse direction.

[0108] The first readout circuit, under the control of a first ramp voltage, counts the high conversion gain image signal in a second direction for quantization processing. The second direction is opposite to the first direction. For example, the first direction could be downward, and the second direction could be upward.

[0109] S114: When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting.

[0110] For example, when the first ramp voltage drops to the same level as the first conversion gain image signal, the first counter completes the quantization processing of the high conversion gain image signal.

[0111] S115: Input the second conversion gain image signal to the first input terminal of the second comparator, input the second ramp voltage to the second input terminal of the second comparator, and control the second counter to count in the reverse direction.

[0112] Optionally, the second ramp voltage has a higher amplitude than the first ramp voltage. For example, in the reading of a low conversion gain image, since the quantization of the reset signal reads a high conversion gain reset signal, the final counting result can be compensated and adjusted by using a second ramp voltage higher than the initial level of the first ramp voltage in the quantization reading of the low conversion gain image signal.

[0113] S116: When the state of the output signal of the second comparator flips, the second counter is controlled to stop counting.

[0114] For example, when the second ramp voltage drops to the same level as the second conversion gain image signal, the second counter completes the quantization processing of the low conversion gain image signal.

[0115] Since the initial level of the second ramp voltage is higher than the initial level of the first ramp voltage, the counter can increase the counting time in the second direction during the quantization reading of the low conversion gain image signal, thereby compensating for the over-counted numbers in the first direction.

[0116] Please refer to Figure 5(b). Optionally, the second readout circuit performs quantization compensation on the second conversion gain image signal or the first conversion gain reset signal by controlling the second conversion gain counting signal.

[0117] For example, in reading a low-conversion-gain image, since the quantization of the reset signal reads a high-conversion-gain reset signal, it is necessary to compensate for the counting result of the second conversion-gain counting signal in order to ultimately read the correct image information. Understandably, compensation can be achieved by reducing the counting result in the first direction or by increasing the counting result in the second direction; and vice versa.

[0118] Optionally, the second readout circuit controls the counting of the first conversion gain reset signal by controlling the second conversion gain counting signal to stop counting in advance in order to perform quantization compensation.

[0119] For example, the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal may include:

[0120] S121: Input the first conversion gain reset signal to the first input terminal of the first comparator and the second comparator respectively, input the first ramp voltage to the second input terminal of the first comparator and the second comparator respectively, and control the first counter and the second counter to count in the first direction.

[0121] For example, the first comparator and the second comparator simultaneously begin quantizing and reading the first conversion gain reset signal.

[0122] S122: When the preset conditions are met, control the second counter to stop counting in advance.

[0123] For example, a preset counting duration for the second counter in the first direction is established. When the preset counting duration is reached, the second counter is controlled to stop counting prematurely.

[0124] S123: When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting.

[0125] For example, when the first ramp voltage drops to the same level as the first conversion gain image signal, the first counter completes the quantization processing of the high conversion gain reset signal.

[0126] S124: Input the first conversion gain image signal to the first input terminal of the first comparator, input the first ramp voltage to the second input terminal of the first comparator, and control the first counter to count in the reverse direction.

[0127] For example, the first readout circuit, under the control of a first ramp voltage, counts the high conversion gain image signal in a second direction for quantization processing. The second direction is opposite to the first direction. Optionally, the first direction can be downward, and the second direction can be upward.

[0128] S125: When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting.

[0129] For example, when the first ramp voltage drops to the same level as the first conversion gain image signal, the first counter completes the quantization processing of the high conversion gain image signal.

[0130] S126: Input the second conversion gain image signal to the first input terminal of the second comparator, input the first ramp voltage to the second input terminal of the second comparator, and control the second counter to count in the reverse direction.

[0131] For example, since the counting results have been adjusted accordingly in the counting of the first direction, the counting results in the counting of the second direction of the low conversion gain image can be directly controlled by the first ramp voltage.

[0132] S127: When the state of the output signal of the second comparator flips, the second counter is controlled to stop counting.

[0133] For example, when the first ramp voltage drops to the same level as the second conversion gain image signal, the second counter completes the quantization processing of the low conversion gain image signal.

[0134] Please refer to Figure 5(c). Optionally, the second readout circuit controls the counting of the second conversion gain image signal by controlling the second conversion gain counting signal in a way that extends the counting process to perform quantization compensation.

[0135] For example, the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal may include:

[0136] S131: Input the first conversion gain reset signal to the first input terminal of the first comparator and the second comparator respectively, input the first ramp voltage to the second input terminal of the first comparator and the second comparator respectively, and control the first counter and the second counter to count.

[0137] For example, the first comparator and the second comparator simultaneously begin quantizing and reading the first conversion gain reset signal.

[0138] S132: When the output signals of the first comparator and the second comparator flip, control the first counter and the second counter to stop counting.

[0139] For example, since the first comparator and the second comparator simultaneously begin quantizing and reading the first conversion gain reset signal, the first counter and the second counter also perform the same counting in the first direction under the joint control of the first ramp voltage.

[0140] S133: Input the first conversion gain image signal to the first input terminal of the first comparator, input the first ramp voltage to the second input terminal of the first comparator, and control the first counter to count in the reverse direction.

[0141] For example, the first readout circuit, under the control of a first ramp voltage, counts the high conversion gain image signal in a second direction for quantization processing. The second direction is opposite to the first direction. Optionally, the first direction can be downward, and the second direction can be upward.

[0142] S134: When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting.

[0143] For example, when the first ramp voltage drops to the same level as the first conversion gain image signal, the first counter completes the quantization processing of the high conversion gain image signal.

[0144] S135: Input the second conversion gain image signal to the first input terminal of the second comparator, input the first ramp voltage to the second input terminal of the second comparator, and control the second counter to count in the reverse direction.

[0145] For example, since the counting results can be adjusted accordingly in the counting of the second direction, the counting results can be directly controlled by the first ramp voltage in the counting of the second direction of the low conversion gain image reading.

[0146] S136: When the preset conditions are met, control the second counter to extend the counting.

[0147] For example, a minimum counting duration for the second counter in the second direction is preset. When the preset minimum counting duration is not reached, the second counter is controlled to continue counting. Optionally, the extended counting can be set to occur before the first ramp level begins to decrease. Optionally, during the extended counting, the first ramp level can be controlled to stop decreasing. Optionally, the extended counting can be set to occur after the first ramp level has decreased, and then the second counter is controlled to continue counting.

[0148] S137: When the state of the output signal of the second comparator flips, the second counter is controlled to stop counting.

[0149] For example, when the first ramp voltage drops to the same level as the second conversion gain image signal, the second counter completes the quantization processing of the low conversion gain image signal.

[0150] In this embodiment of the invention, optionally, before the step of controlling the first readout circuit to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal, and controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal, the method further includes:

[0151] The first comparator of the first readout circuit and the second comparator of the second readout circuit are cleared to zero.

[0152] The clearing of the first comparator and the clearing of the second comparator can be performed under the same reset signal reference, under different reset signal references, or both can be set under the reference of the low conversion gain reset signal.

[0153] Optionally, the step of clearing the second comparator of the second readout circuit may include:

[0154] Enable the first conversion gain reset mode to obtain the first conversion gain reset signal, and use the first conversion gain reset signal as a reference to clear the second comparator.

[0155] For example, the clearing of the first comparator and the clearing of the second comparator can be jointly set to be performed based on the high conversion gain reset signal.

[0156] Optionally, the step of clearing the second comparator of the second readout circuit may include:

[0157] Enable the second conversion gain reset mode to obtain the second conversion gain reset signal, and use the second conversion gain reset signal as a reference to clear the second comparator.

[0158] For example, the first comparator can be cleared based on a high conversion gain reset signal, and the second comparator can be cleared based on a low conversion gain reset signal.

[0159] Fourth embodiment

[0160] This application also provides an image reading apparatus for implementing the image reading method with dual conversion gain as described above. Figure 6 This is a block diagram of an image reading device according to an embodiment of this application.

[0161] Please see Figure 6 In one embodiment, the image reading device includes a pixel circuit 10 and a first readout circuit 20 and a second readout circuit 30 respectively connected to the pixel circuit 10.

[0162] The pixel circuit 10 is configured to output pixel signals to the first readout circuit 20 and the second readout circuit 30. The pixel signals include a first conversion gain reset signal, a first conversion gain image signal, and a second conversion gain image signal.

[0163] The first readout circuit 20 is configured to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal.

[0164] The second readout circuit 30 is configured to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal. The second quantization process includes quantization compensation on either the first conversion gain reset signal or the second conversion gain image signal.

[0165] Please continue reading. Figure 6 The image reading device further includes a compensation control circuit 40 connected to the second readout circuit 30, the compensation control circuit 40 being configured to perform quantization compensation on the second quantization process. In one embodiment, the function performed by the compensation control circuit 40 is as described in this invention. Figure 1 The control circuit 104 in the image sensor shown performs some of the functions, so no new hardware structure is added. It is understandable that, without considering hardware costs, this function could also be performed through a separately configured external circuit structure.

[0166] In the design of image readout imaging for image sensors, using dual conversion gain to read multiple frames of images and then synthesizing them is a mainstream approach to achieve high dynamic range in CMOS image sensors. Before activating the first conversion gain reset mode, the reset switch and conversion gain switch can be turned on to reset the floating diffusion node. Resetting the floating diffusion node before quantizing the image signal ensures the accuracy of the readout circuit's quantization.

[0167] Traditional pixel structures and control timing employing dual conversion gain to achieve high dynamic range typically switch between high and low conversion gain modes by toggling a dual conversion gain switch. In the following embodiments of this application, high conversion gain is used as the first conversion gain, and low conversion gain as the second conversion gain for specific illustration. However, this application is not limited to this; in other embodiments, low conversion gain may be used as the first conversion gain, and high conversion gain as the second conversion gain.

[0168] After the image sensor is disconnected from the reset switch and the conversion gain switch, the high conversion gain reset mode is enabled. First, the first readout circuit 20 and the second readout circuit 30 read the high conversion gain reset signal.

[0169] Simultaneous reading of the same conversion gain reset signal by two readout circuits can effectively reduce readout time and improve imaging efficiency. During the quantization process of the second readout circuit 30, since the gain conversion mode of the reset signal differs from that of the image signal, appropriate compensation is required in the quantization process to ensure the final quantization result is accurate and effective.

[0170] After the first and second readout circuits read the high conversion gain reset signal, they control the image sensor to turn on the transmission switch to guide the charge after photosensitive diodes are introduced into the floating diffusion node, thus entering the high conversion gain image mode, thereby enabling the first readout circuit to read the high conversion gain image signal.

[0171] Optionally, the transmission switch in the pixel circuit can be turned on; then the transmission switch can be turned off after a preset time to enable the high conversion gain image mode.

[0172] A short-time conduction transmission switch allows the charge from the photodiode to be directed to a floating diffusion node, enabling a high-conversion-gain image mode. An up-counting method can be used to perform A / D conversion on the reset level, achieving image signal quantization from the image sensor.

[0173] Please also refer to Figure 2 and Figure 6In one embodiment, the pixel circuit 10 includes a photodiode PD and a transmission switch TX. The photodiode PD is connected to the floating diffusion node FD through the transmission switch TX. The control terminal of the transmission switch TX is connected to the control circuit 104.

[0174] In one embodiment, the pixel circuit 10 further includes a supplementary capacitor Cdcg, a reset switch RST, and a conversion gain switch DCG. The control terminals of the reset switch RST and the conversion gain switch DCG are connected to the control circuit 104. The first terminal of the supplementary capacitor Cdcg is grounded or a fixed voltage source, and the second terminal of the supplementary capacitor Cdcg is connected between the reset switch RST and the conversion gain switch DCG. The floating diffusion node FD is connected through the conversion gain switch DCG.

[0175] Figure 7 This is a schematic diagram of a readout circuit used to perform the above-described readout method in one embodiment of this application.

[0176] like Figure 7 As shown, in one embodiment, the first readout circuit 20 includes a first comparator 504 and a first counter 505.

[0177] The first input terminal Vinn of the first comparator 504 receives a pixel signal, which may include a first conversion gain reset signal or a first conversion gain image signal. The second input terminal Vinp of the first comparator 504 receives a ramp voltage hcg_vramp. The output terminal Vout of the first comparator 504 is connected to a first counter 505, which is configured to quantize the first conversion gain reset signal and the first conversion gain image signal based on the output of the first comparator 504. For example:

[0178] When the first conversion gain reset signal is input to the first input terminal Vinn of the first comparator 504 and the first ramp voltage is input to the second input terminal Vinp of the first comparator 504, the count is down.

[0179] The counting stops when the state of the output signal of the first comparator 504 flips.

[0180] When the first conversion gain image signal is input to the first input terminal Vinn of the first comparator 504, and the second input terminal of the first ramp voltage is input, the count is increased.

[0181] The counting stops when the state of the output signal of the first comparator 504 flips.

[0182] Taking the quantization processing of high conversion gain image signals as an example, the reset signal and pixel signal can be converted into an A / D converter by counting down first and then up, so as to realize the quantization reading of pixel signals of image circuit.

[0183] Please continue reading. Figure 7 The second readout circuit 30 includes a second comparator 501 and a second counter 502.

[0184] The first input terminal Vinn of the second comparator 501 receives a pixel signal, which may include a first conversion gain reset signal and a second conversion gain image signal. The second input terminal Vinp of the second comparator 501 receives a ramp voltage lcg_vramp. The output terminal Vout of the second comparator 501 is connected to a second counter 502, which is configured to quantize the first conversion gain reset signal or the second conversion gain image signal based on the output of the second comparator 501 or based on the second conversion gain count signal. For example:

[0185] When the first conversion gain reset signal is input to the first input terminal Vinn of the second comparator 501, and the first ramp voltage is input to the second input terminal Vinp of the second comparator 501, the count is down.

[0186] The counting stops when the preset conditions are met.

[0187] When the second conversion gain image signal is input to the first input terminal Vinn of the second comparator 501, and the second ramp voltage is input to the second input terminal Vinp of the second comparator 501, the count is increased.

[0188] The counting stops when the output signal of the second comparator 501 flips.

[0189] Taking the quantization processing of low conversion gain image signals as an example, the reset signal and pixel signal can be converted from analog to digital by counting down first and then up, thus realizing the quantization reading of pixel signals from the image circuit. During the quantization reading process, since the gain conversion mode of the reset signal differs from that of the image signal, appropriate compensation is needed to ensure the accuracy and effectiveness of the final quantization result.

[0190] Please also refer to Figure 6 and Figure 7 Optionally, the compensation control circuit 40 can be connected to the enable terminal of the second counter 502, and the compensation control circuit 40 sets the preset condition that the second counter 502 counts down for a preset duration.

[0191] Depending on whether it's a high-conversion-gain reset signal or a low-conversion-gain reset signal, the preset duration can be less than or greater than the quantization duration of the first readout circuit 20 for the first conversion-gain reset signal, so as to adjust the final value of the down-counting by the second readout circuit 30 accordingly. For example, in an embodiment where the first readout circuit 20 and the second readout circuit 30 simultaneously quantize the high-conversion-gain reset signal, the preset duration can be set to be less than the quantization duration of the first readout circuit 20 for the high-conversion-gain reset signal, thereby reducing the down-counting time.

[0192] Optionally, when the second counter 502 counts down for a preset time, the compensation control circuit 40 adjusts the enable signal of the second counter 502 to a low level, thereby causing the second counter 502 to stop counting earlier, so as to reduce the value of the downward count and achieve the purpose of compensation adjustment.

[0193] Please also refer to Figure 6 and Figure 7 Optionally, the compensation control circuit 40 is connected to the output terminal of the second counter 502 (not shown in the figure), and the compensation control circuit 40 can adjust the second quantization processing result through an algorithm.

[0194] Depending on whether the reset signal is high-conversion-gain or low-conversion-gain, the quantization result of the second readout circuit 30 can be adjusted accordingly using an algorithm. For example, in an embodiment where the first readout circuit 20 and the second readout circuit 30 simultaneously quantize the high-conversion-gain reset signal, the final counting result of the second readout circuit can be adjusted upwards using an algorithm to increase the final counting result.

[0195] Please also refer to Figure 6 and Figure 7 Optionally, the compensation control circuit 40 can be connected to the second input terminal Vout of the second comparator 501, and the compensation control circuit 40 controls the initial value of the second ramp voltage to be different from the initial value of the first ramp voltage. It should be noted that, in other embodiments, the initial value of the second ramp voltage can be equal to the initial value of the first ramp voltage.

[0196] Depending on whether the reset signal is high-conversion-gain or low-conversion-gain, the quantization result of the second readout circuit 30 can be adjusted by setting an unspecified initial value for the second ramp voltage. For example, in an embodiment where the first readout circuit 20 and the second readout circuit 30 simultaneously quantize the high-conversion-gain reset signal, the initial value of the second ramp voltage can be set to be greater than the initial value of the first ramp voltage, thereby increasing the upward counting time of the second readout circuit 30 and thus increasing the final counting result.

[0197] By setting a specific initial value for the second ramp voltage, and / or by reasonably setting preset conditions to control the counting signal of the second conversion gain, and / or by compensating and adjusting the final counting result through software, the accuracy and effectiveness of the quantization reading result can be effectively achieved.

[0198] Optionally, the second readout circuit 30 includes a second comparator 501 and a clear circuit connected to each other. Please continue reading. Figure 7 The reset circuit may include a reset switch 503. The reset circuit 303 is configured as follows:

[0199] The second comparator 501 is cleared using the first conversion gain reset signal as a reference.

[0200] The clearing of the first comparator 504 and the clearing of the second comparator 501 can be performed under the same reset signal reference or under different reset signal references.

[0201] For example, the clearing of the first comparator 504 and the clearing of the second comparator 501 can be performed together under the reference of the high conversion gain reset signal, or they can be performed together under the reference of the low conversion gain reset signal.

[0202] Optionally, the second conversion gain reset mode can be enabled to obtain the second conversion gain reset signal, and the second comparator 501 can be cleared based on the second conversion gain reset signal.

[0203] For example, the clearing of the first comparator 504 can be performed based on a high conversion gain reset signal, and the clearing of the second comparator 501 can be performed based on a low conversion gain reset signal.

[0204] In one embodiment, the first readout circuit 20 and the second readout circuit 30 simultaneously quantize the first conversion gain reset signal.

[0205] By configuring both readout circuits to quantize the first conversion gain reset signal, the quantization process of the first conversion gain reset signal by both readout circuits can be performed simultaneously, effectively reducing quantization reading time and speeding up the reading process.

[0206] Fifth embodiment

[0207] Figure 8 This application is an embodiment of the application. Figure 7 The readout circuit executes the specific circuit timing of the image reading method shown in Figure 5(a). Figure 1 Please combine Figure 2 Figure 5(a) Figure 7 and Figure 8 The specific timing sequence is as follows:

[0208] At time t0, the row selection signal rowsel is set to high level, the transistor RS is turned on, the selection switches hcg_en and lcg_en are turned on, and the pixel circuit output pixout is connected to the first readout circuit and the second readout circuit;

[0209] At time t1, the low conversion gain reset switch lcg_cmp_az and the high conversion gain reset switch hcg_cmp_az are turned on. The input terminals Vinp of the two comparators are shorted together with the first stage output terminal Vop1, and the input terminal Vinn is shorted together with the first stage output terminal Von1, thus starting the reset process.

[0210] At time t2, the reset signal rst is used, and DCG is set to low level to obtain the image reset signal under high conversion gain.

[0211] At time t3, the high and low conversion gain reset switches hcg_cmp_az and lcg_cmp_az are turned off, and the selection switch lcg_en is turned off; the vramp ramp voltage is raised from the reference state to the first rise amplitude V1.

[0212] At time t4, the vramp ramp voltage begins to decrease. The high and low conversion gain counters, hcg_count_en and lcg_count_en, control the two second counters to start counting downwards. When the vramp ramp voltage and pixout overlap at Vinp and Vinn of the first comparator (coupled via capacitors), the first comparator outputs 0, and the first counter stops counting. Similarly, when Vinp and Vinn overlap at the second comparator, the second comparator outputs 0, and the second counter stops counting. This yields the quantized result of the reset signal under high conversion gain.

[0213] At time t5, the high conversion gain reset signal quantization ends, and the vramp returns to the first rise amplitude V1.

[0214] From time t6 to t7, the control signal tx is set to high level, the transmission transistor TX is turned on, and the image signal is started to be transmitted. The pixel circuit output pixout is coupled to the first comparator Vinn through a capacitor to obtain the image signal under high conversion gain.

[0215] At time t8, the vramp ramp voltage begins to decrease, and the high conversion gain counter enable hcg_count_en controls the first counter to start counting upwards. The vramp ramp voltage and pixout are coupled to Vinp and Vinn of the first comparator through a capacitor. When Vinp and Vinn overlap, the comparator outputs 0, the counting stops, and the difference between the image signal under high conversion gain and the reset signal is obtained, that is, the correlated double-sampled image quantization value is obtained under high conversion gain. The selection switch hcg_en is then turned off.

[0216] At time t9, the high conversion gain image signal quantization ends, and the VRamp ramp voltage begins to gradually rise.

[0217] At time t10, the selector switch lcg_en is turned on;

[0218] At time t11, the control signal DCG is set to high level, the DCG transistor is turned on, and the pixel array circuit switches to low conversion gain mode; the vramp ramp voltage begins to rise to the second rise amplitude V2.

[0219] From time t12 to t13, the control signal tx is set to high level, the transmission transistor TX is turned on, and the image signal is started to be transmitted. pixout is coupled to the comparator Vinn through a capacitor to obtain the image signal with low conversion gain.

[0220] At time t14, the vramp ramp voltage begins to decrease, and the low conversion gain counter enable lcg_count_en starts controlling the second counter to count upwards. The vramp ramp voltage and pixout are coupled to Vinp and Vinn of the second comparator through a capacitor. When Vinp and Vinn overlap, the second comparator outputs 0, the counting stops, and the difference between the image signal under low conversion gain and the reset signal is obtained, that is, the correlated double sampled image quantization value is obtained under low conversion gain.

[0221] At time t15, the image signal quantization ends under low conversion gain, and the vramp ramp voltage returns to the reference state.

[0222] Sixth Embodiment

[0223] Figure 9 This application is an embodiment of the application. Figure 7 The specific circuit timing of the readout circuit executing the image reading method shown in Figure 5(b) or Figure 5(c) Figure 2 Please combine Figure 2 Figure 5(b) or Figure (c) Figure 7 and Figure 9 The specific timing sequence is as follows:

[0224] At time t0, the row selection signal rowsel is set to high level, the transistor RS is turned on, the selection switch lcg_en is turned on, the pixel circuit outputs pixout and the second readout circuit is connected;

[0225] At time t1, the low conversion gain reset switch lcg_cmp_az and the high conversion gain reset switch hcg_cmp_az are turned on. The input terminals Vinp of the two comparators are shorted together with the first stage output terminal Vop1, and the input terminal Vinn is shorted together with the first stage output terminal Von1, thus starting the reset process.

[0226] At time t2, the reset signal rst is set to low level to obtain the image reset signal under low conversion gain.

[0227] At time t3, the low conversion gain clear switch lcg_cmp_az is turned off, and at time t5, the selection switch hcg_en is turned on, connecting the pixel circuit output pixout and the first readout circuit.

[0228] At time t6, the conversion gain control signal dcg is set to low level, the selection switch lcg_en is opened, the transistor DCG is turned off, and a reset signal under high conversion gain is obtained.

[0229] At time t7, the high-conversion-gain reset switch hcg_cmp_az is open; at time t8, the vramp ramp voltage begins to decrease, and the high-low conversion-gain counting enable hcg_count_en and lcg_count_en control the first and second counters to start counting downwards. When the vramp ramp voltage and pixout overlap at the high-gain Vinp and Vinn via capacitor coupling, the first comparator outputs 0, and the first counter stops counting; by controlling lcg_count_en, the second counter stops counting when it reaches a preset duration. A reset signal under high-low conversion gain is obtained. At time t9, the quantization of the reset signal under high-low conversion gain ends, and the vramp ramp voltage begins to return to the reference state.

[0230] At times t10 to t11, the control signal tx is set to high level, the transmission transistor TX is turned on, and the image signal is started to be transmitted. The pixel circuit output pixout is coupled to two comparators Vinn through a capacitor to obtain the image signal under high conversion gain.

[0231] At time t12, the vramp ramp voltage begins to decrease, and the high conversion gain counter enable hcg_count_en controls the first counter to start counting upwards. The vramp ramp voltage and pixout are coupled to Vinp and Vinn of the first comparator through a capacitor. When Vinp and Vinn overlap, the first comparator outputs 0, and the first counter stops counting, obtaining the difference between the image signal under high conversion gain and the reset signal, that is, obtaining the correlated double-sampled image quantization value under high conversion gain. At time t13, the high conversion gain image signal quantization ends, and the vramp ramp voltage begins to return to the reference state.

[0232] At time t14, the selection switch hcg_en is off, and at time t15, the selection switch lcg_en is on, turning on the pixel circuit output pixout and the low conversion gain analog-to-digital converter circuit.

[0233] At time t16, the control signal dcg is set to high level, the DCG transistor is turned on, and the pixel array circuit switches to low conversion gain mode.

[0234] From time t17 to t18, the control signal tx is set to high level, the transmission transistor TX is turned on, and the image signal is started to be transmitted. pixout is coupled to the second comparator Vinn through a capacitor to obtain the image signal under low conversion gain.

[0235] At time t19, the vramp ramp voltage begins to decrease, and the low conversion gain counter enable lcg_count_en controls the second counter to start counting upwards. The vramp ramp voltage and pixout are coupled to Vinp and Vinn of the second comparator through a capacitor. When Vinp and Vinn overlap, the second comparator outputs 0, and the second counter stops counting, obtaining the difference between the image signal under low conversion gain and the reset signal, that is, obtaining the correlated double-sampled image quantization value under low conversion gain. At time t20, the image signal quantization under low conversion gain ends, and the vramp ramp voltage returns to the reference state.

[0236] Seventh Embodiment

[0237] On the other hand, this application also provides a readable storage medium, optionally storing a computer program on the readable storage medium, which, when executed by a processor, implements the steps of the image reading method as described above.

[0238] As described above, the dual-conversion-gain image reading method, imaging device, and readable storage medium provided in this application can simultaneously perform the quantization processing of the first conversion-gain reset signal by configuring both readout circuits to quantize the first conversion-gain reset signal, thereby effectively reducing the quantization reading time and accelerating the reading speed.

[0239] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for image reading with dual conversion gain, characterized in that, include: The on-reset switch and the conversion gain switch reset the floating diffusion node, generating the first conversion gain reset signal; Switching the dual conversion gain switch activates the first conversion gain mode, briefly turning on the transmission switch to generate the first gain image signal; The first readout circuit is controlled to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal to obtain an effective first conversion gain image signal; Switching the dual conversion gain switch activates the second conversion gain mode, briefly turning on the transmission switch to generate a second gain image signal; The second readout circuit is controlled to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal to obtain an effective second conversion gain image signal; wherein the time periods during which the first readout circuit and the second readout circuit perform quantization processing on the first conversion gain reset signal respectively overlap to at least partially. When the second readout circuit performs the second quantization process, it performs quantization compensation on the first conversion gain reset signal and / or the second conversion gain image signal to obtain the effective second conversion gain image signal.

2. The method as described in claim 1, characterized in that, The first readout circuit and the second readout circuit simultaneously begin quantization processing of the first conversion gain reset signal.

3. The method as described in claim 1, characterized in that, The second readout circuit performs quantization compensation on the second conversion gain image signal by adjusting the ramp voltage.

4. The method as described in claim 3, characterized in that, The second readout circuit performs quantization compensation on the second conversion gain image signal by increasing the amplitude of the ramp voltage to prolong the counting process.

5. The method as described in claim 4, characterized in that, The first readout circuit includes a first comparator and a first counter; the second readout circuit includes a second comparator and a second counter, and the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal includes: The first conversion gain reset signal is input to the first input terminal of the first comparator and the second comparator respectively, and the first ramp voltage is input to the second input terminal of the first comparator and the second comparator respectively, and the first counter and the second counter are controlled to count. When the output signals of the first comparator and the second comparator flip, the first counter and the second counter are controlled to stop counting. The first conversion gain image signal is input to the first input terminal of the first comparator, the first ramp voltage is input to the second input terminal of the first comparator, and the first counter is controlled to count in the reverse direction. When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting; The second conversion gain image signal is input to the first input terminal of the second comparator, the second ramp voltage is input to the second input terminal of the second comparator, and the second counter is controlled to count in the reverse direction; wherein, the amplitude of the second ramp voltage is higher than that of the first ramp voltage; When the state of the output signal of the second comparator flips, it controls the second counter to stop counting.

6. The method as described in claim 1, characterized in that, The second readout circuit performs quantization compensation on the second conversion gain image signal or the first conversion gain reset signal by controlling the second conversion gain counting signal.

7. The method as described in claim 6, characterized in that, The second readout circuit controls the counting of the first conversion gain reset signal by controlling the second conversion gain counting signal to stop counting in advance in order to perform quantization compensation.

8. The method as described in claim 7, characterized in that, The first readout circuit includes a first comparator and a first counter; the second readout circuit includes a second comparator and a second counter, and the step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal includes: The first conversion gain reset signal is input to the first input terminal of the first comparator and the second comparator respectively, and the first ramp voltage is input to the second input terminal of the first comparator and the second comparator respectively, and the first counter and the second counter are controlled to count. When a preset condition is met, the second counter is controlled to stop counting in advance; When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting; The first conversion gain image signal is input to the first input terminal of the first comparator, the first ramp voltage is input to the second input terminal of the first comparator, and the first counter is controlled to count in the reverse direction. When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting; The second conversion gain image signal is input to the first input terminal of the second comparator, the first ramp voltage is input to the second input terminal of the second comparator, and the second counter is controlled to count in the reverse direction; When the state of the output signal of the second comparator flips, it controls the second counter to stop counting.

9. The method as described in claim 6, characterized in that, The second readout circuit controls the counting of the second conversion gain image signal by controlling the second conversion gain counting signal to extend the counting process for quantization compensation.

10. The method as described in claim 9, characterized in that, The step of controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal includes: The first conversion gain reset signal is input to the first input terminal of the first comparator and the second comparator respectively, and the first ramp voltage is input to the second input terminal of the first comparator and the second comparator respectively, and the first counter and the second counter are controlled to count. When the output signals of the first comparator and the second comparator flip, the first counter and the second counter are controlled to stop counting. The first conversion gain image signal is input to the first input terminal of the first comparator, the first ramp voltage is input to the second input terminal of the first comparator, and the first counter is controlled to count in the reverse direction. When the state of the output signal of the first comparator flips, the first counter is controlled to stop counting; The second conversion gain image signal is input to the first input terminal of the second comparator, the first ramp voltage is input to the second input terminal of the second comparator, and the second counter is controlled to count in the reverse direction; When the preset conditions are met, the second counter is controlled to extend the counting. When the state of the output signal of the second comparator flips, it controls the second counter to stop counting.

11. The method as described in claim 1, characterized in that, The first conversion gain is a high conversion gain, and the second conversion gain is a low conversion gain.

12. The method as described in claim 1, characterized in that, The quantization compensation is determined based on the gain difference between the first conversion gain and the second conversion gain.

13. The method as described in claim 1, characterized in that, Before the step of controlling the first readout circuit to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal, and controlling the second readout circuit to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal, the following steps are included: The first comparator of the first readout circuit and the second comparator of the second readout circuit are cleared to zero.

14. The method as described in claim 13, characterized in that, The steps for clearing the second comparator of the second readout circuit include: Enable the first conversion gain reset mode to obtain the first conversion gain reset signal, and use the first conversion gain reset signal as a reference to clear the second comparator; Alternatively, enable the second conversion gain reset mode to obtain the second conversion gain reset signal, and use the second conversion gain reset signal as a reference to clear the second comparator.

15. An image reading apparatus for performing the dual-conversion-gain image reading method according to any one of claims 1-14, characterized in that, The image reading device includes a pixel circuit and a first readout circuit and a second readout circuit respectively connected to the pixel circuit; The pixel circuit is configured to output pixel signals to the first readout circuit and the second readout circuit, and the pixel signals include a first conversion gain reset signal, a first conversion gain image signal, and a second conversion gain image signal; The first readout circuit is configured to perform a first quantization process on the first conversion gain reset signal and the first conversion gain image signal; The second readout circuit is configured to perform a second quantization process on the first conversion gain reset signal and the second conversion gain image signal, the second quantization process including quantization compensation on the first conversion gain reset signal or the second conversion gain image signal.

16. The image reading device as claimed in claim 15, characterized in that, The first readout circuit includes a first comparator and a first counter; the second readout circuit includes a second comparator and a second counter. The first input terminal of the first comparator receives the first conversion gain reset signal or the first conversion gain image signal, the second input terminal of the first comparator receives a ramp voltage, and the output terminal of the first comparator is connected to the first counter. The first counter is used to quantize the first conversion gain reset signal or the first conversion gain image signal according to the output result of the first comparator. The first input terminal of the second comparator receives the first conversion gain reset signal or the second conversion gain image signal, the second input terminal of the second comparator receives the first ramp voltage or the second ramp voltage, the output terminal of the second comparator is connected to the second counter, and the second counter is configured to quantize the first conversion gain reset signal or the second conversion gain image signal according to the output result of the second comparator or according to the second conversion gain count signal.

17. The image reading device as claimed in claim 15, characterized in that, The second readout circuit includes a second comparator and a clear circuit connected to each other, the clear circuit being configured to: The second comparator is cleared using the first conversion gain reset signal as a reference. Alternatively, enable the second conversion gain reset mode to obtain the second conversion gain reset signal, and use the second conversion gain reset signal as a reference to clear the second comparator.

18. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the image reading method as described in any one of claims 1 to 14.

Images