Semiconductor device and method of fabrication

Abstract

The application discloses a semiconductor device and a manufacturing method. The semiconductor device comprises a substrate, a plurality of storage node pads, a capacitor structure, and a support structure. The substrate comprises a storage area and a peripheral area. The plurality of storage node pads are disposed on the substrate and located in the storage area. The capacitor structure is disposed on the storage node pads and comprises a plurality of bottom electrodes in contact with the storage node pads. The support structure is disposed on the storage node pads and physically contacts the bottom electrodes. The support structure comprises a first support layer and a second support layer disposed in sequence from bottom to top. The second support layer has a first thickness and a second thickness. The second thickness is greater than the first thickness. The second support layer with the first thickness is located in the storage area. The second support layer with the second thickness is located between the storage area and the peripheral area. The embodiments of the application can improve the performance and reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to semiconductor memory devices and their manufacturing methods. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells arranged in an array to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs, leading to a decrease in the performance and reliability of related memory devices. Summary of the Invention

[0003] One objective of this invention is to provide a semiconductor device and manufacturing method to solve the technical problem that the continuous increase in memory cell density leads to increasing difficulties and complexity in related manufacturing processes and designs, resulting in reduced performance and reliability of related memory devices.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device, comprising: a substrate including a storage region and a peripheral region; a plurality of storage node pads disposed on the substrate and located within the storage region; a capacitor structure disposed on the storage node pads, including a plurality of bottom electrodes respectively contacting the storage node pads; and a support structure disposed on the storage node pads, the support structure being disposed between the bottom electrodes and physically contacting the bottom electrodes, the support structure including a first support layer and a second support layer sequentially disposed from bottom to top, the second support layer having a first thickness and a second thickness, wherein the second thickness is greater than the first thickness, the second support layer having the first thickness is located in the storage region, and the second support layer having the second thickness is located between the storage region and the peripheral region.

[0005] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: First, a substrate is provided, the substrate including a storage region and a peripheral region; a plurality of storage node pads located within the storage region are formed on the substrate; a capacitor structure is formed on the storage node pads, the capacitor structure including a plurality of bottom electrodes respectively contacting the storage node pads; and a support structure is formed on the storage node pads, the support structure being positioned between and physically contacting each of the bottom electrodes, the support structure including a first support layer and a second support layer sequentially disposed from bottom to top, the second support layer having a first thickness and a second thickness, wherein the second thickness is greater than the first thickness, the second support layer having the first thickness is located in the storage region, and the second support layer having the second thickness is located between the storage region and the peripheral region.

[0006] Beneficial effects

[0007] The beneficial effects of the embodiments disclosed herein compared with the prior art include at least the following: by forming a support structure with a relatively large local thickness between the storage area and the peripheral area, more optimized structural support is provided for the capacitor structure, thereby greatly improving the performance and reliability of the semiconductor device. Attached Figure Description

[0008] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 6 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention is provided, wherein:

[0010] Figure 1 This is a schematic cross-sectional view of the semiconductor device of the present invention after forming a stacked layer structure;

[0011] Figure 2 This is a schematic cross-sectional view of the semiconductor device of the present invention after the patterned mask layer;

[0012] Figure 3 This is a schematic cross-sectional view of the semiconductor device of the present invention after the perforation is formed;

[0013] Figure 4 This is a schematic cross-sectional view of the semiconductor device of the present invention after the mask pattern has been formed;

[0014] Figure 5 This is a schematic cross-sectional view of the semiconductor device of the present invention after the bottom electrode has been formed; and

[0015] Figure 6 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the capacitor structure and plug have been formed.

[0016] Figures 7 to 8 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention is provided, wherein:

[0017] Figure 7 This is a schematic cross-sectional view of the semiconductor device of the present invention after the formation of a through-hole; and

[0018] Figure 8 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the capacitor structure and plug have been formed.

[0019] Figures 9 to 10 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention is provided, wherein:

[0020] Figure 9 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the mask pattern has been formed; and

[0021] Figure 10 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the capacitor structure and plug have been formed.

[0022] Figure 11 A cross-sectional schematic diagram of a semiconductor device according to a fourth embodiment of the present invention is shown.

[0023] The reference numerals in the attached figures are explained as follows:

[0024]

[0025]

[0026] Detailed Implementation

[0027] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0028] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be located directly or indirectly on that other component. When a component is referred to as "connected to" another component, it can be directly or indirectly connected to that other component. The terms "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or position based on the orientation or position shown in the accompanying drawings, and are only for ease of description and should not be construed as limiting the present technical solution.

[0029] Please refer to Figures 1 to 6 The illustration shows the steps of the method for manufacturing the semiconductor device 10 in the first embodiment of the present invention.

[0030] First, such as Figure 1 As shown, a substrate 100 is provided. The substrate type of the substrate 100 can be any of the following: a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate. The substrate 100 further includes a region with a relatively high component density, such as a cell region 100a, and another region with a relatively low component density, such as a peripheral region 100b. The cell region 100a and the peripheral region 100b can be arranged adjacent to each other. Preferably, from a top view (not shown), the peripheral region 100b can surround the outside of the cell region 100a, but this is not a limitation.

[0031] At least one insulating region, such as a shallow trench isolation (STI) 112, is formed within the substrate 100, and multiple active areas (AA) 110 are defined within the substrate 100. Thus, from the aforementioned top view, the shallow trench isolation 112 can surround the outside of all active areas 110. In one embodiment, the shallow trench isolation 112 can be formed by first etching multiple trenches (not shown) in the substrate 100, and then filling each trench with at least one insulating material (such as silicon oxide or silicon oxynitride) to form multiple shallow trench isolations 112 with surfaces flush with the top surface of the substrate 100, but this is not a limitation.

[0032] Next, a plurality of gates, preferably buried gates 120, are formed within the substrate 100. The buried gates 120 are generally formed within the storage region 100a; in this embodiment, they are preferably formed within the storage region 100a and a portion of the peripheral region 100b adjacent to the storage region 100a, such as... Figure 1As shown. The fabrication process of the buried gate 120 includes, but is not limited to, the following steps. First, a plurality of trenches (not shown) extending parallel to each other are formed in the substrate 100. Then, a dielectric layer 122 covering the entire surface of each trench, a gate dielectric layer 124 covering the lower half of the surface of each trench, a gate 126 filling the lower half of each trench, and a capping layer 128 filling the upper half of each trench are formed in each trench. Thus, the surface of the capping layer 128 can be flush with the top surface of the substrate 100, so that the buried gate 120 located in the substrate 100 can serve as a buried word line (BWL) of the semiconductor device 10.

[0033] Then, a plurality of bit lines (not shown, BL) and a plurality of storage node contacts (SNCs) 132 are formed on the substrate 100. In this embodiment, the bit lines and storage node contacts 132 are also preferably formed in the storage region 100a and a portion of the peripheral region 100b adjacent to the storage region 100a. Although the bit lines are not specifically shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that each bit line extends parallel to each other, is electrically isolated from the buried gate 120 located in the substrate 100 by an insulating layer (not shown, for example, containing a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100, and is electrically connected to the substrate 100 by bit line contacts (not shown, BLCs) formed correspondingly below each bit line extending into the active region 110. Those skilled in the art will readily understand that, from the aforementioned top-down view, the extension directions of the active region 110, the buried gate 120, and the bit line are all different. The extension direction of the bit line should be perpendicular to the extension direction of the buried gate 120 and intersect with both the active region 110 and the buried gate 120. The memory node plugs 132 are respectively disposed between the bit lines.

[0034] Storage node plugs 132 physically contact the active region 110, with storage node pads 134 disposed above them. Adjacent storage node plugs 132 and adjacent storage node pads 134 are isolated from each other by storage node contact isolation (SCISO) 136 disposed directly above each buried gate 120. Thus, the storage node plugs 132 are electrically connected to the substrate 100 to receive and transmit voltage signals from the substrate 100 (such as transistor components within the substrate 100). In one embodiment, the storage node plugs 132 may be made of epitaxial materials such as silicon (Si), silicon-phosphorus (SiP), silicon-germanium (SiGe), or germanium (Ge), and the storage node pads 134 may be made of low-resistivity metals such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but are not limited thereto. Those skilled in the art will readily understand that the storage node pad 134 may also be integrally formed with the storage node plug 132 based on the same conductive material, but is not limited thereto.

[0035] On the other hand, at least one gate structure 140 and a plurality of plugs 154 are formed on the substrate 100 within the peripheral region 100b. It should be noted that the fabrication process of the gate structure 140 can be similar to that of the bit line, so that the gate structure 140 has a structure and materials similar to those of the bit line. For example, it may include a gate dielectric layer 142 (containing the same material as the insulating layer, such as a silicon oxide-silicon nitride-silicon oxide structure), a semiconductor layer 144 (which may be made of polysilicon), a barrier layer 146 (which may be made of titanium and / or titanium nitride), a conductive layer 148 (which may be made of a low-resistivity metal such as tungsten, aluminum or copper), and a capping layer 150 (which may be made of silicon oxide, silicon nitride or silicon oxynitride). The spacer wall 152 disposed on the sidewall of the gate structure 140 may be formed together with the bit line spacer (not shown) disposed on the sidewall of the bit line. The spacer wall 152 and the bit line spacer may include the same dielectric material, but are not limited thereto. Furthermore, the fabrication process of the plug 154 can be similar to that of the storage node plug 132 and the storage node pad 134, such that each plug 154 includes sequentially stacked epitaxial material 154a (the material of which may include silicon, silicon phosphorus, silicon germanium, or germanium, etc.) and low-resistivity metal material 154b (the material of which may include aluminum, titanium, copper, or tungsten, etc.). The plug 154 is formed in the dielectric layer 156 on both opposite sides of the gate structure 140 and is electrically connected to the substrate 100.

[0036] For example Figure 1As shown, a support layer structure 160 and a mask layer structure 170 are further formed on the substrate 100, wherein both the support layer structure 160 and the mask layer structure 170 integrally cover the storage region 100a and the peripheral region 100b of the substrate 100. Specifically, the support layer structure 160 may include at least one oxide layer and at least one nitride layer alternately stacked. In this embodiment, the support layer structure 160 may include, but is not limited to, a first support material layer 162 (the material of which may include silicon oxide), a second support material layer 164 (the material of which may include silicon nitride or silicon carbonitride), a third support material layer 166 (the material of which may include silicon oxide), and a fourth support material layer 168 (the material of which may include silicon nitride or silicon carbonitride) stacked sequentially from bottom to top. Preferably, the oxide layer (e.g., including a first support material layer 162 and a third support material layer 166) may have a relatively large thickness, for example, the thickness of the oxide layer is 5 to 10 times or more the thickness of the nitride layer (e.g., including a second support material layer 164 or a fourth support material layer 168). Furthermore, the thickness t11 of the nitride layer (e.g., the fourth support material layer 168) disposed away from the substrate 100 is preferably greater than the thickness of the nitride layer (e.g., the second support material layer 164) disposed adjacent to the substrate 100. Figure 1 As shown, but not limited thereto. Thus, the overall thickness of the support layer structure 160 is approximately 1600 to 2000 angstroms, but not limited thereto. Those skilled in the art will understand that the specific stacking number of the aforementioned oxide layer and the aforementioned nitride layer is not limited to this. Figure 1 The number of layers shown is for illustrative purposes only and may be adjusted to other numbers depending on actual needs. The mask layer structure 170 is formed on the support layer structure 160 and preferably has a composite structure. In this embodiment, the mask layer structure 170 may include, but is not limited to, sequentially stacked organic underlayer 172, silicon hard mask bottom anti-reflective coating 174, and photoresist layer 176.

[0037] like Figure 2 As shown, a photolithography process is performed. This photolithography process includes, but is not limited to, the following steps: First, a photomask (not shown) is provided, and the pattern of the photomask is transferred to the photoresist layer 176, then patterned as shown... Figure 1 The photoresist layer 176 is shown. Next, the patterned photoresist layer 176 is transferred onto the underlying silicon hard mask bottom anti-reflective coating 174 and organic substrate 172, forming a layer as shown. Figure 2The diagram shows the silicon hard mask bottom anti-reflective coating 174 and the organic underlayer 172. It should be noted that, since the pattern of the photomask is mainly located in the storage region 100a, while the peripheral region 100b is entirely covered by the mask layer structure 170, the difference in pattern accumulation between the two regions (storage region 100a and peripheral region 100b) leads to an etching loading effect (micro-loading effect). Therefore, during pattern transfer, due to localized high etching gas consumption or uneven etching gas distribution, the silicon hard mask bottom anti-reflective coating 174 located in the storage region 100a has a reduced thickness t22 after the photolithography process, while the silicon hard mask bottom anti-reflective coating 174 in the peripheral region 100b maintains its original thickness t21 after the photolithography process. In other words, after the photolithography process is performed, the top surface of the bottom anti-reflective coating 174 of the silicon hard mask located in the peripheral region 100b and the top surface of the bottom anti-reflective coating 174 of the silicon hard mask located in the storage region 100a are not coplanar with each other, such as Figure 2 As shown.

[0038] Then, through, as Figure 2 The silicon hard mask shown is etched using an etching process, such as a dry etching process, to the bottom anti-reflective coating 174 and organic substrate 172, sequentially penetrating the fourth support material layer 168, the third support material layer 166, the second support material layer 164, and the first support material layer 162. Multiple through-holes 160a are formed within the support layer structure 160. Figure 3 As shown. Each via 160a is aligned with the corresponding memory node pad 134 below, so that the top surface of each memory node pad 1340 can be exposed through each via 160a. Figure 2 The silicon hard mask bottom anti-reflective coating 174 and organic underlayer 172 shown are simultaneously consumed during the etching process, or completely removed after the etching process. It should also be noted that due to the difference in pattern density of the silicon hard mask bottom anti-reflective coating 174 in the two regions (memory region 100a and peripheral region 100b), an etching load effect occurs, causing the fourth support material layer 168a in memory region 100a to be partially consumed during the etching process, resulting in a corresponding reduction in thickness t12, while the fourth support material layer 168b in peripheral region 100b retains its original thickness t11. That is, after the etching process, the top surface of the fourth support material layer 168b in peripheral region 100b and the top surface of the fourth support material layer 168a in memory region 100a are not coplanar, as shown... Figure 3 As shown.

[0039] like Figure 4As shown, a deposition and etch-back fabrication process is performed to form multiple bottom electrode layers 178 within a support layer structure 160, and a mask layer structure 190 is formed on the support layer structure 160 and the bottom electrode layers 178. In one embodiment, the fabrication process of the bottom electrode layers 178 includes, but is not limited to, the following steps. First, an electrode material layer is formed on the support layer structure 160, such as a low-resistivity metal material including aluminum, titanium, copper, or tungsten. Preferably, the metal material may include titanium. A portion of the electrode material layer is formed within each through-hole 160a and conformally covers the inner surface of each through-hole 160a, while another portion is formed outside each through-hole 160a and covers the top surface of the support layer structure 160. Then, the electrode material layer formed outside each through-hole 160a is removed, forming multiple bottom electrode layers 178, each having a U-shaped structure, located within each through-hole 160a. It should be noted that, due to the thickness difference (t12 / t11) between the fourth support material layer 168a located in storage area 100a and the fourth support material layer 168b located in peripheral area 100b, the bottom electrode layer 178b formed at the boundary between storage area 100a and peripheral area 100b has side walls of unequal height. The side wall of the bottom electrode layer 178b adjacent to the peripheral area 100b has a relatively higher top surface, while the side wall of the bottom electrode layer 178b adjacent to the storage area 100a has a relatively lower top surface and is at the same height as the top surface of the fourth support material layer 168a in storage area 100a, thus exhibiting an asymmetrical structure. The bottom electrode layer 178a formed in storage area 100a, however, has side walls of equal height, and both side walls are at the same height as the fourth support material layer 168a in storage area 100a, thus exhibiting a symmetrical structure.

[0040] For example Figure 4 As shown, the mask layer structure 190 also has a composite structure, such as including, but not limited to, a sequentially stacked organic substrate 180, a silicon hard mask bottom anti-reflective coating 182, a photoresist layer 184, and multiple mask patterns 186. Each mask pattern 186 covers the support layer structure 160 within the memory region 100a in such a way that it simultaneously covers two adjacent bottom electrode layers 178a and partially covers one bottom electrode layer 178a on each side of the aforementioned two adjacent bottom electrode layers 178a. Furthermore, one of the mask patterns 186 also simultaneously covers a portion of the memory region 100a and a portion of the peripheral region 100b, completely covering the bottom electrode layer 178b formed at the boundary between the memory region 100a and the peripheral region 100b.

[0041] Then, through, as Figure 4The mask pattern 186 shown performs at least one etching process on the support layer structure 160, such as a first dry etching process, to remove a portion of the underlying photoresist layer 184, a portion of the silicon hard mask bottom anti-reflective coating 182, a portion of the organic underlayer 180, a portion of the fourth support material layer 168a, and a portion of the third support material layer 166. Then, a first wet etching process is performed, introducing an etchant such as tetramethylammonium hydroxide (TMAH) to remove the remaining portion of the third support material layer 166. Next, another etching process is performed, such as a second dry etching process, to further remove a portion of the second support material layer 164 and a portion of the first support material layer 162. Then, a second wet etching process is performed, introducing an etchant such as tetramethylammonium hydroxide to remove the remaining portion of the first support material layer 162. In other words, the mask layer structure 190 and the support layer structure 160 formed within the peripheral region 100b are completely removed, and then the remaining portion of the mask layer structure 190 is completely removed.

[0042] It should be noted that, as Figure 4 The mask pattern 186 and the portion of the bottom electrode layer 178a within the storage area 100a shown are simultaneously consumed during the first dry etching process and / or the first wet etching process. This not only removes the mask pattern 186 but also shortens one sidewall of the bottom electrode layer 178a. Under this operation, as... Figure 5 As shown, a plurality of bottom electrodes 278 are formed on the storage node plug structure 130, including a bottom electrode 278a with a symmetrical U-shaped electrode structure and disposed within the storage area 100a, a bottom electrode 278b with an asymmetrical U-shaped electrode structure and disposed at the junction of the storage area 100a and the peripheral area 100b, and a bottom electrode 278c with an asymmetrical U-shaped electrode structure and disposed within the storage area 100a. One sidewall of the bottom electrode 278b is connected to the bottom electrode 278. The two sidewalls of bottom electrode 278a are at the same height, while the other sidewall of bottom electrode 278b is higher than the two sidewalls of bottom electrode 278a. One sidewall of bottom electrode 278c is also at the same height as the two sidewalls of bottom electrode 278a, while the other sidewall of bottom electrode 278c is lower than the two sidewalls of bottom electrode 278a. This arrangement can further increase the space between some bottom electrodes 278 within the storage area 100a (such as between bottom electrodes 278a and 278c) to facilitate subsequent deposition processes.

[0043] On the other hand, the remaining fourth support material layers 168a and 168b, together with the remaining second support material layer 164, form second support layers 264a and 264b and a first support layer 262 arranged sequentially from top to bottom, respectively, together constituting a support structure 260 disposed on the memory node pad 134. The support structure 260 is disposed between each bottom electrode 278, physically contacting at least one sidewall of each bottom electrode 278 and providing corresponding structural support. In detail, such as... Figure 5 As shown, the second support layer 264a disposed within the storage region 100a has a relatively small first thickness t12, and its top surface is coplanar with the top surface of the bottom electrode 278a within the storage region 100a. The second support layer 264b disposed within the peripheral region 100b has a relatively large second thickness t11, and its highest top surface is higher than the top surface of the second support layer 264a, and is coplanar with the top surface of the higher sidewall of the bottom electrode 278b, while its bottom surface is coplanar with the bottom surface of the second support layer 264a. In other words, the height of the second support layer 264b relative to the top surface of the substrate 100 is greater than the height of the second support layer 264a relative to the top surface of the substrate 100. Thus, the arrangement of the second support layer 264b further optimizes the structural support of the bottom electrode 278b disposed at the junction of the storage region 100a and the peripheral region 100b.

[0044] like Figure 6As shown, at least one deposition process is performed on the support structure 260 to sequentially form a capacitor dielectric layer 280 and a top electrode layer 282. The capacitor dielectric layer 280 conformally covers the exposed surfaces of each bottom electrode 278 and the support structure 260, while the top electrode layer 282 covers the capacitor dielectric layer 280 and fills the remaining space between the bottom electrodes 278. Parts of the capacitor dielectric layer 280 and the top electrode layer 282 may further be formed in the space between the second support layer 264 and the first support layer 262, and also in the space between the first support layer 262 and the memory node pad 134, to increase the contact area and improve the capacitance value. In one embodiment, the capacitor dielectric layer 280 may include a high dielectric constant dielectric material, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), and strontium bismuth tantalum oxide. tantalate, SrBi2Ta2O9, SBT), lead zirconate titanate (Lead zirconate titanate, PbZrxTi 1- x O3, PZT) or Barium Strontium Titanate (BaxSr) 1-x TiO3, BST, etc., preferably including zirconium oxide-aluminum oxide-zirconium oxide (ZAZ), and the top electrode layer 282 may include low-resistivity metal materials such as aluminum, titanium, copper or tungsten, preferably including titanium, but not limited thereto.

[0045] Then, by performing a patterning process, the top electrode layer 282 and the capacitor dielectric layer 280 located outside the storage region 100a are removed to form a capacitor structure 284. This completes the fabrication process of the capacitor structure 284. The capacitor structure 284 is composed of a bottom electrode 278, a capacitor dielectric layer 280, and a top electrode layer 282 stacked sequentially, and includes a plurality of vertically extending capacitors to serve as storage nodes (SN) of the semiconductor device 10. Each capacitor can be electrically connected to a transistor assembly (not shown) within the substrate 100 through a storage node plug 132. With this configuration, the semiconductor device 10 of this embodiment can form a dynamic random access memory (DRAM) device, which consists of at least one transistor assembly and at least one capacitor forming the smallest memory cell in the DRAM array to receive voltage information from the bit lines and the buried word lines (buried gate 120).

[0046] Subsequently, for example Figure 6 As shown, an interlayer dielectric layer 286 is formed on the substrate 100, covering the capacitor structure 284 in the storage region 100a and the gate structure 140 in the peripheral region 100b. At least one plug 290 electrically connecting the capacitor structure 284 and the gate structure 140 is formed within the interlayer dielectric layer 286. Specifically, the plug 290a electrically connecting the capacitor structure 284 is formed in the storage region 100a and physically contacts the capacitor structure 284. The plug 290b electrically connecting the gate structure 140 is formed in the peripheral region 100b, has a relatively large aspect ratio, and physically contacts the plug 154. In one embodiment, each plug 290a, 290b includes sequentially stacked barrier layers 292, 296 and conductive layers 294, 298. The barrier layers 292, 296 may be made of materials such as titanium, tantalum, titanium nitride or tantalum nitride, while the conductive layers 294, 298 may be made of materials such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably including tungsten, but not limited thereto.

[0047] Thus, the fabrication process of the semiconductor device 10 in this embodiment is completed. Subsequently, the capacitor structure 284 formed in the storage region 100a and the gate structure 140 formed in the peripheral region 100b can be further connected to an external circuit via the plug 290 and the subsequently formed metal interconnects. Those skilled in the art will readily understand that the specific wiring configuration and quantity of the metal interconnects can be adjusted according to actual device requirements. For example, it may include at least wires 302 and 304 electrically connecting the plugs 290a and 290b, and a dielectric layer 306 surrounding the wires 302 and 304. Figure 6 As shown, but not limited to.

[0048] According to the method for fabricating a semiconductor device 10 according to a first embodiment of the present invention, a support structure 260 with a relatively large local thickness is formed at the junction of the storage region 100a and the peripheral region 100b. For example, the second support layer 264a disposed in the storage region 100a has a relatively small first thickness t12, while the second support layer 264b disposed at the junction of the storage region 100a and the peripheral region 100b has a relatively large second thickness t11. Thus, when forming the bottom electrode 278, the bottom electrode 278b formed at the junction of the storage region 100a and the peripheral region 100b has correspondingly different sidewalls. The sidewall of the bottom electrode 278b adjacent to the peripheral region 100b is in physical contact with the second support layer 264b and has a relatively high top surface, while the sidewall of the bottom electrode 278b adjacent to the storage region 100a has a relatively low top surface and is at the same height as the top surface of the second support layer 264a, so that the bottom electrode 278b presents an asymmetrical structure as a whole. In this operation, the fabrication method of this embodiment can create a gap between adjacent bottom electrodes 278 within the storage region 100a by forming locally asymmetrical bottom electrodes 278 (such as between bottom electrodes 278b and 278c), thereby facilitating subsequent deposition processes. Furthermore, the fabrication method of this embodiment can also strengthen the structural support of the bottom electrodes 278 at the junction of the storage region 100a and the peripheral region 100b by forming a locally thicker support structure 260. In addition, the subsequently formed capacitor dielectric layer 280 further covers the second support layer 264b, so that the sidewalls and surface of the second support layer 264b physically contact the bottom electrode 278b or the capacitor dielectric layer 280, respectively, increasing the contact area between the capacitor dielectric layer 280, the top electrode layer 282, and the second support layer 264b to enhance physical support. Therefore, the fabrication method of the semiconductor device 10 of this embodiment can effectively improve the structural reliability of the semiconductor device 10 and optimize its function and performance, even as the density of the storage cells continues to increase and the complexity of the fabrication process gradually increases.

[0049] According to the first embodiment of the semiconductor device 10 of the present invention, a support structure 260 with a locally thicker structure is provided at the junction of the storage region 100a and the peripheral region 100b to strengthen the structural support of the bottom electrode 278 at the junction of the storage region 100a and the peripheral region 100b. Simultaneously, the contact area between the capacitor dielectric layer 280, the top electrode layer 282, and the second support layer 264b is increased to enhance physical support. Furthermore, the semiconductor device 10 of this embodiment also provides bottom electrodes 278 with locally asymmetrical structures (such as bottom electrodes 278b and 278c) to effectively increase the space between adjacent bottom electrodes 278 within the storage region 100a, thereby facilitating subsequent deposition processes. Therefore, the semiconductor device 10 of this embodiment can maintain the structural reliability of the semiconductor device 10 and achieve optimized functionality and performance while continuously increasing the density of the storage cells.

[0050] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and manufacturing method of the present invention may also have other forms, and are not limited to those described above. The following will further describe other embodiments or variations of the semiconductor device and manufacturing method of the present invention. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same aspects. Furthermore, the same components in the various embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0051] Please refer to Figures 7 to 8 The diagram illustrates the steps of fabricating the semiconductor device 20 in the second embodiment of the present invention. The fabrication steps of the semiconductor device 20 in this embodiment are generally the same as those of the semiconductor device 10 in the first embodiment, and the similarities will not be repeated. The main difference between the fabrication method of this embodiment and the fabrication method of the first embodiment is that, due to the aforementioned etching load effect, the thickness t21 of the anti-reflection coating 174 at the bottom of the silicon hard mask in the peripheral region 100b is reduced (e.g., ...). Figure 2 The image shown also shrinks during the pattern transfer process, and the fourth support material layer 168b below it is also partially etched during the subsequent etching process, finally forming a notch R1 on the fourth support material layer 168c.

[0052] In detail, such as Figure 7 As shown, in this embodiment, the fourth support material layer 168a formed in the storage region 100a is partially consumed during the etching process, and correspondingly has a similarly reduced thickness t12. The fourth support material layer 168b located in the peripheral region 100b is subjected to... Figure 2The silicon hard mask shows that the bottom anti-reflective coating 174 (original thickness t21) and organic underlayer 172 provide complete protection, maintaining the original thickness t11. The fourth support material layer 168c, located at the junction of memory region 100a and peripheral region 100b, is partially consumed during the etching process, resulting in a reduced thickness t12 for the portion adjacent to memory region 100a, while the portion adjacent to peripheral region 100b maintains the original thickness t11, thus creating an overall stepped structure.

[0053] Then, as Figure 8 As shown, the process continues as described in the first embodiment above. Figures 4 to 6 The fabrication steps sequentially form a bottom electrode 378, a support structure 260, a capacitor dielectric layer 380, and a top electrode layer 282. The sequentially stacked bottom electrode 378, capacitor dielectric layer 380, and top electrode layer 282 together constitute the capacitor structure 384 of this embodiment. It should be noted that because the second support layer 264c formed at the boundary between the storage region 100a and the peripheral region 100b has a relatively large second thickness t11 and a relatively small first thickness t12, the bottom electrode 378b formed at the boundary between the storage region 100a and the peripheral region 100b has sidewalls of equal height on both sides, exhibiting a symmetrical structure. Furthermore, both sidewalls of the bottom electrode 378b are of the same height as the sidewalls of the bottom electrode 378a within the storage region 100a. Similarly, the bottom electrode 378 formed within the storage region 100a has both symmetrical bottom electrode 378a and asymmetrical bottom electrode 378c, facilitating subsequent deposition processes. Thus, the fabrication process of the semiconductor device 20 in this embodiment is completed. The semiconductor device 20 in this embodiment can also be formed as a dynamic random access memory device, including a plurality of vertically extending capacitors as storage nodes of the semiconductor device 20, and electrically connected to transistor components (not shown) in the substrate 100 through storage node plugs 132.

[0054] According to the method for fabricating a semiconductor device 20 according to a second embodiment of the present invention, a second support layer 264c with a stepped structure is formed at the boundary between the storage region 100a and the peripheral region 100b. This allows the locally asymmetrical bottom electrode 378 (such as bottom electrode 378c) to be formed only in the storage region 100a, while the bottom electrode 378b formed at the boundary between the storage region 100a and the peripheral region 100b exhibits a symmetrical U-shaped electrode structure. Under this operation, the fabrication method of this embodiment can also create space between adjacent bottom electrodes 378 within the storage region 100a by forming locally asymmetrical bottom electrodes 378 (such as bottom electrode 378c), thereby facilitating subsequent deposition processes. Furthermore, the fabrication method of this embodiment can also strengthen the structural support of the bottom electrode 378 at the junction of the storage region 100a and the peripheral region 100b by forming a support structure 260 with a larger local thickness. For example, a second support layer 264c with a stepped structure can be formed at the junction of the storage region 100a and the peripheral region 100b, so that the subsequently formed capacitor dielectric layer 380 and top electrode layer 282 and the second support layer 264c can obtain more contact area to increase physical support. Thus, the fabrication method of the semiconductor device 20 of this embodiment can effectively improve the structural reliability of the semiconductor device 20 and optimize the function and performance of the semiconductor device 20 under the premise that the density of the storage cells continues to increase and the complexity of the fabrication process gradually increases.

[0055] According to the second embodiment of the semiconductor device 20 of the present invention, a second support layer 264c with a locally thicker structure is provided at the junction of the storage region 100a and the peripheral region 100b to strengthen the structural support of the bottom electrode 378 at the junction of the storage region 100a and the peripheral region 100b. Furthermore, the semiconductor device 20 of this embodiment also provides a locally asymmetrical bottom electrode 378 (such as bottom electrode 378c) to effectively increase the space between adjacent bottom electrodes 378 within the storage region 100a, thereby facilitating subsequent deposition processes. Thus, the semiconductor device 20 of this embodiment can maintain structural reliability and achieve optimized functionality and performance while continuously increasing the density of the storage cells.

[0056] Please refer to Figures 9 to 10 The diagram illustrates the steps of a method for fabricating a semiconductor device 30 according to a third embodiment of the present invention. The fabrication steps of the semiconductor device 30 in this embodiment are generally the same as those of the semiconductor device 10 in the first embodiment described above, and the similarities will not be repeated. The main difference between the fabrication method of this embodiment and that of the first embodiment is that in this embodiment, a plurality of columnar bottom electrodes 478 are formed.

[0057] In detail, such as Figure 9As shown, a deposition and etch-back fabrication process is performed to form a bottom electrode 478 within the support layer structure 170. The bottom electrode 478a formed in the storage region 100a has a completely flat top surface, exhibiting a symmetrical columnar electrode structure, while the bottom electrode 478b formed at the junction of the storage region 100a and the peripheral region 100b has a stepped top surface, exhibiting an asymmetrical columnar electrode structure.

[0058] Then, as Figure 10 As shown, the process continues as described in the first embodiment above. Figures 4 to 6 The fabrication steps sequentially form a support structure 260, a capacitor dielectric layer 480, and a top electrode layer 482. The sequentially stacked bottom electrode 478, capacitor dielectric layer 480, and top electrode layer 482 together constitute the capacitor structure 484 of this embodiment. It should be noted that because the second support layer 264b formed at the boundary between the storage region 100a and the peripheral region 100b has a relatively large second thickness t11, the bottom electrode 478b formed at the boundary between the storage region 100a and the peripheral region 100b has a stepped top surface, exhibiting an asymmetrical columnar structure. On the other hand, the bottom electrodes 478a and 478c formed within the storage region 100a each have symmetrical or asymmetrical columnar electrode structures, facilitating subsequent deposition processes. Thus, the fabrication process of the semiconductor device 30 of this embodiment is completed. The semiconductor device 30 in this embodiment can also form a dynamic random access memory device, including a plurality of vertically extending capacitors as storage nodes of the semiconductor device 30, and electrically connected to transistor components (not shown) in the substrate 100 through storage node plugs 132.

[0059] According to the method for fabricating the semiconductor device 30 of the third embodiment of the present invention, a support structure 260 with a relatively large local thickness is formed at the junction of the storage region 100a and the peripheral region 100b. Thus, when forming the bottom electrode 478, the bottom electrode 478b formed at the junction of the storage region 100a and the peripheral region 100b has sidewalls of unequal height. Specifically, the sidewall of the bottom electrode 478b adjacent to the peripheral region 100b physically contacts the second support layer 264b and has a relatively high top surface, while the sidewall of the bottom electrode 478b adjacent to the storage region 100a has a relatively low top surface and is at the same height as the top surface of the second support layer 264a, resulting in an asymmetrical columnar electrode structure for the bottom electrode 478b. Under this operation, the fabrication method of this embodiment can create a space between adjacent bottom electrodes 478 within the storage region 100a by forming locally asymmetrical bottom electrodes 478 (such as between bottom electrodes 478b and 478c), thereby facilitating subsequent deposition processes. Furthermore, the fabrication method of this embodiment can also strengthen the structural support of the bottom electrode 478 at the junction of the storage region 100a and the peripheral region 100b by forming a support structure 260 with a larger local thickness. The physical support is increased by further covering the second support layer 264b with the subsequently formed capacitor dielectric layer 480, thereby increasing the contact area between the capacitor dielectric layer 480, the top electrode layer 482, and the second support layer 264b. Thus, the fabrication method of the semiconductor device 30 of this embodiment can effectively improve the structural reliability of the semiconductor device 30 and optimize its function and performance, even as the density of the storage cells continues to increase and the complexity of the fabrication process gradually increases.

[0060] According to the third embodiment of the semiconductor device 30 of the present invention, a support structure 260 with a relatively large local thickness is provided at the junction of the storage region 100a and the peripheral region 100b to strengthen the structural support of the bottom electrode 478 at the junction of the storage region 100a and the peripheral region 100b. Furthermore, the semiconductor device 30 of this embodiment also provides bottom electrodes 478 with locally asymmetrical structures (such as bottom electrodes 478b and 478c) to effectively increase the space between adjacent bottom electrodes 478 within the storage region 100a, thereby facilitating subsequent deposition processes. Thus, the semiconductor device 30 of this embodiment can maintain the structural reliability of the semiconductor device 30 and achieve optimized functionality and performance while continuously increasing the density of the storage cells.

[0061] Please refer to Figure 11The diagram illustrates a cross-sectional view of the semiconductor device 40 in the fourth embodiment of the present invention. The structure of the semiconductor device 40 in this embodiment is generally the same as that of the semiconductor device 10 in the first embodiment described above; the similarities will not be repeated here. The main difference between the semiconductor device 40 in this embodiment and the semiconductor device 10 in the first embodiment is that, during the second dry etching process and / or the second wet etching process, the etching selection is controlled to partially consume the remaining portion of the fourth support material layer 168a, or during the formation of such... Figure 4 When the bottom electrode layers 178 are shown, the etching selectivity ratio between the electrode material layer and the fourth support material layer 168 is adjusted, thereby reducing the thickness of the remaining portion of the fourth support material layers 168a and 168b to be flush with or below the top surface of the bottom electrode 278a.

[0062] In detail, such as Figure 11 As shown, the second support layer 364a disposed within the storage region 100a has a relatively small first thickness t14, and its top surface is lower than the top surface of the bottom electrode 278a located within the storage region 100a. On the other hand, the second support layer 364b disposed within the peripheral region 100b has a relatively large second thickness t13, and its highest top surface is higher than the top surface of the second support layer 364a, and its highest top surface is lower than the top surface of the bottom electrode 278b located at the junction of the storage region 100a and the peripheral region 100b, while its bottom surface is coplanar with the bottom surface of the second support layer 364a. Subsequently, a capacitor dielectric layer 580 and a top electrode layer 582 are formed, and the sequentially stacked bottom electrode 278, capacitor dielectric layer 580, and top electrode layer 582 together constitute the capacitor structure 584 of this embodiment. It should be noted that the subsequently formed capacitor dielectric layer 580 will further cover the second support layer 364b, so that the sidewalls and surface of the second support layer 364b physically contact the bottom electrode 278b or the capacitor dielectric layer 580, thereby optimizing the structural support of the second support layer 364b for the bottom electrode 278b. Although the accompanying drawings of this embodiment do not show that the second support layer 364b located between the storage region 100a and the peripheral region 100b can also have other forms, those skilled in the art should easily understand that the second support layer 364b can also be as shown in the figures. Figure 8 The second support layer 264c shown also presents a stepped structure, but is not limited to this.

[0063] Therefore, the semiconductor device 40 in this embodiment can also form a dynamic random access memory device, including a plurality of vertically extending capacitors as storage nodes of the semiconductor device 40, and electrically connected to transistor components (not shown) in the substrate 100 through storage node plugs 132.

[0064] According to the fourth embodiment of the present invention, the semiconductor device 40 has a locally thicker support structure 260 at the junction of the storage region 100a and the peripheral region 100b to strengthen the structural support of the bottom electrode 278 at the junction of the storage region 100a and the peripheral region 100b. Furthermore, the semiconductor device 40 of this embodiment also has locally asymmetrical bottom electrodes 278 (such as bottom electrodes 278b and 278c) to effectively increase the space between adjacent bottom electrodes 278 within the storage region 100a, thereby facilitating subsequent deposition processes. Thus, the semiconductor device 40 of this embodiment can maintain structural reliability and achieve optimized functionality and performance while continuously increasing the density of the storage cells.

[0065] The beneficial effects of the embodiments disclosed herein compared with the prior art include at least the following: by forming a support structure with a relatively large local thickness between the storage area and the peripheral area, more optimized structural support is provided for the capacitor structure, thereby greatly improving the performance and reliability of the semiconductor device.

[0066] Overall, according to the semiconductor device and fabrication method of the present invention, a locally thicker support structure is formed between the storage region and the peripheral region to improve the structural support provided by the support structure to the capacitor structure. Simultaneously, the subsequently formed bottom electrode has a correspondingly locally asymmetrical structure, thereby increasing the space between adjacent bottom electrodes within the storage region to facilitate subsequent deposition processes. Thus, the semiconductor device of the present invention can maintain structural reliability and achieve optimized functionality and performance while continuously increasing the density of storage cells.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a storage region and a peripheral region, and multiple shallow trench isolations are located within the substrate; Multiple memory node pads are disposed on the substrate and located within the memory area; The capacitor structure disposed on the pads of the storage node includes a plurality of bottom electrodes that are respectively in contact with the pads of the storage node; as well as A support structure is disposed on the pads of the storage node. The support structure is disposed between the bottom electrodes and physically contacts the bottom electrodes. The support structure includes a first support layer and a second support layer disposed sequentially from bottom to top. The second support layer has a first thickness and a second thickness, wherein the second thickness is greater than the first thickness. The second support layer with the first thickness is located in the storage area, and the second support layer with the second thickness is located between the storage area and the peripheral area. The highest top surface of the second support layer having the second thickness is coplanar with the top surface of the bottom electrode disposed between the storage area and the peripheral area, and the top surface of the second support layer having the first thickness is lower than the top surface of the bottom electrode; The second support layer having the second thickness has a stepped structure located between the storage area and the peripheral area.

2. The semiconductor device according to claim 1, characterized in that, The highest top surface of the second support layer having the second thickness is higher than the top surface of the second support layer having the first thickness.

3. The semiconductor device according to claim 2, characterized in that, The bottom surface of the second support layer having the second thickness is coplanar with the bottom surface of the second support layer having the first thickness.

4. The semiconductor device according to claim 2, characterized in that, The capacitor structure further includes a capacitor dielectric layer and a top electrode layer stacked in sequence, and the sidewall of the second support layer with the second thickness is in physical contact with the capacitor dielectric layer and the bottom electrode.

5. The semiconductor device according to claim 4, characterized in that, The two opposite sidewalls of the second support layer having the second thickness are respectively close to / away from the storage area, with the sidewall close to the storage area physically contacting the bottom electrode and the sidewall away from the storage area physically contacting the capacitor dielectric layer.

6. The semiconductor device according to claim 1, characterized in that, The height of the second support layer with the second thickness relative to the top surface of the substrate is greater than the height of the second support layer with the first thickness relative to the top surface of the substrate.

7. The semiconductor device according to claim 1, characterized in that, The capacitor structure further includes a capacitor dielectric layer and a top electrode layer stacked in sequence, which cover the second support layer having the second thickness, the second support layer having the first thickness, and the bottom electrode. The capacitor dielectric layer also physically contacts the two opposite sidewalls of the second support layer having the second thickness.

8. The semiconductor device according to claim 1, characterized in that, Each of the bottom electrodes has a U-shaped electrode structure or a columnar electrode structure.

9. A method for fabricating a semiconductor device, characterized in that... Include: A substrate is provided, the substrate including a storage region and a peripheral region; Multiple memory node pads located within the memory area are formed on the substrate; A capacitor structure is formed on the storage node pad, the capacitor structure including a plurality of bottom electrodes respectively in contact with the storage node pad; as well as A support structure is formed on the storage node pads. The support structure is located between and physically contacts each of the bottom electrodes. The support structure includes a first support layer and a second support layer arranged sequentially from bottom to top. The second support layer has a first thickness and a second thickness, wherein the second thickness is greater than the first thickness. The second support layer with the first thickness is located in the storage area, and the second support layer with the second thickness is located between the storage area and the peripheral area. The highest top surface of the second support layer having the second thickness is coplanar with the top surface of the bottom electrode disposed between the storage area and the peripheral area, and the top surface of the second support layer having the first thickness is lower than the top surface of the bottom electrode; The second support layer having the second thickness has a stepped structure located between the storage area and the peripheral area.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Also includes: A first support material layer, a second support material layer, a third support material layer, and a fourth support material layer are formed on the substrate in a sequentially stacked manner; Multiple perforations are formed, penetrating the fourth support material layer, the third support material layer, the second support material layer, and the first support material layer; Each bottom electrode is formed within each of the aforementioned perforations; Multiple mask patterns are formed on the fourth support material layer, one of which simultaneously covers a portion of the storage area and a portion of the peripheral area; The mask pattern is removed by removing a portion of the fourth support material layer and a portion of the third support material layer; Remove a portion of the second support material layer and a portion of the first support material layer; The support structure is thus formed.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The process includes, prior to forming the mask pattern, the following: An electrode material layer is formed on the sidewall of the perforation and on the fourth support material layer; and The electrode material layer on the fourth support material layer is removed to form the bottom electrode, and each bottom electrode has a U-shaped electrode structure.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, After forming the mask pattern, the following is also included: Perform a first wet etching process to remove the remaining portion of the third support material layer; and A second wet etching process is performed to remove the remaining portion of the first support material layer.

13. The method for fabricating a semiconductor device according to claim 11, characterized in that, When removing the electrode material layer on the fourth support material layer, the thickness of the fourth support material layer is reduced so that the top surface of the fourth support material layer is lower than the top surface of the bottom electrode.

14. The method for fabricating a semiconductor device according to claim 10, characterized in that, When removing a portion of the second support material layer and a portion of the first support material layer, the thickness of the remaining portion of the fourth support material layer is reduced so that the top surface of the fourth support material layer is lower than the top surface of the bottom electrode.

15. The method for fabricating a semiconductor device according to claim 10, characterized in that, The process includes, prior to forming the mask pattern, the following: An electrode material layer is formed within the perforation and on the fourth support material layer, the electrode material layer filling the perforation; and The electrode material layer on the fourth support material layer is removed to form the bottom electrode, each of the bottom electrodes having a columnar electrode structure.

16. The method for fabricating a semiconductor device according to claim 9, characterized in that, Also includes: A capacitor dielectric layer and a top electrode layer are sequentially formed on the bottom electrode and the support structure, covering the second support layer having the second thickness, the second support layer having the first thickness, and the bottom electrode.

17. A semiconductor device, characterized in that, include: The substrate includes a storage region and a peripheral region, and multiple shallow trench isolations are located within the substrate; Multiple memory node pads are disposed on the substrate and located within the memory area; The capacitor structure disposed on the pads of the storage node includes a plurality of bottom electrodes that are respectively in contact with the pads of the storage node; as well as A support structure is disposed on the pads of the storage node. The support structure is disposed between the bottom electrodes and physically contacts the bottom electrodes. The support structure includes a first support layer and a second support layer disposed sequentially from bottom to top. The second support layer has a first thickness and a second thickness, wherein the second thickness is greater than the first thickness. The second support layer with the first thickness is located in the storage area, and the second support layer with the second thickness is located between the storage area and the peripheral area. The top surface of the second support layer having the first thickness is lower than the top surface of the bottom electrode it contacts, and the top surface of the second support layer having the second thickness is lower than the top surface of the bottom electrode it contacts.

18. The semiconductor device according to claim 17, characterized in that, The highest top surface of the second support layer having the second thickness is higher than the top surface of the second support layer having the first thickness.

19. The semiconductor device according to claim 17, characterized in that, The bottom surface of the second support layer having the second thickness is coplanar with the bottom surface of the second support layer having the first thickness.

20. The semiconductor device according to claim 17, characterized in that, The capacitor structure further includes a capacitor dielectric layer and a top electrode layer stacked in sequence, and a second support layer having the second thickness physically contacts the capacitor dielectric layer and the bottom electrode.

21. The semiconductor device according to claim 17, characterized in that, The two opposite sidewalls of the second support layer having the second thickness are respectively close to / away from the storage area, and the sidewall close to the storage area is in physical contact with the bottom electrode.

22. The semiconductor device according to claim 17, characterized in that, The height of the second support layer with the second thickness relative to the top surface of the substrate is greater than the height of the second support layer with the first thickness relative to the top surface of the substrate.

23. A semiconductor device, characterized in that, include: The substrate includes a storage region and a peripheral region, and multiple shallow trench isolations are located within the substrate; Multiple memory node pads are disposed on the substrate and located within the memory area; The capacitor structure disposed on the pads of the storage node includes a plurality of bottom electrodes that are respectively in contact with the pads of the storage node; as well as A support structure is disposed on the pads of the storage node. The support structure is disposed between the bottom electrodes and physically contacts the bottom electrodes. The support structure includes a first support layer and a second support layer disposed sequentially from bottom to top. The second support layer has a first thickness and a second thickness, wherein the second thickness is greater than the first thickness. The second support layer with the first thickness is located in the storage area, and the second support layer with the second thickness is located between the storage area and the peripheral area. The top surface of the bottom electrode that contacts the second support layer having the second thickness is higher than the top surface of the bottom electrode that contacts the second support layer having the first thickness.

24. The semiconductor device according to claim 23, characterized in that, The highest top surface of the second support layer having the second thickness is higher than the top surface of the second support layer having the first thickness.

25. The semiconductor device according to claim 23, characterized in that, The bottom surface of the second support layer having the second thickness is coplanar with the bottom surface of the second support layer having the first thickness.

26. The semiconductor device according to claim 23, characterized in that, The capacitor structure further includes a capacitor dielectric layer and a top electrode layer stacked in sequence, and a second support layer having the second thickness physically contacts the capacitor dielectric layer and the bottom electrode.

27. The semiconductor device according to claim 23, characterized in that, The two opposite sidewalls of the second support layer having the second thickness are respectively close to / away from the storage area, and the sidewall close to the storage area is in physical contact with the bottom electrode.

28. The semiconductor device according to claim 23, characterized in that, The height of the second support layer with the second thickness relative to the top surface of the substrate is greater than the height of the second support layer with the first thickness relative to the top surface of the substrate.

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