Multilayer electronic components

Abstract

We provide highly reliable stacked electronic components. [Solution] The stacked electronic component 100 includes a capacitance forming section including a dielectric layer and internal electrodes alternately arranged in the dielectric layer in a first direction X, a main body 110 including a first and second surface facing each other in a first direction X, a third and fourth surface connected to the first and second surfaces and facing each other in a second direction Y, a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing each other in a third direction Z, external electrodes 131 and 132 arranged on the third and fourth surfaces respectively, and side margin sections 114 and 115 arranged on the fifth and sixth surfaces respectively. When the number of moles of Mn and Mg per 100 moles of Ti contained in the side margin section is S1 and S2, respectively, and the number of moles of Mn and Mg per 100 moles of Ti contained in the dielectric layer of the capacitance forming section is A1 and A2, respectively, the following conditions are met: 0.2 moles ≤ S1 - A1 ≤ 0.8 moles and S2 - A2 < 0.25 moles.

Description

[Technical Field]

[0001] This invention relates to a stacked electronic component. [Background technology]

[0002] Multi-layered ceramic capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors mounted on printed circuit boards of various electronic products such as liquid crystal displays (LCDs), plasma display panels (PDPs), computers, smartphones, and mobile phones, where they play the role of charging or discharging electricity. MLCCs are used as components in a wide range of electronic devices due to their advantages of being small, yet guaranteeing high capacitance, and being easy to mount.

[0003] To miniaturize and increase the capacitance of MLCCs, it is necessary to maximize the effective area of ​​the internal electrodes. Therefore, in order to maximize the widthwise area of ​​the internal electrodes, a method is applied in which a margin-forming sheet is separately attached to the widthwise cross-section of the laminated chip before firing.

[0004] The sintering behavior and microstructure of the side margin area are factors that significantly affect the reliability of MLCCs. Therefore, research on the optimal design of the components constituting the side margin formation sheet is necessary. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Korean Published Patent Gazette No. 10-2015-0135092 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] One of several objects of the present invention is to provide a laminated electronic component with excellent reliability.

[0007] However, the object of the present invention is not limited to the above content and can be more easily understood in the process of explaining specific embodiments of the present invention.

Means for Solving the Problems

[0008] The laminated electronic component according to an embodiment of the present invention includes a capacitance forming portion including a dielectric layer and internal electrodes alternately arranged with the dielectric layer in a first direction, a first surface and a second surface facing each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and facing each other in a second direction, a fifth surface and a sixth surface connected to the first surface, the second surface, the third surface and the fourth surface and facing each other in a third direction, external electrodes respectively arranged on the third surface and the fourth surface, and side margin portions respectively arranged on the fifth surface and the sixth surface. When the number of moles of Mn and Mg with respect to 100 moles of Ti contained in the side margin portions are S1 and S2 respectively, and the number of moles of Mn and Mg with respect to 100 moles of Ti contained in the dielectric layer of the capacitance forming portion are A1 and A2 respectively, 0.2 mol ≤ S1 - A1 ≤ 0.8 mol and S2 - A2 < 0.25 mol can be satisfied.

Advantages of the Invention

[0009] As one of various advantages of the present invention, a laminated electronic component with excellent reliability can be provided.

Brief Description of the Drawings

[0010] [Figure 1] It is a perspective view schematically showing a laminated electronic component according to an embodiment of the present invention. [Figure 2] It is a perspective view schematically showing the main body and the side margin portion of FIG. 1. [Figure 3] It is a perspective view schematically showing the main body of FIG. 1. [Figure 4] It is a cross-sectional view schematically showing a cut cross-section along the line I-I' of FIG. 1. [Figure 5] This is a schematic cross-sectional view showing a section along the line II-II' in Figure 1. [Figure 6] Figure 5 is a cross-sectional view excluding the internal electrodes, illustrating a schematic method for measuring the hardness of the side margin. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of the ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0012] Furthermore, in order to clearly illustrate the present invention in the drawings, parts unrelated to the explanation have been omitted, and the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation; therefore, the present invention is not necessarily limited to what is shown. Components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part "includes" a certain component, this does not exclude other components unless otherwise stated, but rather means that it may further include other components.

[0013] In the drawing, the first direction X can be defined as the thickness T direction, the second direction Y as the length L direction, and the third direction Z as the width W direction.

[0014] Multilayer electronic components Figure 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention; Figure 2 is a schematic perspective view of the main body and side margin portion of Figure 1; Figure 3 is a schematic perspective view of the main body of Figure 1; Figure 4 is a schematic cross-sectional view of a cross section along line I-I' of Figure 1; Figure 5 is a schematic cross-sectional view of a cross section along line II-II' of Figure 1; and Figure 6 is a cross-sectional view of Figure 5 excluding the internal electrodes, schematically illustrating a method for measuring the hardness of the side margin portion.

[0015] Hereinafter, with reference to Figures 1 to 6, a multilayer electronic component 100 according to one embodiment of the present invention will be described in detail. Furthermore, a multilayer ceramic capacitor will be described as an example of a multilayer electronic component, but the present invention is not limited thereto and can be applied to various multilayer electronic components, such as inductors, piezoelectric elements, varistors, or thermistors.

[0016] A stacked electronic component 100 according to one embodiment of the present invention may include a main body 110, external electrodes 131, 132, and side margin portions 114, 115.

[0017] There are no particular restrictions on the specific shape of the main body 110, but as shown in the figure, the main body 110 can be a hexahedron or a similar shape. Due to the shrinkage of the ceramic powder contained in the main body 110 during the firing process, or due to the polishing process on the corners of the main body 110, the main body 110 may not be a perfectly straight hexahedron, but may have a substantially hexahedron shape.

[0018] The main body 110 may have a first surface 1 and a second surface 2 facing each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and facing each other in a second direction, a fifth surface 5 and a sixth surface 6 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and facing each other in a third direction.

[0019] The main body 110 can include a capacitance forming portion Ac that is disposed inside the main body 110 and forms a capacitance including a dielectric layer 111 and internal electrodes 121 and 122 that are alternately arranged with the dielectric layer 111 in the first direction. The plurality of dielectric layers 111 forming the main body 110 are in a fired state, and the boundary between adjacent dielectric layers 111 can be integrated so as to be difficult to confirm without using a scanning electron microscope (SEM).

[0020] The dielectric layer 111 can include, for example, a perovskite compound represented by ABO3 as a main component. The perovskite compound represented by ABO3 is, for example, BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3 (0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3 (0 < x ≤ 0.5, 0 < y ≤ 0.5), and can include one or more of them.

[0021] The internal electrodes 121 and 122 can include, for example, a first internal electrode 121 and a second internal electrode 122 that are alternately arranged in the first direction with the dielectric layer 111 interposed therebetween. The first internal electrode 121 and the second internal electrode 122 can be electrically separated from each other by the dielectric layer 111 disposed therebetween.

[0022] The first internal electrode 121 can be exposed on the third surface 3, the fifth surface 5, and the sixth surface 6, and can be arranged separately from the fourth surface 4. The first internal electrode 121 can be connected to the first external electrode 131 on the third surface 3. The second internal electrode 122 can be exposed on the fourth surface 4, the fifth surface 5, and the sixth surface 6, and can be arranged separately from the third surface 3. The second internal electrode 122 can be connected to the second external electrode 132 on the fourth surface 4.

[0023] The conductive metal included in the internal electrodes 121 and 122 may be one or more of Ni, Cu, Pd, Ag, Au, Pt, Sn, W, Ti, and alloys thereof, and more preferably, it may contain Ni, but the present invention is not limited thereto.

[0024] The main body 110 can include cover portions 112 and 113 disposed on both surfaces facing the first direction of the capacitance forming portion Ac.

[0025] The side margin portions 114 and 115 may be respectively disposed on the fifth surface 5 and the sixth surface 6 of the main body 110. The multilayer electronic component 100 can include a first side margin portion 114 disposed on the fifth surface 5 and a second side margin portion 115 disposed on the sixth surface 6.

[0026] The cover portions 112 and 113 and the side margin portions 114 and 115 can include, for example, a perovskite-type compound represented by ABO3 as a main component. The perovskite-type compound represented by ABO3 is, for example, BaTiO3, (Ba 1-x Ca x )TiO3(0 < x < 1), Ba(Ti 1-y Ca y )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3(0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Tiy )One or more of O3(0 < x ≤ 0.5, 0 < y ≤ 0.5) can be included.

[0027] The external electrodes 131 and 132 may be respectively disposed on the third surface 3 and the fourth surface 4 of the main body 110. The multilayer electronic component 100 can include a first external electrode 131 disposed on the third surface 3 and a second external electrode 132 disposed on the fourth surface 4. The first external electrode 131 can be disposed on the third surface 3 and extend onto a part of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6, and the second external electrode 132 can be disposed on the fourth surface 4 and extend onto a part of the first surface 1, the second surface 2, the fifth surface 5, and the sixth surface 6.

[0028] The types and forms of the external electrodes 131 and 132 are not particularly limited and may have a multilayer structure. For example, the external electrodes 131 and 132 can include a base electrode layer 131a, 132a that contacts the internal electrodes 121, 122 and a plating layer 131b, 132b disposed on the base electrode layer 131a, 132a.

[0029] The base electrode layers 131a and 132a may be fired electrode layers containing metal and glass. The metal contained in the base electrode layers 131a and 132a can include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, and / or an alloy containing these. The glass contained in the base electrode layers 131a and 132a can include, for example, one or more oxides of Ba, Ca, Zn, Al, B, and Si.

[0030] The base electrode layers 131a and 132a may be composed only of fired electrode layers, but the present invention is not limited thereto. The base electrode layers 131a and 132a may include a fired electrode layer containing metal and glass and a resin electrode layer disposed on the fired electrode layer and containing metal particles and resin.

[0031] The metal particles contained in the resin electrode layer may include one or more spherical particles and flake-shaped particles. Here, spherical particles may include forms that are not perfectly spherical, for example, forms with a ratio of the length of the long axis to the short axis (long axis / short axis) of 1.45 or less. Flake-shaped particles mean particles that are flat and elongated, for example, with a ratio of the length of the long axis to the short axis (long axis / short axis) of 1.95 or more. The metal particles contained in the resin electrode layer may include, for example, Cu, Ni, Pd, Pt, Au, Ag, Pb, Sn and / or alloys containing these. The resin contained in the resin electrode layer may include, for example, one or more epoxy resin, acrylic resin, and ethylcellulose.

[0032] The plating layers 131b and 132b may include, for example, Ni, Sn, Pd, and / or alloys containing these, and may be formed in multiple layers. The plating layers 131b and 132b may be, for example, a Ni plating layer or a Sn plating layer, and may be in a form in which the Ni plating layer and the Sn plating layer are formed sequentially. The plating layers 131b and 132b may also include multiple Ni plating layers and / or multiple Sn plating layers.

[0033] The drawings illustrate a structure in which the stacked electronic component 100 has two external electrodes 131 and 132, but it is not limited to this, and the number and shape of the external electrodes 131 and 132 can be changed according to the form of the internal electrodes 121 and 122 or other purposes.

[0034] If the same dielectric composition as the dielectric layer 111 of the capacitance-forming portion Ac is applied to the side margin portions 114 and 115, it may become difficult to ensure the sinterability of the side margin portions 114 and 115. This is because the capacitance-forming portion Ac has internal electrodes 121 and 122 containing conductive metals, which have a lower sintering start temperature compared to the dielectric material.

[0035] Therefore, if the same dielectric composition as the dielectric layer 111 is applied to the side margin portions 114 and 115, the density of the side margin portions 114 and 115 may decrease. As a result, the reliability of the stacked electronic component 100 may deteriorate due to moisture penetration from the outside through the side margin portions 114 and 115.

[0036] Conventionally, in order to improve the density of the side margins 114 and 115, a certain amount of Mg was added to the side margins 114 and 115. However, since Mg leads to the formation of oxygen vacancy defects within the ABO3 perovskite compound, this may have a negative effect of degrading the reliability of the multilayer electronic component 100.

[0037] Similar to Mg, Mn can improve the density of the side margin regions 114 and 115 by lowering the densification start temperature of these regions. In particular, because Mn has multi-valence properties, it may have fewer negative effects from oxygen vacancy defects compared to Mg.

[0038] Therefore, in the stacked electronic component 100 according to one embodiment of the present invention, when S1 is the number of moles of Mn per 100 moles of Ti contained in the side margin portions 114 and 115, and A1 is the number of moles of Mn per 100 moles of Ti contained in the dielectric layer 111 of the capacitance forming portion Ac, the following conditions can be met: 0.2 moles ≤ S1 - A1 ≤ 0.8 moles. By satisfying the above range for S1 - A1 (hereinafter referred to as ΔMn), the density of the side margin portions 114 and 115 can be ensured, and the reliability of the stacked electronic component 100 can be effectively improved.

[0039] If ΔMn is less than 0.2 moles, the effect of improving the density of the side margins 114 and 115 may be slight. If ΔMn exceeds 0.8 moles, it may actually promote grain growth of dielectric crystal grains contained in the side margins 114 and 115, and the excess Mn may diffuse into the dielectric layer 111, potentially causing a negative effect of degrading the capacitance aging rate of the multilayer electronic component 100.

[0040] On the other hand, if the multilayer electronic component 100 satisfies 0.2 mol ≤ ΔMn ≤ 0.8, the Mg content in the side margin portions 114 and 115 must also be adjusted appropriately. If the Mg content in the side margin portions 114 and 115 increases excessively compared to the dielectric layer 111, it may induce excessive grain growth of dielectric crystal grains in the side margin portions 114 and 115, potentially reducing the density of the side margin portions 114 and 115. This could degrade the moisture resistance reliability of the multilayer electronic component 100.

[0041] Therefore, in the stacked electronic component 100 according to one embodiment of the present invention, when S2 is the number of moles of Mg per 100 moles of Ti contained in the side margin portions 114 and 115, and A2 is the number of moles of Mg per 100 moles of Ti contained in the dielectric layer 111 of the capacitance forming portion Ac, the following conditions can be met: S2 - A2 < 0.25 moles. When 0.2 moles ≤ ΔMn ≤ 0.8 moles are met, if S2 - A2 (hereinafter referred to as ΔMg) exceeds 0.25 moles, the density of the side margin portions 114 and 115 decreases, which may reduce the reliability of the stacked electronic component 100. The lower limit of ΔMg is not particularly limited and may be 0 or greater.

[0042] The above S1 is not particularly limited, but in one embodiment, it can satisfy 0.1 moles ≤ S1 ≤ 1.1 moles. That is, the Mn content in the side margin portions 114 and 115 may be 0.1 moles or more and 1.1 moles or less per 100 moles of Ti. When 0.1 moles ≤ S1 ≤ 1.1 moles is satisfied, the reliability improvement effect of the present invention may become even more pronounced.

[0043] The above S2 is not particularly limited, but for example, it can satisfy 0.45 moles ≤ S2 ≤ 1.25 moles. That is, the Mg content in the side margin portions 114 and 115 may be 0.45 moles or more and 1.25 moles or less per 100 moles of Ti. When 0.45 moles ≤ S2 ≤ 1.25 moles is satisfied, the reliability improvement effect of the present invention may become even more pronounced.

[0044] The values ​​S1 and S2 above may be measured, for example, at the central part Cm in the first and third directions of the side margin portion. The values ​​A1 and A2 above may be measured, for example, at the central part Ca in the first and third directions of the volume forming portion.

[0045] The above S1, S2, A1, and A2 can be measured from image data observed using, for example, SEM-EDS (Scanning Electron Microscope-Energy Dispersive X-ray Spectrometer), TEM-EDS (Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), STEM-EDS (Scanning Transmission Electron Microscope-Energy Dispersive X-ray Spectrometer), or FE-SEM-EDS (Field Emission-scanning Electron Microscope-Energy Dispersive X-ray Spectrometer).

[0046] More specifically, as shown in Figure 5, the multilayer electronic component 100 is polished up to the halfway point in the second direction, exposing the cross-sections of the multilayer electronic component 100 in the first and third directions. Then, the content (mol%) of Ti, Mn, and Mg is measured in the central part Cm of the first and third directions of the side margin using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x). This makes it possible to calculate the number of moles of Mn and Mg (S1 and S2) per 100 moles of Ti contained in the side margin parts 114 and 115. Alternatively, S1 and S2 can also be measured by calculating the number of moles of Mn and Mg per 100 moles of Ti at multiple points in the central part Cm of the first and third directions of the side margin, for example, five equally spaced points, and then averaging these values. In this case, the central portion Cm of the first and third directions of the side margin portion can mean, for example, a region of size 5 μm × 4 μm (third direction × first direction) based on the midpoint of the first and third directions of the side margin portions 114 and 115.

[0047] Similarly, the content (mol%) of Ti, Mn, and Mg in the central Ca portion of the first and third directions of the capacitance-forming section is measured using FE-SEM-EDS (acceleration voltage: 2kV, magnification: 50,000x). This allows the number of moles of Mn and Mg per 100 moles of Ti contained in the dielectric layer 111 of the capacitance-forming section Ac to be calculated (A1 and A2). Alternatively, A1 and A2 can be measured by calculating the number of moles of Mn and Mg per 100 moles of Ti at multiple points in the central Ca portion of the first and third directions of the capacitance-forming section, for example, five equally spaced points, and then averaging these values. In this case, the central Ca portion of the first and third directions of the capacitance-forming section can refer to, for example, a region of size 5μm × 4μm (third direction × first direction) with respect to the center of the first and third directions of the capacitance-forming section Ac. Furthermore, the five equally spaced points can be specified by one or more dielectric layers 111.

[0048] From the calculated S1, S2, A1, and A2, ΔMn(S1-A1) and ΔMg(S2-A2) can be measured.

[0049] In one embodiment, the average Vickers hardness of the side margin portions 114 and 115 may be 1100 HV or higher. This prevents the laminated electronic component 100 from cracking due to external impact. The Vickers hardness of the side margin portions 114 and 115 can be increased as the density of the side margin portions 114 and 115 improves. There is no particular upper limit to the average Vickers hardness of the side margin portions 114 and 115, but it may be, for example, 1160 HV.

[0050] Using a Vickers hardness tester, the hardness can be measured at five equally spaced points in the first side margin section 114 and at five equally spaced points in the second side margin section 115. The average value of the hardness at these 10 points can then be used as the average Vickers hardness of the side margin sections 114 and 115. As shown in Figure 6, the Vickers hardness (HV) can be expressed as (load × 9.8) / (d1 × d2) (where d1 and d2 are the diagonal lengths of the indentation).

[0051] In one embodiment, the side margin portions 114 and 115 in the cross-sections of the stacked electronic component 100 in the first and third directions may include at least one 20 μm × 10 μm region having 70 or fewer pores. Having at least one 20 μm × 10 μm region having 70 or fewer pores in the side margin portions 114 and 115 can be interpreted as the side margin portions 114 and 115 having a density of a certain level or higher.

[0052] The number of pores can be measured, for example, by analyzing the cross-sections in the first and third directions of the stacked electronic component 100, polished up to the halfway point in the second direction, using an image analysis program. Pores present in the side margins 114 and 115 can be easily distinguished by their color, brightness, etc.

[0053] The dielectric layer 111 and the side margin portions 114 and 115 can selectively contain other different subcomponents.

[0054] In one embodiment, the dielectric layer 111 and the side margin portions 114 and 115 may contain one or more of Dy, Tb, Y, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu (hereinafter referred to as the first minor component). The first minor component can play a role in improving the reliability of the multilayer electronic component 100. The total content of the first minor component contained in the side margin portions 114 and 115 may be, for example, 0.6 moles or more and 3.0 moles or less per 100 moles of Ti.

[0055] In one embodiment, the dielectric layer 111 and the side margin portions 114 and 115 may contain one or more of Si and Al (hereinafter referred to as the second minor component). The Si can suppress grain growth of dielectric crystal grains contained in the side margin portions 114 and 115, thereby improving the density of the side margin portions 114 and 115. The Al can contribute to low-temperature densification by becoming liquid during sintering, improve the high-temperature withstand voltage characteristics of the stacked electronic component 100, and act as an acceptor to reduce electron concentration.

[0056] The Si content in the side margin portions 114 and 115 may be, for example, 0.75 moles or more and 4.0 moles or less per 100 moles of Ti. The Al content in the side margin portions 114 and 115 may be, for example, more than 0 moles and 0.6 moles or less per 100 moles of Ti.

[0057] In one embodiment, the dielectric layer 111 and the side margin portions 114 and 115 may contain one or more of V, Cr, Fe, Ni, Co, and Zn (hereinafter referred to as the third minor component). The third minor component, together with Mn, corresponds to a valence-variable acceptor element. The third minor component can play a role in lowering the firing temperature and improving the high-temperature withstand voltage characteristics of the multilayer electronic component 100.

[0058] In order to appropriately control the microstructure of the side margin portions 114 and 115, the side margin portions 114 and 115 may further contain, for example, Dy, Si, Al, and V from the aforementioned minor components.

[0059] On the other hand, the cover portions 112 and 113 may contain Mn and Mg at levels similar to those of the dielectric layer 111 of the capacitance forming portion Ac. In one embodiment, when C1 is the number of moles of Mn per 100 moles of Ti contained in the cover portions 112 and 113, the condition 0.2 moles ≤ S1 - C1 ≤ 0.8 moles can be satisfied. In one embodiment, when C2 is the number of moles of Mg per 100 moles of Ti contained in the cover portions 112 and 113, the condition 0 moles ≤ S2 - C2 < 0.25 moles can be satisfied.

[0060] The size of the multilayer electronic component 100 is not particularly limited. However, in order to simultaneously achieve miniaturization and high capacitance, multilayer electronic components of size 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm) or smaller, which increase the number of layers by thinning the thickness of the dielectric layer and internal electrodes, are likely to have reduced reliability. Therefore, when the multilayer electronic component 100 according to one embodiment of the present invention is applied to an ultra-miniature multilayer electronic component having a size of 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm) or smaller, the reliability improvement effect may be more pronounced.

[0061] The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 are not particularly limited. However, generally, the thinner the dielectric layer and internal electrodes, the lower the reliability of the multilayer electronic component tends to be, and in particular, when the average thickness of the dielectric layer and internal electrodes is 1.0 μm or less, it may become difficult to ensure the reliability of the multilayer electronic component. Therefore, when the multilayer electronic component 100 according to one embodiment of the present invention is applied to an ultra-small multilayer electronic component in which the average thickness td of the dielectric layer 111 is 1.0 μm or less and / or the average thickness te of the internal electrodes 121 and 122 is 1.0 μm or less, the reliability improvement effect may be more pronounced.

[0062] The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 refer to the average thickness of the dielectric layer 111 and the internal electrodes 121 and 122 in the first direction, respectively. The average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be measured by scanning the cross-sections of the main body 110 in the first and third directions with a scanning electron microscope (SEM) at 10,000x magnification. More specifically, the average thickness td of the dielectric layer 111 can be measured by taking the average value after measuring the thickness at multiple points on one dielectric layer 111, for example, five points equally spaced in the third direction. Similarly, the average thickness te of one internal electrode 121 and 122 can be measured by taking the average value after measuring the thickness at multiple points on one internal electrode 121 and 122, for example, five points equally spaced in the third direction. The five equally spaced points can be specified in the capacitance forming section Ac. On the other hand, if such average values ​​are measured for 10 dielectric layers 111 and 10 internal electrodes 121 and 122, and then the average values ​​are measured, the average thickness td of the dielectric layer 111 and the average thickness te of the internal electrodes 121 and 122 can be further generalized.

[0063] The average thickness tc of the cover portions 112 and 113 is not particularly limited. The average thickness tc of the cover portions 112 and 113 may be, for example, 5 μm or more and 100 μm or less. For example, if the multilayer electronic component 100 has a size of 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm) or less, the average thickness tc of the cover portions 112 and 113 may be 5 μm or more and 35 μm or less. The average thickness tc of the cover portions 112 and 113 means the average thickness of the first cover portion 112 and the second cover portion 113, respectively. The average thickness tc of the cover portions 112 and 113 can mean the average thickness of the cover portions 112 and 113 in the first direction, and can be the average value of the thickness in the first direction measured at five equally spaced points in the cross-section of the main body 110 in the first and third directions.

[0064] The average thickness wm of the side margin portions 114 and 115 is not particularly limited. The average thickness wm of the side margin portions 114 and 115 may be, for example, 3 μm or more and 100 μm or less. For example, if the multilayer electronic component 100 has a size of 1005 (length: approximately 1.0 mm, width: approximately 0.5 mm) or less, the average thickness wm of the side margin portions 114 and 115 may be 3 μm or more and 25 μm or less. The average thickness wm of the side margin portions 114 and 115 refers to the average thickness of the first side margin portion 114 and the second side margin portion 115, respectively. The average thickness tm of the side margin portions 114 and 115 can refer to the average thickness of the side margin portions 114 and 115 in the third direction, and may be the average value of the thickness in the third direction measured at five equally spaced points in the cross-section of the main body 110 in the first and third directions.

[0065] The following describes an example of a method for forming a stacked electronic component 100. However, the manufacturing method of the stacked electronic component 100 is not limited to this.

[0066] First, prepare the ceramic powder for forming the dielectric layer 111. The ceramic powder may be, for example, BaTiO3, (Ba 1-x Ca x )TiO3(0 <x<1)、Ba(Ti 1-y Cay )O3(0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 < x < 1, 0 < y < 1), Ba(Ti 1-y Zr y )O3(0 < y < 1), CaZrO3, and (Ca 1-x Sr x )(Zr 1-y Ti y )O3(0 < x ≤ 0.5, 0 < y ≤ 0.5), and can contain one or more of them. BaTiO3 powder can be synthesized, for example, by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. As the method for synthesizing the ceramic powder, for example, there are a solid-phase method, a sol-gel method, a hydrothermal synthesis method, etc., but the present invention is not limited thereto. Next, after drying and pulverizing the prepared ceramic powder, an organic solvent such as ethanol and a binder such as polyvinyl butyral are mixed to produce a ceramic slurry, and the ceramic slurry is applied and dried on a carrier film to provide a sheet for forming a dielectric layer.

[0067] Next, an internal electrode conductive paste containing metal powder, binder, organic solvent, etc. is printed on the sheet for forming a dielectric layer with a predetermined thickness using a screen printing method or a gravure printing method, etc. to form an internal electrode pattern.

[0068] After that, after peeling the sheet for forming a dielectric layer on which the internal electrode pattern is printed from the carrier film, the sheets for forming a dielectric layer on which the internal electrode pattern is printed are laminated and pressure-bonded by a predetermined number of layers to form a ceramic laminate. On the upper and lower parts of the ceramic laminate, in order to form the cover parts 112 and 113 after firing, sheets for forming a cover part on which no internal electrode pattern is formed can be laminated by a predetermined number of layers. Then, the ceramic laminate is cut so as to have a predetermined chip size. At this time, the ends of the internal electrode pattern are exposed on both surfaces facing the third direction of the cut chip.

[0069] Next, the margin-forming sheet can be attached to both sides of the cut chip in the third direction, and then fired to form the main body 110 and the side margin portions 114 and 115. The firing temperature may be, for example, 1000°C or more and 1400°C or less, but the present invention is not limited thereto.

[0070] The margin-forming sheet can be formed in a similar manner to the dielectric layer-forming sheet, but the content of the minor components included in the margin-forming sheet may differ from that of the dielectric layer-forming sheet.

[0071] For example, both the margin-forming sheet and the dielectric layer-forming sheet may contain ABO3 perovskite powder as the main component, but the Mn content in the margin-forming sheet may be higher than the Mn content in the dielectric layer-forming sheet, and the Mg content in the margin-forming sheet may be higher than the Mg content in the dielectric layer-forming sheet.

[0072] In addition to Mn and Mg, the above margin-forming sheet may also contain one or more first minor component powders from Dy, Tb, Y, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu, one or more second minor component powders from Si and Al, and / or one or more third minor component powders from V, Cr, Fe, Ni, Co, and Zn.

[0073] The first to third auxiliary component powders described above may be added to the margin-forming sheet in the form of oxides and / or carbonates, but the present invention is not limited thereto.

[0074] Next, external electrodes 131 and 132 are formed. For example, if the base electrode layers 131a and 132a include a fired electrode layer, the main body 110 can be dipped in a conductive paste for external electrodes containing metal powder, glass frit, binder, and organic solvent, and then the conductive paste for external electrodes can be fired at a temperature of 500°C to 900°C to form a fired electrode layer.

[0075] For example, if the base electrode layers 131a and 132a include a resin electrode layer, the main body can be dipped in a conductive resin composition containing metal powder, resin, binder, and organic solvent, and then cured at a temperature of 250°C to 550°C to form the resin electrode layer.

[0076] Furthermore, electroplating and / or electroless plating can be used to further form plating layers 131b and 132b on the underlying electrode layers 131a and 132a.

[0077] (Example of experiment) Sample chips of size 0603 (length: approximately 0.6 mm, width: approximately 0.3 mm, thickness: approximately 0.3 mm) were prepared using the manufacturing method described above. Mn, Mg, Dy, Si, Al, and V were added to the sheet used to form the side margin of the sample chip. Meanwhile, the content of Mn and Mg added to the margin-forming sheet was adjusted for each sample number to produce different values ​​of ΔMn and ΔMg. ΔMn and ΔMg were measured by analyzing the cross-sections in the first and third directions of the sample chip, which had been polished to the halfway point in the second direction, via FE-SEM-EDS (acceleration voltage: 2 kV, magnification: 50,000 times). S1 and S2 were measured in the central part of the first and third directions of the side margin, and A1 and A2 were measured in the dielectric layer located in the central part of the first and third directions of the capacitance-forming section.

[0078] 1. Measuring the number of stomata The cross-sections in the first and third directions (hereinafter referred to as "analytical cross-sections") of each sample tip, polished to the halfway point in the second direction, were analyzed using an image analysis program to determine the number of pores present in the side margin area. The number of pores was measured in the 20 μm (T-direction dimension) × 10 μm (W-direction dimension) area of ​​the side margin area that is in contact with the volume-forming portion in the analytical cross-section.

[0079] 2. Measurement of the average size of dielectric crystal grains The above-mentioned cross-sectional views of each sample chip with a specific sample number were analyzed using an image analysis program, and the average size of dielectric crystal grains contained in the side margin was measured. The average size of dielectric crystal grains contained in the side margin was measured in the same region where the number of pores was analyzed.

[0080] 3. Measurement of aging rate Five sample chips for each sample number were heat-treated at approximately 150°C for approximately 1 hour. The volume values ​​were then measured after 0hr, 2hr, 4hr, 8hr, 12hr, 16hr, 20hr, 24hr, 30hr, 36hr, 50hr, 62hr, 74hr, 88hr, and 100hr. Subsequently, the x-axis was plotted as log(hr) and the y-axis as the average volume reduction rate (%) of the five chips. The slope of the graph was calculated as the aging rate.

[0081] 4. Evaluation of moisture resistance reliability After mounting 400 sample chips for each sample number onto printed circuit boards (PCBs), a voltage of 6.3V was applied for 8 hours under conditions of 85°C and 85%RH. If the IR (Insulation Resistance) value dropped by 2 orders of magnitude or more from the initial IR value, it was determined to be defective, and the number of defective chips was measured.

[0082] 5. Evaluation of MTTF For each sample number, 40 sample chips were subjected to accelerated lifetime evaluation (HALT) under conditions of 105°C and 15V until all sample chips failed. The Mean Time to Failure (MTTF) was then calculated.

[0083] 6. Measurement of hardness For each sample tip with a specific sample number, the Vickers hardness of the side margin was measured using a Vickers hardness tester (under the conditions of a load of 25 gf and a holding time of 5 seconds). After measuring the hardness at five equally spaced points in the first direction in the first side margin and five equally spaced points in the first direction in the second side margin, the average value of the hardness at a total of 10 points was calculated. After measuring the average value for five sample tips for each sample number, the average value was calculated as the average Vickers hardness and is shown in Table 1 below.

[0084] [Table 1]

[0085] Samples 2-4 and 6 satisfy all the conditions of 0.2 mol ≤ ΔMn ≤ 0.8 mol and ΔMg < 0.25 mol, confirming that they are excellent in terms of aging rate, moisture resistance reliability, MTTF, and hardness.

[0086] However, in sample number 1, a decrease in moisture resistance reliability, MTTF, and hardness was observed. This is presumably because ΔMn became smaller than 0.2 moles, resulting in insufficient densification of the side margin area.

[0087] Furthermore, while sample number 5 exhibited excellent moisture resistance reliability, MTTF, and hardness, a sharp decrease in aging rate was observed. This is presumably because the excess Mn, exceeding ΔMn of 0.8 moles, diffused into the dielectric layer, degrading the capacitance of the sample chip.

[0088] Samples 7 and 8 satisfy the condition 0.2 mol ≤ ΔMn ≤ 0.8 mol, but the density of the side margin decreases when ΔMg is greater than or equal to 0.25 mol, resulting in reduced moisture resistance, MTTF, and hardness of the sample tip.

[0089] This shows that when both 0.2 mol ≤ ΔMn ≤ 0.8 mol and ΔMg < 0.25 mol are satisfied, the reliability of the multilayer electronic component can be improved while maintaining its capacitance characteristics.

[0090] The present invention is not limited by the embodiments described above or the accompanying drawings, but is limited by the claims provided. Therefore, within the scope of the present invention, various forms of substitution, modification, and alteration are possible by persons with ordinary skill in the art, without departing from the technical idea of ​​the invention as described in the claims, and these also fall within the scope of the present invention.

[0091] Furthermore, the expression "one embodiment" does not mean that each embodiment is the same as another, but is provided to highlight and explain the unique and distinct characteristics of each embodiment. However, the above-presented embodiments do not preclude their realization in combination with the features of other embodiments. For example, even if a matter described in one embodiment is not described in another embodiment, it can be understood as a description related to the other embodiment, unless there is a description in the other embodiment that contradicts or is contrary to that matter.

[0092] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component. [Explanation of symbols]

[0093] 100: Stacked Electronic Components 110: Main unit 111: Dielectric layer 112, 113: Cover section 114, 115: Side margin section 121, 122: Internal electrode 131, 132: External electrode 131a, 132a: Base electrode layer 131b, 132b: Plating layer

Claims

1. A capacitance forming portion including a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction; a body including a first and second surface facing each other in the first direction, a third and fourth surface connected to the first and second surfaces and facing each other in a second direction, and a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing each other in a third direction; External electrodes arranged on the third and fourth surfaces, respectively, The fifth and sixth surfaces respectively include side margin portions, When the number of moles of Mn and Mg per 100 moles of Ti contained in the side margin portion is S1 and S2, respectively, and the number of moles of Mn and Mg per 100 moles of Ti contained in the dielectric layer of the capacitance forming portion is A1 and A2, respectively, A multilayer electronic component satisfying 0.2 moles ≤ S1 - A1 ≤ 0.8 moles and S2 - A2 < 0.25 moles.

2. The stacked electronic component according to claim 1, wherein S1 satisfies 0.1 moles ≤ S1 ≤ 1.1 moles.

3. The stacked electronic component according to claim 1, wherein S2 satisfies 0.45 moles ≤ S2 ≤ 1.25 moles.

4. The values ​​S1 and S2 above were measured at the central portion in the first and third directions of the side margin portion, The stacked electronic component according to claim 1, wherein A1 and A2 are measured at the central portion in the first and third directions of the capacitance forming portion.

5. The stacked electronic component according to claim 1, wherein the side margin portion further comprises one or more of Dy, Tb, Y, Sc, La, Nd, Eu, Gd, Ho, Er, Yb, and Lu.

6. The stacked electronic component according to claim 1, wherein the side margin portion further comprises one or more of Si and Al.

7. The stacked electronic component according to claim 1, wherein the side margin portion further comprises one or more of V, Cr, Fe, Ni, Co, and Zn.

8. The stacked electronic component according to claim 1, wherein the side margin portion further comprises Dy, Si, Al, and V.

9. The stacked electronic component according to claim 1, wherein the average Vickers hardness of the side margin portion is 1100 HV or more.

10. In the cross-sections of the stacked electronic component in the first and third directions, The stacked electronic component according to claim 1, wherein the side margin portion includes at least one 20 μm × 10 μm region having 70 or fewer pores.

11. The main body includes cover portions arranged on both sides of the volume forming portion facing the first direction, When C1 is the number of moles of Mn relative to 100 moles of Ti contained in the cover portion, A multilayer electronic component according to any one of claims 1 to 10, satisfying 0.2 moles ≤ S1 - C1 ≤ 0.8 moles.

12. The main body includes cover portions arranged on both sides of the volume forming portion facing the first direction, When C2 is the number of moles of Mg relative to 100 moles of Ti contained in the cover portion, A stacked electronic component according to any one of claims 1 to 10, satisfying S2-C2 < 0.25 moles.

13. The stacked electronic component according to any one of claims 1 to 10, wherein the average thickness of the dielectric layer is 1.0 μm or less.

14. The stacked electronic component according to any one of claims 1 to 10, wherein the average thickness of the internal electrodes is 1.0 μm or less.

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