Processor, sorting method and electronic device

Abstract

The present application provides a processor, a sorting method and an electronic device, which can reduce the number of instructions used in the sorting process to improve the sorting efficiency. The processor includes: an instruction storage circuit, a control circuit and a sorting circuit. The control circuit is configured to read a first instruction from the instruction storage circuit and send the decoded first instruction to the sorting circuit. The sorting circuit is configured to, in response to the decoded first instruction, read M first sequences according to the storage addresses, and if the M first sequences are all ordered sequences, output an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, output M ordered sequences with a length of N. In this way, the sorting circuit in the processor can sort multiple sequences in response to the decoded first instruction. In other words, the processor can sort multiple sequences by executing 1 first instruction, which can avoid executing a large number of repeated instructions, reduce the number and execution time of sorting instructions, and improve the sorting efficiency.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and in particular, to a processor, a sorting method, and an electronic device. Background Art

[0002] Sorting is an operation often performed in electronic devices such as computers, and can adjust an unordered sequence into an ordered sequence. Currently, various sorting algorithms can be implemented by a processor in an electronic device executing a computer program (such as a sorting program).

[0003] However, the above sorting program usually includes a large number of repeated instructions, such as arithmetic instructions, access instructions, control instructions, etc., resulting in the processor consuming a large amount of time and low sorting efficiency. Summary of the Invention

[0004] Embodiments of this application provide a processor, a sorting method, and an electronic device, which can reduce the number of instructions used in the sorting process to improve sorting efficiency.

[0005] To achieve the above object, this application adopts the following technical solutions:

[0006] In a first aspect, a processor is provided. The processor includes: an instruction storage circuit, a control circuit, and a sorting circuit. The instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the sorting circuit. The control circuit is configured to read a first instruction from the instruction storage circuit and decode the first instruction. Among them, the decoded first instruction includes storage addresses of M first sequences, the length of each first sequence is N, M is an integer greater than 1, and N is an integer greater than 1. The control circuit is further configured to send the decoded first instruction to the sorting circuit. The sorting circuit is configured to respond to the decoded first instruction and perform the following steps: read M first sequences according to the storage addresses, and if the M first sequences are all ordered sequences, output an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, output M ordered sequences with a length of N.

[0007] Based on the processor described in the first aspect, the sorting circuit in the processor can respond to the decoded first instruction to arrange M ordered sequences into an ordered sequence with a length of M*N, or arrange M sequences with unordered sequences into M ordered sequences with a length of N. In other words, the processor can sort multiple sequences by executing 1 first instruction, so that the processor can execute fewer instructions to complete the sorting operation of multiple sequences, avoiding executing a large number of repeated instructions, reducing the number and execution time of sorting instructions to be executed, and thus improving sorting efficiency.

[0008] In a possible design solution, the sorting circuit described in the first aspect may include: a sorting controller, a sorter, and M first buffers. The sorting controller is coupled to the M first buffers, and the M first buffers are all coupled to the sorter. The sorting controller is configured to read M first sequences according to the storage address and store the M first sequences in the M first buffers. Wherein, each first buffer stores one first sequence. The sorter is configured to, if the M first sequences are all ordered sequences, read out an ordered sequence with a length of M*N from the M first buffers, or, if there are unordered sequences among the M first sequences, read out M ordered sequences with a length of N from the M first buffers. Since the first buffer can be implemented by an internal buffer, such as a buffer, the reading and writing speed is faster than that of an external memory (such as global memory, etc.), and it can be used as the first-level cache between the external memory and the sorter to avoid the sorter reading data from the external memory, which can reduce the latency of the sorter reading data, thereby further improving the sorting efficiency.

[0009] Optionally (hereinafter simply referred to as Solution 1), the above-mentioned sorter is further configured to, if the M first sequences are all ordered sequences, read out an ordered sequence with a length of M*N from the M first buffers according to the first reading rule. Wherein, the first reading rule may be: read out the data arranged first in the M first buffers each time. In other words, during the process of reading data from the M first buffers, the sorter can arrange the M ordered sequences into an ordered sequence. In this way, the processor can sort the M ordered sequences by executing the first instruction once, thereby reducing the number and execution time of the sorting instructions that need to be executed and improving the sorting efficiency.

[0010] Alternatively, optionally (hereinafter simply referred to as Solution 2), the above-mentioned sorter is further configured to, if there are unordered sequences among the M first sequences, read out M ordered sequences with a length of N from the M first buffers according to the second reading rule. Wherein, the second reading rule may be: read out an ordered sequence with a length of N in the M first buffers each time. In other words, during the process of reading data from the M first buffers, the sorter can arrange the M sequences with unordered sequences into M ordered sequences. In this way, the processor can sort the M sequences with unordered sequences by executing the first instruction once, thereby reducing the number and execution time of the sorting instructions that need to be executed and improving the sorting efficiency.

[0011] Scheme 1 and Scheme 2 can be implemented independently or in combination. The combined implementation of Scheme 1 and Scheme 2 may include: first execute Scheme 2 to arrange M unordered sequences into M ordered sequences. Then execute Scheme 1 to arrange the M ordered sequences into one ordered sequence. In this way, the processor can arrange M sequences into 1 ordered sequence by executing the first instruction twice, so that the processor can execute fewer instructions to complete the sorting operation of multiple sequences, avoid executing a large number of repeated instructions, reduce the number and execution time of sorting instructions to be executed, and improve the sorting efficiency.

[0012] Optionally, the sorting circuit described in the first aspect may further include: a second buffer, and the second buffer is coupled to the sorting controller. The sorting controller is used to read M first sequences according to the storage address and store the M first sequences in the second buffer. The sorting controller is also used to move the M first sequences from the second buffer to the M first buffers. Since the second buffer can be implemented by a memory such as a unified buffer (UB), a cache memory, or a static memory, and its read and write speed is faster than that of an external memory (such as global memory), it can be used as a second-level cache between the external memory and the sorter, avoiding the first buffer from reading data from the external memory, further reducing the latency of the first buffer receiving data, and further reducing or even eliminating the latency of the sorter reading data from the first buffer, thereby further improving the sorting efficiency.

[0013] Furthermore, the above sorting controller may include: a first read / write controller and a second read / write controller. The first read / write controller is coupled to the second read / write controller. The second buffer is respectively coupled to the first read / write controller and the second read / write controller. The M first buffers are all coupled to the first read / write controller. The second read / write controller is used to read M first sequences according to the storage address and store the M first sequences in the second buffer. The first read / write controller is used to move the M first sequences from the second buffer to the M first buffers. In this way, the first read / write controller, the second read / write controller, and the second buffer can be combined to continuously receive the data to be sorted and continuously send the data to be sorted to the M first buffers, so that the sorter can continuously sort the data to be sorted, thereby further improving the sorting efficiency.

[0014] Still further, the above first read / write controller is further used to send the information of the amount of data that has been moved to the second read / write controller when moving the M first sequences. Since the information of the amount of data that has been moved is equivalent to the information of the free storage space size of the second buffer, the second read / write controller can move the data in the M first sequences that has not been moved to the second buffer to the second buffer as soon as possible according to the information of the amount of data that has been moved. In this way, the sorting efficiency can be further improved.

[0015] Further, the above sorting controller further includes a third read / write controller, which is coupled to the sorter and the second buffer respectively. The third read / write controller is configured to move the ordered sequence output by the sorter to the second buffer. Since the second buffer can be implemented by a memory such as a unified buffer, a cache memory, or a static memory, and its read / write speed is faster than that of the external memory, it can be used as a second-level cache between the external memory and the sorter. Sending the sorted data to the second buffer by the third read / write controller can avoid sending the sorted data to the external memory, thereby reducing the latency of the sorter outputting the sorted data and improving the sorting efficiency.

[0016] In a second aspect, a processor is provided. The processor includes: an instruction storage circuit, a control circuit, and a sorting circuit. The instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the sorting circuit. Among them, the sorting circuit includes: I sorters, and each sorter includes J input terminals and J output terminals. The J input terminals of the first sorter among the I sorters are the J input terminals of the sorting circuit, the J output terminals of the I-th sorter among the I sorters are the J output terminals of the sorting circuit, and the J output terminals of the i-th sorter among the I sorters are respectively connected to the J input terminals of the (i + 1)-th sorter, where i ≤ I, I is a positive integer, and J is a positive even number. The control circuit is configured to read a second instruction from the instruction storage circuit and decode the second instruction. The decoded second instruction includes the storage addresses of H data, where H ≤ J. The control circuit is further configured to send the decoded second instruction to the sorting circuit. The sorting circuit is configured to respond to the decoded second instruction and perform the following steps: read H data according to the storage addresses, and use the i-th sorter in the sorting circuit to sort the H data, and the order degree of the sorted H data is higher than that of the H data before sorting.

[0017] Based on the processor described in the second aspect, the sorting circuit in the processor can respond to the decoded second instruction and increase the order degree of the H data by I times. Therefore, by sorting the H data once or multiple times, the sorting circuit can arrange the H data into an ordered sequence. In other words, the processor can sort the H data by executing 1 second instruction, so that the processor can execute fewer instructions to complete the sorting operation of the H data, which can avoid executing a large number of repeated instructions, reduce the number and execution time of the sorting instructions to be executed, and thus improve the sorting efficiency.

[0018] In a possible design, the above-mentioned i-th sorter may include K comparators. Among them, K ≥ J / 2, and K can be a positive integer. The k-th comparator among the K comparators is configured to compare two of the H data. Figure 5Taking the sorting circuit shown (K = 4, J = 8) as an example, each sorter may include 4 comparators (A1 - A4). Each comparator may include two input terminals and two output terminals. Each input terminal of the comparator can be connected to a register, and each output terminal of the comparator can be connected to a register. The register can be used to temporarily store data. The 8 input terminals of the 4 comparators of the i-th sorter are the 8 input terminals of this sorter, and the 8 output terminals of the 4 comparators of the i-th sorter are the 8 output terminals of this sorter. Among them, the two output terminals of A1 of the first sorter can be respectively connected to one input terminal of A1 and one input terminal of A2 of the second comparison unit. The two output terminals of A2 of the first sorter can be respectively connected to one input terminal of A2 and one input terminal of A3 of the second comparison unit. The two output terminals of A3 of the first sorter can be respectively connected to one input terminal of A3 and one input terminal of A4 of the second comparison unit. The two output terminals of A4 of the first sorter can be respectively connected to one input terminal of A4 and one input terminal of A1 of the second comparison unit. And so on, the connection method between other adjacent two sorters can refer to the connection method between the first sorter and the second sorter.

[0019] When using Figure 5 the sorting circuit shown to sort 8 data (i.e., H = 8), assume that the sorting circuit sorts the data to be sorted in ascending order. First, the data to be sorted input to the first sorter is: "8, 7, 6, 5, 4, 3, 2, 1". The first sorter sorts this sequence, and the sorted sequence becomes: "7, 8, 5, 6, 3, 4, 1, 2". Then, the second sorter sorts the sequence output by the first sorter, and the sorted sequence becomes: "2, 5, 8, 3, 6, 1, 4, 7". And so on, the sequence output by the seventh sorter is: "1, 2, 3, 4, 5, 6, 7, 8". Based on Figure 5 the sorting circuit shown, the orderliness of the data to be sorted will be improved every time it passes through the K comparators of a sorter. In this way, an implementation method of the sorter can be provided, so that the sorter can improve the orderliness of H data.

[0020] Optionally, the K comparators may include J / 2 first comparators and (J / 2)-1 second comparators. The J - 2 output terminals of the J / 2 first comparators are respectively connected to the J - 2 input terminals of the (J / 2)-1 second comparators. The J input terminals of the J / 2 first comparators can be the J input terminals of the i-th sorter, and the other 2 output terminals of the J / 2 first comparators and the J - 2 output terminals of the (J / 2)-1 second comparators can be the J output terminals of the i-th sorter. Taking Figure 4Taking the sorting circuit shown (K = 7, J = 8) as an example, each sorter includes 7 comparators. The seven comparators in each sorter include: 4 first comparators (A1 - A4) and 3 second comparators (B1 - B3). Each comparator includes two input terminals and two output terminals. Among them, taking the 7 comparators in the 1st second comparator as an example, the 8 input terminals of A1 - A4 are the 8 input terminals of this sorter. The 6 output terminals of A1 - A4 are respectively connected to the 6 input terminals of B1 - B3. The other 2 output terminals of A1 - A4 and the 6 output terminals of B1 - B3 are the 8 output terminals of the 1st sorter. The two input terminals of each comparator can be respectively connected to a register, and the two output terminals of each comparator can be respectively connected to a register. This register can be used to temporarily store data.

[0021] When using Figure 4 the sorting circuit shown to sort 8 data (i.e., H = 8), assuming that this sorting circuit sorts the data to be sorted in ascending order. First, the data to be sorted input to this sorting circuit is: "8, 7, 6, 5, 4, 3, 2, 1". The 1st sorter sorts this sequence, and the sorted sequence becomes: "7, 5, 8, 3, 6, 1, 4, 2". Then, the 2nd sorter sorts the sequence output by the 1st sorter, and the sorted sequence becomes: "5, 3, 7, 1, 8, 2, 6, 4". And so on, the sequence output by the 4th sorter is: "1, 2, 3, 4, 5, 6, 7, 8". Based on Figure 4 the sorting process shown, it can be seen that for the data to be sorted, every time it passes through the K comparators of a sorter, the degree of orderliness will be improved. In this way, an implementation method of the sorter can be provided, enabling the sorter to improve the degree of orderliness of H data.

[0022] Optionally, the number of sorting times of I sorters for H data is greater than or equal to J / 2. For example, referring to the above Figure 4 sorting process again, the data to be sorted input to this sorting circuit: "8, 7, 6, 5, 4, 3, 2, 1", the degree of orderliness of this sequence is the lowest among the sequences with a length of 8. After being sorted by the Figure 4 sorting circuit shown, this sequence can just be arranged into an ordered sequence. In other words, when the number of sorting times of I sorters for H data is greater than or equal to J / 2, this sorting circuit can sort H data into an ordered sequence.

[0023] Further, the J input ends of the first sorter among the I sorters are respectively connected to the output ends of J selectors. The first input ends of the J selectors can be the J input ends of the sorting circuit described in the second aspect, and the J output ends of the I-th sorter among the I sorters are respectively connected to the second input ends of the J selectors. Since the data to be sorted can be output from the J output ends of the I-th sorter and then input again into the sorting circuit described in the second aspect through the second input ends of the J selectors, that is to say, the data to be sorted can be cyclically sorted in the sorting circuit described in the second aspect. Thus, under the condition that I is less than J / 2, by controlling the number of times the data to be sorted is cyclically sorted, the number of times the I sorters sort H data can be greater than or equal to J / 2, thereby reducing the hardware scale and saving costs.

[0024] Still further, I and J described above can satisfy the following relationship: I≥J / 2. In other words, the number of sorters is greater than or equal to J / 2, so that the number of times the I sorters sort H data can be greater than or equal to J / 2, thereby enabling the sorting circuit to sort H data into an ordered sequence.

[0025] In a third aspect, a sorting method is provided. It is applied to the processor described in the first aspect. The processor includes: an instruction storage circuit, a control circuit, and a sorting circuit. The instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the sorting circuit. The sorting method includes: the control circuit reads a first instruction from the instruction storage circuit and decodes the first instruction. Among them, the decoded first instruction includes the storage addresses of M first sequences, the length of each first sequence is N, M is an integer greater than 1, and N is an integer greater than 1. The control circuit sends the decoded first instruction to the sorting circuit. The sorting circuit responds to the decoded first instruction, reads M first sequences according to the storage addresses, and if the M first sequences are all ordered sequences, outputs an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, outputs M ordered sequences with a length of N.

[0026] In a possible design solution, the above sorting circuit may include: a sorting controller, a sorter, and M first buffers. The sorting controller is coupled to the M first buffers, and the M first buffers are all coupled to the sorter. The above sorting circuit responds to the decoded first instruction, reads M first sequences according to the storage address, and if all M first sequences are ordered sequences, outputs an ordered sequence with a length of M*N, or, if there are unordered sequences among the M first sequences, outputs M ordered sequences with a length of N, and may include: the sorting controller reads M first sequences according to the storage address and stores the M first sequences in the M first buffers. Wherein, each first buffer stores one first sequence. If all M first sequences are ordered sequences, the sorter reads out an ordered sequence with a length of M*N from the M first buffers, or, if there are unordered sequences among the M first sequences, the sorter reads out M ordered sequences with a length of N from the M first buffers.

[0027] Optionally, the above if all M first sequences are ordered sequences, the sorter reads out an ordered sequence with a length of M*N from the M first buffers, and may include: if all M first sequences are ordered sequences, the sorter reads out an ordered sequence with a length of M*N from the M first buffers according to the first reading rule. Wherein, the first reading rule may be: each time, read out the data arranged first in the M first buffers.

[0028] Or optionally, the above if there are unordered sequences among the M first sequences, the sorter reads out M ordered sequences with a length of N from the M first buffers, and may include: if there are unordered sequences among the M first sequences, the sorter reads out M ordered sequences with a length of N from the M first buffers according to the second reading rule. Wherein, the second reading rule may be: each time, read out an ordered sequence with a length of N in the M first buffers.

[0029] Optionally, the above sorting circuit may further include: a second buffer, and the second buffer is coupled to the sorting controller. The above sorting controller reads M first sequences according to the storage address and stores the M first sequences in the M first buffers, and may include: the sorting controller reads M first sequences according to the storage address and stores the M first sequences in the second buffer. The sorting controller moves the M first sequences from the second buffer to the M first buffers.

[0030] Further, the above sorting controller may include a first read / write controller and a second read / write controller. The first read / write controller is coupled to the second read / write controller. The second buffer is respectively coupled to the first read / write controller and the second read / write controller. The M first buffers are all coupled to the first read / write controller. The above sorting controller reads the M first sequences according to the storage address and stores the M first sequences in the second buffer, which may include: The second read / write controller reads the M first sequences according to the storage address and stores the M first sequences in the second buffer. The above sorting controller moves the M first sequences from the second buffer to the M first buffers, which may include: The first read / write controller moves the M first sequences from the second buffer to the M first buffers.

[0031] Still further, the method described in the above third aspect may further include: When moving the M first sequences, the first read / write controller sends the information of the amount of data that has been moved to the second read / write controller.

[0032] Further, the above sorting controller may further include a third read / write controller. The third read / write controller is respectively coupled to the sorter and the second buffer. The method described in the above third aspect may further include: The third read / write controller moves the ordered sequence output by the sorter to the second buffer.

[0033] In addition, the technical effects of the sorting method described in the third aspect may refer to the technical effects of the processor described in the first aspect, which will not be elaborated here.

[0034] Fourth aspect, a sorting method is provided. It is applied to the processor described in the second aspect. The processor includes: an instruction storage circuit, a control circuit, and a sorting circuit. The instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the sorting circuit. The sorting circuit includes: I sorters, each sorter includes J input terminals and J output terminals. The J input terminals of the first sorter among the I sorters are the J input terminals of the sorting circuit. The J output terminals of the I-th sorter among the I sorters are the J output terminals of the sorting circuit. The J output terminals of the i-th sorter among the I sorters are respectively connected to the J input terminals of the (i + 1)-th sorter, i ≤ I, I is a positive integer, and J is a positive even number. The sorting method includes: The control circuit reads a second instruction from the instruction storage circuit and decodes the second instruction. Among them, the decoded second instruction includes the storage addresses of H data, H ≤ J. The control circuit sends the decoded second instruction to the sorting circuit. The sorting circuit responds to the decoded second instruction and reads H data according to the storage address. The sorting circuit uses the i-th sorter in the sorting circuit to sort the H data, and the order degree of the sorted H data is higher than that of the H data before sorting.

[0035] In a possible design solution, the above-mentioned \(i\)-th sorter may include \(K\) comparators, where \(K\geq J / 2\) and \(K\) can be a positive integer. The above sorting circuit sorts \(H\) data by using the \(i\)-th sorter in the sorting circuit, which may include: the \(k\)-th comparator among the \(K\) comparators compares two of the \(H\) data.

[0036] Optionally, the above-mentioned \(K\) comparators may include \(J / 2\) first comparators and \((J / 2)-1\) second comparators. The \(J - 2\) output terminals of the \(J / 2\) first comparators are respectively connected to the \(J - 2\) input terminals of the \((J / 2)-1\) second comparators. The \(J\) input terminals of the \(J / 2\) first comparators may be the \(J\) input terminals of the \(i\)-th sorter. The other 2 output terminals of the \(J / 2\) first comparators and the \(J - 2\) output terminals of the \((J / 2)-1\) second comparators may be the \(J\) output terminals of the \(i\)-th sorter.

[0037] Optionally, the number of times the \(I\) sorters sort the \(H\) data is greater than or equal to \(J / 2\).

[0038] Furthermore, the \(J\) input terminals of the first sorter among the above-mentioned \(I\) sorters are respectively connected to the output terminals of \(J\) selectors. The first input terminals of the \(J\) selectors may be the \(J\) input terminals of the sorting circuit. The \(J\) output terminals of the \(I\)-th sorter among the \(I\) sorters are respectively connected to the second input terminals of the \(J\) selectors.

[0039] Still further, \(I\) and \(J\) may satisfy the following relationship: \(I\geq J / 2\).

[0040] In addition, the technical effects of the sorting method described in the fourth aspect can refer to the technical effects of the processor described in the second aspect, which will not be elaborated here.

[0041] In a fifth aspect, a sorting method is provided. It is applied to a processor, which includes: an instruction storage circuit, a control circuit, and multiple sorting circuits. The instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the multiple sorting circuits. The sorting method includes: the control circuit reads a second instruction from the instruction storage circuit and decodes the second instruction; the decoded second instruction includes the storage address of the data to be sorted. The control circuit sends the decoded second instruction to the multiple sorting circuits. The multiple sorting circuits respond to the decoded second instruction and read the data to be sorted according to the storage address. The multiple sorting circuits sort the data to be sorted. Among them, the data to be sorted includes multiple sequences. The sorting circuit is used to read \(M\) sequences among the multiple sequences, and if all \(M\) sequences are ordered sequences, then output an ordered sequence with a length of \(M*N\), or if there are unordered sequences among the \(M\) sequences, then output \(M\) ordered sequences with a length of \(N\).

[0042] Based on the sorting method described in the fifth aspect, multiple sorting circuits can be used to sort the data to be sorted. In this way, when the amount of data to be sorted is too large (e.g., more than 1 million data), this sorting method can enable multiple sorting circuits to perform sorting simultaneously, improving the sorting efficiency.

[0043] Among them, the above sorting circuit can be the sorting circuit in the processor described in the first aspect.

[0044] In a possible design, the above multiple sorting circuits sorting the data to be sorted may include: the multiple sorting circuits iteratively sort the data to be sorted until the data to be sorted is arranged into 1 ordered sequence. In each iteration, the multiple sorting circuits are used to arrange the N ordered sequences output in the previous iteration into ordered sequences, where M is an integer greater than 1.

[0045] Optionally, the above multiple sorting circuits iteratively sort the data to be sorted until the data to be sorted is arranged into 1 ordered sequence, which may include: each sorting circuit arranges part of the data to be sorted into 1 ordered sequence. Based on sorting circuits among the multiple sorting circuits, E ordered sequences are arranged into ordered sequences. If then is determined as E, and the step of arranging E ordered sequences into ordered sequences based on sorting circuits among the multiple sorting circuits is returned for execution; otherwise, the ordered sequence corresponding to the data to be sorted is output. In this way, during the sorting process of the data to be sorted, the number of sorting circuits participating in the sorting can be gradually reduced, reducing the occupied processing resources.

[0046] In a sixth aspect, an electronic device is provided. The electronic device includes the processor described in any possible implementation manner of the first aspect, and / or, the processor described in any possible implementation manner of the second aspect.

[0047] In addition, the technical effects of the processor described in the sixth aspect can refer to the technical effects of the processor described in any implementation manner of the first aspect and the second aspect, which will not be elaborated here.

[0048] In a seventh aspect, a computer-readable storage medium is provided, including: a computer program or instruction; when the computer program or instruction runs on a computer, the computer is enabled to execute the sorting method described in any possible implementation manner of the third aspect - the fifth aspect.

[0049] In addition, the technical effects of the computer-readable storage medium described in the seventh aspect can refer to the technical effects of the sorting method described in any one of the implementation manners in the third aspect to the fifth aspect, which will not be elaborated herein.

[0050] In an eighth aspect, there is provided a computer program product including a computer program or instructions. When the computer program or instructions are run on a computer, the computer is caused to execute the sorting method described in any one of the possible implementation manners in the third aspect to the fifth aspect.

[0051] In addition, the technical effects of the computer program product described in the eighth aspect can refer to the technical effects of the sorting method described in any one of the implementation manners in the third aspect to the fifth aspect, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 FIG. is a schematic structural diagram of a processor provided by an embodiment of the present application;

[0053] Figure 2 FIG. is a schematic structural diagram of a sorting circuit provided by an embodiment of the present application;

[0054] Figure 3 FIG. is a schematic diagram of data transceiver of a first buffer provided by an embodiment of the present application;

[0055] Figure 4 is for using Figure 2 The shown sorting circuit to sort M sequences;

[0056] Figure 5 FIG. is a schematic structural diagram of another processor provided by an embodiment of the present application;

[0057] Figure 6 FIG. is a schematic structural diagram of another sorting circuit provided by an embodiment of the present application Figure 1 ;

[0058] Figure 7 FIG. is a schematic structural diagram of another sorting circuit provided by an embodiment of the present application Figure 2 ;

[0059] Figure 8 FIG. is a schematic structural diagram of another sorting circuit provided by an embodiment of the present application Figure 3 ;

[0060] Figure 9 FIG. is a schematic structural diagram of another sorting circuit provided by an embodiment of the present application Figure 4 ;

[0061] Figure 10 is for using Figure 6 The shown sorting circuit to sort H data;

[0062] Figure 11 Schematic diagram of the structure of the electronic device provided by the embodiment of the present application;

[0063] Figure 12 Flow chart of the sorting method provided by the embodiment of the present application Figure 1 ;

[0064] Figure 13 Flow chart of the sorting method provided by the embodiment of the present application Figure 2 ;

[0065] Figure 14 Flow chart of the sorting method provided by the embodiment of the present application Figure 3 ;

[0066] Figure 15 Flow chart of the sorting method provided by the embodiment of the present application Figure 4 ;

[0067] Reference numerals: 100 - processor; 110 - instruction storage circuit; 120 - control circuit; 130 - sorting circuit; 210 - sorter; 220 - first buffer; 230 - sorting controller; 231 - first read / write controller; 232 - second read / write controller; 233 - third read / write controller; 240 - second buffer; 250 - output buffer; 500 - processor; 510 - instruction storage circuit; 520 - control circuit; 530 - sorting circuit; 531 - sorter. Detailed implementation manners

[0068] First, the embodiment of the present application briefly introduces the technical terms that may be involved.

[0069] Sequence: It refers to multiple data arranged in a column. The length of a sequence is equal to the number of data included in the sequence. For example, assuming a sequence is: "7, 3, 6, 5, 10, 15", then the length of this sequence is 6. Among them, the sequence includes an ordered sequence and an unordered sequence.

[0070] Ordered sequence: It refers to that the data in a sequence are arranged according to the sorting rule. Assuming the sorting rule of the data is arranged from small to large, then the sequence: "3, 5, 6, 7, 10, 15" can be called an ordered sequence. Among them, the sorting rule can include: arranged from small to large or from large to small.

[0071] Unordered sequence: It refers to that the data in a sequence are not arranged according to the sorting rule. Assuming the sorting rule of the data is arranged from small to large, then the sequence: "7, 3, 6, 5, 10, 15" can be called an unordered sequence.

[0072] Degree of order of a sequence: It refers to the degree of order of a sequence. The degree of order of a sequence can be represented by the number of inversions in the sequence. Among them, the number of inversions in a sequence is negatively correlated with the degree of order of the sequence.

[0073] TOPK sorting: It refers to finding the largest K data in a sequence or finding the smallest K data in a sequence.

[0074] Exemplarily, assuming that the sorting rule of data is from small to large, then for the sequence: "7, 3, 6, 5, 10, 15", the number of inversions in this sequence is 4, which are: (7, 3), (7, 6), (7, 5), (6, 5). For the sequence: "3, 7, 6, 5, 10, 15", the number of inversions in this sequence is 3, which are: (7, 6), (7, 5), (6, 5). Obviously, the degree of order of the former is lower than that of the latter.

[0075] Microarchitecture: It is the internal design of a processor that implements an instruction set.

[0076] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0077] Hereinafter, terms such as "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features.

[0078] It should be noted that in the present application, words such as "exemplarily" or "for example" are used to give examples, illustrations or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplarily" or "for example" aims to present relevant concepts in a specific manner.

[0079] In the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may refer to a direct physical connection, or may refer to an electrical connection through an intermediate medium, such as a connection achieved through a resistor, an inductor, a capacitor, or other electronic devices.

[0080] The embodiments of the present application provide a processor 100. Figure 1 It is a schematic structural diagram of a processor 100 provided by the embodiments of the present application. Please refer to Figure 1, the processor 100 includes: an instruction storage circuit 110, a control circuit 120, and a sorting circuit 130. The instruction storage circuit 110 is coupled to the control circuit 120, and the control circuit 120 is coupled to the sorting circuit 130.

[0081] The above-mentioned processor 100 may be a central processing unit (CPU), and the processor 100 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, such as a vector processor, a coprocessor, an ARM (advanced RISC machines) processor, etc. The embodiments of the present application do not limit this.

[0082] Among them, the instruction storage circuit 110 can store multiple instructions. The instruction storage circuit 110 can be implemented by an instruction cache or an instruction register and can be included in the memory subsystem of the processor 100. The control circuit 120 can preprocess the instructions, including operations such as instruction fetching and decoding. The control circuit 120 can be a control unit in the processor 100, and this control unit can also be called the front end. The sorting circuit 130 can be implemented by a microarchitecture. The sorting circuit 130 can be included in the execution engine of the processor 100, and this execution engine can also be called an arithmetic unit.

[0083] In the embodiments of the present application, the control circuit 120 is configured to read a first instruction from the instruction storage circuit 110 and decode the first instruction. Among them, the decoded first instruction includes storage addresses of M first sequences, the length of each first sequence is N, M is an integer greater than 1, and N is an integer greater than 1. The control circuit 120 is further configured to send the decoded first instruction to the sorting circuit 130. The sorting circuit 130 is configured to respond to the decoded first instruction and perform the following steps: read M first sequences according to the storage addresses, and if the M first sequences are all ordered sequences, output an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, output M ordered sequences with a length of N.

[0084] In a possible design solution, please refer to Figure 2 , Figure 2 FIG. 216 is a schematic structural diagram of a sorting circuit 130 provided by an embodiment of the present application. The sorting circuit 130 may include: a sorter 210, a sorting controller 230, and M first buffers 220 ( Figure 2 taking M = 4 as an example in FIG. 217). Among them, the sorting controller 230 is coupled to the M first buffers 220, and the M first buffers 220 are all coupled to the sorter 210.

[0085] The first buffer 220 may be implemented by a register or a register-related circuit component, and may be used to store sequences. Specifically, the first buffer 220 may be implemented by a built-in buffer (such as a buffer). For example, the first buffer 220 may be an input buffer (IB). The sorter 210 may be implemented by a comparator or a comparator-related circuit component, and may be used to sort multiple data and output an ordered sequence.

[0086] The sorter 210, the sorting controller 230, and the M first buffers 220 together can implement the data sorting function. The following introduces the specific implementation process.

[0087] The sorting controller 230 is configured to read M first sequences according to the storage address and send one first sequence to each of the first buffers 220. Among them, the sorting controller 230 may receive M first sequences from other units, devices, or equipment. Exemplarily, assuming that the M first sequences are stored in a global memory (GM), then the sorting controller 230 may respond to the decoded first instruction, send a read instruction to the global memory according to the storage address and through the bus, and the read instruction is used to instruct the global memory to send the M first sequences to the sorting controller 230. Then, the sorting controller 230 may receive the M first sequences from the global memory and send one first sequence to each of the first buffers 220. Of course, the sorting controller 230 may also receive the M first sequences from the global memory without sending a read instruction to the global memory.

[0088] Each of the first buffers 220 is configured to receive one first sequence, so that the M first buffers 220 can receive and store the M first sequences. These M first sequences may also be referred to as data to be sorted.

[0089] Among them, these M first sequences can all be ordered sequences, or there can be unordered sequences. If the M first sequences can all be ordered sequences, the sorter 210 can arrange the M ordered sequences into one ordered sequence through the following method 1. If there are unordered sequences among the M first sequences, the sorter 210 can arrange the M sequences with unordered sequences into M ordered sequences through the following method 2.

[0090] Method 1: The sorter 210 is used to read out an ordered sequence with a length of M*N from the M first buffers 220. Specifically, the sorter 210 is used to, if the M first sequences are all ordered sequences, read out an ordered sequence with a length of M*N from the M first buffers 220 according to the first reading rule. That is to say, the above sorting circuit 130 can realize the function of arranging M ordered sequences into one ordered sequence.

[0091] Among them, the first reading rule can be: each time read out the data ranked first in the M first buffers 220. That is to say, each time read out the data ranked first in the M ordered sequences. For example, assume there are two ordered sequences, which are: "3, 5, 6, 9" and "7, 13, 25, 26", and the sorting rule of the ordered sequences is arranged from small to large. Then the data ranked first in these two ordered sequences is 3. Optionally, when the first buffer 220 is implemented by an input buffer, the sorter 210 can read out a data ranked first at the output end of the M first buffers 220 each time.

[0092] Exemplarily, assume the sorting rule of the ordered sequences is arranged from small to large, N = 4, M = 4, and the 4 first buffers 220 are respectively: IB0, IB1, IB2, IB3. Table 1 is the situation table of the first sequences received by these 4 first buffers 220. Among them, the first sequence received by IB0 is: "3, 5, 6, 9", the first sequence received by IB1 is: "7, 13, 25, 26", the first sequence received by IB2 is: "2, 8, 9, 15", and the first sequence received by IB3 is: "33, 36, 50, 72".

[0093] Table 1

[0094]

[0095] Referring to Table 1, the sorter 210 can first read out the data ranked first among these 4 first sequences, that is, the data 2 in IB2. After reading out this data, the data 2 is no longer stored in IB2, so the first data in the first sequence in IB2 becomes 13. Then, the sorter 210 can read out the data ranked first again among these 4 first sequences, that is, the data 3 in IB0. And so on. The sorter 210 can read out the data in these 4 first buffers 220 multiple times according to the first reading rule, and the read data can be arranged in an ordered sequence with a length of 4*4 in the reading order, including: "2, 3, 5, 6, 7, 8, 9, 9, 13, 15, 25, 26, 33, 36, 50, 72".

[0096] It should be understood that based on the above Method 1, the processor can sort the M ordered sequences by executing the first instruction once, thereby reducing the number of sorting instructions to be executed and the execution time, and improving the sorting efficiency.

[0097] Among them, when the above sorting circuit 130 arranges the M ordered sequences into an ordered sequence, TOPK sorting can also be performed. For example, referring to Table 1 again, assuming to find the smallest 3 data in a sequence (i.e., perform TOP3 sorting), then during the process of the sorter 210 reading out the data in these 4 first buffers 220 multiple times, when the third data (5) is read, the smallest 3 data (2, 3, 5) in a sequence can be found. At this time, the sorting circuit 130 can stop sorting and abandon sorting the data after the 3rd one, so as to further reduce the calculation amount, save the sorting time, and thus improve the sorting efficiency.

[0098] In addition, if the above sorting circuit 130 needs to arrange more than M ordered sequences into an ordered sequence, it can be achieved through multiple rounds of sorting. For example, assuming M = 4 and 10 ordered sequences need to be arranged into an ordered sequence, then first these 10 ordered sequences can be divided into 3 groups. The first group includes 4 ordered sequences, the second group includes 4 ordered sequences, and the third group includes 2 ordered sequences. Then the sorting circuit 130 can respectively arrange the ordered sequences in each group into an ordered sequence and output 3 ordered sequences. Finally, the sorting circuit 130 arranges these 3 ordered sequences into an ordered sequence, thereby achieving the purpose of arranging more than M ordered sequences into an ordered sequence.

[0099] Mode 2, a sorter 210, which is configured to read out M ordered sequences of length N from M first buffers 220 if there are unordered sequences among the M first sequences. Specifically, the sorter 210 is configured to read out M ordered sequences of length N from M first buffers 220 according to a second reading rule if there are unordered sequences among the M first sequences. That is to say, the above sorting circuit 130 can implement the function of arranging M sequences with unordered sequences into M ordered sequences.

[0100] Among them, the second reading rule can be: read out an ordered sequence of length N from the M first buffers 220 each time. Specifically, the sorter 210 can read out x data from each first buffer 220 each time, and then arrange these M * x data into an ordered sequence, where x is a positive integer. For example, assume x = 1 and M = 4. The first sequences stored in the 4 first buffers 220 are: "10, 8, 20, 3", "1, 25, 33, 7", "6, 4, 16, 23", "11, 15, 16, 18". Then the sorter 210 can read out 1 data from each of these 4 first buffers 220 for the first time, that is, read out "10, 1, 6, 11", and then arrange these 4 data into an ordered sequence: "1, 6, 10, 11". Optionally, when the first buffer 220 is implemented by an input buffer, the sorter 210 can read out x data from the output end of each first buffer 220 each time. It can be understood that since x can take an integer greater than or equal to 1, when the value of x becomes larger, the sorter 210 can read out more data for sorting from the M first buffers 220 at one time, thereby improving the sorting efficiency.

[0101] Exemplarily, assume that the sorting rule of the ordered sequence is arranged from small to large, N = 4, M = 4, and the 4 first buffers 220 are: IB0, IB1, IB2, IB3. Table 2 is a table showing the situations of the first sequences received by these 4 first buffers 220. Among them, the first sequence received by IB0 is: "9, 6, 20, 3", the first sequence received by IB1 is: "6, 25, 33, 7", the first sequence received by IB2 is: "1, 9, 8, 2", and the first sequence received by IB3 is: "2, 50, 36, 33".

[0102] Table 2

[0103]

[0104] Referring to Table 2, the sorter 210 can first read the leading data of these 4 first sequences, namely 9, 6, 1, 2, and sort the leading data of these 4 first sequences, that is, sort 9, 6, 1, 2, to obtain an ordered sequence: "1, 2, 6, 9". Among them, after reading the leading data of these 4 first sequences, the leading data of these 4 first sequences become 6, 25, 9, 50. Then, the sorter 210 can read the leading data of these 4 first sequences (i.e., 6, 25, 9, 50) again, and sort the leading data of these 4 first sequences according to the sorting rule, to obtain an ordered sequence: "6, 9, 25, 50". And so on, the sorter 210 can read the data in these 4 first buffers 220 multiple times according to the second reading rule, and the read data are 4 ordered sequences with a length of 4, including: "1, 2, 6, 9", "6, 9, 25, 50", "8, 20, 33, 36", and "2, 3, 7, 33".

[0105] It should be understood that based on the above Method 2, the processor can sort M sequences with unordered sequences by executing the first instruction once, thereby reducing the number and execution time of sorting instructions that need to be executed, and improving the sorting efficiency.

[0106] The above Method 1 and Method 2 can be implemented independently or in combination. When Method 1 and Method 2 are implemented in combination, it may include: first execute Method 2 to arrange M unordered sequences into M ordered sequences. Then execute Method 1 to arrange the M ordered sequences into one ordered sequence. In other words, the sorting circuit 130 can implement arranging M sequences into one ordered sequence, that is, sorting a large amount of unordered data. For example, assume that there are 10,000 unordered data that need to be sorted, then these 10,000 data can be divided into 4 sequences with a length of 2,500, and then input to Figure 2 the shown sorting circuit 130, and the sorting circuit 130 sorts these 4 sequences with a length of 2,500 to obtain 4 ordered sequences with a length of 2,500, and then input these 4 ordered sequences with a length of 2,500 to Figure 2 the shown sorting circuit 130 to obtain an ordered sequence with a length of 10,000. In this way, the processor can arrange M sequences into 1 ordered sequence by executing the first instruction twice, so that the processor can execute fewer instructions to complete the sorting operation of multiple sequences, and can avoid executing a large number of repeated instructions, so as to reduce the number and execution time of sorting instructions that need to be executed, and improve the sorting efficiency.

[0107] Since Figure 2The first buffer 220 in the sorting circuit 130 shown can be implemented using a built-in buffer, which has a faster read and write speed than an external memory (such as global memory, etc.), and can be used as the first-level buffer between the external memory and the sorter 210 to prevent the sorter 210 from reading data from the external memory, thereby reducing the latency of the sorter 210 reading data and further improving the sorting efficiency. Additionally, since the sorting controller 230 can control the input of the data to be sorted, it can control the data sorting process of the sorter 210 to implement the function of controlling data sorting. For example, the sorting controller 230 can control the rate of receiving data and the rate of sending data to the M first buffers 220, thereby controlling the rate of the sorter 210 outputting an ordered sequence to control the sorting speed of the sorting circuit.

[0108] When the first buffer 220 is implemented using an input buffer, the first buffer 220 can store the sequence in the form of a queue. Among them, when the sorter 210 reads data from the first buffer 220, it can read data from the head of the queue (i.e., the output end of the first buffer 220). When the first buffer 220 receives the first sequence from the sorting controller 230, it can write data at the tail of the queue (i.e., the input end of the first buffer 220).

[0109] Exemplarily, Figure 3 is a schematic diagram of the first buffer 220 for receiving and transmitting data provided by an embodiment of the present application. As Figure 3 shown, assume that a first buffer 220 can store at most 10 data, the length of the first sequence received by the first buffer 220 is 20, and the first buffer 220 has already received 10 data in the first sequence, including: 4, 6, 7, 14, 16, 22, 23, 51, 71, 89. Then, when the sorter 210 reads the data 4 at the head of the queue from the first buffer 220, the order of the remaining data in the first buffer 220 will shift 1 bit towards the head of the queue in sequence. That is to say, the remaining data 6 becomes the new head data of the queue, and the remaining data 89 is the tail data of the queue. Since there are still 10 data in the first sequence that have not been received by the first buffer 220, the first buffer 220 can still receive data in a first sequence. Assume that the data received by the first buffer 220 is 90. Then, 90 becomes the new tail data of the queue. And so on. As the sorter 210 reads data from the first buffer 220, the first buffer 220 can receive all the data in the first sequence in turn. In this way, even if the length of the first buffer 220 is less than the length of the first sequence, the first buffer 220 can still implement the function of receiving sequences of any length.

[0110] Optionally, in order to further reduce the latency of the first buffer 220 receiving data, Figure 2 the sorting circuit 130 shown may further include a second buffer 240 (Figure 2 (shown by the dashed box), the second buffer 240 is coupled to the sorting controller 230. Among them, the second buffer 240 can be implemented by a memory such as a unified buffer (UB), a cache, or a static random access memory (SRAM).

[0111] The second buffer 240 can implement the function of temporarily storing data. The specific implementation process is introduced below.

[0112] The sorting controller 230 can be used to read M first sequences according to the storage address and store the M first sequences in the second buffer 240. The sorting controller 230 can also be used to move the M first sequences from the second buffer 240 to the M first buffers 220.

[0113] Exemplarily, assuming that the M first sequences are stored in the global memory, then the sorting controller 230 can send a first read instruction to the global memory according to the storage address and through the bus. The first read instruction is used to instruct the global memory to send the M first sequences to the second buffer 240. Then, the second buffer 240 can receive the M first sequences from the global memory and send the M first sequences to the sorting controller 230. After that, the sorting controller 230 receives the M first sequences from the second buffer 240 and sends one first sequence to each first buffer 220, so as to realize moving the M first sequences from the second buffer 240 to the M first buffers 220, and the M first buffers 220 and the sorter 210 perform data sorting. In this process, the second buffer 240 can implement the function of temporarily storing data.

[0114] In addition, since the second buffer 240 can be implemented by a memory such as a unified buffer, a cache, or a static memory, the read and write speed is faster than that of an external memory (such as the global memory). It can be used as a second-level cache between the external memory and the sorter 210, avoiding the first buffer 220 from reading data from the external memory, which can further reduce the delay of the first buffer 220 receiving data, and can further reduce or even eliminate the delay of the sorter 210 reading data from the first buffer 220, thereby further improving the sorting efficiency.

[0115] Furthermore, the above-mentioned sorting controller 230 may include a first read / write controller 231( Figure 2 (shown by the dashed box) and a second read / write controller 232( Figure 2(shown in dashed boxes), the first read / write controller 231 is coupled to the second read / write controller 232, the second buffer 240 is respectively coupled to the first read / write controller 231 and the second read / write controller 232, and the M first buffers 220 are all coupled to the first read / write controller 231.

[0116] The first read / write controller 231, the second read / write controller 232, and the second buffer 240 together can implement the function of continuously forwarding the data to be sorted. The following introduces the specific implementation process.

[0117] The second read / write controller 232 is configured to read M first sequences according to the storage address and store the M first sequences in the second buffer 240. The first read / write controller 231 is configured to move the M first sequences from the second buffer 240 to the M first buffers 220.

[0118] Specifically, the second read / write controller 232 is configured to send a first read instruction to read M first sequences and store the M first sequences in the second buffer 240. Among them, the first read instruction can refer to the description in the above function of the second buffer 240 for temporarily storing data, and will not be elaborated here.

[0119] The second read / write controller 232 is further configured to receive the first information and send the first information to the first read / write controller 231.

[0120] Among them, the first information may be: information of the M first sequences written into the second buffer 240. In other words, the first information can indicate the data that has been written into the second buffer 240 among the M first sequences. For example, if there are 10,000 data in the M first sequences and 2,000 of these 10,000 data have been stored in the second buffer 240, then the first information can indicate the storage addresses of these 2,000 data.

[0121] In a possible implementation manner, the second read / write controller 232 is further configured to receive the first information, which may include: the second read / write controller 232 receives the first information from other memories (such as global memory), and the first information indicates the data that has been written into the second buffer 240 among the M first sequences.

[0122] In another possible implementation manner, the second read / write controller 232 is further configured to receive the first information, which may include: the second read / write controller 232 and the second buffer 240 receive simultaneously (such as Figure 2As shown, M first sequences are received through the same data line. The second read / write controller 232 determines the data already stored in the second buffer 240 based on the received M first sequences, that is, determines the first information. Of course, the second read / write controller 232 may not store the data, but only record the storage addresses of these data in the second buffer 240.

[0123] The first read / write controller 231 is configured to send a second read instruction to the second buffer 240 based on the first information. The second read instruction is used to request M first sequences.

[0124] Optionally, if there is unused storage space in the m-th first buffer 220 among the M first buffers 220, the first read / write controller 231 sends a second read instruction to the second buffer 240 based on the first information.

[0125] The second buffer 240 is further configured to receive M first sequences.

[0126] The second buffer 240 is further configured to receive the second read instruction from the first read / write controller 231 and send M first sequences to the first read / write controller 231.

[0127] The first read / write controller 231 is further configured to receive M first sequences from the second buffer 240 and send one first sequence to each first buffer 220, so as to move the M first sequences from the second buffer 240 to the M first buffers 220.

[0128] When implementing the above function of continuously forwarding the data to be sorted, the following two cases are included:

[0129] Case 1, the storage space of the second buffer 240 is greater than or equal to the storage space occupied by the M first sequences.

[0130] Case 2, the storage space of the second buffer 240 is less than the storage space occupied by the M first sequences.

[0131] Next, the processes of implementing the above function of continuously forwarding the data to be sorted are described for the above two cases respectively.

[0132] For Case 1, since the storage space of the second buffer 240 is greater than or equal to the storage space occupied by M first sequences, that is to say, the second buffer 240 can receive all the data to be sorted at one time. In this case, after the second read / write controller 232 sends the first read instruction, the second buffer 240 can receive M first sequences at one time. Then, the first read / write controller 231 sends a second read instruction to the second buffer 240 based on the first information, can read the M first sequences in the second buffer 240, and send one first sequence to each of the first buffers 220. Of course, the first read / write controller 231 can forward the received data to the M first buffers 220 without storing the received data.

[0133] For Case 2, the storage space of the second buffer 240 is less than the storage space occupied by M first sequences, that is to say, the second buffer 240 cannot receive all the data to be sorted at one time. In this case, the second buffer 240 can receive all the data to be sorted through multiple write and multiple read processes.

[0134] For each write process, the second read / write controller 232 can send a first read instruction, which is used to request partial data in M first sequences, and the storage space size occupied by this partial data is less than or equal to the storage space size of the second buffer 240. When receiving M first sequences, the second buffer 240 can receive partial data in M first sequences, thus completing one write process.

[0135] For each read process, the second read / write controller 232 can receive the first information and send the first information to the first read / write controller 231. The first read / write controller 231 can, based on this first information, read the data in M first sequences that has been written into the second buffer 240, and send partial data of one first sequence to each of the first buffers 220, thus completing one read process.

[0136] Among them, in order to ensure that each first buffer 220 can receive the first sequence and avoid the situation where the data sorting cannot be completed because there is no first sequence in the first buffer 220, in each read process of the above Case 2, the first read instruction can request partial data in M first sequences, and the data proportion of each first sequence in this partial data is the same. For example, assume M = 4, the length of each first sequence is 2500, and the first read instruction requests 100 data in M first sequences. Then, among these 100 data, each first sequence can account for 25 data.

[0137] It should be understood that during multiple write and read operations of the second buffer 240, the second buffer 240 can continuously receive a portion of the data to be sorted. The first read / write controller 231 can continuously read a portion of the data to be sorted that has been stored in the second buffer 240, and continuously send a portion of the data of the first sequence to each of the first buffers 220. In this way, the first read / write controller 231, the second read / write controller 232, and the second buffer 240 can cooperate to continuously receive the data to be sorted and continuously send the data to be sorted to the M first buffers 220, enabling the sorter 210 to continuously sort the data to be sorted, thereby realizing the function of continuously forwarding the data to be sorted and further improving the sorting efficiency.

[0138] It should be noted that for case 2, during multiple write and read operations, the first read instruction can request the complete M first sequences. During multiple write and read operations, the second read instruction can request the complete M first sequences, causing the second buffer 240 to send the complete M first sequences to the first read / write controller 231.

[0139] In addition, since the first read / write controller 231 can read the data in the second buffer 240, the first read / write controller 231 can be referred to as a local read controller (LRC). Since the second read / write controller 232 can read the data to be sorted in other memories, the second read / write controller 232 can be referred to as an auto read controller (ARC).

[0140] Furthermore, the above-mentioned first read / write controller 231 is also used to send the information of the amount of data moved to the second read / write controller 232 when moving the M first sequences.

[0141] The information of the amount of data moved can be: the amount of data of the M first sequences that the first read / write controller 231 has read from the second buffer 240. Since the information of the amount of data moved is equivalent to the information of the free storage space size of the second buffer 240, the second read / write controller 232 can send the first read instruction according to this information of the amount of data moved, so that the data in the M first sequences that has not been written into the second buffer 240 can be written into the second buffer 240 as soon as possible. In this way, the sorting efficiency can be further improved.

[0142] Exemplarily, during each read operation in the above-mentioned Case 2, when the first read-write controller 231 receives M first sequences, it can also send the information of the amount of data that has been moved to the second read-write controller 232. During each write operation in the above-mentioned Case 2, the second read-write controller 232 can also send a first read instruction according to the information of the amount of data that has been moved. For example, when the information of the amount of data that has been moved indicates that 100 data have been read out from the second buffer 240, the second read-write controller 232 sends a first read instruction to request the remaining data in the M first sequences to be moved to the second buffer 240.

[0143] Based on the descriptions of the above first read-write controller 231, second read-write controller 232, and second buffer 240, it can be understood that the first read-write controller 231, second read-write controller 232, and second buffer 240 combined can achieve: when there is free storage space in the second buffer 240, writing part or all of the data of the M first sequences into the second buffer 240; and when part or all of the data of the M first sequences are stored in the second buffer 240, reading out these data and inputting them into the M first buffers 220, so that the sorter 210 can continuously sort the data to be sorted.

[0144] Furthermore, the above-mentioned sorting controller 230 may further include a third read-write controller 233 ( Figure 2 shown by the dashed box), and the third read-write controller 233 can be coupled to the sorter 210 and the second buffer 240 respectively. Optionally, the way the third read-write controller 233 is coupled to the sorter 210 may include: the sorter 210 is coupled to an output buffer 250 ( Figure 2 shown by the dashed box), and the output buffer 250 is coupled to the third read-write controller 233.

[0145] Among them, the output buffer 250 can be implemented by using a register or a register-related circuit component and can be used to store sequences. For example, the output buffer 250 can be implemented by using a built-in buffer, such as a buffer. Specifically, the output buffer 250 can be an output buffer (OB).

[0146] The third read-write controller 233 can implement the function of writing out ordered data, and the specific implementation process is introduced below.

[0147] The third read-write controller 233 is configured to receive the ordered sequence output by the sorter 210 and send the ordered sequence output by the sorter 210 to the second buffer 240. In other words, the third read-write controller 233 is configured to move the ordered sequence output by the sorter 210 to the second buffer 240.

[0148] For example, the sorter 210 may write an ordered sequence to the output buffer 250. Then, the third read / write controller 233 reads the ordered sequence from the output buffer 250 and sends the ordered sequence to the second buffer 240. In this way, the third read / write controller 233 can implement the function of writing out ordered data. Moreover, since the second buffer 240 can be implemented by using a memory such as a unified buffer, a cache memory, or a static memory, and its read / write speed is faster than that of an external memory, it can be used as a second-level cache between the external memory and the sorter 210. The third read / write controller 233 can send the sorted data to the second buffer 240, avoiding sending the sorted data to the external memory, thereby reducing the latency of the first buffer 220 outputting the sorted data and improving the sorting efficiency.

[0149] Optionally, if the length of the ordered sequence output by the sorter 210 stored in the second buffer 240 is greater than the output threshold, the third read / write controller 233 is used to read the ordered sequence output by the sorter 210 stored in the second buffer 240 and send the ordered sequence to an external memory (such as global memory) according to the status of the bus (such as whether it is occupied).

[0150] In addition, the third read / write controller 233, which receives the ordered sequence output by the sorter 210, can also be used to send the ordered sequence output by the sorter 210 to an external memory (such as global memory).

[0151] Since the third read / write controller 233 can write the sorted data to the second buffer 240 or other memories, the third read / write controller 233 can be called an auto write control (AWC).

[0152] It should be noted that the above sorting controller 230 and the first read / write controller 231, the second read / write controller 232, and the third read / write controller 233 in the sorting controller 230 can be implemented by one or more of the following: one or more coupled gate circuits, one or more field programmable gate arrays (FPGAs), one or more central processing units (CPUs), or application specific integrated circuits (ASICs), etc.

[0153] Since the sorter 210 can merge multiple sequences into one ordered sequence, the above sorting circuit 130 can also be called a mergesort circuit.

[0154] Based on the above Figure 1The illustrated processor 100. The sorting circuit 130 in the processor 100 can, in response to the decoded first instruction, arrange M ordered sequences into an ordered sequence with a length of M*N, or arrange M sequences with unordered sequences into M ordered sequences with a length of N. In other words, the processor 100 can sort multiple sequences by executing 1 first instruction, so that the processor 100 can execute fewer instructions to complete the sorting operation of multiple sequences, avoid executing a large number of repeated instructions, reduce the number and execution time of sorting instructions to be executed, and thus improve the sorting efficiency. Among them, the above Figure 1 The illustrated processor 100 may include multiple sorting circuits 130 to implement multi-core parallel sorting. The multi-core parallel sorting process may refer to the following Figure 15 .

[0155] In addition, the data structure of each data included in the first sequence may be: {value (score), index}. Among them, the "value" can be implemented by any one of the following: 16-bit floating-point number (FP), 32-bit floating-point number, 8-bit integer (INT), 16-bit integer, or 32-bit integer, etc. The "index" corresponds to the "value". The "index" includes the address of various information of the "value" and can be implemented by a pointer. That is to say, through the "index", various information of the corresponding "value" can be obtained. When the sorter 210 sorts such data, it can compare the sizes of the data based on the "values" of each data, thereby implementing the sorting function. In this way, the processor 100 can process data with a wider number of bits, and there is no redundant data during the sorting process, thereby improving the bus utilization rate and sorting efficiency.

[0156] Exemplarily, Figure 4 is a schematic diagram of the sorting circuit 130 provided by the embodiment of the present application for sorting M sequences. Refer to Figure 4 . The M first sequences include: sequence 0, sequence 1,..., sequence M-1. Each sequence includes N data, and the data structure of each data is: {value, index}. The above sorting circuit 130 (mergesort) can sort these M sequences and output an ordered sequence.

[0157] The above Figures 1 - 4 illustrated embodiment illustrates a processor 100 provided by the embodiment of the present application. The following combines Figures 5 - 9 to illustrate another processor 500 provided by the embodiment of the present application.

[0158] Please refer to Figure 5 . Figure 5Another processor 500 provided by an embodiment of the present application. The processor 500 includes: an instruction storage circuit 510, a control circuit 520, and a sorting circuit 530. The instruction storage circuit 510 is coupled to the control circuit 520, and the control circuit 520 is coupled to the sorting circuit 530.

[0159] The above-mentioned processor 500 may be a central processing unit (CPU). The processor 100 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, such as a vector processor, a coprocessor, an ARM (advanced RISC machines) processor, etc. The embodiments of the present application do not limit this.

[0160] Among them, the instruction storage circuit 510 can store multiple instructions. The instruction storage circuit 510 can be implemented by an instruction cache or an instruction register and can be included in the memory subsystem of the processor 500. The control circuit 520 can preprocess the instructions, including operations such as instruction fetching and decoding. The control circuit 520 can be a control unit in the processor 500, and the control unit can also be called the front end. The sorting circuit 530 can be implemented by a microarchitecture. The sorting circuit 530 can be included in the execution engine of the processor 500, and the execution engine can also be called an arithmetic unit.

[0161] In an embodiment of the present application, the sorting circuit 530 may include: I sorters 531, each sorter 531 includes J input terminals and J output terminals, where I is a positive integer and J is a positive even number.

[0162] Among them, the J input terminals of the first sorter 531 among the I sorters 531 are the J input terminals of the sorting circuit 530. That is, the J input terminals of the first sorter 531 can be used to receive the data to be sorted.

[0163] The J output terminals of the I-th sorter 531 in the I sorters 531 are the J output terminals of the device. That is, the J input terminals of the first sorter 531 can be used to output sorted data.

[0164] The J output terminals of the i-th sorter 531 in the I sorters 531 are respectively connected to the J input terminals of the (i + 1)-th sorter 531. That is to say, the I sorters 531 are connected in sequence. Among them, i ≤ I. Of course, since the structures of different sorters 531 are the same, in actual implementation, in order to save physical resources, the sorters can be reused. For example, the I sorters 531 included in the sorting circuit 530 actually reuse a physical sorter 531.

[0165] The control circuit 520 is configured to read a second instruction from the instruction storage circuit 510 and decode the second instruction. The decoded second instruction includes the storage addresses of H data, where H ≤ J. The control circuit 520 is further configured to send the decoded second instruction to the sorting circuit 530. The sorting circuit 530 is configured to respond to the decoded second instruction and perform the following steps: read H data according to the storage addresses, and use the i-th sorter 531 in the sorting circuit 530 to sort the H data, and the orderliness of the sorted H data is higher than that of the H data before sorting.

[0166] The following combines Figure 6 to describe the above sorting circuit 530. Figure 6 is a schematic structural diagram of a sorting circuit 530 provided by an embodiment of the present application. Figure 1 Among them, Figure 6 shows the structure of the sorting circuit 530 with I = 4 and J = 8.

[0167] Please refer to Figure 6 This sorting circuit 530 includes 4 sorters 531. Each sorter 531 includes 8 input terminals and 8 output terminals. The 8 input terminals of each sorter 531 are respectively: I1, I2, I3,..., I8, and the 8 output terminals of each sorter 531 are respectively: O1, O2, O3,..., O8. The 8 input terminals of the first sorter 531 are the 8 input terminals of this sorting circuit 530, and the 8 output terminals of the fourth sorter 531 are the 8 output terminals of this sorting circuit 530.

[0168] Table 3 is the input of the data to be sorted. Figure 6Case table of the sorting circuit 530 shown. Referring to Table 3, if the data to be sorted is: "15, 8, 9, 6, 7, 20, 13, 1" (i.e., H = 8), then when this sequence is input to the 8 input terminals of the sorting circuit 530, it can be input to I1, I2, I3, …, I8 of the first sorter 531 in the order of the sequence arrangement, that is, 15 is input to I1, 8 is input to I2, …, 1 is input to I8. That is to say, the data to be sorted is input to the sorting circuit 530 in the order of the arrangement of J input terminals.

[0169] Table 3

[0170]

[0171]

[0172] Table 4 shows the case where the sorted data is output by Figure 6 the sorting circuit 530 shown. Referring to Table 4, if the sorted data is: "1, 6, 7, 8, 9, 13, 15, 20", then when this sequence is output from the 8 output terminals of the sorting circuit 530, it can be output from O1, O2, O3, …, O8 of the fourth sorter 531 in the order of the sequence arrangement, that is, 1 is output from O1, 6 is output from O2, …, 20 is output from O8. That is to say, the sorted data is output from the sorting circuit 530 in the order of the arrangement of J output terminals.

[0173] Table 4

[0174]

[0175] When using the above sorting circuit 530 to sort data, the i-th sorter 531 can be used to receive H data. The i-th sorter 531 can also be used to output the sorted H data, where the orderliness of the sorted H data is higher than that of the H data before sorting.

[0176] It should be understood that each sorter 531 can sort the received H data and improve the orderliness of these H data during the sorting process. Therefore, starting from the input of the first sorter 531 for the H data, every time the H data passes through a sorter 531, the orderliness of the H data is improved once. Thus, after passing through one or more sorters 531, the H data can finally be sorted into an ordered sequence. In this way, the above sorting circuit 530 can realize the function of sorting data.

[0177] In some possible embodiments, the above i-th sorter 531 may include K comparators. Among them, K ≥ J / 2, and K is a positive integer. The k-th comparator among the K comparators is used to receive two of the H data. The k-th comparator is also used to compare the two of the H data and output the two compared data.

[0178] The following will describe the above K comparators in conjunction with Figure 6 and Figure 7 to explain the above K comparators.

[0179] Refer to Figure 6 , taking the first sorter 531 as an example. The first sorter 531 includes 7 comparators ( Figure 6 shown by a dashed box in

[0180] ). Each comparator can receive two data, compare the magnitudes of the two data, and output the two data after comparison.

[0181] Among them, when the comparator outputs the two data after comparison, there are the following two output methods:

[0182] Method 3: Output the two data after comparison in ascending order. For example, assume that for comparator A1 of the first sorter 531, the data received from I1 is 8 and the data received from I2 is 7. Then this comparator A1 can exchange the order of these two data and output them. That is to say, send 7 to O1 and send 8 to comparator B1.

[0183] Method 4: Output the two data after comparison in descending order. For example, assume that for comparator A1 of the first sorter 531, the data received from I1 is 8 and the data received from I2 is 7. Then this comparator A1 sends 8 to O1 and sends 7 to comparator B1.

[0184] It can be understood that when the comparator outputs the two data after comparison, which output method is selected is determined by the sorting method of the sorting circuit 530. For example, when the sorting circuit 530 sorts the data from small to large, each comparator in the sorting circuit 530 works according to the above Method 3; when the sorting circuit 530 sorts the data from large to small, each comparator in the sorting circuit 530 works according to the above Method 4. Among them, the sorting method of the sorting circuit 530 can be configured.

[0184] Please refer to Figure 7, taking K = 4 and J = 8 as an example, each sorter 531 can include 4 comparators (A1 - A4). Each comparator can include two input terminals and two output terminals. Each input terminal of the comparator can be connected to a register, and each output terminal of the comparator can be connected to a register. The register can be used to temporarily store data. The 8 input terminals of the 4 comparators of the i-th sorter 531 are the 8 input terminals of the sorter 531, and the 8 output terminals of the 4 comparators of the i-th sorter 531 are the 8 output terminals of the sorter 531. Among them, the two output terminals of A1 of the first sorter 531 can be respectively connected to one input terminal of A1 and one input terminal of A2 of the second comparison unit. The two output terminals of A2 of the first sorter 531 can be respectively connected to one input terminal of A2 and one input terminal of A3 of the second comparison unit. The two output terminals of A3 of the first sorter 531 can be respectively connected to one input terminal of A3 and one input terminal of A4 of the second comparison unit. The two output terminals of A4 of the first sorter 531 can be respectively connected to one input terminal of A4 and one input terminal of A1 of the second comparison unit. And so on, the connection method between other adjacent two sorters 531 can refer to the connection method between the first sorter 531 and the second sorter 531. Of course, the connection between the comparators in the sorter 531 is not limited to Figure 7 being connected through registers as shown, and can also be directly connected.

[0185] When using Figure 7 the shown sorting circuit 530 to sort 8 data (i.e., H = 8), assuming that the sorting circuit 530 sorts the data to be sorted in ascending order. First, the data to be sorted input to the first sorter 531 is: "8, 7, 6, 5, 4, 3, 2, 1". The first sorter 531 sorts this sequence, and the sorted sequence becomes: "7, 8, 5, 6, 3, 4, 1, 2". Then, the second sorter 531 sorts the sequence output by the first sorter 531, and the sorted sequence becomes: "2, 5, 8, 3, 6, 1, 4, 7". And so on, the sequence output by the seventh sorter 531 is: "1, 2, 3, 4, 5, 6, 7, 8".

[0186] Based on Figure 7 the shown sorting process, it can be seen that for the data to be sorted, every time it passes through the K comparators of a sorter 531, the degree of orderliness will be improved. In this way, an implementation method of the sorter 531 can be provided, so that the sorter 531 can improve the degree of orderliness of H data.

[0187] Optionally, the K comparators may include: J / 2 first comparators and (J / 2)-1 second comparators. The J-2 output terminals of the J / 2 first comparators are respectively connected to the J-2 input terminals of the (J / 2)-1 second comparators.

[0188] Among them, the J input terminals of the J / 2 first comparators are: the J input terminals of the i-th sorter 531. The other 2 output terminals of the J / 2 first comparators and the J-2 output terminals of the (J / 2)-1 second comparators are: the J output terminals of the i-th sorter 531.

[0189] The following combines Figure 6 to illustrate the implementation manner of the above K comparators and the sorting process.

[0190] Referring to Figure 6 , each sorter 531 includes 7 comparators. These seven comparators include: 4 first comparators (A1 - A4) and 3 second comparators (B1 - B3). Each comparator includes two input terminals and two output terminals.

[0191] Among them, taking the 7 comparators in the 1st second comparator as an example, the 8 input terminals of A1 - A4 are the 8 input terminals of this sorter 531. The 6 output terminals of A1 - A4 are respectively connected to the 6 input terminals of B1 - B3. The other 2 output terminals of A1 - A4 and the 6 output terminals of B1 - B3 are the 8 output terminals of the 1st sorter 531.

[0192] Furthermore, the two input terminals of each comparator can be respectively connected to a register, and the two output terminals of each comparator can be respectively connected to a register. The register can be used to temporarily store data. Exemplarily, referring to Figure 6 the comparator A1 in the 1st second comparator of Figure 6 shown by a dashed box in

[0193] Assume that the sorting circuit 530 sorts 8 data in ascending order (i.e., H = 8). First, the data to be sorted input to the sorting circuit 530 is: "8, 7, 6, 5, 4, 3, 2, 1". After the 1st sorter 531 sorts this sequence, the output sequence becomes: "7, 5, 8, 3, 6, 1, 4, 2". Then, the 2nd sorter 531 sorts the sequence output by the 1st sorter 531, and the sorted sequence becomes: "5, 3, 7, 1, 8, 2, 6, 4". And so on. The sequence output by the 4th sorter 531 is: "1, 2, 3, 4, 5, 6, 7, 8", thus realizing the function of sorting data.

[0194] It should be understood that based on Figure 6 As can be seen from the description of the implementation manner of the K comparators and the sorting process, the order degree of the data to be sorted will be improved every time it passes through the K comparators of a sorter 531. In this way, an implementation manner of the sorter 531 can be provided, so that the sorter 531 can improve the order degree of H data.

[0195] Optionally, the number of times the I sorters 531 sort the H data is greater than or equal to J / 2.

[0196] Among them, when the number of times the I sorters 531 sort the H data is greater than or equal to J / 2, for the data to be sorted with the lowest order degree, the sorting circuit 530 can also arrange the data to be sorted into an ordered sequence. For example, referring to the above Figure 6 shown sorting process, the data to be sorted input to the sorting circuit 530: "8, 7, 6, 5, 4, 3, 2, 1", the order degree of this sequence is the lowest among the sequences with a length of 8. After Figure 6 being sorted by the shown sorting circuit 530, this sequence can just be arranged into an ordered sequence. In other words, when the number of times the I sorters 531 sort the H data is greater than or equal to J / 2, the sorting circuit 530 can sort the H data into an ordered sequence.

[0197] Next, two implementation manners of "the number of times the I sorters 531 sort the H data is greater than or equal to J / 2" are introduced.

[0198] Method 5, I and J satisfy the following relationship: I≥J / 2. In other words, the number of sorters 531 is greater than or equal to J / 2. In this way, it can be ensured that the number of times the I sorters 531 sort the H data is greater than or equal to J / 2, so that the sorting circuit 530 can sort the H data into an ordered sequence.

[0199] Method 6, the J input ends of the first sorter 531 among the I sorters 531 are respectively connected to the output ends of J selectors. The first input ends of the J selectors are the J input ends of the sorting circuit 530, and the J output ends of the I-th sorter 531 among the I sorters 531 are respectively connected to the second input ends of the J selectors.

[0200] In this way, since the data to be sorted is output from the J output terminals of the I-th sorter 531 and can be input into the sorting circuit 530 described in the second aspect again through the second input terminals of the J selectors, that is to say, the data to be sorted can be circularly sorted in the sorting circuit 530 described in the second aspect. Thus, under the condition that I is less than J / 2, by controlling the number of times the data to be sorted is circularly sorted, the number of times the I sorters 531 sort the H data can be greater than or equal to J / 2, thereby reducing the hardware scale and saving costs.

[0201] The following introduces an implementation manner of Method 6.

[0202] Please refer to Figure 6 , the 8 input terminals (I1 - I8) of the 1st sorter 531 are respectively connected to the output terminals of 8 selectors (multiplexer, MUX). The first input terminals of these 8 selectors ( Figure 6 shown by the dashed boxes) are respectively: Din1, Din2,..., Din8, and the second input terminals of the 8 selectors are respectively: loop1, loop2,..., loop8. The 8 output terminals (O1 - O8) of the 4th sorter 531 are respectively connected to loop1, loop2,..., loop8. Among them, the data to be sorted can be input into the sorting circuit 530 from Din1, Din2,..., Din8. That is to say, the 8 input terminals of the sorting circuit 530 are Din1, Din2,..., Din8. In addition, the above-mentioned selector can be a two-way selector.

[0203] These 8 selectors can all be connected to a counter ( Figure 6 shown by the dashed box), and the counter can control which input terminal of the selector is selected. For example, when the counter controls the first input terminal of each selector to be selected, the data to be sorted can be input from Din1 - Din8 into the sorting circuit 530, and the sorting circuit 530 performs sorting. When the counter controls the second input terminal of each selector to be selected, the data output by the sorting circuit 530 will be input into the sorting circuit 530 again through loop1 - loop8, and the sorting circuit 530 continues to perform sorting.

[0204] Therefore, the counter can control the number of times the data to be sorted is circularly sorted in the sorting circuit 530. Thus, under the condition that the number of I remains unchanged, by controlling the number of times the data to be sorted is circularly sorted in the sorting circuit 530, the number of times the I sorters 531 sort the H data can be increased, realizing that even if I is less than J / 2, the number of times the I sorters 531 sort the H data can be greater than or equal to J / 2, and further reducing the hardware scale and saving costs.

[0205] Of course, when implementing the above-mentioned Mode 6, the J output terminals of the i-th sorter 531 among the I sorters 531 can also be respectively connected to the second input terminals of the J selectors.

[0206] It should be noted that the above sorting circuit 530 can also be referred to as an initial sorting (initsort) circuit. When implementing this device, a microarchitecture can be adopted.

[0207] In addition, Figure 6 the implementation manner of the comparator structure in the shown sorting circuit 530 is not limited to Figure 6 shown. In practical applications, the number of comparators in each sorter 531 can also be increased or decreased, or the connection manner between the comparators in each sorter 531 can be adjusted. For example, the implementation manner of the comparator structure can also be as Figure 8 shown.

[0208] Please refer to Figure 8 , each sorter 531 includes 7 comparators, and these seven comparators include: 3 first comparators (A1 - A3) and 4 second comparators (B1 - B4). Each comparator includes two input terminals and two output terminals.

[0209] Among them, taking the 7 comparators in the 1st second comparator as an example, the 8 output terminals of B1 - B4 are the 8 output terminals of this sorter 531. The 6 input terminals of B1 - B4 are respectively connected to the 6 output terminals of A1 - A3. The other 2 input terminals of B1 - B4 and the 6 input terminals of A1 - A3 are the 8 input terminals of the 1st sorter 531.

[0210] Furthermore, the two input terminals of each comparator can be respectively connected to a register, and the two output terminals of each comparator can be respectively connected to a register. The register can be used to temporarily store data. Exemplarily, referring to Figure 8 the comparator A1 in the 1st second comparator of Figure 8 which is shown by a dashed box, the two input terminals (I2, I3) of this comparator A1 are respectively connected to a register (

[0211] Assume that the sorting circuit 530 sorts the data in ascending order. First, the data to be sorted input to the sorting circuit 530 is: "8, 7, 6, 5, 4, 3, 2, 1". After the first sorter 531 sorts this sequence, the output sequence becomes: "6, 8, 4, 7, 2, 5, 1, 3". Then, the second sorter 531 sorts the sequence output by the first sorter 531, and the sorted sequence becomes: "4, 6, 2, 8, 1, 7, 3, 5". And so on, the sequence output by the fourth sorter 531 is: "1, 2, 3, 4, 5, 6, 7, 8", thus realizing the function of sorting the data.

[0212] It should be understood that Figure 8 the shown sorting circuit is different from Figure 6 the shown sorting circuit in structure, but both can achieve the same effect, that is, a way to implement the sorter 531 can be provided, such that the sorter 531 can improve the order degree of J data.

[0213] In a possible embodiment, the above sorting circuit 530 can also arrange H data into an ordered sequence in the way of bitonic sorting. Specifically, the above-mentioned i-th sorter 531 can include K comparators. Wherein, K≥J / 2 and K is a positive integer. And, the two input terminals of each comparator are respectively connected to the output terminals of a 1-of-H selector. The 1-of-H selector means that it can select 1 data from H data and output it. Using the 1-of-H selector, the comparator can select and compare 2 data from H data according to certain rules and output.

[0214] Please refer to Figure 9 , Figure 9 which is the structural schematic of another sorting circuit provided by the embodiment of the present application Figure 4Taking K = 4, J = 8, and H = 8 as an example, each sorter 531 can include 4 comparators (A1 - A4). Each comparator can include two input terminals and two output terminals. Each input terminal of the comparator can be connected to the output terminal of an H - to - 1 selector. Each output terminal of the comparator can be connected to a register, and the register can be used to temporarily store data. The 8 input terminals of the 4 comparators of the i - th sorter 531 are the 8 input terminals of the sorter 531, and the 8 output terminals of the 4 comparators of the i - th sorter 531 are the 8 output terminals of the sorter 531. Among them, the two H - to - 1 selectors connected to A1 of the first sorter 531 can select 2 data from 8 data to be sorted for comparison and output according to certain rules. The two H - to - 1 selectors connected to A2 of the first sorter 531 can select 2 data from 8 data to be sorted for comparison and output according to certain rules. In other words, the 8 H - to - 1 selectors of the first sorter 531 can input 8 data to be sorted into 4 comparators for sorting according to certain rules. By analogy, the 8 H - to - 1 selectors of the (i + 1) - th sorter 531 can input the 8 data output by the i - th sorter 531 into 4 comparators for sorting according to certain rules.

[0215] Among them, when the above - mentioned rule is the sorting rule corresponding to the bitonic sorting algorithm, the sorting circuit 530 can arrange H data into an ordered sequence in the way of bitonic sorting. It can be understood that compared with Figure 6 or Figure 7 the sorting process shown, the sorting efficiency of bitonic sorting is higher, so that the sorting efficiency of the sorting circuit 530 can be further improved.

[0216] Based on the above - mentioned Figure 5 processor 500 shown, the sorter 531 in the processor 500 can respond to the decoded second instruction to increase the orderliness of H data by I times. Thus, the sorter 531 can arrange H data into an ordered sequence by sorting H data once or multiple times. In other words, when the processor 500 executes the second instruction, it can sort H data, so that the processor 500 can execute fewer instructions to complete the sorting operation of H data. This can avoid executing a large number of repeated instructions, reduce the number and execution time of sorting instructions to be executed, and thus improve the sorting efficiency.

[0217] The data structure of each of the above H data can also be: {value (score), index}. Among them, the "value" can be implemented by any of the following: 16-bit floating-point number (FP), 32-bit floating-point number, 8-bit integer (INT), 16-bit integer, or 32-bit integer, etc. The "index" corresponds to the "value". The "index" includes the addresses of various information of the "value" and can be implemented by a pointer. That is to say, through the "index", various information of the corresponding "value" can be obtained. When the above comparator sorts such data, it can compare the magnitudes of the data based on the "values" of each data. In this way, the above sorting circuit 530 can process data with a wider number of bits and there is no redundant data during the sorting process, thereby improving the bus utilization rate and sorting performance.

[0218] Exemplarily, Figure 10 For use Figure 6 The schematic diagram of sorting H data by the sorting circuit 530 shown. Refer to Figure 10 , the H data include: {value 0, index 0}, {value 1, index 1}, …, {value H-1, index H-1}. The above sorting circuit 530 (initsort) can output an ordered sequence for these H data: {value 0', index 0'}, {value 1', index 1'}, …, {value (H-1)', index (H-1)'}.

[0219] In addition, the above sorting circuit 530 can also sort data of different data types. Assume that the data type that the above sorting circuit 530 can sort is 32-bit floating-point number. Then, when there are other types of data in the data to be sorted (such as 8-bit integer, 16-bit integer, etc.), through data type conversion, the other types of data can be uniformly converted into 32-bit floating-point numbers, so as to achieve the purpose that the sorting circuit 530 can sort data of different data types. Among them, the data type conversion between different data types can refer to the existing regulations and will not be elaborated here.

[0220] The above sorting circuit 530 can also arrange X (X > J) data into multiple ordered sequences through multiple rounds of sorting. For example, it can rounds of sorting to output ordered sequences, Denotes rounding up X / J. Among them, when the data input to the sorting circuit 530 is Z (Z < J), the sorting of Z data can be achieved by complementing the data. For example, when the sorting circuit 530 sorts the data from small to large, when inputting Z data to the sorting circuit 530, J - Z infinite large numbers (the infinite large number is larger than any input data and can be realized through predefined) can be input, so that the data input to the sorting circuit 530 is J, and the first Z data in the sequence output by the sorting circuit 530 are the sorted Z data.

[0221] The above combination Figures 1 - 10 has described in detail two processors provided by the embodiments of the present application. The following combination Figure 11 will describe the electronic device provided by the embodiments of the present application.

[0222] The embodiments of the present application provide an electronic device, which may include one or more of the above-mentioned processors 100, and / or one or more of the above-mentioned processors 500. Among them, the electronic device may include but is not limited to: servers, computers, mobile phones, tablets (Pads), computers with wireless transceiver functions, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical, wireless terminals in smart grid, wireless terminals in transportation safety, wireless terminals in smart city, wireless terminals in smart home, vehicle-mounted terminals, RSUs with terminal functions, etc.

[0223] Figure 11 is a schematic structural diagram of the electronic device provided by the embodiments of the present application. As Figure 11 shown, the electronic device 1100 may include a processor 1101. Optionally, the electronic device 1100 may further include a memory 1102 and / or a transceiver 1103. Among them, the processor 1101 is coupled to the memory 1102 and the transceiver 1103, such as being connected through a communication bus.

[0224] Next, in combination with Figure 11 each component of the electronic device 1100 will be specifically introduced:

[0225] Among them, the processor 1101 is the control center of the electronic device 1100, which can be a single processor or a collective term for multiple processing elements. For example, the processor 1101 is one or more central processing units (CPUs), or can also be one or more vector processors, coprocessors, etc. It can also be an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application. For example: one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs).

[0226] Optionally, the processor 1101 can execute various functions of the electronic device 1100 by running or executing software programs stored in the memory 1102 and invoking data stored in the memory 1102.

[0227] In a specific implementation, as an embodiment, the processor 1101 may include one or more CPUs, such as Figure 11 the CPU0 and CPU1 shown in

[0228] In a specific implementation, as an embodiment, the electronic device 1100 may also include multiple processors, such as Figure 11 the processor 1101 and the processor 1104 shown in

[0229] Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions). Figures 12 - 15 The method embodiments shown in

[0230] Optionally, the memory 1102 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or may also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or any other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1102 may be integrated with the processor 1101, or may exist independently, and is coupled to the processor 1101 through the interface circuit of the electronic device 1100 ( Figure 11 not shown in the figure), and the embodiments of the present application do not make specific limitations on this.

[0231] The transceiver 1103 is used for communication with other electronic devices. For example, if the electronic device 1100 is a terminal device, the transceiver 1103 may be used for communication with a network device or with another terminal device. Another example is that if the electronic device 1100 is a network device, the transceiver 1103 may be used for communication with a terminal device or with another network device.

[0232] Optionally, the transceiver 1103 may include a receiver and a transmitter ( Figure 11 not shown separately). Among them, the receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0233] Optionally, the transceiver 1103 may be integrated with the processor 1101, or may exist independently, and is coupled to the processor 1101 through the interface circuit of the electronic device 1100 ( Figure 11 not shown in the figure), and the embodiments of the present application do not make specific limitations on this.

[0234] It should be noted that Figure 11 the structure of the electronic device 1100 shown in the figure does not constitute a limitation on the electronic device. The actual electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different component layout.

[0235] In addition, the technical effects of the electronic device 1100 may refer to Figures 12 - 15 the technical effects of the method shown in the figure, which will not be elaborated here.

[0236] The above-mentioned Figure 1 illustrates a processor 100 provided by the present application. The following will be combined with Figure 12 to illustrate a sorting method for sorting data using the processor 100.

[0237] Figure 12 is a flowchart of the sorting method provided by the embodiments of the present application Figure 1 . Please refer to Figure 12 , this method can be applied to Figure 1 the illustrated processor 100. This method includes the following steps:

[0238] S1201, the control circuit reads a first instruction from the instruction storage circuit and decodes the first instruction.

[0239] S1202, the control circuit sends the decoded first instruction to the sorting circuit.

[0240] S1203, the sorting circuit responds to the decoded first instruction and reads M first sequences according to the storage address.

[0241] In a possible design, the above-mentioned sorting circuit 130 may include: a sorting controller 230, a sorter 210, and M first buffers 220. The sorting controller 230 is coupled to the M first buffers 220, and the M first buffers 220 are all coupled to the sorter 210. In S1203, the sorting circuit 130 responds to the decoded first instruction and reads M first sequences according to the storage address, which may include: the sorting controller 230 reads M first sequences according to the storage address and stores the M first sequences in the M first buffers 220. Wherein, each first buffer 220 stores one first sequence.

[0242] Exemplarily, assuming that the M first sequences are stored in the global memory, then the sorting controller 230 may respond to the decoded first instruction, send a read instruction to the global memory according to the storage address and through the bus, and this read instruction is used to instruct the global memory to send these M first sequences to the sorting controller 230. Then, the sorting controller 230 may receive the M first sequences from the global memory and send one first sequence to each of the M first buffers 220. Among them, these M first sequences may all be ordered sequences or there may be unordered sequences.

[0243] In addition, the specific implementation manner and effect of S1203 can refer to the above Figure 2 description of the sorting controller 230 moving data, which will not be elaborated here.

[0244] S1204. If all M first sequences are ordered sequences, the sorting circuit outputs an ordered sequence with a length of M * N.

[0245] In a possible design solution, S1204 may include: If all M first sequences are ordered sequences, the sorter 210 reads out an ordered sequence with a length of M * N from the M first buffers 220.

[0246] Optionally, if all M first sequences are ordered sequences, the sorter 210 reads out an ordered sequence with a length of M * N from the M first buffers 220 according to the first reading rule. Among them, the first reading rule may be: Each time, read out the data ranked first in the M first buffers 220. That is to say, each time, read out the data ranked first in the M ordered sequences. For example, assume there are two ordered sequences, namely: "3, 5, 6, 9" and "7, 13, 25, 26", and the sorting rule of the ordered sequences is from small to large. Then the data ranked first in these two ordered sequences is 3. When the first buffer 220 is implemented by an input buffer, the sorter 210 can read out the data ranked first at the output ends of the M first buffers 220 each time. It should be understood that the above S1204 can implement the function of arranging M ordered sequences into one ordered sequence.

[0247] In addition, for the specific implementation manner and effect of S1204, reference may be made to the above-mentioned manner 1, which will not be elaborated here.

[0248] S1205. If there are unordered sequences among the M first sequences, the sorting circuit outputs M ordered sequences with a length of N.

[0249] In a possible design solution, S1205 may include: If there are unordered sequences among the M first sequences, the sorter 210 reads out M ordered sequences with a length of N from the M first buffers 220.

[0250] Optionally, if there are unordered sequences among the M first sequences, the sorter 210 reads out M ordered sequences of length N from the M first buffers 220 according to the second reading rule. The second reading rule may be: read out an ordered sequence of length N from the M first buffers 220 each time. Specifically, the sorter 210 can read out x data from each first buffer 220 each time, and then arrange these M * x data into an ordered sequence, where x is a positive integer. For example, assume x = 1 and M = 4. The first sequences stored in the 4 first buffers 220 are: "10, 8, 20, 3", "1, 25, 33, 7", "6, 4, 16, 23", "11, 15, 16, 18". Then the sorter 210 can read out 1 data from each of these 4 first buffers 220 for the first time, that is, read out "10, 1, 6, 11", and then arrange these 4 data into an ordered sequence: "1, 6, 10, 11". Optionally, when the first buffer 220 is implemented using an input buffer, the sorter 210 can read out x data from the output end of each first buffer 220 each time. It can be understood that since x can take an integer greater than or equal to 1, when the value of x increases, the sorter 210 can read out more data for sorting from the M first buffers 220 at a time, thereby improving the sorting efficiency. It should be understood that the above S1205 can implement the function of arranging the M unordered sequences into M ordered sequences.

[0251] In addition, for the specific implementation manner and effect of S1205, reference can be made to the above manner 2, which will not be elaborated here.

[0252] The above manner 1 and manner 2 can be implemented independently or in combination. When manner 1 and manner 2 are implemented in combination, it may include: first execute manner 2 to arrange the M unordered sequences into M ordered sequences. Then execute manner 1 to arrange the M ordered sequences into one ordered sequence.

[0253] Optionally, the sorting circuit 130 further includes a second buffer 240, and the second buffer 240 is coupled to the sorting controller 230. To implement the function of the second buffer 240 for temporarily storing data, the above method may further include:

[0254] Step 1, the sorting controller 230 reads the M first sequences according to the storage address and stores the M first sequences in the second buffer 240.

[0255] Step 2, the sorting controller 230 moves the M first sequences from the second buffer 240 to the M first buffers 220.

[0256] It can be understood that for the specific implementation manner and effect of the second buffer 240 for temporarily storing data, reference can be made to the above Figure 2The related description of how the sorting circuit 130 shown implements the function of temporarily storing data in the second buffer 240 will not be elaborated here.

[0257] Further, the sorting controller 230 includes a first read / write controller 231 and a second read / write controller 232. The first read / write controller 231 is coupled to the second read / write controller 232. The second buffer 240 is respectively coupled to the first read / write controller 231 and the second read / write controller 232. All M first buffers 220 are coupled to the first read / write controller 231. To improve the sorting efficiency, step 1 above may include: The second read / write controller 232 reads M first sequences according to the storage address and stores the M first sequences in the second buffer 240. Step 2 above may include: The first read / write controller moves the M first sequences from the second buffer 240 to the M first buffers 220. It can be understood that for the specific implementation manners and effects of step 1 and step 2, reference can be made to the above Figure 2 The related description of how the sorting circuit 130 shown implements the function of continuously forwarding data to be sorted will not be elaborated here.

[0258] Still further, to improve the sorting efficiency, the above method may further include:

[0259] Step 3, when moving the M first sequences, the first read / write controller 231 sends information on the amount of data moved to the second read / write controller 232.

[0260] It can be understood that for the specific implementation manner and effect of step 3, reference can be made to the above Figure 2 The related description of how the sorting circuit 130 shown that the first read / write controller 231 sends information on the amount of data moved to the second read / write controller 232 will not be elaborated here.

[0261] Further, the above sorting controller 230 may further include a third read / write controller 233. The third read / write controller 233 is respectively coupled to the sorter 210 and the second buffer 240. To implement the function of the third read / write controller 233 to write out ordered data, the above method may further include:

[0262] Step 4, the third read / write controller 233 moves the ordered sequence output by the sorter 210 to the second buffer 240.

[0263] It can be understood that for the specific implementation manner and effect of step 4, reference can be made to the above Figure 2 The related description of how the sorting circuit 130 shown implements the function of writing out ordered data will not be elaborated here.

[0264] The above Figures 5 - 9 The embodiment shown illustrates another structure of the processor 500 provided by the present application. Below, in combination with Figure 13Introduce a data sorting method implemented based on the above-mentioned another processor 500.

[0265] Figure 13 The flow diagram of the sorting method provided by the embodiments of the present application Figure 2 . Please refer to Figure 13 , this method can be applied to Figures 5 - 9 any of the processors 500 shown in the implementation manners, and this method includes the following steps:

[0266] S1301, the control circuit reads the second instruction from the instruction storage circuit and decodes the second instruction.

[0267] S1302, the control circuit sends the decoded second instruction to the sorting circuit.

[0268] S1303, the sorting circuit responds to the decoded second instruction and reads H data according to the storage address.

[0269] S1304, the sorting circuit uses the i-th sorter in the sorting circuit to sort the H data.

[0270] It can be understood that the specific implementation manners and effects of S1301 - S1304 can refer to the usage process of the processor 500 shown in any of the above Figures 5 - 9 implementation manners, and will not be elaborated here.

[0271] In some possible embodiments, if the i-th sorter 531 includes K comparators, K ≥ J / 2, and K is a positive integer, then in S1304, the sorting circuit 530 uses the i-th sorter 531 in the sorting circuit 530 to sort the H data, which may include:

[0272] The k-th comparator among the K comparators receives two of the H data. The k-th comparator compares the two data among the H data and outputs the two compared data. For the specific implementation manners and effects, reference can be made to the relevant descriptions of the K comparators of the processor 500 shown in any of the above Figures 5 - 9 implementation manners, and will not be elaborated here.

[0273] The above Figures 1 - 13 respectively illustrate the implementation manners of two processors. Based on the two processors shown in Figures 1 - 13 , the embodiments of the present application provide another sorting method to sort data by combining the two processors.

[0274] Figure 14 The flow diagram of the sorting method provided by the embodiments of the present application Figure 3 . Please refer to Figure 14 , this method can be applied to an electronic device, the electronic device includes a processor, and the processor includes the aboveFigure 1 the sorting circuit 130 shown below (hereinafter simply referred to as the first sorting circuit) and Figures 5 - 9 the sorting circuit 530 shown in any of the implementation manners below (hereinafter simply referred to as the second sorting circuit). The method includes the following steps:

[0275] S1401, arranging the data to be sorted into multiple ordered sequences based on the second sorting circuit.

[0276] Exemplarily, assuming there are 512 data to be sorted, and the second sorting circuit can sort 32 data each time (i.e., J = 32), then these 512 data can be divided into 16 groups, with 32 data in each group. Then, use the second sorting circuit to sort the data in each group, and output 16 ordered sequences with a length of 32.

[0277] S1402, arranging the multiple ordered sequences into one ordered sequence based on the first sorting circuit.

[0278] Exemplarily, assuming there are 16 ordered sequences with a length of 32, and the first sorting circuit can arrange 8 ordered sequences into one ordered sequence each time (i.e., M = 8), then these 16 ordered sequences can be divided into 2 groups, with 8 ordered sequences in each group. Then, use the first sorting circuit to sort the 8 ordered sequences in each group, and output 2 ordered sequences with a length of 256. Finally, use the first sorting circuit to sort these 2 ordered sequences with a length of 256, and output 1 ordered sequence with a length of 512.

[0279] Among them, the specific implementation process of the second sorting circuit arranging multiple data to be sorted into one ordered sequence can refer to the above Figure 13 shown sorting method. The specific implementation process of the first sorting circuit arranging M ordered sequences into one ordered sequence can refer to the above Figure 12 shown sorting method, which will not be elaborated here.

[0280] The above Figures 1 - 14 respectively illustrate the implementation manners of two processors. Based on the above Figures 1 - 14 two processors shown, the embodiment of the present application provides another sorting method to sort the data to be sorted using multiple processing cores of the processor, so as to further improve the sorting efficiency.

[0281] Please refer to Figure 15 , this method can be applied to an electronic device, which includes a processor. The processor includes multiple processing cores, and each processing core includes: the above Figure 1 , Figure 2 shown sorting circuit 130 and Figures 5 - 9 the sorting circuit 530 shown in any of the implementation manners below, or each processing core includes: the above Figure 1、 Figure 2 The sorting circuit 130 shown in FIG. 1 includes the following steps:

[0282] S1501: The control circuit reads a second instruction from the instruction storage circuit and decodes the second instruction, wherein the decoded second instruction includes a storage address of the data to be sorted.

[0283] S1502: The control circuit sends the decoded second instruction to the multiple processing cores.

[0284] S1503 , the multiple processing cores respond to the decoded second instruction and read the data to be sorted according to the storage address.

[0285] S1504, multiple processing cores sort the data to be sorted.

[0286] The data to be sorted may include multiple sequences, and the sorting circuit is used to read M sequences from the multiple sequences, and if the M sequences are all ordered sequences, then output an ordered sequence with a length of M*N, or if there is an unordered sequence among the M sequences, then output M ordered sequences with a length of N. The specific implementation process can refer to the above Figure 2 The process of sorting data by the sorting circuit 130 is not described in detail here.

[0287] In a possible design, the multiple processing cores may sort the data to be sorted, which may include: the multiple processing cores iteratively sort the data to be sorted until the data to be sorted is arranged into an ordered sequence. In each iteration, the multiple processing cores are used to arrange the N ordered sequences outputted in the previous iteration into An ordered sequence, where M is an integer greater than 1.

[0288] Optionally, iteratively sorting the data to be sorted by the multiple processing cores until the data to be sorted is arranged into an ordered sequence may include: determining a number E of the multiple processing cores to be started, where E is an integer greater than 1. Arranging the data to be sorted into an ordered sequence based on the E processing cores.

[0289] For example, the number of processors to be started, E, is determined based on the amount of data to be sorted (denoted as Q), the number of processing cores (denoted as P), and the minimum amount of data processed by each processing core (denoted as T). For example, when Q / P is greater than or equal to T, E=P; when Q / P is less than T, in, is the rounding symbol, for example, Indicates rounding up Q / T.

[0290] Optionally, arranging the data to be sorted into an ordered sequence based on E processing cores may include the following steps:

[0291] Step 5: Assign the data to be sorted to each of the E processing cores.

[0292] Optionally, evenly distribute the data to be sorted to each of the E processing cores. For example, assume that the amount of data to be sorted assigned to each processing core is F. Then, when Q / P is greater than or equal to T, F = Q / P; when Q / P is less than T, F = Q / E.

[0293] Step 6: Each processing core arranges the assigned data to be sorted into 1 ordered sequence.

[0294] Among them, the E processing cores arrange the assigned data to be sorted into E ordered sequences. When each processing core includes both sorting circuit 130 and sorting circuit 530, the specific implementation process of each processing core arranging the data to be sorted into 1 ordered sequence can refer to the sorting method shown above. Figure 14 When each processing core includes the sorting circuit 130 shown above. Figure 1 The specific implementation process of each processing core arranging the data to be sorted into 1 ordered sequence can refer to the combined implementation of Method 1 and Method 2 above to arrange M ordered sequences into one ordered sequence, which will not be elaborated here.

[0295] Step 7: Based on processing cores among the multiple processing cores, arrange the E ordered sequences into ordered sequences. Among them, M is the number of the first buffers 220 in the sorting circuit 130 shown in Figure 2 above.

[0296] Step 8: If is determined as E, return to execute Step 7; otherwise, determine that the sorting is completed and output the ordered sequence corresponding to the data to be sorted. For example, assume E = 18 and M = 4. Then, in the first round of sorting, based on

[0297] processing cores, arrange 18 ordered sequences into 5 ordered sequences. Among them, 4 processing cores can respectively arrange 4 of the 18 ordered sequences into 1 ordered sequence, and 1 processing core can arrange the remaining 2 of the 18 ordered sequences into 1 ordered sequence. Then, since 5 > 1, 5 is determined as E and enter the second round of sorting, that is, based on processing cores, arrange the 5 ordered sequences obtained from the previous round of sorting into 2 ordered sequences. After that, since 2 > 1, 2 is determined as E and enter the third round of sorting, that is, based on processing cores, arrange the 2 ordered sequences obtained from the previous round of sorting into 1 ordered sequence. Then, since 1 = 1, determine that the sorting is completed and output the ordered sequence corresponding to the data to be sorted. A processing core arranges the two ordered sequences sorted in the previous round into one ordered sequence. Finally, since Therefore, it is determined that the sorting is completed, and one ordered sequence corresponding to the data to be sorted is output. In this way, during the sorting process of the data to be sorted, the number of sorting circuits participating in the sorting can be gradually reduced, and the occupied processing resources can be reduced.

[0298] It should be understood that if the amount of data to be sorted is too large (such as more than 1 million data), Figure 15 the sorting method shown can perform sorting simultaneously with multiple processing cores, improving the sorting efficiency.

[0299] In addition, when executing Figure 15 the method shown, if TOPK sorting needs to be performed on the data to be sorted, then each processing core can arrange the allocated data to be sorted into one ordered sequence through TOPK sorting. Among them, the implementation process of the processing core performing TOPK sorting can refer to the description in the sorting circuit 130 shown in Figure 2 above, and will not be elaborated here.

[0300] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A processor, characterized in that, Including: An instruction storage circuit, a control circuit, and a sorting circuit, where the instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the sorting circuit; The control circuit is configured to read a first instruction from the instruction storage circuit and decode the first instruction; the decoded first instruction includes storage addresses of M first sequences, the length of each first sequence is N, M is an integer greater than 1, and N is an integer greater than 1; The control circuit is further configured to send the decoded first instruction to the sorting circuit; The sorting circuit is configured to respond to the decoded first instruction and perform the following steps: read M first sequences according to the storage addresses, and if the M first sequences are all ordered sequences, output an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, output M ordered sequences with a length of N.

2. The processor according to claim 1, wherein The sorting circuit includes: a sorting controller, a sorter, and M first buffers, where the sorting controller is coupled to the M first buffers, and the M first buffers are all coupled to the sorter; The sorting controller is configured to read M first sequences according to the storage addresses and store the M first sequences in the M first buffers; each first buffer stores one first sequence; The sorter is configured to, if the M first sequences are all ordered sequences, read an ordered sequence with a length of M*N from the M first buffers, or if there are unordered sequences among the M first sequences, read M ordered sequences with a length of N from the M first buffers.

3. The processor according to claim 2, wherein The sorter is further configured to, if the M first sequences are all ordered sequences, read an ordered sequence with a length of M*N from the M first buffers according to a first reading rule; the first reading rule is: read the data arranged first in the M first buffers each time; or The sorter is further configured to, if there are unordered sequences among the M first sequences, read M ordered sequences with a length of N from the M first buffers according to a second reading rule; the second reading rule is: read an ordered sequence with a length of N in the M first buffers each time.

4. The processor according to claim 2 or 3, characterized in that, The sorting circuit further includes: a second buffer, and the second buffer is coupled to the sorting controller; The sorting controller is configured to read M first sequences according to the storage addresses and store the M first sequences in the second buffer; The sorting controller is further configured to move the M first sequences from the second buffer to the M first buffers.

5. The processor according to claim 4, wherein The sorting controller includes a first read / write controller and a second read / write controller, the first read / write controller is coupled to the second read / write controller, the second buffer is respectively coupled to the first read / write controller and the second read / write controller, and the M first buffers are all coupled to the first read / write controller; The second read / write controller is configured to read M of the first sequences according to the storage address and store the M first sequences in the second buffer; The first read / write controller is configured to move the M first sequences from the second buffer to the M first buffers.

6. The processor according to claim 5, wherein The first read / write controller is further configured to send information on the amount of data moved to the second read / write controller when moving the M first sequences.

7. The processor according to claim 5 or 6, characterized in that, The sorting controller further includes a third read / write controller, and the third read / write controller is respectively coupled to the sorter and the second buffer; The third read / write controller is configured to move the ordered sequence output by the sorter to the second buffer.

8. A sorting method, characterized in that, Applied to a processor, the processor includes: an instruction storage circuit, a control circuit, and a sorting circuit, the instruction storage circuit is coupled to the control circuit, and the control circuit is coupled to the sorting circuit; The method includes: The control circuit reads a first instruction from the instruction storage circuit and decodes the first instruction; the decoded first instruction includes the storage address of M first sequences, the length of each first sequence is N, M is an integer greater than 1, and N is an integer greater than 1; The control circuit sends the decoded first instruction to the sorting circuit; The sorting circuit responds to the decoded first instruction, reads M first sequences according to the storage address, and if the M first sequences are all ordered sequences, outputs an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, outputs M ordered sequences with a length of N.

9. The method according to claim 8, wherein The sorting circuit includes: a sorting controller, a sorter, and M first buffers, the sorting controller is coupled to the M first buffers, and the M first buffers are all coupled to the sorter; The sorting circuit responds to the decoded first instruction, reads M first sequences according to the storage address, and if the M first sequences are all ordered sequences, outputs an ordered sequence with a length of M*N, or if there are unordered sequences among the M first sequences, outputs M ordered sequences with a length of N, including: The sorting controller reads M first sequences according to the storage address and stores the M first sequences in the M first buffers; each first buffer stores one first sequence; If the M first sequences are all ordered sequences, the sorter reads an ordered sequence with a length of M*N from the M first buffers; or If there are unordered sequences among the M first sequences, the sorter reads M ordered sequences with a length of N from the M first buffers.

10. The method according to claim 9, characterized in that, If the M first sequences are all ordered sequences, the sorter reads an ordered sequence with a length of M*N from the M first buffers, including: If the M first sequences are all ordered sequences, the sorter reads out an ordered sequence of length M*N from the M first buffers according to the first reading rule; the first reading rule is: read out the data ranked first each time from the M first buffers; If there are unordered sequences among the M first sequences, the sorter reads out M ordered sequences of length N from the M first buffers, including: If there are unordered sequences among the M first sequences, the sorter reads out M ordered sequences of length N from the M first buffers according to the second reading rule; the second reading rule is: read out an ordered sequence of length N from the M first buffers each time.

11. The method according to claim 9 or 10, characterized in that, The sorting circuit further includes: a second buffer, and the second buffer is coupled to the sorting controller; The sorting controller reads out M first sequences according to the storage address and stores the M first sequences in the M first buffers, including: The sorting controller reads out M first sequences according to the storage address and stores the M first sequences in the second buffer; The sorting controller moves the M first sequences from the second buffer to the M first buffers.

12. The method according to claim 11, wherein The sorting controller includes a first read-write controller and a second read-write controller, the first read-write controller is coupled to the second read-write controller, the second buffer is respectively coupled to the first read-write controller and the second read-write controller, and the M first buffers are all coupled to the first read-write controller; The sorting controller reads out M first sequences according to the storage address and stores the M first sequences in the second buffer, including: The second read-write controller reads out M first sequences according to the storage address and stores the M first sequences in the second buffer; The sorting controller moves the M first sequences from the second buffer to the M first buffers, including: The first read-write controller moves the M first sequences from the second buffer to the M first buffers.

13. The method according to claim 12, wherein The method further includes: When moving the M first sequences, the first read-write controller sends information on the amount of data moved to the second read-write controller.

14. The method according to claim 12 or 13, characterized in that, The sorting controller further includes a third read-write controller, and the third read-write controller is respectively coupled to the sorter and the second buffer; The method further includes: The third read-write controller moves the ordered sequence output by the sorter to the second buffer.

15. An electronic device, characterized in that, The electronic device includes a processor according to any one of claims 1-7.

Images