Display panel and display device

Abstract

This disclosure relates to a display panel and a display device. The display panel includes at least one sensing module disposed in a peripheral area. The sensing module includes at least one sensing unit, and the sensing unit includes a sensing transistor. A first terminal of the sensing transistor receives an electrical signal, a gate of the sensing transistor receives a first control signal, and a second terminal of the sensing transistor outputs a light-sensitive signal. When the sensing transistor receives the first control signal, the gate of the sensing transistor is set to an off state. When illuminated, the voltage output from the drain of the sensing transistor increases. The voltage change is read as a light-sensitive signal. Based on the response results to different wavelengths and combined with the spectral characteristics of common ambient light, ambient light is identified. Based on this function, the display color temperature can be optimized to improve the display effect.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Even with the same color temperature set on the display panel, different ambient lighting conditions will result in different visual effects, leading to color discrepancies and other issues. To improve the viewing experience, the display color temperature needs to be adjusted for different ambient lighting conditions.

[0003] Currently, the use of preset color temperature values ​​results in poor real-time performance and low adjustment accuracy for color temperature.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Public content

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0007] According to one aspect of this disclosure, a display panel is provided, including a display area and a peripheral area outside the display area. The display panel further includes a substrate and a sensing module. The sensing module is disposed on one side of the substrate and located in the peripheral area. The sensing module includes a sensing unit, which includes a sensing transistor. A first terminal of the sensing transistor receives an electrical signal, and a control terminal of the sensing transistor receives a first control signal. The sensing transistor is used to receive ambient light and convert the ambient light into an electrical signal, which is output from a second terminal of the sensing transistor.

[0008] In one embodiment of this disclosure, the sensing unit further includes a storage capacitor and a switching transistor. A first terminal of the storage capacitor is connected to a second terminal of the sensing transistor, and the second terminal of the storage capacitor is grounded. The storage capacitor stores the photosensitive signal output from the second terminal of the sensing transistor. A first terminal of the switching transistor is connected to a first terminal of the storage capacitor, and a control terminal of the switching transistor receives a second control signal to acquire the photosensitive signal stored in the storage capacitor.

[0009] In one embodiment of this disclosure, the sensing module includes multiple sensing units. The first terminals of the sensing transistors of the multiple sensing units all receive electrical signals. The control terminals of the sensing transistors of the multiple sensing units sequentially receive a first control signal, and the control terminals of the switching transistors of the multiple sensing units sequentially receive a second control signal, so as to sequentially acquire the photosensitive signals stored in the multiple storage capacitors.

[0010] In one embodiment of this disclosure, the sensing module includes a first sensing unit and a second sensing unit, wherein the sensing transistor of the first sensing unit and the sensing transistor of the second sensing unit are both top-gate polysilicon transistors with transparent gates.

[0011] In one embodiment of this disclosure, a filter layer is provided on the side of the first sensing unit away from the substrate, and the orthographic projection of the channel region of the sensing transistor of the first sensing unit onto the substrate is located within the orthographic projection of the filter layer onto the substrate. The filter layer is used to transmit monochromatic light.

[0012] In one embodiment of this disclosure, the distance between the edge of the filter layer projected orthogonally onto the substrate and the edge of the channel region of the sensing transistor of the first sensing unit projected orthogonally onto the substrate is greater than 3 μm.

[0013] In one embodiment of this disclosure, the sensing module further includes a third sensing unit, wherein the sensing transistor of the third sensing unit is a bottom-gate metal-oxide transistor.

[0014] In one embodiment of this disclosure, the switching transistor is a bottom-gate transistor or a top-gate transistor with a transparent gate. The display panel also includes a plurality of light-shielding portions, which are disposed on the side of the switching transistor away from the substrate. The orthographic projection of the channel region of the switching transistor onto the substrate is located within the orthographic projection of the corresponding light-shielding portion onto the substrate.

[0015] In one embodiment of this disclosure, the distance between the edge of the light-shielding portion projected onto the substrate and the edge of the channel region of the switching transistor projected onto the substrate is greater than 3 μm.

[0016] In one embodiment of this disclosure, the switching transistor is a top-gate transistor with an opaque gate, and the channel region of the switching transistor is projected onto the substrate in the same direction as the gate.

[0017] In one embodiment of this disclosure, the switching transistor is an oxide transistor or a polysilicon transistor.

[0018] In one embodiment of this disclosure, the sensing module has multiple sensing units, and the sensing transistors of the multiple sensing units are bottom-gate polysilicon transistors or top-gate polysilicon transistors with transparent gates. The display panel also includes a color filter layer, which is disposed on the side of the filter layer away from the substrate. The color filter layer includes multiple filter portions of different colors, each filter portion corresponding to a sensing transistor. The orthographic projection of the channel region of the sensing transistor onto the substrate is located within the orthographic projection of the filter portion onto the substrate.

[0019] In one embodiment of this disclosure, the color filter layer further includes a light-blocking portion, wherein the orthographic projection of the channel region of the switching transistor onto the substrate is located within the orthographic projection of the light-blocking portion onto the substrate.

[0020] In one embodiment of this disclosure, the spacing between two adjacent sensing units is greater than 6 μm; the spacing between adjacent sensing transistors and switching transistors within each sensing unit is greater than 6 μm.

[0021] In one embodiment of this disclosure, the length of the channel region of the sensing transistor along a first direction is greater than the length of the channel region of the sensing transistor along a second direction. The first direction and the second direction are perpendicular to each other. The first direction is the width direction of the sensing transistor, and the second direction is the length direction of the sensing transistor.

[0022] In one embodiment of this disclosure, there are multiple sensing modules, which are evenly distributed in the peripheral area along the outline of the display panel.

[0023] According to another aspect of this disclosure, a display device is provided, including the display panel described in one aspect of this disclosure.

[0024] In this disclosed display panel, when the gate of the sensing transistor receives a first control signal, the gate of the sensing transistor is set to the off state. When illuminated, the voltage output from the drain of the sensing transistor increases, and the voltage change is read as a photosensitizing signal. Based on the response results to different wavelengths and the spectral characteristics of common ambient light, ambient light is identified. Based on this function, the display color temperature can be optimized, improving the display effect.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a top view of the display panel involved in an embodiment of this disclosure.

[0028] Figure 2 This is a circuit diagram of the sensing module involved in an embodiment of this disclosure.

[0029] Figures 3 to 9 This is a schematic diagram illustrating the manufacturing process of the first type of display panel according to an embodiment of this disclosure.

[0030] Figure 10 This is a top view of the first sensing transistor of the first type of display panel according to an embodiment of this disclosure.

[0031] Figure 11 This is a top view of the second sensing transistor of a first type of display panel according to an embodiment of this disclosure.

[0032] Figure 12 This is a top view of the third sensing transistor of the first type of display panel according to an embodiment of this disclosure.

[0033] Figure 13 This is a top view of the switching transistor of the first type of display panel according to an embodiment of this disclosure.

[0034] Figures 14 to 17 This is a schematic diagram illustrating the manufacturing process of the second type of display panel according to an embodiment of this disclosure.

[0035] Figure 18 This is a schematic diagram of the structure of a third type of display panel according to an embodiment of this disclosure.

[0036] Figure 19 This is a schematic diagram of the structure of the fourth type of display panel according to an embodiment of this disclosure.

[0037] Figure 20 This is a schematic diagram of the structure of the fifth type of display panel according to an embodiment of this disclosure.

[0038] Explanation of reference numerals in the attached figures:

[0039] 100. Sensing module; 101. First sensing unit; 1011. First sensing transistor; 1012. First switching transistor; 1013. First storage capacitor; 102. Second sensing unit; 1021. Second sensing transistor; 1022. Second switching transistor; 1023. Second storage capacitor; 103. Third sensing unit; 1031. Third sensing transistor; 1032. Third switching transistor; 1033. Third storage capacitor;

[0040] 1. Substrate; 2. Buffer layer; 301. First active portion; 302. Second active portion; 303. Third active portion; 304. Fourth active portion; 305. Fifth active portion; 306. Sixth active portion; 307. Seventh active portion; 4. Gate insulating layer; 501. First gate; 502. Second gate; 503. Third gate; 504. Fourth gate; 505. Fifth gate; 506. Sixth gate; 507. Seventh gate; 508. Eighth gate; 509. Ninth gate; 6. Dielectric layer; 701. First drain; 702. First source; 703. Second drain; 704. Second source 705, Third drain; 706, Third source; 707, Fourth drain; 708, Fourth source; 709, Fifth drain; 710, Fifth source; 711, Sixth drain; 712, Sixth source; 713, Seventh drain; 714, Seventh source; 10, Protective layer; 11, Planarization layer; 120, First electrode; 121, First light-shielding part; 122, Second light-shielding part; 123, Third light-shielding part; 13, Pixel defining layer; 14, Color filter layer; 141, First filter part; 142, Second filter part; 143, Third filter part; 144, Light-blocking part; 15, Optical adhesive layer; 16, Cover plate. Detailed Implementation

[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0042] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0043] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0044] As living standards improve, people have increasingly higher demands for display quality. Wide color gamut, high contrast, high refresh rate, and multi-level brightness and color temperature adjustment are all future development directions for displays. Color temperature is an indicator for evaluating the color tone of a display; the lower the color temperature, the warmer the color tone, while the higher the color temperature, the cooler the color tone. Setting an appropriate display color temperature can greatly enhance the viewing experience.

[0045] However, even with the same color temperature setting, monitors will appear differently to the human eye under varying ambient lighting conditions, resulting in color discrepancies and other issues. To improve the viewing experience, the display color temperature needs to be adjusted for different ambient lighting conditions.

[0046] like Figures 1 to 20 As shown, this embodiment of the disclosure provides a display panel capable of adjusting the display color temperature. The display panel includes a display area A and a peripheral area B outside the display area A. The display panel also includes a substrate 1 and at least one sensing module 100. The sensing module 100 is disposed on one side of the substrate 1 and located in the peripheral area. The sensing module 100 includes at least one sensing unit, which includes a sensing transistor. The first terminal of the sensing transistor receives an electrical signal, and the control terminal of the sensing transistor receives a first control signal. The sensing transistor is used to receive ambient light and convert the ambient light into an electrical signal, which is output from the second terminal of the sensing transistor.

[0047] When the gate of the sensing transistor receives the first control signal, the gate of the sensing transistor is set to the off state. When exposed to light, the voltage output from the drain of the sensing transistor increases. The voltage change is read as a photosensitizing signal. Based on the response to different wavelengths and the spectral characteristics of common ambient light, the ambient light is identified. Based on this function, the display color temperature can be optimized to improve the display effect.

[0048] It should be noted that electrical signals include, but are not limited to, voltage signals, and can also be set as current signals.

[0049] like Figure 1 As shown, the display panel includes a display area and a peripheral area outside the display area. The display panel also includes a substrate 1 and four sensing modules 100. The four sensing modules 100 are disposed on one side of the substrate 1 and are evenly distributed in the peripheral area along the outline of the display panel.

[0050] like Figure 2 As shown, the sensing module 100 includes a sensing unit, which includes a sensing transistor, a storage capacitor, and a switching transistor. The first terminal of the sensing transistor receives an electrical signal vdd, and the control terminal of the sensing transistor receives a first control signal vbias. The second terminal of the sensing transistor is used to output a photosensitive signal. The first terminal of the storage capacitor is connected to the second terminal of the sensing transistor, and the second terminal of the storage capacitor is grounded. It is used to store the photosensitive signal output by the second terminal of the sensing transistor. The first terminal of the switching transistor is connected to the first terminal of the storage capacitor, and the control terminal of the switching transistor receives a second control signal to acquire the photosensitive signal stored in the storage capacitor.

[0051] The number of sensing units can be three, including a first sensing unit 101, a second sensing unit 102, and a third sensing unit 103. The sensing transistor of the first sensing unit 101 is the first sensing transistor 1011, the sensing transistor of the second sensing unit 102 is the second sensing transistor 1021, and the sensing transistor of the third sensing unit 103 is the third sensing transistor 1031. The switching transistor of the first sensing unit 101 is the first switching transistor 1012, the switching transistor of the second sensing unit 102 is the second switching transistor 1022, and the switching transistor of the third sensing unit 103 is the third switching transistor 1032. The storage capacitor of the first sensing unit 101 is the first storage capacitor 1013, the storage capacitor of the second sensing unit 101 is the second storage capacitor 1023, and the storage capacitor of the third sensing unit 101 is the third storage capacitor 1033.

[0052] The first terminal of the sensing transistor in each of the three sensing units receives an electrical signal. The control terminals of the sensing transistors in the three sensing units sequentially receive a first control signal, and the control terminals of the switching transistors in the three sensing units sequentially receive a second control signal, so as to sequentially acquire the photosensitive signals stored in the three storage capacitors. It should be noted that the number of sensing units can also be increased or decreased according to the photosensitive requirements, for example, the number of sensing units can be set to two or four.

[0053] The control process of the first sensing unit 101 is described below. When the second control signal is stopped from being input by the first gate line Gate1, the first switching transistor 1012 is turned off. At this time, the electrical signal vdd is set to V1, and the first control signal vbias controls the first sensing transistor 1011 to turn on. The voltage at point A1 becomes V1 and is stored in the first storage capacitor 1013.

[0054] When the input of the first control signal vbias is stopped, the first sensing transistor 1011 is turned off, and the electrical signal vdd is set to V2. When the first sensing transistor 1011 is exposed to light, the leakage current increases, and the voltage at point A1 changes from V1 to V2. The second terminal of the first sensing transistor 1011 outputs a photosensitive signal, which is the voltage change at point A1. The first storage capacitor 1013 stores the photosensitive signal output from the second terminal of the first sensing transistor 1011. The second control signal is input through the first gate line Gate1, and the second control signal controls the first switching transistor 1012 to turn on. The voltage change at point A1 is read through the data line Date1 connected to the drain of the first switching transistor 1012. Different wavelengths of light can be detected based on the voltage change. The specific detection process is not covered by the embodiments of this disclosure and will not be described in detail here.

[0055] The control process of the second sensing unit 102 is described below. When the second control signal is stopped from being input by the second gate line Gate2, the second switching transistor 1022 is turned off. At this time, the electrical signal vdd is set to V1, and the first control signal vbias controls the second sensing transistor 1021 to turn on. The voltage at point A2 becomes V1 and is stored in the second storage capacitor 1023.

[0056] When the first control signal vbias is stopped, the second sensing transistor 1021 is turned off, and the electrical signal vdd is set to V2. When the second sensing transistor 1021 is exposed to light, the leakage current increases, and the voltage at point A2 changes from V1 to V2. The second terminal of the second sensing transistor 1021 outputs a photosensitive signal, which is the voltage change at point A2. The second storage capacitor 1023 stores the photosensitive signal output from the second terminal of the second sensing transistor 1021. The second control signal is input through the second gate line Gate2. The second control signal controls the second switching transistor 1022 to turn on. The voltage change at point A2 is read through the data line Date2 connected to the drain of the second switching transistor 1022.

[0057] The control process of the third sensing unit 103 is described below. When the second control signal is stopped by the third gate line Gate3, the third switching transistor 1032 is turned off. At this time, the electrical signal vdd is set to V1, and the first control signal vbias controls the third sensing transistor 1031 to turn on. The voltage at point A3 becomes V1 and is stored in the third storage capacitor 1033.

[0058] When the first control signal vbias is stopped, the third sensing transistor 1031 is turned off, and the electrical signal vdd is set to V2. When the third sensing transistor 1031 is exposed to light, the leakage current increases, and the voltage at point A3 changes from V1 to V2. The second terminal of the third sensing transistor 1031 outputs a photosensitive signal, which is the voltage change at point A3. The photosensitive signal output from the second terminal of the first storage sensing transistor of the third storage capacitor 1033 is input to the second control signal via the third gate line Gate3. The second control signal controls the third switching transistor 1032 to turn on, and the voltage change at point A3 is read through the data line Date3 connected to the drain of the third switching transistor 1032.

[0059] By controlling the opening and closing sequence of the first switching transistor 1012, the second switching transistor 1022, and the third switching transistor 1032, the timing sequence for reading the voltage changes at points A1, A2, and A3 can be controlled.

[0060] Figure 9 The basic structure of a first type of display panel is shown. The display panel has a display area and a peripheral area outside the display area. The display panel includes a substrate 1. A buffer layer 2 is provided on one side of the substrate 1. A driving layer group is provided on the side of the buffer layer 2 away from the substrate 1. The driving layer group in the peripheral area includes a first sensing transistor, a first switching transistor, a second sensing transistor, a second switching transistor, a third sensing transistor, and a third switching transistor.

[0061] It should be noted that, for ease of description, a first sensing transistor is used instead of the sensing transistor of the first sensing unit 101, a second sensing transistor is used instead of the sensing transistor of the second sensing unit 102, a third sensing transistor is used instead of the sensing transistor of the third sensing unit 103, a first switching transistor is used instead of the switching transistor of the first sensing unit 101, a second switching transistor is used instead of the switching transistor of the second sensing unit 102, and a third switching transistor is used instead of the switching transistor of the third sensing unit 103.

[0062] The first and second sensing transistors are both top-gate polysilicon transistors with transparent gates, while the third sensing transistor is a bottom-gate metal-oxide transistor. A filter layer is provided on the side of the first sensing unit 101 facing away from the substrate 1, and the orthographic projection of the channel region of the first sensing transistor onto the substrate 1 lies within the orthographic projection of the filter layer onto the substrate 1. The filter layer transmits monochromatic light, such as red or green light. The channel region of the second sensing transistor can absorb the full spectrum of visible light, while the third sensing transistor, being a bottom-gate metal-oxide transistor, only absorbs ultraviolet light.

[0063] The first, second, and third switching transistors are all bottom-gate metal-oxide transistors (MOS transistors). These MOS transistors can be arranged together, i.e., adjacent to each other. Alternatively, they can be spaced apart, i.e., the first switching transistors are all located on the side of the first sensing transistor that is furthest from or closest to the display area, the second switching transistors are all located on the side of the second sensing transistor that is furthest from or closest to the display area, and the third switching transistors are all located on the side of the third sensing transistor that is furthest from or closest to the display area. A first light-shielding portion 121 is provided on the side of the first switching transistor furthest from the substrate 1, and the orthographic projection of the first light-shielding portion 121 onto the substrate 1 completely covers the orthographic projection of the channel region of the first switching transistor onto the substrate 1. A second light-shielding portion 122 is provided on the side of the second switching transistor furthest from the substrate 1, and the orthographic projection of the second light-shielding portion 122 onto the substrate 1 completely covers the orthographic projection of the channel region of the second switching transistor onto the substrate 1. The third sensing unit 103 has a third light-shielding part 123 on the side of the switching transistor away from the substrate. The orthogonal projection of the third light-shielding part 123 on the substrate completely covers the orthogonal projection of the channel region of the third switching transistor on the substrate.

[0064] The driving layer group includes a first active layer, a gate insulating layer 4, a first gate layer, a dielectric layer 6, a second active layer, a first source-drain layer, a second source-drain layer, and a protective layer 10. The first active layer is disposed on one side of the substrate 1. The gate insulating layer 4 is disposed on the side of the first active layer away from the substrate 1, covering the first active layer and the substrate 1. The first gate layer is disposed on the side of the gate insulating layer 4 away from the substrate 1. The dielectric layer 6 is disposed on the side of the gate away from the substrate 1, covering the first gate layer and the gate insulating layer 4. The second active layer is disposed on the side of the dielectric layer 6 away from the substrate 1. The first source-drain layer is disposed on the side of the dielectric layer 6 away from the substrate 1. The second source-drain layer is disposed on the side of the second active layer away from the substrate 1. The protective layer 10 covers the first source-drain layer and the second source-drain layer. The first active layer is a polycrystalline silicon layer, the second active layer is a metal oxide layer that only transmits ultraviolet light, such as indium gallium zinc oxide (IGZO); the first gate layer is a transparent conductive layer, such as indium tin oxide (ITO).

[0065] The first active layer of the peripheral region includes a first active portion 301 and a second active portion 302. The first gate layer of the peripheral region includes a first gate 501, a second gate 502, a third gate 503, a fourth gate 504, a fifth gate 505, and a sixth gate 506. The first source-drain layer of the peripheral region includes a first source 702 and a first drain 701, a second source 704, and a second drain 703. The orthographic projection of the first gate 501 onto the substrate 1 is located within the orthographic projection of the first active portion 301 onto the substrate 1. The orthographic projection of the second gate 502 onto the substrate 1 is located within the orthographic projection of the second active portion 302 onto the substrate 1. The first source 702 and the first drain 701 are respectively connected to the first active portion 301, and the second source 704 and the second drain 703 are respectively connected to the second active portion 302.

[0066] The second active layer includes a third active portion 303, a fourth active portion 304, a fifth active portion 305, and a sixth active portion 306. The second source-drain layer includes a third source 706 and a third drain 705, a fourth source 708 and a fourth drain 707, a fifth source 710 and a fifth drain 709, and a sixth source 712 and a sixth drain 711. The orthographic projection of the third gate 503 onto the substrate 1 is located within the orthographic projection of the third active portion 303 onto the substrate 1. The orthographic projection of the fourth gate 504 onto the substrate 1 is located within the orthographic projection of the fourth active portion 304 onto the substrate 1. The orthographic projection of the fifth gate 505 onto the substrate 1 is located within the orthographic projection of the fifth active portion 305 onto the substrate 1. The orthographic projection of the sixth gate 506 onto the substrate 1 is located within the orthographic projection of the sixth active portion 306 onto the substrate 1. The third source 706 and the third drain 705 are connected to the third active part 303, the fourth source 708 and the fourth drain 707 are connected to the fourth active part 304, the fifth source 710 and the fifth drain 709 are connected to the fifth active part 305, and the sixth source 712 and the sixth drain 711 are connected to the sixth active part 306.

[0067] like Figure 10 As shown, the first sensing transistor includes a first active portion 301, a first gate 501, a first source 702, and a first drain 701; as Figure 11 As shown, the second sensing transistor includes a second active portion 302, a second gate 502, a second source 704, and a second drain 703; as Figure 12 As shown, the third sensing transistor includes a third active portion 303, a third gate 503, a third source 706, and a third drain 705; as Figure 13As shown, the first switching transistor includes a fourth active portion 304, a fourth gate 504, a fourth source 708, and a fourth drain 707; the second switching transistor includes a fifth active portion 305, a fifth gate 505, a fifth source 710, and a fifth drain 709; and the third switching transistor includes a sixth active portion 306, a sixth gate 506, a sixth source 712, and a sixth drain 711.

[0068] The filter layer can be a planarization layer 11, which is disposed on the side of the protective layer 10 away from the substrate 1. The orthographic projection of the channel region of the first sensing transistor onto the substrate 1 lies within the orthographic projection of the planarization layer 11 onto the substrate 1. (See also...) Figure 10 The distance between the edge of the filter layer in the orthographic projection of the substrate 1 and the edge of the active layer of the first sensing transistor in the orthographic projection of the substrate 1 is greater than 3 μm. That is, the distance between the edge of the filter layer in the orthographic projection of the substrate 1 and the channel region of the first active portion 301 is greater than 3 μm, so as to ensure the filtering effect. The planarization layer 11 can transmit monochromatic light, which includes, but is not limited to, red light, and can also be blue light or green light.

[0069] The first light-shielding portion 121, the second light-shielding portion 122, and the third light-shielding portion 123 are disposed on the side of the planarization layer 11 away from the substrate 1. The orthographic projection of the first light-shielding portion 121 onto the substrate 1 must at least cover the orthographic projection of the channel region of the fourth active portion 304 onto the substrate 1. The orthographic projection of the second light-shielding portion 122 onto the substrate 1 must at least cover the orthographic projection of the channel region of the fifth active portion 305 onto the substrate 1. The orthographic projection of the third light-shielding portion 123 onto the substrate 1 must at least cover the orthographic projection of the channel region of the sixth active portion 306 onto the substrate 1. See also Figure 13 The distance between the first light-shielding portion 121 projected onto the substrate 1 and the edge of the channel region of the fourth active portion 304 projected onto the substrate 1 is greater than 3 μm. Similarly, the distance between the second light-shielding portion 122 projected onto the substrate 1 and the edge of the channel region of the fifth active portion 305 projected onto the substrate 1 is greater than 3 μm, and the distance between the third light-shielding portion 123 projected onto the substrate 1 and the edge of the channel region of the sixth active portion 306 projected onto the substrate 1 is greater than 3 μm, to ensure a light-shielding effect.

[0070] The driving layer group of the display area includes driving transistors. The first active layer of the display area also includes a seventh active portion 307, the first gate layer also includes a seventh gate 507, and the first source-drain layer also includes a seventh source 714 and a seventh drain 713. The orthographic projection of the seventh gate 507 onto the substrate 1 is located within the orthographic projection of the seventh active portion 307 onto the substrate 1. The seventh source 714 and the seventh drain 713 are respectively connected to the seventh active portion 307. A first electrode 120 is provided on the side of the planarization layer 11 away from the substrate 1. The first electrode 120 passes through vias on the planarization layer 11 and the protective layer 10 and is connected to the seventh drain 713. The first electrode 120 is disposed in the same layer and with the same material as the first light-shielding portion 121, the second light-shielding portion 122, and the third light-shielding portion 123.

[0071] like Figures 3 to 9 As shown, the fabrication process of this display panel is as follows: First, a buffer layer 2 is deposited on a substrate 1. A polysilicon layer is then deposited and patterned on the side of the buffer layer 2 away from the substrate 1 to form a first active layer. The first active layer includes a first active portion 301, a second active portion 302, and a seventh active portion 307. A gate insulating layer 4 is then deposited on the first active layer. A first gate layer, which is a transparent conductive layer, is then deposited on the gate insulating layer 4. The first gate layer includes a first gate 501, a second gate 502, a third gate 503, a fourth gate 504, a fifth gate 505, a sixth gate 506, and a seventh gate 507. Photoresist is coated and photolithography is performed. Using the first gate layer and the photoresist as a mask, an N+ doping process is carried out, forming doped regions in the first active portion 301, the second active portion 302, and the seventh active portion 307, respectively. A dielectric layer 6 is deposited on the side of the first gate layer away from the substrate 1, and the dielectric layer 6 covers the first gate layer and the gate insulating layer 4.

[0072] A second active layer is formed on the side of dielectric layer 6 away from the substrate 1, and then dielectric layer 6 is patterned. A first source-drain layer and a second source-drain layer are formed. The first source-drain layer includes a first source 702 and a first drain 701, a second source 704 and a second drain 703, a seventh source 714 and a seventh drain 713. The first source 702 and the first drain 701 are respectively connected to two doped regions of the corresponding first active portion 301 through vias. The second source 704 and the second drain 703 are respectively connected to two doped regions of the corresponding second active portion 302 through vias. The seventh source 714 and the seventh drain 713 are respectively connected to two doped regions of the corresponding seventh active portion 307 through vias. The second source-drain layer includes a third source 706 and a third drain 705, a fourth source 708 and a fourth drain 707, a fifth source 710 and a fifth drain 709, and a sixth source 712 and a sixth drain 711. The third source 706 and the third drain 705 are respectively connected to two doped regions of the corresponding third active portion 303. The fourth source 708 and the fourth drain 707 are respectively connected to two doped regions of the corresponding fourth active portion 304. The fifth source 710 and the fifth drain 709 are respectively connected to two doped regions of the corresponding fifth active portion 305. The sixth source 712 and the sixth drain 711 are respectively connected to two doped regions of the corresponding sixth active portion 306. A protective layer 10 is formed on the side of the first and second source-drain layers away from the substrate 1.

[0073] A planarization layer 11 is formed on the side of the protective layer 10 away from the first sensing unit 101 and opposite to the substrate 1. The orthographic projection of the planarization layer 11 onto the substrate 1 at least covers the orthographic projection of the first active part 301 onto the substrate 1. A first electrode layer is deposited and patterned. A first light-shielding part 121, a second light-shielding part 122, and a third light-shielding part 123 are formed on the side of the switching transistor away from the substrate 1. A first electrode 120 is formed on the side of the driving transistor away from the substrate 1. A first pixel defining layer 13 is covered and patterned on the side of the first electrode layer away from the substrate 1, thus completing the fabrication of a display backplate with color temperature compensation function.

[0074] Understandably, since the planarization layer 11 only transmits red light, the first sensing transistor only absorbs red light. The second sensing transistor absorbs the full spectrum of visible light. The third active part 303 only absorbs ultraviolet light, therefore the third sensing transistor only absorbs ultraviolet light. Based on the light response of different sensing transistors and the spectral characteristics of the ambient light source, the ambient light can be identified in order to adjust the display color temperature.

[0075] Figure 17 The basic structure of the second type of display panel is shown. The difference from the first type of display panel is that the first, second, and third switching transistors in this display panel are all top-gate oxide transistors.

[0076] Specifically, a second gate layer is provided on the side of the protective layer 10 away from the substrate 1. The second gate layer in the peripheral region includes a fourth gate 504, a fifth gate 505 and a sixth gate 506. The orthographic projection of the fourth gate 504 onto the substrate 1 is located within the orthographic projection of the fourth active portion 304 onto the substrate 1. The orthographic projection of the fifth gate 505 onto the substrate 1 is located within the orthographic projection of the fifth active portion 305 onto the substrate 1. The orthographic projection of the sixth gate 506 onto the substrate 1 is located within the orthographic projection of the sixth active portion 306 onto the substrate 1.

[0077] Specifically, the orthographic projection of the fourth gate 504 onto the substrate 1 can coincide with the orthographic projection of the fourth active portion 304 onto the substrate 1, the orthographic projection of the fifth gate 505 onto the substrate 1 can coincide with the orthographic projection of the fifth active portion 305 onto the substrate 1, and the orthographic projection of the sixth gate 506 onto the substrate 1 can coincide with the orthographic projection of the sixth active portion 306 onto the substrate 1. Alternatively, the orthographic projection of the fourth gate 504 onto the substrate 1 can be slightly smaller than the orthographic projection of the fourth active portion 304 onto the substrate 1, the orthographic projection of the fifth gate 505 onto the substrate 1 can be slightly smaller than the orthographic projection of the fifth active portion 305 onto the substrate 1, and the orthographic projection of the sixth gate 506 onto the substrate 1 can be slightly smaller than the orthographic projection of the sixth active portion 306 onto the substrate 1.

[0078] Understandably, the first, second, and third switching transistors in this display panel require different methods to eliminate the influence of ambient light when they are turned off. Here, the fourth active portion 304 is blocked by the fourth gate 504, the fifth active portion 305 is blocked by the fifth gate 505, and the sixth active portion 306 is blocked by the sixth gate 506, thereby preventing ambient light from affecting the fourth active portion 304, the fifth active portion 305, and the sixth active portion 306.

[0079] The fourth source 708 and fourth drain 707, the fifth source 710 and fifth drain 709, and the sixth source and sixth drain 711 are all located in the first electrode layer. The fourth source 708 and fourth drain 707 are connected to the fourth active portion 304 through vias in the protective layer 10 and the planarization layer 11, respectively. The fifth source 710 and fifth drain 709 are connected to the fifth active portion 305 through vias in the protective layer 10 and the planarization layer 11, respectively. The sixth source 712 and sixth drain 711 are connected to the sixth active portion 306 through vias in the protective layer 10 and the planarization layer 11, respectively.

[0080] The driving layer group of the display area includes driving transistors. The first active layer of the display area also includes a seventh active portion 307, and the second gate layer also includes an eighth gate 508. The eighth gate 508 and the seventh gate 507 are projected onto the substrate 1 and are located within the projection of the seventh active portion 307 onto the substrate 1. The eighth gate 508 is connected to the seventh gate 507 through vias on the protective layer 10 and the dielectric layer 6. A first electrode 120 is provided on the side of the planarization layer 11 away from the substrate 1. The first electrode 120 is connected to the seventh drain 713 through vias on the planarization layer 11 and the protective layer 10. The first electrode 120 is located in the first electrode layer.

[0081] like Figures 14 to 17 As shown, the fabrication process of this display panel is as follows: First, a buffer layer 2 is deposited on a substrate 1. A polysilicon layer is deposited and patterned on the side of the buffer layer 2 away from the substrate 1 to form a first active layer. The first active layer includes a first active portion 301, a second active portion 302, and a seventh active portion 307. A gate insulating layer 4 is covered on the first active layer. A first gate layer is deposited on the gate insulating layer 4. The first gate layer is a transparent conductive layer and includes a first gate 501, a second gate 502, a third gate 503, and a seventh gate 507. Photoresist is coated and photolithography and etching are performed. Using the first gate layer and the photoresist as a mask, an N+ doping process is performed to form doped regions in the first active portion 301, the second active portion 302, and the seventh active portion 307, respectively. A dielectric layer 6 is deposited on the side of the first gate layer away from the substrate 1, and the dielectric layer 6 covers the first gate layer and the gate insulating layer 4.

[0082] A second active layer is formed on the side of dielectric layer 6 away from the substrate 1, and then dielectric layer 6 is patterned. A first source-drain layer and a second source-drain layer are formed. The first source-drain layer includes a first source 702 and a first drain 701, a second source 704 and a second drain 703, a seventh source 714 and a seventh drain 713. The first source 702 and the first drain 701 are respectively connected to two doped regions of the corresponding first active portion 301 through vias. The second source 704 and the second drain 703 are respectively connected to two doped regions of the corresponding second active portion 302 through vias. The seventh source 714 and the seventh drain 713 are respectively connected to two doped regions of the corresponding seventh active portion 307 through vias.

[0083] The second source-drain layer includes a third source 706 and a third drain 705, which are respectively connected to two doped regions of the corresponding third active portion 303. A protective layer 10 is formed on the side of the first and second source-drain layers away from the substrate 1. A second gate layer is formed on the side of the protective layer 10 away from the substrate 1, including a fourth gate 504, a fifth gate 505, a sixth gate 506, an eighth gate 508, and a ninth gate 509. An N+ doping process is performed using the second gate layer and photoresist as a mask to conduct the overlap region between the seventh active portion 307 and the seventh source 714 and the seventh drain 713. A planarization layer 11 is formed on the side of the second gate layer away from the substrate 1, and the orthographic projection of the planarization layer 11 on the substrate 1 at least covers the orthographic projection of the first active portion 301 on the substrate 1. The ninth gate 509 corresponding to the third sensing transistor 1031 is removed by wet etching.

[0084] A first electrode layer is deposited and patterned. The first electrode layer includes a fourth source 708 and a fourth drain 707, a fifth source 710 and a fifth drain 709, a sixth source 712 and a sixth drain 711, and a first electrode 120. The fourth source 708 and the fourth drain 707 are respectively connected to two doped regions of the corresponding fourth active portion 304. The fifth source 710 and the fifth drain 709 are respectively connected to two doped regions of the corresponding fifth active portion 305. The sixth source 712 and the sixth drain 711 are respectively connected to two doped regions of the corresponding sixth active portion 306. The first electrode 120 passes through a via on the planarization layer 11 and the protective layer 10 and is connected to the seventh drain 713. A first pixel defining layer 13 is covered and patterned on the side of the first electrode layer away from the substrate 1, thus completing the fabrication of a display backplane with color temperature compensation function.

[0085] The third type of display panel differs from the first type in that its sensing module 100 does not include a third sensing unit 103. Correspondingly, it also needs to be determined from... Figure 2 Remove the third sensing unit 103. Figure 18 The basic structure of the third type of display panel is shown. Both the first and second switching transistors are top-gate polysilicon transistors.

[0086] Specifically, the driving layer group of the peripheral region includes only a first active layer, a first gate layer, and a first source-drain layer. The first active layer includes only a first active portion 301, a second active portion 302, a third active portion 303, and a fourth active portion 304. The first source-drain layer includes a first source 702 and a first drain 701, a second source 704 and a second drain 703, a third source 706 and a third drain 705, and a fourth source 708 and a fourth drain 707. The first source 702 and the first drain 701 are respectively connected to the first active portion 301. The second source 704 and the second drain 703 are respectively connected to the second active portion 302. The third source 706 and the third drain 705 are respectively connected to the third active portion 303. The fourth source 708 and the fourth drain 707 are respectively connected to the fourth active portion 304.

[0087] The first switching transistor has a first light-shielding portion 121 on the side away from the substrate 1, and the orthographic projection of the first light-shielding portion 121 on the substrate 1 completely covers the orthographic projection of the channel region of the third active portion 303 on the substrate 1. The second sensing unit 102 has a second light-shielding portion 122 on the side of the switching transistor away from the substrate 1, and the orthographic projection of the second light-shielding portion 122 on the substrate 1 completely covers the orthographic projection of the channel region of the fourth active portion 304 on the substrate 1.

[0088] The fabrication process of this display panel is as follows: First, a buffer layer 2 is deposited on a substrate 1. A polysilicon layer is then deposited and patterned on the side of the buffer layer 2 away from the substrate 1 to form a first active layer. The first active layer includes a first active portion 301, a second active portion 302, a third active portion 303, a fourth active portion 304, and a seventh active portion 307. A gate insulating layer 4 is then deposited on the first active layer. A first gate layer, which is a transparent conductive layer, is then deposited on the gate insulating layer 4. The first gate layer includes a first gate 501, a second gate 502, a third gate 503, a fourth gate 504, and a seventh gate 507. Photoresist is coated and photolithography and etching are performed. N+ doping process is performed using the first gate layer and photoresist as a mask. Doped regions are formed in the first active part 301, the second active part 302, the third active part 303, the fourth active part 304 and the seventh active part 307 respectively. A dielectric layer 6 is deposited on the side of the first gate layer away from the substrate 1. The dielectric layer 6 covers the first gate layer and the gate insulating layer 4.

[0089] A first source-drain layer is formed on the side of the dielectric layer 6 away from the substrate 1. The first source-drain layer includes a first source 702 and a first drain 701, a second source 704 and a second drain 703, a third source 706 and a third drain 705, a fourth source 708 and a fourth drain 707, and a seventh source 714 and a seventh drain 713. The first source 702 and the first drain 701 are respectively connected to two doped regions of the corresponding first active portion 301 through vias. The second source 704 and the second drain 703 are respectively connected to two doped regions of the corresponding second active portion 302 through vias. The third source 706 and the third drain 705 are respectively connected to two doped regions of the corresponding third active portion 303. The fourth source 708 and the fourth drain 707 are respectively connected to two doped regions of the corresponding fourth active portion 304. The seventh source 714 and the seventh drain 713 are respectively connected to the two doped regions of the corresponding seventh active part 307, and a protective layer 10 is formed on the side of the first source and drain layer away from the substrate 1.

[0090] A planarization layer 11 is formed on the side of the protective layer 10 away from the first sensing unit 101 and opposite to the substrate 1. The orthographic projection of the planarization layer 11 onto the substrate 1 at least covers the orthographic projection of the first active portion 301 onto the substrate 1. A first electrode layer is deposited and patterned. A first electrode layer is formed on the side of the switching transistor away from the substrate 1. The first electrode layer includes a first light-shielding portion 121, a second light-shielding portion 122, and a first electrode 120. A first pixel defining layer 13 is covered and patterned on the side of the first electrode layer away from the substrate 1, thus completing the fabrication of a display backplane with color temperature compensation function. It is understood that this display panel can sense red light and full-spectrum visible light, but cannot sense ultraviolet light, and is only suitable for indoor use.

[0091] Figure 19 The basic structure of the fourth type of display panel is shown. Unlike the first type of display panel, the first sensing transistor, the second sensing transistor, and the third sensing transistor are all top-gate polysilicon transistors with transparent gates. The planarization layer 11 disposed on the side of the first sensing unit 101 facing away from the substrate 1 does not have a light-filtering function.

[0092] An optical adhesive layer 15 is provided on the side of the planarization layer 11 away from the substrate 1. A color filter layer 14 is provided on the side of the optical adhesive layer 15 away from the substrate. A cover plate 16 is provided on the side of the color filter layer 14 away from the substrate. The color filter layer 14 includes multiple color filters, each corresponding to a sensing transistor. The channel region of the sensing transistor is projected onto the substrate 1 in orthographic projection, and the projection of the filter onto the substrate 1 is within the projection of the filter onto the substrate 1. A light-blocking portion is provided between adjacent filters. Each light-blocking portion corresponds to a switching transistor of a sensing unit. The channel region of the switching transistor is projected onto the substrate 1 in orthographic projection, and the projection of the light-blocking portion onto the substrate 1 is within the projection of the light-blocking portion onto the substrate 1.

[0093] The channel region of the first sensing transistor is projected onto the substrate 1 in the orthographic projection of the first filter 141 within the orthographic projection of the substrate 1. The channel region of the second sensing transistor is projected onto the substrate 1 in the orthographic projection of the second filter 142 within the orthographic projection of the substrate 1. The channel region of the third sensing transistor is projected onto the substrate 1 in the orthographic projection of the third filter 143 within the orthographic projection of the substrate 1. The channel regions of the first switching transistor, the second switching transistor, and the third switching transistor are projected onto the substrate 1 in the orthographic projection of their respective light-blocking portions 144 within the orthographic projection of the substrate 1.

[0094] Specifically, the driving layer group in the peripheral region includes only a first active layer, a first gate layer, and a first source-drain layer. The first active portion 301, the second active portion 302, the third active portion 303, the fourth active portion 304, the fifth active portion 305, and the sixth active portion 306 are all located in the first active layer. The channel region of the first active portion 301, when projected onto the substrate 1, lies within the projection of the first filter portion 141 onto the substrate 1. The channel region of the second active portion 302, when projected onto the substrate 1, lies within the projection of the second filter portion 142 onto the substrate 1. The channel region of the third active portion 303, when projected onto the substrate 1, lies within the projection of the third filter portion 143 onto the substrate 1. The projections of the fourth active portion 304, the fifth active portion 305, and the sixth active portion 306 onto the substrate 1 lie within the projection of their corresponding light-shielding portions 144 onto the substrate 1.

[0095] The first source 702 and the first drain 701, the second source 704 and the second drain 703, the third source 706 and the third drain 705, the fourth source 708 and the fourth drain 707, the fifth source 710 and the fifth drain 709, and the sixth source 712 and the sixth drain 711 are all located in the first source-drain layer. The first source 702 and the first drain 701 are respectively connected to the first active part 301. The second source 704 and the second drain 703 are respectively connected to the second active part 302. The third source 706 and the third drain 705 are respectively connected to the third active part 303. The fourth source 708 and the fourth drain 707 are respectively connected to the fourth active part 304. The fifth source 710 and the fifth drain 709 are respectively connected to the fifth active part 305. The sixth source 712 and the sixth drain 711 are respectively connected to the sixth active part 306. The first gate layer includes a first gate 501, a second gate 502, a third gate 503, a fourth gate 504, a fifth gate 505, and a sixth gate 506, and is disposed on the side of the gate insulating layer 4 away from the substrate 1.

[0096] Figure 20The basic structure of the fifth type of display panel is shown. Unlike the first type of display panel, the planarization layer 11 disposed on the side of the first sensing transistor facing away from the substrate 1 does not have a light-filtering function. The first sensing transistor, the second sensing transistor, and the third sensing transistor are all bottom-gate polysilicon transistors with transparent gates.

[0097] Specifically, the first gate layer of the display panel includes a first gate 501, a second gate 502, a third gate 503, a fourth gate 504, a fifth gate 505, a sixth gate 506, and a seventh gate 507. The first gate layer is disposed on one side of the substrate 1, and the buffer layer 2 is disposed on the side of the first gate layer away from the substrate 1. The display panel does not have a gate insulating layer 4; instead, the buffer layer 2 serves as the gate insulating layer 4. Doped layers are formed on the side of the first active portion 301, the second active portion 302, the third active portion 303, the fourth active portion 304, the fifth active portion 305, and the sixth active portion 306 away from the substrate 1. The first source 702 and the first drain 701 are connected to the first active part 301 through the doped regions on both sides of the first active part 301, the second source 704 and the second drain 703 are connected to the second active part 302 through the doped regions on both sides of the second active part 302, the third source 706 and the third drain 705 are connected to the third active part 303 through the doped regions on both sides of the third active part 303, the fourth source 708 and the fourth drain 707 are connected to the fourth active part 304 through the doped regions on both sides of the fourth active part 304, the fifth source 710 and the fifth drain 709 are connected to the fifth active part 305 through the doped regions on both sides of the fifth active part 305, and the sixth source 712 and the sixth drain 711 are connected to the sixth active part 306 through the doped regions on both sides of the third active part 303. The seventh source 714 and the sixth drain 713 are connected to the seventh active portion 307 through doped regions on both sides of the seventh active portion 307. The display panel does not have a dielectric layer 6, and a protective layer 10 is directly provided on the side of the first source and drain layer away from the substrate 1.

[0098] It is understandable that in the first to third display panels, the difference between the edge of the light-filtering layer projected onto the substrate 1 and the edge of the active layer of the sensing transistor of the first sensing unit 101 projected onto the substrate 1 can all be greater than 3μm. That is, the difference between the edge of the light-filtering layer projected onto the substrate 1 and the first active portion 301 can all be greater than 3μm to ensure the light-filtering effect. Similarly, the difference between the edge of the light-shielding portion projected onto the substrate 1 and the edge of the sensing transistor projected onto the substrate 1 can be greater than 3μm to ensure the light-shielding effect.

[0099] In the five types of display panels mentioned above, the length of the channel region of the sensing transistor along the first direction is greater than the length of the channel region of the sensing transistor along the second direction, and the first and second directions are perpendicular to each other. The first direction is the width direction of the sensing transistor, and the second direction is the length direction of the sensing transistor. The amount of light-sensitive signal is the product of responsivity and light-receiving area. Reducing the length of the channel region will reduce the light-receiving area but increase the responsivity, while the overall signal amount remains unchanged; while increasing the width of the channel region can increase the light-receiving area while keeping the responsivity unchanged, thus effectively increasing the signal amount.

[0100] The longer the channel region of the sensing transistor along the first direction, the greater the signal strength, and the overall change is linear without an inflection point. The length of the channel region along the second direction only affects the area occupied by the sensing transistor. The photoresponse capability of the sensing transistor is improved by increasing the aspect ratio. Specifically, the ratio of the length of the channel region along the first direction to the length of the channel region along the second direction is greater than 2. For example, the width of the first sensing transistor 1011, the second sensing transistor 1021, and the third sensing transistor 1031 is greater than 10 μm, and the length is less than 5 μm.

[0101] Considering the ambient light incident angle, the spacing between two adjacent sensing units is greater than 6μm, and the spacing between adjacent sensing transistors within each sensing unit, as well as between adjacent sensing transistors and switching transistors, is greater than 6μm. This spacing of greater than 6μm avoids the influence of the filter layer on the sensing transistor of the first sensing unit on adjacent sensing units, and also prevents the light-shielding or blocking portion of the switching transistor of one sensing unit from affecting adjacent sensing units.

[0102] This disclosure provides a display device including the display panel described above. The structure of the display panel has been described in detail above and will not be repeated here. The beneficial effects of this display device can also be referred to the beneficial effects of the display panel.

[0103] Display devices can be used in traditional electronic devices, such as mobile phones, computers, televisions, and video recorders, or in emerging wearable devices, such as virtual reality devices and augmented reality devices, which will not be listed here.

[0104] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts, such as the casing, circuit board, power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0105] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising a display area and a peripheral area outside the display area, characterized in that, The display panel also includes: Substrate; A sensing module is disposed on one side of the substrate and located in the peripheral region. The sensing module includes a sensing unit, which includes: A sensing transistor, wherein a first terminal of the sensing transistor receives an electrical signal, a control terminal of the sensing transistor receives a first control signal, and the sensing transistor is used to receive ambient light and convert the ambient light into an electrical signal, which is output from the second terminal of the sensing transistor. The sensing module includes a first sensing unit and a second sensing unit. The sensing transistors of the first sensing unit and the second sensing unit are both top-gate polysilicon transistors with transparent gates. A filter layer is provided on the side of the first sensing unit away from the substrate, and the orthographic projection of the channel region of the sensing transistor of the first sensing unit onto the substrate is located within the orthographic projection of the filter layer onto the substrate. The filter layer is used to transmit monochromatic light.

2. The display panel according to claim 1, characterized in that, The sensing unit further includes: A storage capacitor, the first terminal of which is connected to the second terminal of the sensing transistor, the second terminal of which is grounded, and the storage capacitor stores the photosensitive signal output from the second terminal of the sensing transistor; A switching transistor, wherein the first terminal of the switching transistor is connected to the first terminal of the storage capacitor, and the control terminal of the switching transistor receives a second control signal to obtain the photosensitive signal stored in the storage capacitor.

3. The display panel according to claim 2, characterized in that, The sensing module includes multiple sensing units. The first terminal of the sensing transistor of each of the multiple sensing units receives an electrical signal. The control terminal of the sensing transistor of each of the multiple sensing units receives a first control signal in sequence, and the control terminal of the switching transistor of each of the multiple sensing units receives a second control signal in sequence, so as to acquire the photosensitive signals stored in the multiple storage capacitors in sequence.

4. The display panel according to claim 3, characterized in that, The distance between the edge of the filter layer projected orthogonally onto the substrate and the edge of the channel region of the sensing transistor of the first sensing unit projected orthogonally onto the substrate is greater than 3 μm.

5. The display panel according to claim 3, characterized in that, The sensing module further includes a third sensing unit, wherein the sensing transistor of the third sensing unit is a bottom-gate metal-oxide transistor.

6. The display panel according to claim 2, characterized in that, The switching transistor is a bottom-gate transistor or a top-gate transistor with a transparent gate. The display panel also includes: A light-shielding portion is disposed on the side of the switching transistor away from the substrate, and the orthographic projection of the channel region of the switching transistor onto the substrate is located within the orthographic projection of the light-shielding portion onto the substrate.

7. The display panel according to claim 6, characterized in that, The distance between the edge of the light-shielding portion projected onto the substrate and the edge of the channel region of the switching transistor projected onto the substrate is greater than 3 μm.

8. The display panel according to claim 2, characterized in that, The switching transistor is a top-gate transistor with an opaque gate, and the channel region of the switching transistor is projected onto the substrate in the same direction as the gate in the same direction.

9. The display panel according to claim 2, characterized in that, The switching transistor is an oxide transistor or a polysilicon transistor.

10. The display panel according to claim 3, characterized in that, The sensing module comprises multiple sensing units, and the sensing transistors of the multiple sensing units are bottom-gate polysilicon transistors or top-gate polysilicon transistors with transparent gates. The display panel further includes: A color filter layer is disposed on the side of the filter layer away from the substrate. The color filter layer includes multiple filter sections of different colors, each filter section corresponding to a sensing transistor. The channel region of the sensing transistor is projected onto the substrate in the orthographic projection of the filter section onto the substrate.

11. The display panel according to claim 10, characterized in that, The color filter layer includes: The light-shielding portion is located within the orthogonal projection of the channel region of the switching transistor onto the substrate.

12. The display panel according to claim 3 or 10, characterized in that, The spacing between two adjacent sensing units is greater than 6 μm; the spacing between adjacent sensing transistors and switching transistors within each sensing unit is greater than 6 μm.

13. The display panel according to claim 2, characterized in that, The length of the channel region of the sensing transistor along the first direction is greater than the length of the channel region of the sensing transistor along the second direction. The first direction and the second direction are perpendicular to each other. The first direction is the width direction of the sensing transistor, and the second direction is the length direction of the sensing transistor.

14. The display panel according to claim 1, characterized in that, The sensing modules are multiple, and the multiple sensing modules are evenly arranged in the peripheral area along the outline of the display panel.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

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