A low quiescent current LDO circuit

Abstract

The present invention discloses a low static current LDO circuit, belonging to the field of analog integrated circuits. The present invention is based on the adaptive conduction of power transistors and dynamic variable feedback resistors, and includes an error amplifier, a non-inverting amplifier, a first power transistor, a second power transistor, a first resistor, a variable feedback resistor, and a capacitor C M , and load current. The adaptive conduction control mode of the power transistor can simplify the loop structure under light load, and the circuit maintains loop stability within a wide load range. It is realized by the non-inverting amplifier and the second power transistor. Under light load, the non-inverting amplifier is in the triode region and the second power transistor is turned off, and the output current is only provided by the first power transistor. The LDO loop consists of the error amplifier and the first power transistor to form a two-stage structure with high loop stability; under heavy load, the non-inverting amplifier is in the saturation region and the second power transistor is turned on, and the output current is mainly provided by the second power transistor. At this time, the LDO loop consists of the error amplifier, the non-inverting amplifier and the second power transistor to form a three-stage structure with high loop gain.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and particularly to a low quiescent current LDO circuit. Background Art

[0002] The increasing demand for battery-powered mobile devices such as mobile phones and cameras poses a huge challenge to the design of PMIC (Power Management IC). In a baseband mobile phone chip powered by a lithium battery, it is required that the LDO (low dropout regulator) can generate an output of 1.8V at a low input power supply voltage. Therefore, how to design an LDO with high load, high linear regulation rate and PSRR (Power supply rejection ratio) at low quiescent current has become a design difficulty.

[0003] As Figure 1 shown in the figure is a traditional two-stage LDO structure, which cannot achieve wide-range load output, high load regulation rate, high linear regulation rate and good transient response characteristics under the limitation of low quiescent current. Figure 1 In m_EA , g is the transconductance of the EA (error amplifier), g m_MP is the transconductance of M P (output power transistor), the main pole P 1 is located at the output end of the EA, and the secondary pole P 2 is located at the V OUT terminal (circuit output terminal), and P 2 ∝ g m_MP ∝ I load . Since both P 1 and P 2 are related to the load current (I load ), when the circuit is in a light load state, P 1 and P 2 will approach each other, resulting in stability problems in the loop.

[0004] In addition, in the traditional two-stage LDO structure, to meet the requirement of the charging and discharging rate of the gate terminal of M P when a full-load jump occurs at the output terminal to ensure good transient performance, the EA should also have a high slew rate output characteristic, which cannot meet the limitation conditions of low quiescent current applications. Summary of the Invention

[0005] The object of the present invention is to provide a low quiescent current LDO circuit, so as to solve the problem that traditional two-stage LDOs cannot achieve wide-range load output, high load regulation rate, high linear regulation rate and good transient response characteristics under the limited conditions of low quiescent current applications.

[0006] To solve the above technical problems, the present invention provides a low quiescent current LDO circuit, based on adaptive conduction of power transistors and dynamic variable feedback resistors, including an error amplifier, a non-inverting amplifier, a first power transistor, a second power transistor, a first resistor, a variable feedback resistor, and capacitor C M , load current;

[0007] The negative input terminal of the error amplifier is connected to port V REF , the positive input terminal is connected between the second end of the first resistor and the first end of the variable feedback resistor, and the output terminal is simultaneously connected to the upper plate of capacitor C M , the input terminal of the non-inverting amplifier, and the gate terminal of the first power transistor; the output terminal of the non-inverting amplifier is connected to the gate terminal of the second power transistor; the source terminal of the first power transistor is connected to the input voltage V IN , the drain terminal is connected between the drain terminal of the second power transistor and the first end of the first resistor; the source terminal of the second power transistor is connected to the input voltage V IN , the drain terminal is simultaneously connected to the output terminal V OUT and the first end of the first resistor, and the second end of the first resistor is grounded through the variable feedback resistor; the positive terminal of the load current is connected to the drain terminal of the second power transistor, and the negative terminal is grounded;

[0008] The adaptive conduction control mode of the power transistor is realized by the non-inverting amplifier and the second power transistor. When the load is light, the non-inverting amplifier is in the triode region and the second power transistor is turned off. The output current is only provided by the first power transistor, and the LDO loop consists of the error amplifier and the first power transistor to form a two-stage structure with high loop stability;

[0009] When the load is heavy, the non-inverting amplifier is in the saturation region and the second power transistor is turned on. The output current is mainly provided by the second power transistor. At this time, the LDO loop consists of the error amplifier, the non-inverting amplifier and the second power transistor to form a three-stage structure with high loop gain.

[0010] In an embodiment, the low quiescent current LDO circuit includes a first NMOS transistor to a twelfth NMOS transistor, NMOS transistor M NR1 , a first power transistor, a second power transistor, a third PMOS transistor to an eleventh PMOS transistor, a variable feedback resistor, capacitor C M , capacitor C L , a bias current source;

[0011] The upper end of the variable feedback resistor is connected to port V FEEDBACK , and its lower end is grounded; the upper end of capacitor C M is connected to the output terminal VOUT , the lower end is connected to the gate terminal of the twelfth NMOS transistor; capacitor C L 's upper end is connected to the output terminal V OUT , the lower end is grounded; the drain terminal and gate terminal of NMOS transistor M NR1 are both connected to the output terminal V OUT , and the source terminal is connected to port V FEEDBACK ;

[0012] The source terminals of the first power transistor and the second power transistor are both connected to the input voltage V IN , the gate terminal of the first power transistor is connected to the gate terminal of the twelfth NMOS transistor, and the drain terminal is connected to the output terminal V OUT ; the gate terminal of the second power transistor is connected to the drain terminal of the seventh PMOS transistor, and the drain terminal is connected to the output terminal V OUT .

[0013] In one embodiment, the error amplifier is jointly composed of the first NMOS transistor to the fourth NMOS transistor, the eighth NMOS transistor to the eleventh NMOS transistor, the third PMOS transistor to the fifth PMOS transistor, and the ninth PMOS transistor to the eleventh PMOS transistor; the upper end of the bias current source is connected to the drain terminal of the ninth PMOS transistor, and the lower end is connected to the drain terminal of the first NMOS transistor; the drain terminal and gate terminal of the first NMOS transistor are both connected to the gate terminal of the second NMOS transistor, and the source terminal is grounded; the drain terminal of the second NMOS transistor is simultaneously connected to the source terminals of the eighth NMOS transistor and the ninth NMOS transistor, the gate terminal is connected to the gate terminal of the fifth NMOS transistor, and the source terminal is connected to; the drain terminal of the eighth NMOS transistor is connected to the drain terminal of the fourth PMOS transistor, and the gate terminal is connected to port V FEEDBACK ; the drain terminal of the ninth NMOS transistor is connected to the drain terminal of the fifth PMOS transistor, and the gate terminal is connected to port V REF ;

[0014] The drain terminal of the third NMOS transistor is connected to the source terminal of the tenth NMOS transistor, the gate terminal is connected to the gate terminal of the fourth NMOS transistor, and the source terminal is grounded; the drain terminal of the fourth NMOS transistor is connected to the source terminal of the eleventh NMOS transistor, the gate terminal is connected to the drain terminal of the third NMOS transistor, and the source terminal is connected to; the drain terminal of the tenth NMOS transistor is connected to the drain terminal of the tenth PMOS transistor, the gate terminal is connected to the gate terminal of the eleventh NMOS transistor, and the source terminal is connected to the drain terminal of the third NMOS transistor; the drain terminal of the eleventh NMOS transistor is connected to the drain terminal of the eleventh PMOS transistor, the gate terminal is connected to the drain terminal of the tenth NMOS transistor, and the source terminal is connected to the drain terminal of the fourth NMOS transistor; the gate terminal of the tenth PMOS transistor is connected to the gate terminal of the ninth PMOS transistor, and the source terminal is connected to the drain terminal of the fourth PMOS transistor; the gate terminal of the eleventh PMOS transistor is connected to the gate terminal of the ninth PMOS transistor, and the source terminal is connected to the drain terminal of the fifth PMOS transistor; the drain terminal of the fourth PMOS transistor is connected to the source terminal of the tenth PMOS transistor, the gate terminal is connected to the gate terminal of the third PMOS transistor, and the source terminal is connected to the input voltage V IN ; the drain terminal of the fifth PMOS transistor is connected to the source terminal of the eleventh PMOS transistor, the gate terminal is connected to the gate terminal of the third PMOS transistor, and the source terminal is connected to the input voltage V IN; The drain terminal of the third PMOS transistor is connected to the source terminal of the ninth PMOS transistor, the gate terminal is connected to the source terminal of the ninth PMOS transistor, and the source terminal is connected to the input voltage V IN ; The drain terminal of the ninth PMOS transistor is connected to the upper end of the bias current source, the gate terminal is connected to the upper end of the bias current source, and the source terminal is connected to the drain terminal of the third PMOS transistor.

[0015] In one embodiment, the non-inverting amplifier is jointly composed of a fifth NMOS transistor to a seventh NMOS transistor, a twelfth NMOS transistor, a sixth PMOS transistor to an eighth PMOS transistor; the drain terminal of the fifth NMOS transistor is connected to the source terminal of the twelfth NMOS transistor, the gate terminal is connected to the gate terminal of the first NMOS transistor, and the source terminal is grounded; the drain terminal of the sixth NMOS transistor is connected to the drain terminal of the seventh PMOS transistor, the gate terminal is connected to the drain terminal of the seventh NMOS transistor, and the source terminal is grounded; the drain terminal of the seventh NMOS transistor is connected to the drain terminal of the eighth PMOS transistor, the gate terminal is connected to the gate terminal of the sixth NMOS transistor, and the source terminal is grounded; the drain terminal of the twelfth NMOS transistor is connected to the drain terminal of the sixth PMOS transistor, the gate terminal is connected to the drain terminal of the eleventh NMOS transistor, and the source terminal is connected to the drain terminal of the fifth NMOS transistor; the drain terminal of the sixth PMOS transistor is connected to the drain terminal of the twelfth NMOS transistor, the gate terminal is connected to the drain terminal of the twelfth NMOS transistor, and the source terminal is connected to the input voltage V IN ; The drain terminal of the seventh PMOS transistor is connected to the drain terminal of the sixth NMOS transistor, the gate terminal is connected to the gate terminal of the sixth PMOS transistor, and the source terminal is connected to the input voltage V IN ; The drain terminal of the eighth PMOS transistor is connected to the drain terminal of the seventh NMOS transistor, the gate terminal is connected to the gate terminal of the twelfth NMOS transistor, and the source terminal is connected to the input voltage V IN .

[0016] In one embodiment, the variable feedback resistor includes a resistor R F , a capacitor C F , a fourteenth NMOS transistor to an eighteenth NMOS transistor, NMOS transistors M NR2 to M NR3 , a twelfth PMOS transistor, a thirteenth PMOS transistor; the upper end of the resistor R F is connected to the source terminal of the eighteenth NMOS transistor, and the lower end is connected to the upper end of the capacitor C F , and the lower end of the capacitor C F is connected to the port V OUT ; the drain terminal of the fourteenth NMOS transistor is connected to the source terminal of the fifteenth NMOS transistor, the gate terminal is connected to the source terminal of the fifteenth NMOS transistor, and the source terminal is grounded; the drain terminal of the fifteenth NMOS transistor is connected to the source terminal of the seventeenth NMOS transistor, the gate terminal is connected to the source terminal of the seventeenth NMOS transistor, and the source terminal is connected to the drain terminal of the fourteenth NMOS transistor; the drain terminal of the seventeenth NMOS transistor is connected to the drain terminal of the twelfth PMOS transistor, the gate terminal is connected to the port V OUT , and the source terminal is connected to the drain terminal of the fifteenth NMOS transistor; the drain terminal of the twelfth PMOS transistor is connected to the drain terminal of the seventeenth NMOS transistor, the gate terminal is connected to the drain terminal of the seventeenth NMOS transistor, and the source terminal is connected to the input voltage VIN ; The drain terminal of the sixteenth NMOS transistor is connected to the source terminal of the eighteenth NMOS transistor, the gate terminal is connected to the source terminal of the eighteenth NMOS transistor, and the source terminal is grounded; the drain terminal of the eighteenth NMOS transistor is connected to the drain terminal of the thirteenth PMOS transistor, the gate terminal is connected to the drain terminal of the thirteenth PMOS transistor, and the source terminal is connected to the drain terminal of the sixteenth NMOS transistor;

[0017] NMOS transistor M NR2 's drain terminal is connected to port V FEEDBCAK , the gate terminal is connected to the drain terminal of the thirteenth PMOS transistor, and the source terminal is connected to the drain terminal of NMOS transistor M NR3 ; The drain terminal of NMOS transistor M NR3 's drain terminal is connected to the source terminal of NMOS transistor M NR2 , the gate terminal is connected to the gate terminal of the sixteenth NMOS transistor, and the source terminal is grounded; the drain terminal of the thirteenth PMOS transistor is connected to the drain terminal of the eighteenth NMOS transistor, the gate terminal is connected to the drain terminal of the seventeenth NMOS transistor, and the source terminal is connected to the input voltage V IN .

[0018] A low static current LDO circuit provided by the present invention has the following beneficial effects:

[0019] (1) The adaptive conduction control mode of the output power transistor in the circuit can simplify the loop structure under light load, so that the circuit can maintain loop stability within a wide load range;

[0020] (2) The dynamically variable feedback resistor will dynamically adjust its own resistance according to the change of the output voltage, and optimize the transient response performance of the circuit by increasing the charge and discharge rate at the output end of the circuit. Description of the Drawings

[0021] Figure 1 is a schematic diagram of a traditional two-stage structure LDO circuit;

[0022] Figure 2 is a schematic diagram of the structure of a low static current LDO circuit proposed by the present invention;

[0023] Figure 3 is a specific implementation schematic diagram of a low static current LDO circuit proposed by the present invention;

[0024] Figure 4 is a schematic diagram of the implementation method of the variable feedback resistor R var . Specific Embodiments

[0025] The following further describes in detail a low static current LDO circuit proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0026] The present invention provides a low quiescent current LDO circuit, which is designed based on the adaptive conduction of a power transistor and a dynamically variable feedback resistor. Its structure is as follows Figure 2 shown, including an error amplifier EA, a non-inverting amplifier g m2 , a power transistor M P1 , a power transistor M P2 , a resistor R 1 , a variable feedback resistor R var , a capacitor C M , a load current I load . The negative input terminal of the error amplifier EA is connected to the port V REF , and the output terminal is simultaneously connected to the upper plate of the capacitor C M , the input terminal of the non-inverting amplifier g m2 , and the gate terminal of the power transistor M P1 . The positive input terminal is connected between the second terminal of the resistor R 1 and the first terminal of the variable feedback resistor R var ; the output terminal of the non-inverting amplifier g m2 is connected to the gate terminal of the power transistor M P2 ; the source terminal of the power transistor M P1 is connected to the voltage V IN , and the drain terminal is connected between the drain terminal of the power transistor M P2 and the first terminal of the resistor R 1 ; the source terminal of the power transistor M P2 is connected to the voltage V IN , and the drain terminal is simultaneously connected to the output terminal V OUT and the first terminal of the resistor R 1 . The second terminal of the resistor R 1 is grounded through the variable feedback resistor R var ; the positive terminal of the load current I load is connected to the drain terminal of the power transistor M P2 , and the negative terminal is grounded.

[0027] The adaptive conduction control mode of the power transistor is implemented by the non-inverting amplifier g m2 and the power transistor M P2 . When the load is light, the non-inverting amplifier g m2 is in the triode region, and the power transistor M P2 is turned off. The output current is only provided by the power transistor M P1 . At this time, the LDO loop is composed of the error amplifier EA and the power transistor M P1 to form a two-stage structure with relatively high loop stability. When the load is heavy, the non-inverting amplifier g m2 is in the saturation region, and the power transistor M P2 is turned on. The output current is mainly provided by the power transistor M P2 . At this time, the LDO loop is composed of the error amplifier EA, the non-inverting amplifier g m2 and the power transistor MP2 The composition has a relatively high three - level structure loop gain. Figure 3 The dynamic variable feedback resistor R in var will dynamically adjust its own resistance according to the change of the output voltage, and optimize the transient response performance of the circuit by increasing the charge - discharge rate at the output end of the circuit.

[0028] The specific structure of the present invention is as Figure 3 shown, including NMOS transistors M N1 ~M N12 , NMOS transistor M NR1 , PMOS transistors M P1 ~M P11 , variable feedback resistor R var , capacitor C M , capacitor C L , bias current source I BIAS1 . The upper end of the variable feedback resistor R var is connected to the port V FEEDBACK , and its lower end is grounded to GND; the upper end of the capacitor C M is connected to the output end V OUT , and the lower end is connected to the gate terminal of the NMOS transistor M N12 ; the upper end of the capacitor C L is connected to the output end V OUT , and the lower end is grounded to GND; the drain terminal and the gate terminal of the NMOS transistor M NR1 are both connected to the output end V OUT , and the source terminal is connected to the port V FEEDBACK ; the source terminals of the PMOS transistors M P1 and M P2 are both connected to the input voltage V IN , the gate terminal of the PMOS transistor M P1 is connected to the gate terminal of the NMOS transistor M N12 , and the drain terminal is connected to the output end V OUT ; the gate terminal of the PMOS transistor M P2 is connected to the drain terminal of the PMOS transistor M P7 , and the drain terminal is connected to the output end V OUT .

[0029] The NMOS transistors M N1 ~M N4 , the NMOS transistors M N8 ~M N11 , the PMOS transistors M P3 ~M P5 , the PMOS transistors M P9 ~M P11 together constitute an error amplifier EA; the upper end of the bias current source I BIAS1 is connected to the drain terminal of the PMOS transistor M P9 , and the lower end is connected to the drain terminal of the NMOS transistor M N1 ; the NMOS transistor MN1 The drain terminal and the gate terminal of N2 are connected to the gate terminal of NMOS transistor M N2 ; the drain terminal of NMOS transistor M N8 is simultaneously connected to the source terminal of NMOS transistor M N9 and the source terminal of NMOS transistor M N5 ; the gate terminal is connected to the gate terminal of NMOS transistor M N8 and the source terminal is connected to GND; the drain terminal of NMOS transistor M P4 is connected to the drain terminal of PMOS transistor M FEEDBACK ; the gate terminal is connected to port V N9 ; the drain terminal of NMOS transistor M P5 is connected to the drain terminal of PMOS transistor M REF ;

[0030] NMOS transistor M N3 has its drain terminal connected to the source terminal of NMOS transistor M N10 ; the gate terminal is connected to the gate terminal of NMOS transistor M N4 and the source terminal is connected to GND; the drain terminal of NMOS transistor M N4 is connected to the source terminal of NMOS transistor M N11 ; the gate terminal is connected to the gate terminal of NMOS transistor M N3 and the source terminal is connected to GND; the drain terminal of NMOS transistor M N10 is connected to the drain terminal of PMOS transistor M P10 ; the gate terminal is connected to the gate terminal of NMOS transistor M N11 and the source terminal is connected to the drain terminal of NMOS transistor M N3 ; the drain terminal of NMOS transistor M N11 is connected to the drain terminal of PMOS transistor M P11 ; the gate terminal is connected to the gate terminal of NMOS transistor M N10 and the source terminal is connected to the drain terminal of NMOS transistor M N4 ; the drain terminal of PMOS transistor M P10 has its gate terminal connected to the gate terminal of PMOS transistor M P9 and the source terminal is connected to the source terminal of PMOS transistor M P4 ; the drain terminal of PMOS transistor M P11 has its gate terminal connected to the gate terminal of PMOS transistor M P9 and the source terminal is connected to the source terminal of PMOS transistor M P5 ; the drain terminal of PMOS transistor M P4 is connected to the drain terminal of PMOS transistor M P10 ; the source terminal and the gate terminal are connected to the gate terminal of PMOS transistor M P3 and the source terminal is connected to the input voltage V IN ; the drain terminal of PMOS transistor M P5 is connected to the source terminal of PMOS transistor M P11 ; the gate terminal is connected to the gate terminal of PMOS transistor M P3 and the source terminal is connected to the input voltage V IN; The drain terminal of PMOS transistor M P3 is connected to the source terminal of PMOS transistor M P9 and the gate terminal is connected to the source terminal of PMOS transistor M P9 ; the source terminal is connected to the input voltage V IN ; The drain terminal of PMOS transistor M P9 is connected to the upper end of bias current source I BIAS1 and the gate terminal is connected to the upper end of bias current source I BIAS1 ; the source terminal is connected to the drain terminal of PMOS transistor M P3 .

[0031] NMOS transistors M N5 ~M N7 , NMOS transistors M N12 , PMOS transistors M P6 ~M P8 together constitute the non-inverting amplifier g m2 ; The drain terminal of NMOS transistor M N5 is connected to the source terminal of NMOS transistor M N12 and the gate terminal is connected to the gate terminal of NMOS transistor M N1 ; the source terminal is connected to GND; The drain terminal of NMOS transistor M N6 is connected to the drain terminal of PMOS transistor M P7 and the gate terminal is connected to the drain terminal of NMOS transistor M N7 ; the source terminal is connected to GND; The drain terminal of NMOS transistor M N7 is connected to the drain terminal of PMOS transistor M P8 and the gate terminal is connected to the gate terminal of NMOS transistor M N6 ; the source terminal is connected to GND; The drain terminal of NMOS transistor M N12 is connected to the drain terminal of PMOS transistor M P6 and the gate terminal is connected to the drain terminal of NMOS transistor M N11 ; the source terminal is connected to the drain terminal of NMOS transistor M N5 ; The drain terminal of PMOS transistor M P6 is connected to the drain terminal of NMOS transistor M N12 and the gate terminal is connected to the drain terminal of NMOS transistor M N12 ; the source terminal is connected to the input voltage V IN ; The drain terminal of PMOS transistor M P7 is connected to the drain terminal of NMOS transistor M N6 and the gate terminal is connected to the gate terminal of PMOS transistor M P6 ; the source terminal is connected to the input voltage V IN ; The drain terminal of PMOS transistor M P8 is connected to the drain terminal of NMOS transistor M N7 and the gate terminal is connected to the gate terminal of NMOS transistor M N12 ; the source terminal is connected to the input voltage V IN .

[0032] Variable feedback resistor R varThe specific structure is as follows Figure 4 and includes resistor R F , capacitor C F , NMOS transistors M N14 ~M N18 , NMOS transistors M NR2 ~M NR3 , PMOS transistors M P12 ~M P13 ; The upper end of resistor R F is connected to the source terminal of NMOS transistor M N18 , and the lower end is connected to the upper end of capacitor C F . The lower end of capacitor C F is connected to port V OUT ; The drain terminal of NMOS transistor M N14 is connected to the source terminal of NMOS transistor M N15 , the gate terminal is connected to the source terminal of NMOS transistor M N15 , and the source terminal is connected to GND; The drain terminal of NMOS transistor M N15 is connected to the source terminal of NMOS transistor M N17 , the gate terminal is connected to the source terminal of NMOS transistor M N17 , and the source terminal is connected to the drain terminal of NMOS transistor M N14 ; The drain terminal of NMOS transistor M N17 is connected to the drain terminal of PMOS transistor M P12 , the gate terminal is connected to port V OUT , and the source terminal is connected to the drain terminal of NMOS transistor M N15 ; The drain terminal of PMOS transistor M P12 is connected to the drain terminal of NMOS transistor M N17 , the gate terminal is connected to the drain terminal of NMOS transistor M N17 , and the source terminal is connected to the input voltage V IN ; The drain terminal of NMOS transistor M N16 is connected to the source terminal of NMOS transistor M N18 , the gate terminal is connected to the source terminal of NMOS transistor M N18 , and the source terminal is connected to GND; The drain terminal of NMOS transistor M N18 is connected to the drain terminal of PMOS transistor M P13 , the gate terminal is connected to the drain terminal of PMOS transistor M P13 , and the source terminal is connected to the drain terminal of NMOS transistor M N16 ; The drain terminal of NMOS transistor M NR2 is connected to port V FEEDBCAK , the gate terminal is connected to the drain terminal of PMOS transistor M P13 , and the source terminal is connected to the drain terminal of NMOS transistor M NR3 ; The drain terminal of NMOS transistor M NR3 is connected to the source terminal of NMOS transistor M NR2 , the gate terminal is connected to the gate terminal of NMOS transistor M N16 , and the source terminal is connected to GND; PMOS transistor M P13The drain terminal of NMOS transistor M N18 The drain terminal, and the gate terminal is connected to NMOS transistor M N17 The drain terminal, and the source terminal is connected to input voltage V IN .

[0033] The working principle of the present invention is as follows:

[0034] ① Switching of the LDO loop structure under light and heavy loads

[0035] Let the load current be I load , when the load current is small and only the power transistor M P1 is turned on, the following relationship holds, and the current I N7 flowing through NMOS transistor M MN7 is:

[0036]

[0037] In the formula and are the aspect ratios of power transistor M P1 and PMOS transistor M P8 respectively.

[0038] The current I P6 flowing through NMOS transistor M MP6 is:

[0039]

[0040] In the formula and are the aspect ratios of NMOS transistor M N1 and NMOS transistor M N5 respectively.

[0041] At this time, the current I P7 flowing through PMOS transistor M MP7 is greater than the current I N6 flowing through NMOS transistor M MN6 , PMOS transistor M P7 is in the linear region, and power transistor M P2 is turned off.

[0042]

[0043] In the formula and are the aspect ratios of MOS transistors M N6 , M N7 , M P6 and M P7 respectively.

[0044] As can be seen from Equation (3), when Equation (4) holds, the load can be considered small. The LDO loop consists of an EA and a power transistor M P1 and operates in a two-stage structure. Conversely, when Equation (4) does not hold, the load can be considered large. The LDO loop consists of an error amplifier EA, a non-inverting amplifier g m2 and a power transistor M P2 and operates in a three-stage structure.

[0045]

[0046] I load_switch is an arbitrarily adjustable switching point that controls the LDO loop to operate in a light-load or heavy-load state according to the load size.

[0047] By adopting the adaptive conduction control mode of the output power transistor, the LDO loop can be simplified to a two-stage structure under light load, thus avoiding the problems of large transient overshoot or unstable loop operation in the three-stage LDO under light load due to the too-close distance between the two secondary poles in the loop or even the existence of conjugate poles.

[0048] ② Enhancement of transient response by the dynamic variable feedback resistor R var

[0049] Figure 4 The specific implementation of the dynamic variable feedback resistor R var is shown. When a load jump occurs, the instantaneous change in the output voltage is coupled to the gate terminal of the NMOS transistor M F through the capacitor C F and the resistor R NR3 . Therefore, when there is an undershoot in the output voltage, the gate voltage of the NMOS transistor M NR3 drops, causing R var to increase. When there is an overshoot in the output voltage, the gate voltage of the NMOS transistor M NR3 rises, causing R var to decrease.

[0050] The charging and discharging current I Discharge at the output terminal is:

[0051]

[0052]

[0053] In the formula is the gate-source voltage difference of the NMOS transistor M NR3 . Substituting Equation (6) into Equation (5), we get:

[0054] I Discharge ∝V gs (M NR3 ) (7) ​

[0055] As can be seen from equation (7), during the load transition, by increasing (the output voltage has an overshoot) or decreasing (the output voltage has an undershoot) the output charge and discharge current I in real time Discharge , the recovery of the output voltage during the load transition can be accelerated, thereby optimizing the transient response performance of the circuit.

[0056] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A low quiescent current LDO circuit, characterized in that, Based on the adaptive conduction of the power tube and the dynamically variable feedback resistor, it includes an error amplifier, a non-inverting amplifier, a first power tube, a second power tube, a first resistor, a variable feedback resistor, and a capacitor C M , load current; The negative input terminal of the error amplifier is connected to port V REF , the positive input terminal is connected between the second terminal of the first resistor and the first terminal of the variable feedback resistor, and the output terminal is simultaneously connected to the upper plate of capacitor C M , the input terminal of the non-inverting amplifier, and the gate terminal of the first power transistor; the output terminal of the non-inverting amplifier is connected to the gate terminal of the second power transistor; the source terminal of the first power transistor is connected to the input voltage V IN , the drain terminal is connected between the drain terminal of the second power transistor and the first terminal of the first resistor; the source terminal of the second power transistor is connected to the input voltage V IN , the drain terminal is simultaneously connected to the output terminal V OUT and the first terminal of the first resistor, and the second terminal of the first resistor is grounded through the variable feedback resistor; the positive terminal of the load current is connected to the drain terminal of the second power transistor, and the negative terminal is grounded; the adaptive conduction control mode of the power transistor is realized by an in-phase amplifier and a second power transistor. When in light load, the in-phase amplifier is in the triode region, the second power transistor is turned off, and the output current is only provided by the first power transistor. The LDO loop consists of an error amplifier and the first power transistor to form a two-stage structure with high loop stability; when in heavy load, the in-phase amplifier is in the saturation region, the second power transistor is turned on, and the output current is mainly provided by the second power transistor. At this time, the LDO loop consists of an error amplifier, an in-phase amplifier and the second power transistor to form a three-stage structure with high loop gain.

2. The low quiescent current LDO circuit according to claim 1, characterized in that, The low quiescent current LDO circuit includes a first NMOS transistor to a twelfth NMOS transistor, NMOS transistor M NR1 , a first power transistor, a second power transistor, a third PMOS transistor to an eleventh PMOS transistor, a variable feedback resistor, capacitor C M , capacitor C L , and a bias current source; The upper end of the variable feedback resistor is connected to port V FEEDBACK , and its lower end is grounded; capacitor C M has its upper end connected to the output terminal V OUT , and its lower end connected to the gate terminal of the twelfth NMOS transistor; capacitor C L has its upper end connected to the output terminal V OUT , and its lower end grounded; the drain terminal and the gate terminal of NMOS transistor M NR1 are both connected to the output terminal V OUT , and its source terminal is connected to port V FEEDBACK ; The source terminals of the first power transistor and the second power transistor are both connected to the input voltage V IN , the gate terminal of the first power transistor is connected to the gate terminal of the twelfth NMOS transistor, and the drain terminal is connected to the output terminal V OUT ; the gate terminal of the second power transistor is connected to the drain terminal of the seventh PMOS transistor, and the drain terminal is connected to the output terminal V OUT .

3. The low quiescent current LDO circuit according to claim 2, characterized in that, The error amplifier is jointly composed of a first NMOS transistor to a fourth NMOS transistor, an eighth NMOS transistor to an eleventh NMOS transistor, a third PMOS transistor to a fifth PMOS transistor, and a ninth PMOS transistor to an eleventh PMOS transistor; the upper end of the bias current source is connected to the drain end of the ninth PMOS transistor, and the lower end is connected to the drain end of the first NMOS transistor; the drain end and the gate end of the first NMOS transistor are both connected to the gate end of the second NMOS transistor, and the source end is grounded; the drain end of the second NMOS transistor is simultaneously connected to the source end of the eighth NMOS transistor and the source end of the ninth NMOS transistor, the gate end is connected to the gate end of the fifth NMOS transistor, and the source end is connected to; the drain end of the eighth NMOS transistor is connected to the drain end of the fourth PMOS transistor, and the gate end is connected to port V FEEDBACK ; the drain end of the ninth NMOS transistor is connected to the drain end of the fifth PMOS transistor, and the gate end is connected to port V REF ; The drain terminal of the third NMOS transistor is connected to the source terminal of the tenth NMOS transistor, the gate terminal is connected to the gate terminal of the fourth NMOS transistor, and the source terminal is grounded; the drain terminal of the fourth NMOS transistor is connected to the source terminal of the eleventh NMOS transistor, the gate terminal is connected to the drain terminal of the third NMOS transistor, and the source terminal is connected; the drain terminal of the tenth NMOS transistor is connected to the drain terminal of the tenth PMOS transistor, the gate terminal is connected to the gate terminal of the eleventh NMOS transistor, and the source terminal is connected to the drain terminal of the third NMOS transistor; the drain terminal of the eleventh NMOS transistor is connected to the drain terminal of the eleventh PMOS transistor, the gate terminal is connected to the drain terminal of the tenth NMOS transistor, and the source terminal is connected to the drain terminal of the fourth NMOS transistor; the gate terminal of the tenth PMOS transistor is connected to the gate terminal of the ninth PMOS transistor, and the source terminal is connected to the drain terminal of the fourth PMOS transistor; the gate terminal of the eleventh PMOS transistor is connected to the gate terminal of the ninth PMOS transistor, and the source terminal is connected to the drain terminal of the fifth PMOS transistor; the drain terminal of the fourth PMOS transistor is connected to the source terminal of the tenth PMOS transistor, the gate terminal is connected to the gate terminal of the third PMOS transistor, and the source terminal is connected to the input voltage V IN ; the drain terminal of the fifth PMOS transistor is connected to the source terminal of the eleventh PMOS transistor, the gate terminal is connected to the gate terminal of the third PMOS transistor, and the source terminal is connected to the input voltage V IN ; the drain terminal of the third PMOS transistor is connected to the source terminal of the ninth PMOS transistor, the gate terminal is connected to the source terminal of the ninth PMOS transistor, and the source terminal is connected to the input voltage V IN ; the drain terminal of the ninth PMOS transistor is connected to the upper end of the bias current source, the gate terminal is connected to the upper end of the bias current source, and the source terminal is connected to the drain terminal of the third PMOS transistor.

4. The low quiescent current LDO circuit according to claim 2, characterized in that, The in-phase amplifier is jointly composed of a fifth NMOS transistor to a seventh NMOS transistor, a twelfth NMOS transistor, a sixth PMOS transistor to an eighth PMOS transistor; the drain terminal of the fifth NMOS transistor is connected to the source terminal of the twelfth NMOS transistor, the gate terminal is connected to the gate terminal of the first NMOS transistor, and the source terminal is grounded; the drain terminal of the sixth NMOS transistor is connected to the drain terminal of the seventh PMOS transistor, the gate terminal is connected to the drain terminal of the seventh NMOS transistor, and the source terminal is grounded; the drain terminal of the seventh NMOS transistor is connected to the drain terminal of the eighth PMOS transistor, the gate terminal is connected to the gate terminal of the sixth NMOS transistor, and the source terminal is grounded; the drain terminal of the twelfth NMOS transistor is connected to the drain terminal of the sixth PMOS transistor, the gate terminal is connected to the drain terminal of the eleventh NMOS transistor, and the source terminal is connected to the drain terminal of the fifth NMOS transistor; the drain terminal of the sixth PMOS transistor is connected to the drain terminal of the twelfth NMOS transistor, the gate terminal is connected to the drain terminal of the twelfth NMOS transistor, and the source terminal is connected to the input voltage V IN ; the drain terminal of the seventh PMOS transistor is connected to the drain terminal of the sixth NMOS transistor, the gate terminal is connected to the gate terminal of the sixth PMOS transistor, and the source terminal is connected to the input voltage V IN ; the drain terminal of the eighth PMOS transistor is connected to the drain terminal of the seventh NMOS transistor, the gate terminal is connected to the gate terminal of the twelfth NMOS transistor, and the source terminal is connected to the input voltage V IN .

5. The low quiescent current LDO circuit according to claim 1, characterized in that, The variable feedback resistor includes resistor R F , capacitor C F , the fourteenth NMOS transistor to the eighteenth NMOS transistor, NMOS transistors M NR2 to M NR3 , the twelfth PMOS transistor, the thirteenth PMOS transistor; the upper end of resistor R F is connected to the source end of the eighteenth NMOS transistor, and the lower end is connected to the upper end of capacitor C F ; the lower end of capacitor C F is connected to port V OUT ; the drain end of the fourteenth NMOS transistor is connected to the source end of the fifteenth NMOS transistor, the gate end is connected to the source end of the fifteenth NMOS transistor, and the source end is grounded; the drain end of the fifteenth NMOS transistor is connected to the source end of the seventeenth NMOS transistor, the gate end is connected to the source end of the seventeenth NMOS transistor, and the source end is connected to the drain end of the fourteenth NMOS transistor; the drain end of the seventeenth NMOS transistor is connected to the drain end of the twelfth PMOS transistor, the gate end is connected to port V OUT , and the source end is connected to the drain end of the fifteenth NMOS transistor; the drain end of the twelfth PMOS transistor is connected to the drain end of the seventeenth NMOS transistor, the gate end is connected to the drain end of the seventeenth NMOS transistor, and the source end is connected to the input voltage V IN ; the drain end of the sixteenth NMOS transistor is connected to the source end of the eighteenth NMOS transistor, the gate end is connected to the source end of the eighteenth NMOS transistor, and the source end is grounded; the drain end of the eighteenth NMOS transistor is connected to the drain end of the thirteenth PMOS transistor, the gate end is connected to the drain end of the thirteenth PMOS transistor, and the source end is connected to the drain end of the sixteenth NMOS transistor; NMOS transistor M NR2 has its drain terminal connected to port V FEEDBCAK , its gate terminal connected to the drain terminal of the thirteenth PMOS transistor, and its source terminal connected to the drain terminal of NMOS transistor M NR3 ; the drain terminal of NMOS transistor M NR3 is connected to the source terminal of NMOS transistor M NR2 , its gate terminal connected to the gate terminal of the sixteenth NMOS transistor, and its source terminal grounded; the drain terminal of the thirteenth PMOS transistor is connected to the drain terminal of the eighteenth NMOS transistor, its gate terminal connected to the drain terminal of the seventeenth NMOS transistor, and its source terminal connected to the input voltage V IN .

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