Display panel

Abstract

The application discloses a display panel. The pixel circuit comprises a driving module, a storage module, a charging and discharging module and a refreshing switch module. The driving module is used for generating a driving current in response to the voltage of the control end thereof. The storage module is electrically connected with the driving module. The storage module is used for storing the potential of the control end of the driving module. The charging and discharging module is electrically connected with the driving module. The charging and discharging module is used for charging and discharging the control end of the driving module. The charging and discharging path exists between the charging and discharging module and the control end of the driving module. The refreshing switch module is connected in series in the charging and discharging path. The refreshing switch module controls the on-off of the charging and discharging path in response to the refreshing control signal, so as to realize the refreshing frequency switching of the pixel circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel. Background Technology

[0002] With the development of display technology, the application scenarios of display panels are increasing, and users' display needs are becoming more diversified. For example, multiple display scenarios exist on the same screen, and different display scenarios have different requirements for refresh rates. By redesigning the scan drive circuit, it is possible to achieve zoned frequency division, thereby balancing display requirements and low power consumption requirements. However, because the internal structure of the scan drive circuit is cascaded, there are certain limitations when performing zoned frequency division. Therefore, existing display panels cannot achieve flexible zoned frequency division. Summary of the Invention

[0003] This invention provides a display panel that enables flexible segmentation and frequency division of the display panel.

[0004] To achieve the above technical objectives, embodiments of the present invention provide the following technical solution: a pixel circuit, comprising: The drive module generates drive current in response to the voltage at its control terminal; The storage module is electrically connected to the drive module; the storage module is used to store the potential of the control terminal of the drive module. The charging and discharging module is electrically connected to the drive module; the charging and discharging module is used to charge and discharge the control terminal of the drive module; there is a charging and discharging path between the charging and discharging module and the control terminal of the drive module. The refresh switch module is connected in series in the charging and discharging path; the refresh switch module responds to the refresh control signal and controls the on and off of the charging and discharging path to achieve the switching of the refresh frequency of the pixel circuit.

[0005] Accordingly, the present invention also provides a display panel, including: a refresh control signal line and a plurality of pixel circuits as in any embodiment of the present invention; The refresh switch module of at least one row of pixel circuits is electrically connected to the same refresh control signal line, and each row of pixel circuits includes multiple pixel circuits arranged along a first direction.

[0006] Accordingly, the present invention also provides a driving method for a display panel provided in any embodiment of the present invention, comprising: If the scan reaches the pixel circuit that needs to be refreshed, the refresh control signal on the refresh control signal line is at the on level. If the scan reaches a pixel circuit that does not require refreshing, the refresh control signal on the refresh control signal line is at the off level.

[0007] This invention provides a novel pixel circuit by connecting a refresh switch module in series in the charging and discharging path of the driving module. This refresh switch module controls whether the pixel is refreshed. Specifically, when a pixel needs to be refreshed, the refresh switch module is turned on; when a pixel does not need to be refreshed, the refresh switch module is turned off. Since the main power consumption of the pixel circuit is in the charging and discharging process of the driving module, disconnecting the charging and discharging path of the driving module so that the driving module does not refresh will reduce power consumption. This invention can control the pixel refresh frequency without redesigning the scanning driving circuit. Furthermore, this invention can achieve individual control of the refresh frequency of each pixel. The high-frequency (or low-frequency) area can be selected at any position on the display panel, and the high-frequency (or low-frequency) area can be adjusted at any time according to display needs. Therefore, compared with the prior art, the segmented frequency method of this invention is more flexible.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the driving timing for normal pixel refresh provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a driving timing for reducing the refresh rate of a pixel, provided in an embodiment of the present invention. Figure 5 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 6 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 7 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 8 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 9 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 10 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 11 A schematic diagram of yet another pixel circuit provided in an embodiment of the present invention; Figure 12 A schematic diagram of another normal pixel refresh driving timing provided in an embodiment of the present invention; Figure 13 A schematic diagram of another driving timing for reducing the refresh rate of a pixel according to an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 15 This is a schematic diagram illustrating the principle of a display panel implementing frequency division in an embodiment of the present invention; Figure 16 This is a schematic diagram of a structure for two-column pixel circuits sharing a refresh control signal line, provided in an embodiment of the present invention. Figure 17 A schematic diagram illustrating another display panel implementation of frequency division in an embodiment of the present invention; Figure 18 This is a schematic diagram of a driving method for frequency division and partitioning of a display panel provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another driving method for frequency division and partitioning of a display panel provided in an embodiment of the present invention; Figures 20-22 A schematic diagram illustrating another driving method for different frequency division zones of a display panel provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of another display panel frequency division and partitioning structure provided in an embodiment of the present invention; Figure 24 This is a schematic diagram of another display panel frequency division and partitioning structure provided in an embodiment of the present invention; Figure 25 This is a schematic diagram of another display panel frequency division and partitioning structure provided in an embodiment of the present invention. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1 The pixel circuit includes: a driving module 100, a storage module 200, a charging and discharging module 300, and a refresh switch module 400.

[0014] The drive module 100 generates a drive current in response to the voltage at its control terminal 101. The storage module 200 is electrically connected to the drive module 100 and stores the potential of the control terminal 101 of the drive module 100. The charge / discharge module 300 is electrically connected to the drive module 100 and charges / discharges the control terminal 101 of the drive module 100. Specifically, a charge / discharge path exists between the charge / discharge module 300 and the control terminal 101 of the drive module 100 (e.g., ...). Figure 1 (As shown by the dashed arrow in the middle), the charge / discharge module 300 controls the charge / discharge of the drive module 100's control terminal 101 through the charge / discharge path. The refresh switch module 400 is connected in series in the charge / discharge path; the refresh switch module 400 responds to the refresh control signal Data_SW to control the on / off state of the charge / discharge path, thereby switching the refresh frequency of the pixel circuit.

[0015] For example, the working principle of this pixel circuit to achieve refresh rate switching is as follows: When the pixel is refreshed normally, the refresh control signal Data_SW turns on the refresh switch module 400, and the charge / discharge module 300 writes the data signal Data to the control terminal 101 of the driver module 100. The potential of the control terminal 101 changes, realizing the charging and discharging of the driver module 100. At this time, the driver module 100 responds to the potential of its control terminal 101 by generating a corresponding driving current, driving the OLED light-emitting device to emit light. Simultaneously, the storage module 200 stores the potential of the control terminal 101 of the driver module 100 until the next pixel refresh.

[0016] When the refresh rate of this pixel decreases, the refresh control signal Data_SW controls the refresh switch module 400 to disconnect. Even if the charge / discharge module 300 is turned on, the data signal Data cannot be written to the control terminal 101 of the drive module 100, causing the potential of the control terminal 101 to remain in the state of the last refresh. The refresh switch module 400 cuts off the charge / discharge path for the drive module 100, preventing this pixel from being refreshed.

[0017] This invention provides a novel pixel circuit by connecting a refresh switch module 400 in series in the charging and discharging path of the driving module 100. This refresh switch module 400 controls whether the pixel is refreshed. Specifically, when a pixel needs to be refreshed, the refresh switch module 400 is turned on; when a pixel does not need to be refreshed, the refresh switch module 400 is turned off. Since the main power consumption of the pixel circuit is in the charging and discharging process of the driving module 100, disconnecting the charging and discharging path of the driving module 100 prevents it from refreshing, thus reducing power consumption. This invention does not require redesigning the scanning driving circuit to control the pixel refresh frequency. Furthermore, this invention allows for individual control of the refresh frequency of each pixel. The high-frequency (or low-frequency) area can be selected at any position on the display panel, and the high-frequency (or low-frequency) area can be adjusted at any time according to display needs. Therefore, compared with the prior art, the segmented frequency method of this invention is more flexible.

[0018] There are various specific implementations of the pixel circuit provided in the embodiments of the present invention. Several of them will be specifically described below, but they are not intended to limit the present invention.

[0019] Figure 2 A schematic diagram of another pixel circuit provided in an embodiment of the present invention. See also Figure 2 In one embodiment of the present invention, optionally, the charging and discharging module 300 includes: a first data writing unit 310, a threshold compensation unit 320, and a first reset unit 330.

[0020] Specifically, the first data writing unit 310 is electrically connected to the first terminal of the drive module 100, and the first data writing unit 310 is used to write the data signal Data to the first terminal of the drive module 100. The threshold compensation unit 320 is connected between the second terminal of the drive module 100 and the control terminal 101. When the first data writing unit 310 and the threshold compensation unit 320 are turned on, the data signal Data can be written to the control terminal 101 of the drive module 100.

[0021] The first reset unit 330 is electrically connected to the control terminal 101 of the drive module 100. The first reset unit 330 is used to write the reset signal Vref into the control terminal 101 of the drive module 100 to reset the control terminal 101 of the drive module 100.

[0022] See also Figure 2 Optionally, the pixel circuit further includes: a first light-emitting control module 500, a second light-emitting control module 600, and a reset module 700.

[0023] Specifically, the first light-emitting control module 500 is electrically connected to the first terminal of the driving module 100, and the first light-emitting control module 500 is used to write the first power supply ELVDD to the first terminal of the driving module 100. The second light-emitting control module 600 is connected between the second terminal of the driving module 100 and the first electrode (e.g., anode) of the light-emitting device OLED. Since the second electrode (e.g., cathode) of the light-emitting device OLED is connected to the second power supply ELVSS, the first light-emitting control module 500, the driving module 100, the second light-emitting control module 600, and the light-emitting device OLED constitute the path for the driving current. When the first light-emitting control module 500 and the second light-emitting control module 600 are turned on, the driving current generated by the driving module 100 can flow into the light-emitting device OLED. The reset module 700 is electrically connected to the first electrode (e.g., anode) of the light-emitting device OLED, and the reset module 700 is used to write the reset signal Vref to the first electrode (e.g., anode) of the light-emitting device OLED, thereby resetting the first electrode (e.g., anode) of the light-emitting device OLED. If the anode of the light-emitting device OLED is reset, the reset module 700 can also be called the anode reset module.

[0024] exist Figure 2 In the pixel circuit shown, the first data writing unit 310, the driving module 100 and the threshold compensation unit 320 constitute the first charging and discharging path of the driving module 100; the first reset unit 330 constitutes the second charging and discharging path of the driving module 100.

[0025] Accordingly, the refresh switch module 400 includes a first switch unit 410 and a second switch unit 420. The first switch unit 410 and the threshold compensation unit 320 are connected in series between the second terminal and the control terminal of the drive module 100, for controlling the first charging / discharging path. The second switch unit 420 and the first reset unit 330 are connected in series between the control terminal and the reset signal line of the drive module 100, for controlling the second charging / discharging path.

[0026] The working principle of the pixel circuit provided in the embodiments of the present invention will be explained below in conjunction with the driving timing. Figure 3 This is a schematic diagram illustrating the driving timing for normal pixel refresh according to an embodiment of the present invention. (In conjunction with...) Figure 2 and Figure 3 For example, the first data writing unit 310 and the threshold compensation unit 320 are controlled by the first scan signal S1, the first reset unit 330 is controlled by the second scan signal S2, the reset module 700 is controlled by the third scan signal S3, the first light-emitting control module 500 and the second light-emitting control module 600 are controlled by the light-emitting control signal EM, and the first switching unit 410 and the second switching unit 420 are controlled by the refresh control signal Data_SW. For example, when each control signal is low, the corresponding module or unit is turned on; when each control signal is high, the corresponding module or unit is turned off.

[0027] When a pixel is refreshed normally, the driving process of the pixel circuit includes the following stages: In the first initialization phase T11, the refresh control signal Data_SW and the second scan signal S2 are at an on level, for example, a low level, while other control signals are at an off level, for example, a high level. At this time, the refresh control signal Data_SW controls the first switch unit 410 and the second switch unit 420 to be turned on, and the second scan signal S2 controls the first reset unit 330 to be turned on. In this way, the second charging and discharging path is turned on, and the reset signal Vref is written to the control terminal 101 of the drive module 100 through the second switch unit 420 and the first reset unit 330 in sequence, so that the drive module 100 is in a turned-on state in the data writing phase T12.

[0028] During the data writing phase T12, the refresh control signal Data_SW and the first scan signal S1 are at on levels, for example, low levels, while other control signals are at off levels, for example, high levels. At this time, the refresh control signal Data_SW controls the first switching unit 410 and the second switching unit 420 to conduct, and the first scan signal S1 controls the first data writing unit 310 and the threshold compensation unit 320 to conduct. Thus, the first charging / discharging path is activated, and the data signal Data sequentially passes through the first data writing unit 310, the driving module 100, the first switching unit 410, and the threshold compensation unit 320, ensuring that the voltage at the control terminal 101 of the driving module 100 includes the threshold voltage of the driving module 100.

[0029] In the second initialization phase T13, the refresh control signal Data_SW and the third scan signal S3 are at the on level, for example, low level, while other control signals are at the off level, for example, high level. At this time, the refresh control signal Data_SW controls the first switch unit 410 and the second switch unit 420 to be turned on, and the third scan signal S3 controls the reset module 700 to be turned on. The reset signal Vref is written to the anode of the OLED through the reset module 700 to reset the anode of the OLED, thereby preventing the voltage of the previous frame from affecting the current frame.

[0030] During the light-emitting stage T14, the light-emitting control signal EM is at an on level, such as a low level, while other control signals are at an off level, such as a high level. At this time, the light-emitting control signal EM controls the first light-emitting control module 500 and the second light-emitting control module 600 to conduct. This opens the path for the drive current, and the drive module 100 generates a drive current, the magnitude of which is related to the data signal Data being written. Since the voltage at the control terminal 101 of the drive module 100 includes the threshold voltage of the drive module 100 and can be eliminated in the calculation formula of the drive current, the final generated drive current is not affected by the threshold voltage.

[0031] It should be noted that, in Figure 3 The example illustrates that the refresh control signal Data_SW is low during the first initialization phase T11, the data writing phase T12, and the second initialization phase T13, and is off (e.g., high) during the light-emitting phase T14. This is not intended to limit the invention. In other embodiments, the refresh control signal Data_SW can also be set to an on (e.g., low) level during the light-emitting phase T14. As long as the refresh control signal Data_SW is set to an on (e.g., low) level during the first initialization phase T11 and the data writing phase T12, the technical solution provided by the embodiments of the present invention can be achieved.

[0032] Figure 4 This is a schematic diagram illustrating a driving timing scheme for reducing the refresh rate of a pixel, provided as an embodiment of the present invention. (Combined with...) Figure 2 and Figure 4 When a pixel reduces its refresh rate, the driving process of that pixel circuit includes the following stages: In the first initialization phase T21, the second scan signal S2 is at an on level (e.g., low), while other control signals are at an off level (e.g., high). At this time, the refresh control signal Data_SW controls the first switch unit 410 and the second switch unit 420 to disconnect, thus disconnecting the second charging / discharging path. Although the second scan signal S2 controls the first reset unit 330 to conduct, because the second charging / discharging path is disconnected, the reset signal Vref cannot be written to the control terminal 101 of the drive module 100, and the potential of the control terminal 101 of the drive module 100 remains unchanged.

[0033] During the data writing phase T22, the first scan signal S1 is at an on level, for example, a low level, while other control signals are at an off level, for example, a high level. At this time, the refresh control signal Data_SW controls the first switch unit 410 and the second switch unit 420 to disconnect, thus disconnecting the first charging and discharging path. Although the first scan signal S1 controls the first data writing unit 310 and the threshold compensation unit 320 to be on, the data signal Data cannot be written to the control terminal 101 of the drive module 100 because the first charging and discharging path is disconnected, and the potential of the control terminal 101 of the drive module 100 remains unchanged.

[0034] During the second initialization phase T23, the third scan signal S3 is at an on level (e.g., low), while other control signals are at an off level (e.g., high). At this time, the third scan signal S3 controls the reset module 700 to turn on, and the reset signal Vref is written to the anode of the OLED through the reset module 700, resetting the anode of the OLED.

[0035] During the light-emitting phase T24, the light-emitting control signal EM is at an on level, for example, a low level, while other control signals are at an off level, for example, a high level. At this time, the light-emitting control signal EM controls the first light-emitting control module 500 and the second light-emitting control module 600 to conduct. This opens the path for the drive current, and the drive module 100 generates a drive current. Since the voltage at the control terminal 101 of the drive module 100 has not been refreshed, the magnitude of this drive current is related to the data signal Data written in the previous frame.

[0036] Therefore, Figure 2 The pixel circuit shown is a pixel circuit that includes threshold voltage compensation and can achieve refresh rate switching.

[0037] Figure 5 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 5 Based on the above embodiments, the present invention further refines the configuration of each module.

[0038] In one embodiment of the present invention, optionally, the first switching unit 410 includes a first transistor M1, the gate of the first transistor M1 is connected to a first refresh control signal, and the first transistor M1 is connected in series with the threshold compensation unit 320. This configuration of the first switching unit 410 results in a simple circuit structure that is easy to implement.

[0039] In one embodiment of the present invention, optionally, the second switching unit 420 includes a second transistor M2, the gate of the second transistor M2 is connected to a second refresh control signal, and the second transistor M2 is connected in series with the first reset unit 330. This configuration of the second switching unit 420 results in a simple circuit structure that is easy to implement.

[0040] In one embodiment of the present invention, optionally, the first transistor M1 and the second transistor M2 have the same channel type, and the first refresh control signal is multiplexed as the second refresh control signal, that is, both the first transistor M1 and the second transistor M2 are controlled by the refresh control signal Data_SW. Taking a P-type transistor as an example, when a pixel needs to be refreshed, during the first initialization stage and the data writing stage, the refresh control signal Data_SW is at a low level, and the first transistor M1 and the second transistor M2 are simultaneously turned on; when a pixel does not need to be refreshed, during the first initialization stage and the data writing stage, the refresh control signal Data_SW is at a high level, and the first transistor M1 and the second transistor M2 are simultaneously turned off. This configuration simplifies the process, reduces the number of signal lines, and is easy to implement.

[0041] In one embodiment of the present invention, optionally, the driving module 100 includes a fourth transistor M4, the gate G of the fourth transistor M4 serving as the control terminal 101 of the driving module 100, the first terminal S of the fourth transistor M4 serving as the first terminal of the driving module 100, and the second terminal D of the fourth transistor M4 serving as the second terminal of the driving module 100. This configuration of the driving module 100 results in a simple circuit structure that is easy to implement.

[0042] In one embodiment of the present invention, optionally, the first data writing unit 310 includes a fifth transistor M5, the gate of the fifth transistor M5 is connected to a first scan signal S1, the first terminal of the fifth transistor M5 is connected to a data signal Data, and the second terminal of the fifth transistor M5 is electrically connected to the first terminal of the driving module 100. This configuration of the first data writing unit 310 results in a simple circuit structure that is easy to implement.

[0043] In one embodiment of the present invention, optionally, the threshold compensation unit 320 includes a sixth transistor M6, the gate of the sixth transistor M6 is connected to the first scan signal S1, the first terminal of the sixth transistor M6 is electrically connected to the second terminal of the driving module 100, and the second terminal of the sixth transistor M6 is electrically connected to the control terminal 101 of the driving module 100. Preferably, the sixth transistor M6 is a dual-gate transistor, equivalent to transistor M6-1 and transistor M6-2 connected in series. The dual-gate transistor has the advantage of lower leakage current compared to a single-gate transistor. This configuration helps to reduce leakage current in the first charging and discharging path, thereby maintaining voltage stability at the control terminal 101 of the driving module 100.

[0044] Optionally, since the first transistor M1 and the sixth transistor M6 are connected in series, similar to the sixth transistor M6 being configured with a dual-gate structure, the leakage current of the first charging and discharging path is reduced when the first transistor M1 is off. Therefore, in one embodiment, controlling the first transistor M1 and the sixth transistor M6 to be in the same on state during pixel refresh is beneficial for reducing the leakage current of the first charging and discharging path.

[0045] In one embodiment of the present invention, optionally, the first reset unit 330 includes a seventh transistor, the gate of the seventh transistor M7 is connected to the second scan signal S2, the first terminal of the seventh transistor M7 is connected to the reset signal Vref, and the second terminal of the seventh transistor M7 is electrically connected to the control terminal 101 of the drive module 100. Preferably, the seventh transistor M7 is a dual-gate transistor, equivalent to transistors M7-1 and M7-2 connected in series. The dual-gate transistor has the advantage of lower leakage current compared to a single-gate transistor. This configuration helps reduce leakage current in the second charging and discharging path, thereby maintaining voltage stability at the control terminal 101 of the drive module 100.

[0046] Optionally, since the second transistor M2 is connected in series with the seventh transistor M7, similar to the seventh transistor M7 being configured with a dual-gate structure, the leakage current of the second charging and discharging path is reduced when the second transistor M2 is off. Therefore, in one embodiment, controlling the conduction state of the second transistor M2 and the seventh transistor M7 to be the same during pixel refresh is beneficial to reducing the leakage current of the second charging and discharging path.

[0047] In one embodiment of the present invention, optionally, the first light-emitting control module 500 includes an eighth transistor M8, the gate of the eighth transistor M8 is connected to the light-emitting control signal EM, the first terminal of the eighth transistor M8 is electrically connected to the first terminal of the driving module 100, and the second terminal of the eighth transistor M8 is connected to the first power supply ELVDD. This configuration of the first light-emitting control module 500 results in a simple circuit structure that is easy to implement.

[0048] In one embodiment of the present invention, optionally, the second light-emitting control module 600 includes a ninth transistor M9, the gate of the ninth transistor M9 is connected to the light-emitting control signal EM, the first terminal of the ninth transistor M9 is electrically connected to the second terminal of the driving module 100, and the second terminal of the ninth transistor M9 is electrically connected to the first terminal (e.g., the anode) of the light-emitting device OLED. This configuration of the second light-emitting control module 600 results in a simple circuit structure that is easy to implement.

[0049] In one embodiment of the present invention, optionally, the reset module 700 includes a tenth transistor M10, the gate of the tenth transistor M10 is connected to a third scan signal S3, the first electrode of the tenth transistor M10 is connected to a reset signal Vref, and the second electrode of the tenth transistor M10 is electrically connected to the first electrode (e.g., the anode) of the light-emitting device OLED. This configuration of the reset module 700 results in a simple circuit structure that is easy to implement.

[0050] In one embodiment of the present invention, optionally, the storage module 200 includes a storage capacitor Cst, with the first plate of the storage capacitor Cst serving as the first terminal of the storage module 200, and the second plate of the storage capacitor Cst serving as the second terminal of the storage module 200. This configuration of the storage module 200 results in a simple circuit structure that is easy to implement.

[0051] It should be noted that in the above embodiments, the refresh switch module 400 is configured such that the first switch unit 410 and the threshold compensation unit 320 are connected in series to cut off the first charging and discharging path, and the second switch unit 420 and the first reset unit 330 are connected in series to cut off the second charging and discharging path. When the pixel does not need to be refreshed, during the data writing stage T22, the first data writing unit 310 can be normally turned on, and the data signal Data on the data line will still be written to the first terminal of the driver module 100, but this will not affect the normal operation of the pixel circuit. Because during the light emission stage T24, the first power supply ELVDD will be written to the first terminal of the driver module 100, thereby avoiding the influence of the data signal Data on the first terminal of the driver module 100.

[0052] Figure 6 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 6 Based on the above embodiments, optionally, the refresh switch module 400 further includes a third switch unit 430, which is connected in series with the first data writing unit 310 between the first end of the drive module 100 and the data line. When the pixel does not need to be refreshed, the third switch unit 430 can cut off the writing of the data signal Data to the first end of the drive module 100.

[0053] See also Figure 6Optionally, the third switching unit includes a third transistor M3, the gate of which is connected to a third refresh control signal. The third transistor M3 is connected in series with the first data writing unit 310. Optionally, the first transistor M1, the second transistor M2, and the third transistor M3 have the same channel type. The first refresh control signal is multiplexed into a second refresh control signal and a third refresh control signal, that is, the first transistor M1, the second transistor M2, and the third transistor M3 are all controlled by the refresh control signal Data_SW. Taking a P-type transistor as an example, when a pixel needs to be refreshed, during the first initialization stage and the data writing stage, the refresh control signal Data_SW is at a conducting level, for example, a low level, and the first transistor M1, the second transistor M2, and the third transistor M3 are simultaneously turned on; when a pixel does not need to be refreshed, during the first initialization stage and the data writing stage, the refresh control signal Data_SW is at a turning-off level, for example, a high level, and the first transistor M1, the second transistor M2, and the third transistor M3 are simultaneously turned off. This configuration is simple in process, has fewer signal lines, and is easy to implement.

[0054] It should be noted that, in the above embodiments, the first switch unit 410, the second switch unit 420, and the third switch unit 430 are exemplarily shown to be controlled by the same refresh control signal Data_SW. This is not a limitation of the present invention. In other embodiments, the first switch unit 410, the second switch unit 420, and the third switch unit 430 may be controlled by different control signals.

[0055] Figure 7 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 7In one embodiment of the present invention, optionally, the first switching unit 410 is controlled by a first refresh control signal Data_SWb, and the second switching unit 420 is controlled by a second refresh control signal Data_SWa. Optionally, in the same pixel circuit, the first refresh control signal Data_SWb and the second refresh control signal Data_SWa are different and can be transmitted through different refresh control signal lines. Optionally, the first refresh control signal Data_SWb can be transmitted through the first refresh control signal line, and the second refresh control signal Data_SWa can be transmitted through the second refresh control signal line. The advantage of this setup is that it allows for precise control of the timing of each pixel circuit. For example, the refresh control signal Data_SWb is only active during the data writing phase of the pixel circuit that needs to be refreshed, and the refresh control signal Data_SWa is only active during the first initialization phase of the pixel circuit that needs to be refreshed. This avoids the situation where, when the first switching unit 410 and the second switching unit 420 use the same refresh control signal Data_SW, the pixel circuit that needs to be refreshed in the previous row needs to turn off the refresh control signal Data_SW after the data writing phase, while the pixel circuit that doesn't need to be refreshed in the next row needs to turn off the refresh control signal Data_SW before the first initialization phase. Since the data writing phase of the pixel circuit that needs to be refreshed in the previous row and the first initialization phase of the pixel circuit that doesn't need to be refreshed in the next row coincide, the pixel circuit that needs to be refreshed in the previous row cannot write data correctly. Therefore, setting the refresh control signals separately helps avoid display problems caused by inaccurate control, thereby improving the display quality of the display panel. Optionally, in two adjacent rows of pixel circuits, the data writing phase of the previous row of pixel circuits overlaps with the first initialization phase of the next row of pixel circuits, for example, they coincide. The start time of the data writing phase of the previous row of pixel circuits and the start time of the first initialization phase of the next row of pixel circuits are the same, and the end time of the data writing phase of the previous row of pixel circuits and the end time of the first initialization phase of the next row of pixel circuits are the same. At the boundary line of two adjacent frequency division zones, in two adjacent rows of pixel circuits located on both sides of the boundary line, the previous row of pixel circuits adjacent to the boundary line needs to be refreshed, while the next row of pixel circuits adjacent to the boundary line does not need to be refreshed. At the end time of the data writing phase of the previous row of pixel circuits, the first refresh control signal Data_SWb changes from an on level to an off level. At the start time of the first initialization phase of the next row of pixel circuits, the second refresh control signal Data_SWa changes from an on level to an off level.At the boundary line between two adjacent frequency division zones, in the two adjacent rows of pixel circuits located on both sides of the boundary line, the pixel circuit in the row above the boundary line does not need to be refreshed, while the pixel circuit in the row below the boundary line does need to be refreshed. At the end of the data writing phase of the pixel circuit in the row above, the first refresh control signal Data_SWb changes from off level to on level. At the beginning of the first initialization phase of the pixel circuit in the row below, the second refresh control signal Data_SWa changes from off level to on level.

[0056] Figure 8 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 8 In one embodiment of the present invention, optionally, unlike the foregoing embodiments, the first switching unit 410 is connected in series between the threshold compensation unit 320 and the control terminal 101 of the driving module 100, and the second switching unit 420 is not provided. The first end of the first switching unit 410 is electrically connected to the control terminal 101 of the driving module 100, the second end of the first switching unit 410 is electrically connected to the second end of the driving module 100 via the threshold compensation unit 320, and the second end of the first switching unit 410 is electrically connected to the reset signal line via the first reset unit 330. With this configuration, when the pixel circuit is refreshed, the first switching unit 410 can be controlled to be turned on at least during the first initialization stage and the data writing stage; when the pixel circuit does not need to be refreshed, the first switching unit 410 can be controlled to be turned off at least during the first initialization stage and the data writing stage. The specific driving method can be referred to the foregoing embodiments, and will not be repeated here.

[0057] See also Figure 8 Optionally, the first switching unit 410 includes a first transistor M1, which is connected in series between the threshold compensation unit 320 and the control terminal 101 of the driving module 100. The gate of the first transistor M1 is connected to the refresh control signal Data_SW. This configuration results in a simple circuit structure that is easy to implement.

[0058] It should be noted that in the above embodiments, the sixth transistor M6 and the seventh transistor M7 are shown to be dual-gate transistors, which is not a limitation of the present invention. In other embodiments, at least one of them may be a single-gate transistor.

[0059] Figure 9 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 9 In one embodiment of the present invention, optionally, with Figure 8The embodiment shown differs in that the threshold compensation unit 320 is not included. The first terminal of the first switching unit 410 is electrically connected to the control terminal 101 of the drive module 100, the second terminal of the first switching unit 410 is electrically connected to the second terminal of the drive module 100, and the second terminal of the first switching unit 410 is electrically connected to the reset signal line via the first reset unit 330. This configuration allows the control terminal 101 and the second terminal of the drive module 100 to be initialized simultaneously using the reset signal Vref during the first initialization phase when the first switching unit 410 is turned on.

[0060] Figure 10 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 10 In one embodiment of the present invention, optionally, with Figure 8 The difference in the illustrated embodiment is that the first reset unit 330 is electrically connected to the second terminal of the drive module 100, and the threshold compensation unit 320 and the first switch unit 410 are connected in series between the control terminal 101 and the second terminal of the drive module 100. The control terminal of the threshold compensation unit 320 is connected to the fifth scan signal S5. The threshold compensation unit 320 can be turned on in both the first initialization phase and the data writing phase. When the first switch unit 410 and the threshold compensation unit 320 are turned on, the first reset unit 330 can simultaneously initialize the control terminal 101 and the second terminal of the drive module 100 using the reset signal Vref in the first initialization phase. This configuration can further reduce the leakage path of the control terminal 101 of the drive module 100.

[0061] See also Figure 10 Optionally, the first reset unit 330 includes a seventh transistor M7, with the first terminal of the seventh transistor M7 connected to the reset signal Vref, and the second terminal of the seventh transistor M7 electrically connected to the second terminal of the drive module 100. Unlike the previous embodiments, the fifth scan signal S5 is at a conducting level during the first initialization phase and the data writing phase, and the second scan signal S2 is at a conducting level during the first initialization phase. This configuration results in a simple circuit structure that is easy to implement.

[0062] In the above embodiments, the present invention has been specifically described using a pixel circuit with threshold compensation function as an example, which is not intended to limit the present invention. The pixel circuit can also be configured with other structures in the embodiments of the present invention.

[0063] Figure 11 This is a schematic diagram of yet another pixel circuit provided in an embodiment of the present invention. See also... Figure 11In another embodiment of the present invention, optionally, the charging / discharging module 300 includes a second data writing unit 340, which is electrically connected to the control terminal 101 of the driving module 100. The second data writing unit 340 is used to write the data signal Data to the control terminal 101 of the driving module 100. The second data writing unit 340 constitutes the charging / discharging path of the driving module 100. The refresh switch module 400 includes a fourth switch unit 440, which is connected in series with the second data writing unit 340 between the control terminal and the data line of the driving module 100.

[0064] See also Figure 11 Optionally, the second data writing unit 340 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is connected to the fourth scan signal S4, the first terminal of the eleventh transistor M11 is connected to the data signal Data, and the second terminal of the eleventh transistor M11 is electrically connected to the control terminal 101 of the driving module 100. This configuration of the second data writing unit 340 results in a simple circuit structure that is easy to implement.

[0065] See also Figure 11 Optionally, the fourth switching unit 400 includes a twelfth transistor M12, the gate of which is connected to the fourth refresh control signal Data_SW4, and the second terminal of the twelfth transistor M12 is electrically connected to the control terminal 101 of the drive module 100. This configuration of the fourth switching unit 400 results in a simple circuit structure that is easy to implement.

[0066] The working principle of the pixel circuit provided in the embodiments of the present invention will be explained below in conjunction with the driving timing. Figure 12 This is a schematic diagram illustrating another driving timing for normal pixel refresh provided in an embodiment of the present invention. (In conjunction with...) Figure 11 and Figure 12 For example, the fourth transistor M4, the eleventh transistor M11, and the twelfth transistor M12 are all P-type transistors. When their gates are at a low level, the corresponding transistors are turned on; when their gates are at a high level, the corresponding transistors are turned off.

[0067] When a pixel is refreshed normally, the driving process of the pixel circuit includes the following stages: During the data writing phase T31, both the fourth refresh control signal Data_SW and the fourth scan signal S4 are at on level, for example, low level. At this time, the fourth refresh control signal Data_SW controls the twelfth transistor M12 to turn on, and the fourth scan signal S4 controls the eleventh transistor M11 to turn on. In this way, the charging and discharging path is open, and the data signal Data is written to the gate G of the fourth transistor M4 sequentially through the eleventh transistor M11 and the twelfth transistor M12.

[0068] During the light-emitting stage T32, the fourth transistor M4 generates a drive current in response to the data voltage Data written to its gate G. The magnitude of this drive current is related to the data signal Data written this time.

[0069] It should be noted that, in Figure 12 The example illustrates that the fourth refresh control signal Data_SW4 is at an on level (e.g., low) during the data writing phase T31 and at an off level (e.g., high) during the light-emitting phase T32, but this is not intended to limit the invention. In other embodiments, the fourth refresh control signal Data_SW4 can also be set to an on level (e.g., low) during the light-emitting phase T23. As long as the fourth refresh control signal Data_SW4 is set to an on level (e.g., low) during the data writing phase T31, the technical solution provided by the embodiments of the present invention can be achieved.

[0070] Figure 13 This is a schematic diagram illustrating another driving timing method for reducing the refresh rate of pixels, provided in an embodiment of the present invention. (Combined with...) Figure 11 and Figure 13 When a pixel reduces its refresh rate, the driving process of that pixel circuit includes the following stages: During the data writing phase T41, the fourth refresh control signal Data_SW is at a shutdown level (e.g., high), while the fourth scan signal S4 is at a conduction level (e.g., low). At this time, the fourth refresh control signal Data_SW controls the twelfth transistor M12 to turn off, thus disconnecting the charging / discharging path of the fourth transistor M4. Although the fourth scan signal S4 controls the eleventh transistor M11 to turn on, because the charging / discharging path of the fourth transistor M4 is disconnected, the data signal Data cannot be written to the gate G of the fourth transistor M4, causing the gate potential of the fourth transistor M4 to remain unchanged.

[0071] During the light-emitting phase T42, the fourth transistor M4 generates a drive current in response to the data voltage Data written to its gate G. Since the gate potential of the fourth transistor M4 is not refreshed, the magnitude of this drive current is related to the data signal Data written in the previous frame.

[0072] In summary, the embodiments of the present invention are applicable to pixel circuits of any structure. Specifically, a refresh switch module 400 is connected in series in the charging and discharging path of the driving module 100, and this refresh switch module 400 controls whether the pixel is refreshed. When a pixel needs to be refreshed, the refresh switch module 400 is turned on; when a pixel does not need to be refreshed, the refresh switch module 400 is turned off. The embodiments of the present invention can achieve control of the pixel refresh frequency without redesigning the scanning driving circuit. Furthermore, the embodiments of the present invention can achieve individual control of the refresh frequency of each pixel. The high-frequency (or low-frequency) region can be selected at any position on the display panel, and the high-frequency (or low-frequency) region can be adjusted at any time according to display needs. Therefore, compared with the prior art, the segmented frequency method of the embodiments of the present invention is more flexible.

[0073] This invention also provides a display panel. Figure 14 This is a schematic diagram of a display panel provided in an embodiment of the present invention. See also... Figure 14 The display panel includes a refresh control signal line 30 and a plurality of pixel circuits 20 as provided in any embodiment of the present invention. The refresh switch modules of at least one row of pixel circuits 20 are electrically connected to the same refresh control signal line to receive the same refresh control signal. Each row of pixel circuits 20 includes a plurality of pixel circuits 20 arranged along a first direction X.

[0074] Optionally, the display panel also includes a refresh control signal line 30 extending along a first direction X. A first switching unit 410 and / or a second switching unit 420 of a row of pixel circuits 20 are electrically connected to the same refresh control signal line 30; alternatively, the first switching unit 410 and the second switching unit 420 of a row of pixel circuits 20 are electrically connected to one refresh control signal line 30 or two different refresh control signal lines 30. At least one row of pixel circuits 20 shares the same one or two refresh control signal lines 30.

[0075] The refresh control signal line 30 is connected to the refresh switch module in each pixel circuit 20 to control the on / off state of the refresh switch module. Since the display panel includes the pixel circuit 20 provided in any embodiment of the present invention, its technical principle and the resulting effect are similar, and will not be described again.

[0076] Optionally, one or more rows of pixel circuits 20 are electrically connected to a refresh control signal line 30, or multiple rows of pixel circuits 20 are electrically connected to multiple refresh control signal lines 30, and the multiple refresh control signal lines 30 are electrically connected to each other and connected to the same refresh control signal. On the one hand, this can realize flexible segmented frequency control, thereby reducing the power consumption of the display panel; on the other hand, it can reduce the number of signal lines and simplify the structure of the display panel.

[0077] See also Figure 14Based on the above embodiments, optionally, the display panel further includes multiple data lines 60 extending along a first direction X and arranged along a second direction Y, wherein the first direction X and the second direction Y intersect. The extension direction of the refresh control signal line 30 is the same as the extension direction of the data lines.

[0078] Optionally, the display panel further includes a scanning circuit 70 and multiple scanning lines 50 (capable of outputting a first scanning signal S1, a second scanning signal S2, etc.). The multiple scanning lines extend along the second direction Y and are arranged along the first direction X. The scanning circuit 70 is electrically connected to the pixel circuits 20 in the corresponding row via the corresponding scanning lines 50. Each row of pixel circuits 20 includes multiple pixel circuits 20 arranged along the second direction Y. The scanning lines 50 are used to provide scanning signals (e.g., the first scanning signal S1, the second scanning signal S2, etc.) to the pixel circuits 20 for refreshing them. Therefore, the refresh direction of the display panel can be parallel to the first direction X. This arrangement is beneficial for both the wiring design of the display panel and the flexible segmentation and frequency control of the display panel. In some optional embodiments, the extension direction of the refresh control signal line 30 can also be set to be on the same layer as the data line.

[0079] The following description uses the first direction X as the column direction and the second direction Y as the row direction as an example to illustrate the frequency division method of the present invention.

[0080] See also Figure 14 In one implementation, optionally, a row of pixel circuits 20 shares a single refresh control signal line 30. In this case, the level change on the refresh control signal line 30 is adjusted according to whether each pixel circuit 20 needs to be refreshed.

[0081] Specifically, Figure 15 This is a schematic diagram illustrating the principle of a display panel implementing frequency division in an embodiment of the present invention. See also... Figure 15Taking a five-row pixel circuit 20 as an example, the scan signal Scan1 is the scan signal of the first row of pixel circuits 20 (e.g., the first scan signal S1 or the second scan signal S2, etc.), the scan signal Scan2 is the scan signal of the second row of pixel circuits 20, and so on. The refresh direction of the pixel circuits 20 is to refresh row by row from the first row of pixel circuits 20 to the fifth row of pixel circuits 20. When the scan signal Scan1 is low, the first row of pixel circuits 20 is scanned. At this time, the refresh control signal Data_SW is low, and the first row of pixel circuits 20 is refreshed normally. When the scan signal Scan2 is low, the second row of pixel circuits 20 is scanned. At this time, the refresh control signal Data_SW is high, and the second row of pixel circuits 20 retains the data signal of the previous frame, which is equivalent to the second row of pixels not being refreshed. When the scan signal Scan3 is low, the third row of pixel circuits 20 is scanned. At this time, the refresh control signal Data_SW is low, and the third row of pixel circuits 20 is refreshed normally. When the scan signal Scan4 is low, the fourth row of pixel circuits 20 is scanned. At this time, the refresh control signal Data_SW is low, and the fourth row of pixel circuits 20 is refreshed normally. When the scan signal Scan5 is low, the fifth row of pixel circuits 20 is scanned. At this time, the refresh control signal Data_SW is low, and the fifth row of pixel circuits 20 is refreshed normally.

[0082] This control method allows for the control of the refresh rate of any pixel within the entire display panel. Each pixel circuit 20 can constitute the smallest unit for dividing the refresh rate, i.e., a refresh unit. The more times the same pixel circuit is refreshed per unit time, the higher the refresh rate.

[0083] In another embodiment, optionally, two columns of pixel circuits 20 may share a refresh control signal line 30, three columns of pixel circuits 20 may share a refresh control signal line 30, or multiple columns of pixel circuits 20 may share a refresh control signal line 30. In the above embodiments, there are multiple refresh control signal lines 30, which extend along a first direction X and are arranged along a second direction Y. Optionally, each column of pixel circuits 20 is electrically connected to a refresh control signal line 30 extending along the first direction X, and the refresh control signal lines 30 connected to at least two columns of pixel circuits 20 are electrically connected to each other, so that at least two columns of pixel circuits 20 share a refresh control signal line 30 to access the same refresh control signal, thereby reducing the number of ports on the driver chip. Optionally, each column of pixel circuits 20 is electrically connected to two first refresh control signal lines and second refresh control signal lines extending along the first direction X. The first refresh control signal lines to which at least two columns of pixel circuits 20 are electrically connected are interconnected, and the second refresh control signal lines to which at least two columns of pixel circuits 20 are electrically connected are interconnected, so that at least two columns of pixel circuits 20 share refresh control signal lines 30 to access the same refresh control signal, thereby reducing the number of ports on the driver chip.

[0084] Specifically, Figure 16 This is a schematic diagram illustrating a structure where two pixel circuits share a refresh control signal line, as provided in an embodiment of the present invention. See also... Figure 16 In some embodiments, the two refresh control signal lines 30 of the two columns of pixel circuits 20 are electrically connected to each other, or the two columns of pixel circuits 20 share a single refresh control signal line 30, so that the two pixel circuits 20 in the same row constitute a refresh unit 21, which is the smallest unit for dividing the frequency range. Taking the two pixel circuits 20 in the first row and the first two columns as an example, since they both share a single refresh control signal line 30, when the scan line scans the first row of pixel circuits 20, the two pixel circuits receive the same refresh control signal, and therefore the refresh frequency is also the same.

[0085] In other embodiments, the number of refresh control signal lines 30 can be set to only one. In this case, all pixel circuits 20 in the same row constitute a refresh unit 21.

[0086] See also Figure 14 and Figure 16 Based on the above embodiments, optionally, the display panel further includes a driver chip 10, which is connected to each refresh switch module via refresh control signal lines 30; the driver chip 10 is used to control the on / off state of the refresh switch modules. Accordingly, the driver chip 10 includes a number of interfaces equal to the number of refresh control signal lines 30.

[0087] In other embodiments, the extension direction of the refresh control signal line 30 can be set to be the same as the extension direction of the scan line. That is, both the refresh control signal line 30 and the scan line extend along the second direction Y, and the data line extends along the first direction X. Optionally, the number of refresh control signal lines 30 is the same as the number of rows of pixel circuits 20, so that all the pixel circuits 20 in one row constitute a refresh unit 21.

[0088] The signal input method on refresh control signal line 30 also differs from the aforementioned embodiments. Specifically, Figure 17 This is a schematic diagram illustrating another display panel implementation of frequency division in an embodiment of the present invention. See also... Figure 17 Taking the five-row pixel circuit 20 as an example, the scan signal Scan1 is the scan signal of the first row of pixel circuit 20 (e.g., the first scan signal S1 or the second scan signal S2, etc.), the scan signal Scan2 is the scan signal of the second row of pixel circuit 20, and so on. The refresh direction of the pixel circuit 20 is to refresh row by row from the first row of pixel circuit 20 to the fifth row of pixel circuit 20. When the scan signal Scan1 is on, for example, low, it scans to the first row of pixel circuit 20. At this time, the refresh control signal Data_SW1 of the first row is low, and the first row of pixel circuit 20 refreshes normally. When the scan signal Scan2 is on, for example, low, it scans to the second row of pixel circuit 20. At this time, the refresh control signal Data_SW2 is off, for example, high, and the second row of pixel circuit 20 maintains the data signal of the previous frame, which is equivalent to the second row of pixels not being refreshed. When the scan signal Scan3 is on, for example, low, it scans to the third row of pixels. Circuit 20: When the refresh control signal Data_SW3 is at the on level (e.g., low level), the third row pixel circuit 20 refreshes normally. When the scan signal Scan4 is at the on level (e.g., low level), the fourth row pixel circuit 20 is scanned. When the refresh control signal Data_SW4 is at the on level (e.g., low level), the fourth row pixel circuit 20 refreshes normally. When the scan signal Scan5 is at the on level (e.g., low level), the fifth row pixel circuit 20 is scanned. When the refresh control signal Data_SW5 is at the on level (e.g., low level), the fifth row pixel circuit 20 refreshes normally.

[0089] Based on the above embodiments, optionally, the display area of ​​the display panel is divided into at least two frequency division zones; the pixel circuits 20 of adjacent frequency division zones have different refresh frequencies to achieve frequency division.

[0090] Optionally, the boundary lines between adjacent frequency division zones can be adjusted, or the boundary lines between adjacent frequency division zones can be fixed, and can be set as needed in practical applications. Optionally, the boundary lines between adjacent frequency division zones are related to the refresh control signal on the refresh control signal line.

[0091] The following embodiments illustrate the specific partitioning method of the display panel, but are not intended to limit the present invention.

[0092] In one embodiment of the present invention, optionally, Figure 14 The display panel shown can achieve frequency division and partitioning at any position in the first direction X and the second direction Y. Figures 18-22 This is a schematic diagram illustrating the driving method for different frequency division zones of a display panel provided in an embodiment of the present invention. See also... Figure 14 , Figures 18-22 The display panel includes one or more of the following operating modes: In one operating mode, the boundary lines of at least two frequency division partitions extend along a first direction X. For example, see... Figure 18 The display panel includes two frequency-divided zones, separated by a dividing line 40. The left zone has a refresh rate of f1, and the right zone has a refresh rate of f1 / 2. The left zone corresponds to refresh control signal lines 30 numbered 1 to m, with refresh control signals Data_SW1 to Data_SWm respectively; the right zone corresponds to refresh control signal lines 30 numbered m+1 to n, with refresh control signals Data_SWm+1 to Data_SWn respectively.

[0093] The driving method for implementing this working mode is as follows: In frame y, scan signal Scan1 is the scan signal for the first row of pixel circuits 20, ..., scan signal Scanx is the scan signal for the xth row (last row) of pixel circuits 20. The refresh direction of pixel circuits 20 is from the first row of pixel circuits 20 to the xth row of pixel circuits 20. When the scan signal Scan1 is on (e.g., low), scanning reaches the first row of pixel circuits 20. At this time, the refresh control signals Data_SW1~Data_SWm corresponding to the left partition are all on (e.g., low), and the refresh control signals Data_SWm+1~Data_SWn corresponding to the right partition are all on (e.g., low), and the first row of pixel circuits 20 refreshes normally; and so on. When the scan signal Scanx is on (e.g., low), scanning reaches the x-th row of pixel circuits 20. At this time, the refresh control signals Data_SW1~Data_SWm corresponding to the left partition are still on (e.g., low), and the refresh control signals Data_SWm+1~Data_SWn corresponding to the right partition are still on (e.g., low), and the x-th row of pixel circuits 20 refreshes normally. Therefore, in the y-th frame, the pixel circuits 20 in both the left and right partitions refresh normally.

[0094] In frame y+1, the scan signal Scan1 is the scan signal for the first row of pixel circuits 20, ..., the scan signal Scanx is the scan signal for the xth row (last row) of pixel circuits 20. The refresh direction of the pixel circuits 20 is from the first row of pixel circuits 20 to the xth row of pixel circuits 20. When the scan signal Scan1 is on (e.g., low), scanning reaches the first row of pixel circuits 20. At this time, the refresh control signals Data_SW1~Data_SWm corresponding to the left partition are all on (e.g., low), while the refresh control signals Data_SWm+1~Data_SWn corresponding to the right partition are all off (e.g., high). Only the first row of pixel circuits 20 in the left partition refreshes normally, while the first row of pixel circuits 20 in the right partition does not refresh; and so on. When the scan signal Scanx is on (e.g., low), scanning reaches the x-th row of pixel circuits 20. At this time, the refresh control signals Data_SW1~Data_SWm corresponding to the left partition are still on (e.g., low), while the refresh control signals Data_SWm+1~Data_SWn corresponding to the right partition are still off (e.g., high). Only the x-th row of pixel circuits 20 in the left partition refreshes normally, while the x-th row of pixel circuits 20 in the right partition does not refresh. Therefore, in frame y+1, the pixel circuits 20 in the left partition refresh normally, while the pixel circuits 20 in the right partition do not refresh. Therefore, by driving the system with two frames as the minimum loop unit, the refresh rate of the right partition can be half that of the left partition.

[0095] In the above embodiment, the position of the dividing line 40 can be adjusted by changing the value of m, thereby making the position of the vertical dividing line 40 adjustable. In other embodiments, if the position of the dividing line 40 is fixed, the pixel circuits 20 of the left partition can share a refresh control signal line 30, which is equivalent to the refresh control signal lines of the pixel circuits 20 of the left partition being electrically connected to each other; the pixel circuits 20 of the right partition share another refresh control signal line 30, which is equivalent to the refresh control signal lines of the pixel circuits 20 of the right partition being electrically connected to each other. This can be set as needed in practical applications. The refresh control signals of the pixel circuits 20 of the left partition can be the same. The refresh control signals of the pixel circuits 20 of the right partition can be the same. The refresh control signals of the pixel circuits 20 of the left partition are different from those of the pixel circuits 20 of the right partition. The left partition and the right partition can be arranged along the second direction Y.

[0096] In another operating mode, the boundary lines of at least two frequency division partitions extend along the second direction Y. For example, see... Figure 19The display panel includes two frequency-divided zones, separated by a dividing line of 40°. The upper zone has a refresh rate of f1, and the lower zone has a refresh rate of f1 / 2. The upper zone corresponds to scan lines numbered 1 to a, with scan signals Scan1 to Scana respectively; the lower zone corresponds to scan lines numbered a+1 to x, with scan signals Scana+1 to Scanx respectively. Optionally, along the refresh direction, the refresh rate of the frequency-divided zones can gradually decrease, gradually increase, increase first and then decrease, or decrease first and then increase.

[0097] The driving method for implementing this working mode is as follows: In frame y, when the scan signal Scan1 is on (e.g., low), scanning reaches the first row of pixel circuits 20, and all refresh control signals Data_SW1~Data_SWn are on (e.g., low), so the first row of pixel circuits 20 refreshes normally; and so on. When the scan signal Scanx is on (e.g., low), scanning reaches the xth row of pixel circuits 20, and all refresh control signals Data_SW1~Data_SWn are on (e.g., low), so the xth row of pixel circuits 20 refreshes normally. Therefore, in frame y, the pixel circuits 20 in both the upper and lower partitions refresh normally.

[0098] In frame y+1, when the scan signal Scan1 is on (e.g., low), scanning reaches the first row of pixel circuit 20, and all refresh control signals Data_SW1~Data_SWn are on (e.g., low), and the first row of pixel circuit 20 refreshes normally; and so on. When the scan signal Scana is on (e.g., low), scanning reaches the a-th row of pixel circuit 20, and all refresh control signals Data_SW1~Data_SWn are on (e.g., low), and the a-th row of pixel circuit 20 refreshes normally. New; When the scan signal Scana+1 is on (e.g., low), when scanning to the (a+1)th row of pixel circuit 20, all refresh control signals Data_SW1~Data_SWn are off (e.g., high), and the (a+1)th row of pixel circuit 20 does not refresh; and so on; when the scan signal Scanx is on (e.g., low), when scanning to the xth row of pixel circuit 20, all refresh control signals Data_SW1~Data_SWn are off (e.g., high), and the xth row of pixel circuit 20 does not refresh. Therefore, in the (y+1)th frame, the pixel circuit 20 in the upper partition refreshes normally, while the pixel circuit 20 in the lower partition does not refresh. Thus, by driving with two frames as the minimum loop unit (equivalent to one cycle), the refresh frequency of the lower partition can be half the refresh frequency of the upper partition.

[0099] In the above embodiments, the position of the dividing line 40 can be adjusted by adjusting the value of 'a', thereby making the position of the horizontal dividing line 40 adjustable. The position of the horizontal dividing line 40 can also be fixed. In other embodiments, the pixel circuits 20 of the upper partition and the lower partition can share a single refresh control signal line 30, which is equivalent to the refresh control signal lines of the pixel circuits 20 of the upper and lower partitions being electrically connected to each other. This can be configured as needed in practical applications. The refresh control signals of the pixel circuits 20 of the upper and lower partitions can be the same. The upper and lower partitions can be arranged along the first direction X.

[0100] In another operating mode, there are at least three frequency division zones, wherein the boundary lines of at least two frequency division zones extend along a first direction X, and the boundary lines of at least two frequency division zones extend along a second direction Y. For example, see [link to example]. Figures 20-22 The display panel includes four frequency-divided zones, separated by three dividing lines 40°. The refresh rate of the upper left zone is f1, the upper right zone is f1 / 2, the lower left zone is f1 / 4, and the lower right zone is f1 / 8. Driving the display in 8-frame loops achieves the above frequency division, as shown in Table 1.

[0101] Table 1 In Table 1, × indicates that the page is not refreshed.

[0102] For example, the upper left partition corresponds to scan lines numbered 1 to b and refresh control signal lines 30 numbered 1 to m, with scan signals Scan1 to Scanb and refresh control signals Data_SW1 to Data_SWm respectively; the upper right partition corresponds to scan lines numbered 1 to c and refresh control signal lines 30 numbered m+1 to n, with scan signals Scan1 to Scanc and refresh control signals Data_SWm+1 to Data_SWn respectively; the lower left partition corresponds to scan lines numbered b+1 to x and refresh control signal lines 30 numbered 1 to m, with scan signals Scanb+1 to Scanx and refresh control signals Data_SW1 to Data_SWm respectively; the lower right partition corresponds to scan lines numbered c+1 to x and refresh control signal lines 30 numbered m+1 to n, with scan signals Scanc+1 to Scanx and refresh control signals Data_SWm+1 to Data_SWn respectively.

[0103] The driving method for implementing this working mode is as follows: In frame y, when the scan signal Scan1 is on (e.g., low), scanning reaches the first row of pixel circuits 20, and all refresh control signals Data_SW1~Data_SWn are on (e.g., low), so the first row of pixel circuits 20 refreshes normally; and so on. When the scan signal Scanx is on (e.g., low), scanning reaches the xth row of pixel circuits 20, and all refresh control signals Data_SW1~Data_SWn are on (e.g., low), so the xth row of pixel circuits 20 refreshes normally. Therefore, in frame y, pixel circuits 20 in each partition refresh normally.

[0104] In frame y+1, when scanning the pixel circuits 20 from the first to the bth rows, all refresh control signals Data_SW1~Data_SWm are at an on level (e.g., low), and all refresh control signals Data_SWm+1~Data_SWn are at an off level (e.g., high). The pixel circuits 20 in the upper left partition refresh normally. When scanning the remaining rows of pixel circuits 20, all refresh control signals Data_SW1~Data_SWn are at an off level (e.g., high). Therefore, in frame y+1, the pixel circuits 20 in the upper left partition refresh normally, while the other partitions do not refresh.

[0105] In frame y+2, when scanning the pixel circuits 20 from row 1 to row b, all refresh control signals Data_SW1~Data_SWn are at an on level (e.g., low level), and the pixel circuits 20 in the upper left partition and the upper right partition from row 1 to row b are refreshed normally. When scanning the pixel circuits 20 from row b+1 to row c, all refresh control signals Data_SW1~Data_SWm are at an off level (e.g., high level), and all refresh control signals Data_SWm+1~Data_SWn are at an on level (e.g., low level), and the pixel circuits 20 in the upper right partition from row b+1 to row c are refreshed normally. From this point on, the entire upper right partition's pixel circuits 20 are refreshed normally. When scanning the remaining rows of pixel circuits 20, all refresh control signals Data_SW1~Data_SWn are at an off level (e.g., high level). Therefore, in frame y+2, the pixel circuits 20 in the upper left and upper right partitions are refreshed normally, while the other partitions are not refreshed.

[0106] In frame y+3, the driving method is the same as in frame y+1, so it will not be described again.

[0107] In frame y+4, when scanning pixel circuits 20 from row 1 to row c, all refresh control signals Data_SW1~Data_SWn are at the on level (e.g., low level), and the pixel circuits 20 in the upper left and upper right partitions, as well as rows b+1 to c in the lower left partition, are refreshed normally. When scanning pixel circuits 20 from row c+1 to row x, all refresh control signals Data_SW1~Data_SWm are at the on level (e.g., low level), and all refresh control signals Data_SWm+1~Data_SWn are at the off level (e.g., high level), and the pixel circuits 20 in rows c+1 to x in the lower left partition are refreshed normally. From this point on, the entire pixel circuits 20 in the lower left partition are refreshed normally. Therefore, in frame y+4, all partitions are refreshed except for the pixel circuits 20 in the lower right partition.

[0108] In frame y+5, the driving method is the same as in frame y+1, so it will not be described again.

[0109] In frame y+6, the driving method is the same as in frame y+2, so it will not be described again.

[0110] In frame y+7, the driving method is the same as in frame y+1, so it will not be described again.

[0111] Therefore, by driving the system with 8 frames as the minimum loop unit, the refresh rate of the top left partition can be f1, the refresh rate of the top right partition can be f1 / 2, the refresh rate of the bottom left partition can be f1 / 4, and the refresh rate of the bottom right partition can be f1 / 8.

[0112] In the above embodiments, the positions of each dividing line 40 can be adjusted by changing the values ​​of b, c, and m, thereby achieving adjustable positions for the horizontal and vertical dividing lines 40. In other embodiments, if the positions of the dividing lines 40 are fixed, the pixel circuits 20 of each partition can be configured to share a single refresh control signal line 30. In practical applications, this can be configured as needed.

[0113] It should be noted that the foregoing embodiments exemplify frequency division methods such as 2-way, 4-way, and 8-way division, which are not intended to limit the invention. In other embodiments, 3-way, 5-way, and 6-way division can also be implemented, and the settings can be configured as needed in practical applications.

[0114] In other embodiments of the invention, such as Figure 23 and Figure 24 As shown, three partitions can also be implemented; for example... Figure 25 As shown, it can also implement five partitions; and it can also implement flexible partitions of any form. The driving method can be referred to the aforementioned embodiments, and will not be repeated here.

[0115] This invention also provides a driving method for a display panel, applicable to the display panel provided in this invention, and possessing corresponding beneficial effects. The driving method includes: if a pixel circuit requiring refresh is scanned, the refresh control signal on the refresh control signal line is at an on level; if a pixel circuit not requiring refresh is scanned, the refresh control signal on the refresh control signal line is at an off level.

[0116] Optionally, the driving method includes multiple repeatedly refreshed minimum cycle units, each of which includes at least two refresh frames, wherein the number of pixel circuits refreshed by the at least two refresh frames is different, so as to achieve segmentation and frequency division.

[0117] In the refresh frame, the refresh control signal on the refresh control signal line generates a pulse signal following the scan signal; if the scan reaches a pixel circuit that needs to be refreshed, the refresh control signal is at the on level; if the scan reaches a pixel circuit that does not need to be refreshed, the refresh control signal is at the off level.

[0118] In various embodiments of the display panel, specific driving methods are described for different segmentation and frequency divisions. These driving methods can all be considered as driving methods for the display panel provided in the embodiments of the present invention, and repeated content will not be described here.

[0119] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0120] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Refresh control signal lines and multiple pixel circuits; The pixel circuit includes: A drive module, the drive module being used to generate a drive current in response to the voltage at its control terminal; A storage module is electrically connected to the drive module; the storage module is used to store the potential of the control terminal of the drive module. A charging / discharging module is electrically connected to the drive module; the charging / discharging module is used to charge and discharge the control terminal of the drive module; wherein, there is a charging / discharging path between the charging / discharging module and the control terminal of the drive module; A refresh switch module is connected in series in the charging and discharging path; the refresh switch module responds to the refresh control signal to control the on / off state of the charging and discharging path, so as to realize the switching of the refresh frequency of the pixel circuit. The charging and discharging module includes: The first data writing unit is electrically connected to the first terminal of the driving module; the first data writing unit is used to write data signals to the first terminal of the driving module. A threshold compensation unit is connected between the second end of the drive module and the control end; The first reset unit is electrically connected to the control terminal of the drive module; the first reset unit is used to write a reset signal to the control terminal of the drive module. The refresh switch module includes: The first switching unit is connected in series with the threshold compensation unit between the second end and the control end of the drive module; The second switching unit is connected in series with the first reset unit between the control terminal and the reset signal line of the drive module; The refresh control signal line includes a first refresh control signal line and a second refresh control signal line; the first refresh control signal line provides a first refresh control signal for controlling the first switching unit; the second refresh control signal line provides a second refresh control signal for controlling the second switching unit. The refresh switch module of at least one row of the pixel circuits is electrically connected to the same refresh control signal line, and each row of the pixel circuits includes a plurality of the pixel circuits arranged along a first direction; The display panel further includes a scanning circuit and multiple scanning lines. The multiple scanning lines extend along a second direction and are arranged along a first direction. The scanning circuit is electrically connected to the pixel circuit of the corresponding row via the corresponding scanning line. Each row of pixel circuits includes multiple pixel circuits arranged along the second direction. The display panel further includes multiple data lines extending along the first direction and arranged along the second direction, wherein the first direction and the second direction intersect. The refresh control signal line extends along the first direction; The display panel further includes a driver chip, which is connected to each of the refresh switch modules via a refresh control signal line; the driver chip is used to control the on / off state of the refresh switch modules; and the driver chip is connected to each of the pixel circuits via the data line. The driving method of the pixel circuit includes: if the pixel circuit that needs to be refreshed is scanned, the refresh control signal on the refresh control signal line is at the on level; If the scan reaches a pixel circuit that does not require refreshing, the refresh control signal on the refresh control signal line is at the off level. The driving method includes multiple minimum cycle units that are repeatedly refreshed. Each minimum cycle unit includes at least two refresh frames, and the number of pixel circuits refreshed by the at least two refresh frames is different to achieve segmented frequency. The refresh frequency of each pixel circuit is controlled individually, and the segmented frequency area is located at any position on the display panel. In the refresh frame, the refresh control signal on the refresh control signal line generates a pulse signal following the scan signal; if the scan reaches the pixel circuit that needs to be refreshed, the refresh control signal is at the on level, the width of the pulse signal is equal to the width of the scan signal, and there is an interval between the pulse signals of the adjacent rows of pixel circuits that need to be refreshed on the same refresh control signal line; if the scan reaches the pixel circuit that does not need to be refreshed, the refresh control signal is at the off level. In the pixel circuits of two adjacent rows, the data writing stage of the pixel circuit in the previous row overlaps with the first initialization stage of the pixel circuit in the next row; The first data writing unit is used to write a data signal to the first terminal of the driver module during the data writing phase; the first reset unit is used to write a reset signal to the control terminal of the driver module during the first initialization phase. At the boundary line of two adjacent frequency division partitions, in the two adjacent rows of pixel circuits located on both sides of the boundary line, the pixel circuit in the row above the boundary line needs to be refreshed, while the pixel circuit in the row below the boundary line does not need to be refreshed. At the end of the data writing phase of the pixel circuit in the row above, the first refresh control signal changes from an on level to an off level. At the beginning of the first initialization phase of the pixel circuit in the row below, the second refresh control signal changes from an on level to an off level. At the boundary line between two adjacent frequency division zones, in the two adjacent rows of pixel circuits located on both sides of the boundary line, the pixel circuit in the row above the boundary line does not need to be refreshed, while the pixel circuit in the row below the boundary line does need to be refreshed. At the end of the data writing phase of the pixel circuit in the row above, the first refresh control signal changes from a shutdown level to a conduction level. At the beginning of the first initialization phase of the pixel circuit in the row below, the second refresh control signal changes from a shutdown level to a conduction level.

2. The display panel according to claim 1, characterized in that, The first switching unit includes a first transistor, the gate of the first transistor is connected to a first refresh control signal, and the first transistor is connected in series with the threshold compensation unit; The second switching unit includes a second transistor, the gate of which is connected to a second refresh control signal, and the second transistor is connected in series with the first reset unit.

3. The display panel according to claim 2, characterized in that, In the same pixel circuit, the first refresh control signal and the second refresh control signal are different, or the first transistor and the second transistor have the same channel type, and the first refresh control signal is multiplexed as the second refresh control signal.

4. The display panel according to claim 1, characterized in that, The pixel circuit also includes: A first light-emitting control module is electrically connected to a first terminal of the driving module; the first light-emitting control module is used to write a first power supply into the first terminal of the driving module. The second light-emitting control module is connected between the second end of the driving module and the first electrode of the light-emitting device; And / or, a reset module, electrically connected to the first electrode of the light-emitting device; the reset module is used to write a reset signal to the first electrode of the light-emitting device.

5. The display panel according to claim 1, characterized in that, The driving module includes a fourth transistor, the gate of which serves as the control terminal of the driving module, the first electrode of which serves as the first terminal of the driving module, and the second electrode of which serves as the second terminal of the driving module.

6. The display panel according to claim 1, characterized in that, The first data writing unit includes a fifth transistor, the gate of which is connected to a first scan signal, the first terminal of which is connected to the data signal, and the second terminal of which is electrically connected to the first terminal of the driving module.

7. The display panel according to claim 1, characterized in that, The threshold compensation unit includes a sixth transistor, the gate of which is connected to a first scan signal, the first terminal of which is electrically connected to the second terminal of the driving module, and the second terminal of which is electrically connected to the control terminal of the driving module.

8. The display panel according to claim 1, characterized in that, The first reset unit includes a seventh transistor, the gate of which is connected to a second scan signal, the first terminal of which is connected to the reset signal, and the second terminal of which is electrically connected to the control terminal of the drive module.

9. The display panel according to claim 4, characterized in that, The first light-emitting control module includes an eighth transistor, the gate of which is connected to a light-emitting control signal, the first terminal of which is electrically connected to the first terminal of the driving module, and the second terminal of which is connected to the first power supply.

10. The display panel according to claim 4, characterized in that, The second light-emitting control module includes a ninth transistor, the gate of which is connected to a light-emitting control signal, the first terminal of which is electrically connected to the second terminal of the driving module, and the second terminal of which is electrically connected to the anode of the light-emitting device.

11. The display panel according to claim 4, characterized in that, The reset module includes a tenth transistor, the gate of which is connected to a third scan signal, the first terminal of which is connected to the reset signal, and the second terminal of which is electrically connected to the first terminal of the light-emitting device.

12. The display panel according to claim 1, characterized in that, The display panel is divided into at least two frequency-division partitions; the pixel circuits in adjacent frequency-division partitions have different refresh rates.

13. The display panel according to claim 12, characterized in that, The position of the boundary line between adjacent frequency division zones is related to the refresh control signal on the refresh control signal line.

14. The display panel according to claim 12, characterized in that, The display panel includes one or more of the following operating modes: the boundary lines of at least two frequency division zones extend along a first direction; the boundary lines of at least two frequency division zones extend along a second direction; the frequency division zones are at least three, wherein the boundary lines of at least two frequency division zones extend along the first direction, and the boundary lines of at least two frequency division zones extend along the second direction, and the first direction and the second direction intersect.

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