A simplified sc decoding algorithm

Abstract

The application relates to a simplified SC decoding algorithm, and relates to an SC decoding algorithm.The application is used to solve the problems of step redundancy of the SC decoding algorithm and less relevant implementation devices of Polar decoding.The steps of the application are as follows: step one, determining a decision input and an information bit set A and a frozen bit set A c ; step two, judging whether all are frozen bits; step three, judging whether all are not frozen bits; step four, judging whether some are frozen bits and some are not frozen bits; step five, judging whether some are frozen bits and some are not frozen bits; step six, outputting a decoding result and repeating an iteration process of the SC decoding.The application belongs to the technical field of decoding.

Description

Technical Field

[0001] This invention relates to an SC decoding algorithm, belonging to the field of decoding technology. Background Technology

[0002] As the first coding scheme proven to reach the Shannon limit, Polar codes have received widespread attention from academia and industry since their inception. They have also been selected as the coding scheme for the control channel in the eMBB scenario in 5G mobile communication. Furthermore, Polar codes are relatively simple to construct, and their iterative process based on a butterfly structure is well-structured, resulting in relatively low latency and easier hardware implementation. However, certain problems still exist in existing Polar decoding methods. First, the SC decoding algorithm suffers from redundancy. SC decoding is a serial cancellation bit-by-bit decoding algorithm. During the decoding process, initialization is performed first, followed by layer-by-layer node updates and partial updates of the butterfly structure, and finally, decoding decisions are made based on the obtained log-likelihood value. In the final stage of the butterfly structure update process, the operations of f-nodes and g-nodes can be performed simultaneously, further reducing the decoding cycle and thus optimizing redundancy. Second, there are relatively few implementation devices for Polar decoding; FPGA-based hardware implementation can greatly enhance the engineering application value of Polar codes. Due to the design of the corresponding modules, even with the same decoding method, the hardware implementation may produce different results. Furthermore, given the numerous decoding methods for Polar codes, the final results vary considerably. Improving the decision-making process and hardware implementation based on the SC decoding algorithm offers advantages in terms of hardware resource consumption and maximum frequency, potentially expanding the applications of Polar codes. Summary of the Invention

[0003] To address the issues of redundant steps in the SC decoding algorithm and the limited number of implementation devices for Polar decoding, this invention proposes a simplified SC decoding algorithm.

[0004] The technical solution adopted by the present invention to solve the above problems is as follows: The specific steps of the present invention are as follows:

[0005] Step 1: Determine the decision input and Information bit set A and frozen bit set A c ;

[0006] in and It represents the log-likelihood values ​​of two nodes c and d in the n-1 stage of the butterfly operation; set A represents the set of information bits, that is, the information bits to be transmitted. c This represents the frozen bit set, which is the opposite of the information bit set. The bits representing the corresponding sequence number of the sub-channel transmission are fixed values, generally 0, and are known to both the sender and receiver.

[0007] Step 2: Determine if the condition is met. and All are frozen bits;

[0008] Step 3: Determine if the condition is met. and None of them are frozen bits;

[0009] Step 4: Determine if the conditions are met. It is a frozen bit. Not frozen bits;

[0010] Step 5: Determine if the condition is met. It is a frozen bit. Not frozen bits;

[0011] Step 6: Output the decoding result and And repeat the iterative process of SC decoding.

[0012] Furthermore, in step two, it is determined whether the condition is met. and All are frozen bits, that is, determine whether sequence numbers 2i-1 and 2i are both contained in the information bit set A. If not, proceed to the next step.

[0013] If satisfied, calculate The value to be taken. Then, for... Compare the size of the four values:

[0014] If the maximum value is The decoding result is and

[0015] If the maximum value is 0, then the decoding result is and

[0016] If the maximum value is The decoding result is and

[0017] If the maximum value is The decoding result is and

[0018] Furthermore, in step three, it is determined whether the condition is met. and Neither of them are frozen bits, that is, determine whether both index 2i-1 and 2i are contained in the frozen bit set A. cIf the conditions are not met, proceed to the next step; if the conditions are met, directly perform a decoding decision, and the decision result is... and

[0019] Furthermore, in step four, it is determined whether the condition is met. It is a frozen bit. If it is not a frozen bit, then determine whether the sequence number 2i-1 is contained in the frozen bit set A. c And sequence number 2i is contained in the information bit set A. If this condition is not met, proceed to the next step.

[0020] If satisfied, proceed with bitwise operations first. The decoding decision was as follows:

[0021] calculate If the value is greater than or equal to 0, then the decoding decision is made. Conversely, the judgment

[0022] Furthermore, in step five, it is determined whether the condition is met. It is a frozen bit. It is not a frozen bit, that is, it determines whether the sequence number 2i is contained in the frozen bit set A. c And sequence number 2i-1 is included in the information bit set A. If this condition is not met, proceed to the next step.

[0023] If satisfied, proceed with bitwise operations first. The decoding decision was as follows:

[0024] calculate If the value is greater than or equal to 0, then the decoding decision is made. Conversely, the judgment

[0025] The beneficial effects of this invention are as follows: This invention simplifies the iterative process of Polar code SC decoding, primarily in the simplified computation of the final stage of the butterfly structure operation. During this simplification, simultaneous computation of the upper and lower nodes is adopted, minimizing implementation complexity. While maintaining a relatively consistent bit error rate performance, it reduces the decoding cycle of Polar code SC decoding, lowers latency, and better aligns with the high reliability and low latency characteristics of modern communication systems. Furthermore, this invention provides a hardware implementation based on the simplified SC decoding algorithm, demonstrating its feasibility. The specific hardware implementation verifies its advantages in terms of highest frequency and resource utilization, enhancing the industrial application capabilities of Polar codes, making them more competitive and applicable to a wider range of situations. This invention has practical significance and application value. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the Vivado simulation results;

[0027] Figure 2 This is a schematic diagram of part of the present invention and updated simulation results;

[0028] Figure 3 This is a schematic diagram of FPGA board verification;

[0029] Figure 4 This is a diagram illustrating FPGA resource consumption. Detailed Implementation

[0030] Specific implementation method one: Combining Figures 1 to 4 This embodiment describes a simplified SC decoding algorithm implemented through the following steps:

[0031] Step 1: Determine the decision input and Information bit set A and frozen bit set A c ;

[0032] in and It represents the log-likelihood values ​​of two nodes c and d in the n-1 stage of the butterfly operation; set A represents the set of information bits, that is, the information bits to be transmitted. c This represents the frozen bit set, which is the opposite of the information bit set. The bits representing the corresponding sequence number of the sub-channel transmission are fixed values, generally 0, and are known to both the sender and receiver.

[0033] Step 2: Determine if the condition is met. and All are frozen bits;

[0034] Step 3: Determine if the condition is met. and None of them are frozen bits;

[0035] Step 4: Determine if the conditions are met. It is a frozen bit. Not frozen bits;

[0036] Step 5: Determine if the condition is met. It is a frozen bit. Not frozen bits;

[0037] Step 6: Output the decoding result and And repeat the iterative process of SC decoding.

[0038] In this embodiment, for a Polar code of actual length N, N needs to be a power of 2, i.e., N = 2. n The decoding process has a total of n stages; the improvement of the SC decoding algorithm is reflected in the last stage of the butterfly structure operation; assuming that the bit numbers corresponding to the last stage of the butterfly structure are 2i-1 and 2i.

[0039] Specific Implementation Method Two: Combining Figures 1 to 4 This embodiment describes a simplified SC decoding algorithm where step two involves determining whether the following conditions are met. and All are frozen bits, that is, determine whether sequence numbers 2i-1 and 2i are both contained in the information bit set A. If not, proceed to the next step.

[0040] If satisfied, calculate The value to be taken. Then, for... Compare the size of the four values:

[0041] If the maximum value is The decoding result is and

[0042] If the maximum value is 0, then the decoding result is and

[0043] If the maximum value is The decoding result is and

[0044] If the maximum value is The decoding result is and

[0045] Specific implementation method three: Combining Figures 1 to 4 This embodiment describes a simplified SC decoding algorithm. Step three involves determining whether the following conditions are met. and Neither of them are frozen bits, that is, determine whether both index 2i-1 and 2i are contained in the frozen bit set A. c If the conditions are not met, proceed to the next step; if the conditions are met, directly perform a decoding decision, and the decision result is... and

[0046] Specific implementation method four: Combination Figures 1 to 4 This embodiment describes a simplified SC decoding algorithm. Step four involves determining whether the following conditions are met. It is a frozen bit. If it is not a frozen bit, then determine whether the sequence number 2i-1 is contained in the frozen bit set A. c And sequence number 2i is contained in the information bit set A. If this condition is not met, proceed to the next step.

[0047] If satisfied, proceed with bitwise operations first. The decoding decision was as follows:

[0048] calculate If the value is greater than or equal to 0, then the decoding decision is made. Conversely, the judgment

[0049] Specific Implementation Method Five: Combining Figures 1 to 4 This embodiment describes a simplified SC decoding algorithm. Step five involves determining whether the following conditions are met. It is a frozen bit. It is not a frozen bit, that is, it determines whether the sequence number 2i is contained in the frozen bit set A. c And sequence number 2i-1 is included in the information bit set A. If this condition is not met, proceed to the next step.

[0050] If satisfied, proceed with bitwise operations first. The decoding decision was as follows:

[0051] calculate If the value is greater than or equal to 0, then the decoding decision is made. Conversely, the judgment

[0052] Example

[0053] For the simplified SC decoding of Polar with code length N=1024, assume that in a certain decoding step, the final log-likelihood value of the input is... and The corresponding decoded bits are u1 and u2, assuming u1 is a frozen bit;

[0054] Because u1 is a frozen bit, the final output of the decision is: u1 = 0;

[0055] For u2, since Therefore, the judgment result is u2 = 0;

[0056] The final output is u1=0 and u2=0.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A simplified SC decoding algorithm, characterized in that: The simplified SC decoding algorithm is implemented through the following steps: Step 1: Determine the decision input and Information bit collection A And the collection of frozen bits ; in and It is a butterfly operation n -1 Phase Two Nodes c and d Log-likelihood value; set A It represents the set of information bits, that is, the information bits to be transmitted. This represents the frozen bit set, which is the opposite of the information bit set. The bits representing the corresponding sequence number of the sub-channel transmission are fixed values, generally 0, and are known to both the sender and receiver. Step 2: Determine if the condition is met. and All are frozen bits; That is, determine whether it is sequence number 2. i -1 and 2 i All are contained in the information bit set A If the conditions are not met, proceed to the next step; If satisfied, calculate The value to be taken; then for Compare the size of the four values: If the maximum value is The decoding result is and ; If the maximum value is 0, then the decoding result is and ; If the maximum value is The decoding result is and ; If the maximum value is The decoding result is and ; Step 3: Determine if the condition is met. and None of them are frozen bits; That is, determine whether it is sequence number 2. i -1 and 2 i All are included in the frozen bit collection If the conditions are not met, proceed to the next step; if the conditions are met, directly perform a decoding decision, and the decision result is... and ; Step 4: Determine if the conditions are met. It is a frozen bit. Not frozen bits; That is, determine whether it is sequence number 2. i -1 is included in the frozen bit set. And serial number 2 i Included in the information bit set A If the conditions are not met, proceed to the next step; If satisfied, proceed with bitwise operations first. The decoding decision was as follows: ; calculate If the value of is greater than or equal to 0, then the decoding decision is made. Conversely, the judgment is... ; Step 5: Determine if the condition is met. It is a frozen bit. Not frozen bits; That is, determine whether it is sequence number 2. i Included in the frozen bit collection And serial number 2 i -1 is included in the set of information bits. A If the conditions are not met, proceed to the next step; If satisfied, proceed with bitwise operations first. The decoding decision was as follows: ; calculate If the value of is greater than or equal to 0, then the decoding decision is made. Conversely, the judgment is... ; Step 6: Output the decoding result and And repeat the iterative process of SC decoding.

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