A deterministic network delay control method, system and readable storage medium

Abstract

The present invention discloses a deterministic network delay control method, system, and readable storage medium. The method comprises: obtaining network information and information about time-sensitive flows in the network and modeling them; assigning a route to each time-sensitive flow using a pre-routing method; calculating the optimal time slot size and injection time slot offset range for each flow to obtain an optimal time slot set; selecting a time slot from the optimal time slot set as the time slot size; and scheduling using a greedy algorithm. If the scheduling success rate reaches 100% or every time slot in the optimal time slot set is traversed, the optimal scheduling success rate and the corresponding optimal time slot size and injection time slot offset are output. By comprehensively considering the impact of time slot size and injection time slot offset on flow scheduling, obtaining the optimal time slot size set, and using the greedy scheduling algorithm to obtain the optimal injection time slot offset, the deterministic jitter value of the flow is reduced while ensuring the deterministic delay requirement of the flow.

Description

Technical Field

[0001] The present invention belongs to the field of deterministic network technology, and in particular relates to a deterministic network delay control method, system and readable storage medium. Background Art

[0002] The Industrial Internet is booming on the back of 5G, and edge device usage is increasing. This places enormous demands on edge device computing power. However, the heterogeneous nature of edge devices and their limited computing power make it difficult to maintain deterministic end-to-end latency and jitter while meeting the high bandwidth requirements of link transmission. Traditional Ethernet, which transmits data streams on a "best-effort" basis, has long been effective due to its simple network structure and strong scalability and compatibility. However, Industrial Internet applications such as industrial data control, closed-loop industrial monitoring, digital twins, and precise time synchronization all require microsecond-level latency and near-zero jitter. Traditional Ethernet's millisecond-level transmission latency can easily lead to massive data congestion and collapse, and excessive end-to-end transmission delay and jitter make it impossible to guarantee transmission determinism.

[0003] Time-Sensitive Networking (TSN) offers numerous traffic shaping and scheduling solutions. Currently, the two most commonly used traffic shapers for time-sensitive flows are Time-Aware Shaper (TAS) and Round Robin Queue Forwarding (CQF). TAS provides more precise deterministic latency guarantees, utilizing gating lists to control transmission between queues of different priorities. TAS can effectively reduce transmission latency and jitter, but due to the multiple queues on each switch, gating list configuration is complex and requires full time synchronization of network nodes, making implementation challenging. CQF is a variant of TAS, figuratively described as a "ping-pong queue." It utilizes two queues, serving as receive and transmit queues, and transmits flows by alternating between the receive and transmit queues. Furthermore, it ensures that packets in a flow in each time slot only make one hop, allowing the end-to-end latency of a flow to be calculated simply by the number of hops. Its gating list configuration is significantly simpler than that of TAS, achieving zero congestion loss and bounded latency regardless of network topology, making it a more practical and easier mechanism to implement. CQF schedules flows per queue instead of per frame, which results in reduced time accuracy and higher end-to-end latency than the TAS mechanism. However, in deterministic networks, early arrival of flows is not required, and more emphasis is placed on the punctuality of flow arrival. The increase in latency caused by the CQF mechanism is within an acceptable range, making deterministic transmission easier to achieve.

[0004] The CQF mechanism divides time into multiple intervals of equal length, called slot lengths. The shorter the slot length, the greater the number of slots divided within a supercycle, allowing for more selectable injection slot offsets, which in turn improves the flow scheduling success rate. However, due to the deterministic delay constraints of each flow and the queue capacity constraints of CQF, the slot size cannot be infinitely small. Otherwise, deterministic delay will not be guaranteed for the flow, reducing the flow scheduling success rate. Therefore, selecting the optimal slot size for flow scheduling is a crucial issue. Summary of the Invention

[0005] The present invention provides a deterministic network delay control method, system and readable storage medium, which are used to solve the technical problem of being unable to select the optimal time slot size for flow scheduling.

[0006] In a first aspect, the present invention provides a deterministic network delay control method, comprising:

[0007] Obtaining time-sensitive flows and network topology in deterministic networks;

[0008] Use pre-routing to assign routing paths to each time-sensitive flow;

[0009] An optimization model is constructed based on the time-sensitive flows and the network topology with minimizing the deterministic jitter of all time-sensitive flows as an optimization goal, and the optimization model is solved to obtain an optimal time slot size set, wherein the optimal time slot size set includes the optimal time slot size of each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized;

[0010] Selecting any optimal time slot size from the optimal time slot size set, and calculating a corresponding injection time slot offset range based on the optimal time slot size;

[0011] Scheduling the deterministic network using a greedy algorithm according to the mapping score and the queue resource balance value, and calculating a scheduling success rate of scheduling the deterministic network;

[0012] Determine whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed;

[0013] If the scheduling success rate is greater than a preset threshold, the optimal time slot size and injection time slot offset corresponding to the current number of iterations are output;

[0014] If the current iteration is completed, the maximum scheduling success rate in the iteration process, as well as the optimal time slot size and injection time slot offset corresponding to the iteration number of the maximum scheduling success rate are output.

[0015] In a second aspect, the present invention provides a deterministic network delay control system, comprising:

[0016] an acquisition module configured to acquire time-sensitive flows and network topology in a deterministic network;

[0017] an allocation module configured to allocate routing paths to each time-sensitive flow in a pre-routing manner;

[0018] a solving module configured to construct an optimization model based on the time-sensitive flows and the network topology, with minimizing the deterministic jitter of all time-sensitive flows as an optimization goal, and solve the optimization model to obtain an optimal time slot size set, wherein the optimal time slot size set includes an optimal time slot size for each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized;

[0019] a selection module configured to select any optimal time slot size from the optimal time slot size set, and calculate a corresponding injection time slot offset range based on the optimal time slot size;

[0020] a calculation module configured to schedule the deterministic network using a greedy algorithm according to a mapping score and a queue resource balance value, and calculate a scheduling success rate of scheduling the deterministic network;

[0021] A judgment module is configured to judge whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed;

[0022] A first output module is configured to output the optimal time slot size and injection time slot offset corresponding to the current number of iterations if the scheduling success rate is greater than a preset threshold;

[0023] The second output module is configured to output the maximum scheduling success rate in the iteration process, and the optimal time slot size and injection time slot offset corresponding to the iteration number of the maximum scheduling success rate if the current iteration is completed.

[0024] In a third aspect, an electronic device is provided, comprising: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the deterministic network delay control method of any embodiment of the present invention.

[0025] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the program instructions are executed by a processor, the processor executes the steps of the deterministic network delay control method of any embodiment of the present invention.

[0026] The deterministic network delay control method, system and readable storage medium of the present application reduce the deterministic jitter of the flow while ensuring the deterministic delay of the time-sensitive flow, comprehensively consider the time slot size, and inject the time slot offset scheduling algorithm, thereby improving the determinism of the flow transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 A flowchart of a deterministic network delay control method provided by one embodiment of the present invention;

[0029] Figure 2 A flowchart of a deterministic network delay control method according to a specific embodiment of the present invention is provided;

[0030] Figure 3 A simulation diagram of scheduling success rates under different queue capacities provided by an embodiment of the present invention;

[0031] Figure 4 A simulation diagram of scheduling success rates under different topologies provided by an embodiment of the present invention;

[0032] Figure 5 A structural block diagram of a deterministic network delay control system provided by one embodiment of the present invention;

[0033] Figure 6 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] See also Figure 1 , which shows a flowchart of a deterministic network delay control method of the present application.

[0036] like Figure 1 As shown, the deterministic network delay control method specifically includes the following steps:

[0037] Step S101, obtaining a time-sensitive flow and a network topology in a deterministic network;

[0038] Step S102: allocating a routing path to each time-sensitive flow using a pre-routing method;

[0039] Step S103: Based on the time-sensitive flows and the network topology, an optimization model is constructed with minimizing the deterministic jitter of all time-sensitive flows as the optimization goal, and the optimization model is solved to obtain an optimal time slot size set, where the optimal time slot size set includes the optimal time slot size of each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized.

[0040] Step S104, selecting any optimal time slot size from the optimal time slot size set, and calculating a corresponding injection time slot offset range based on the optimal time slot size;

[0041] Step S105 : scheduling the deterministic network using a greedy algorithm according to the mapping score and the queue resource balance value, and calculating a scheduling success rate of scheduling the deterministic network.

[0042] In this step, the expression for calculating the scheduling success rate of scheduling the deterministic network is:

[0043]

[0044] Where N suc is the number of successfully scheduled flows, N fail The total number of scheduling failure flows and scheduling success flows.

[0045] Step S106, determining whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed;

[0046] Step S107: If the scheduling success rate is greater than a preset threshold, the optimal time slot size and injection time slot offset corresponding to the current number of iterations are output;

[0047] Step S108: If the current iteration is completed, the maximum scheduling success rate in the iteration process, as well as the optimal time slot size and injection time slot offset corresponding to the iteration number at which the maximum scheduling success rate occurs are output.

[0048] The method of this embodiment obtains network information and information about time-sensitive flows in the network and models them; then uses pre-routing to assign routes to each time-sensitive flow; then calculates the optimal time slot size and injection time slot offset range for each flow to obtain an optimal time slot set; selects a time slot from the optimal time slot set as the time slot size; and then uses a greedy algorithm for scheduling. If the scheduling success rate reaches 100% or every time slot in the optimal time slot set is traversed, the optimal scheduling success rate and the corresponding optimal time slot size and injection time slot offset are output; otherwise, the iteration is repeated. The present invention comprehensively considers the impact of time slot size and injection time slot offset on flow scheduling, obtains the optimal time slot size set, and uses a greedy scheduling algorithm to obtain the optimal injection time slot offset. This reduces the deterministic jitter value of the flow while ensuring the deterministic delay requirement of the flow.

[0049] See also Figure 2 , which shows a flowchart of a deterministic network delay control method of the present application.

[0050] like Figure 2 As shown, in the first step, the CUC is used in the network to communicate with the central network controller (CNC) to obtain information about the network topology and strategy and time-sensitive flow information, and perform mathematical modeling.

[0051] Specifically, the network topology is modeled as a directed graph G = (V, E), where V is the vertex set, representing the set of switches and terminals, and E is the edge set. m , v n )∈E represents a link in the topology.

[0052] The delay in the system is modeled as: processing delay d proc , transmission delay d tran , propagation delay d prop , queuing delay d aueue Delay sync caused by time synchronization delay .

[0053] For each time-sensitive flow, it is defined as a nine-tuple

[0054] Where s i is the source node of the i-th time-sensitive flow, d i is the end node of the i-th time-sensitive flow, p i is the generation period of the i-th time-sensitive flow, l i is the packet length of the i-th time-sensitive flow, R i is the routing path of the i-th time-sensitive flow in the network, o i is the injection slot offset of the i-th time-sensitive stream, is the maximum deterministic end-to-end delay that can be tolerated by the i-th time-sensitive flow, is the minimum deterministic end-to-end delay required for the i-th time-sensitive flow, J i is the maximum tolerable jitter of the i-th time-sensitive flow.

[0055] In the second step, a weighted calculation is performed based on the flow's source address, destination address, deterministic delay requirement, generation period, packet size, link load rate and other attributes, and the routing path with the highest weight among the shortest paths is selected as the routing path for the flow.

[0056] The third step is to calculate the optimal time slot set and the corresponding injection time slot offset range based on network information and information about time-sensitive flows in the network, with deterministic jitter as the optimization goal. Specifically:

[0057] The expression of the optimization objective is:

[0058]

[0059] In the formula, o i is the injection slot offset of the i-th time-sensitive stream, t is the slot length, N f is the number of time-sensitive flows;

[0060] Since the maximum jitter in the CQF mechanism is two time slots, the objective function is to minimize the deterministic jitter.

[0061] The expression of the deterministic delay constraint is:

[0062]

[0063]

[0064] Where, is the maximum deterministic end-to-end delay that can be tolerated by the i-th time-sensitive flow, is the minimum deterministic end-to-end delay required for the i-th time-sensitive flow, h i is the total number of hops of the i-th time-sensitive flow routing path, (o i +h i +1)t is the maximum end-to-end delay of the i-th time-sensitive flow after routing and injection into the time slot, (o i +h i -1)t is the minimum end-to-end delay of the i-th time-sensitive flow after allocating routing and injecting time slots;

[0065] The expression of the injection slot constraint is:

[0066]

[0067] Where p i is the generation period of the i-th time-sensitive flow;

[0068] The expression of the time slot size constraint is:

[0069]

[0070] Where, d proc For processing delay, d prop is the propagation delay, sync delay is the delay caused by time synchronization, B is the link bandwidth, L Q is the queue length, GCD(p i ) is the greatest common divisor of the periods of all time-sensitive flows.

[0071] Since the objective function is a linear function, when t takes its minimum value that satisfies the constraints, all time-sensitive flows can reach the terminal within the deterministic delay, and the resulting deterministic jitter is minimized. The optimal time slot size for each flow is obtained by solving

[0072]

[0073]

[0074] Where, t min is the minimum optimal time slot size, is the optimal time slot size for the i-th time-sensitive flow.

[0075] The optimal slot size set Each iteration selects one of the time slots t in the optimal time slot size set * ∈T * As the time slot size of this iteration.

[0076] By t * Determine the optimal injection slot offset range that satisfies the minimum deterministic jitter:

[0077]

[0078] In the formula, o i * is the injection slot offset corresponding to the optimal slot size of the i-th time-sensitive stream, is greater than The smallest integer, Not greater than The largest integer, Not greater than The maximum integer.

[0079] In the fourth step, a time slot in the optimal time slot set is selected as the time slot size, and a greedy algorithm is used to schedule the flow according to the mapping score and the queue resource balance value, and the scheduling success rate is calculated.

[0080] The mapping score is:

[0081]

[0082] in, It represents the remaining unoccupied queue resource capacity in port k of node j in time slot t, Q size Refers to the maximum capacity of the queue.

[0083] The queue resource balance is:

[0084]

[0085] in Refers to the queue resource capacity occupied in port k of node j in time slot t, Refers to the average queue resource occupancy, N Pt , N SW , C T are the number of ports, the number of nodes and the size of the hypercycle respectively. v(j,k)=1, representing the kth port at node j.

[0086] In the fifth step, the condition for terminating the iteration is that the scheduling success rate reaches 100% or all time slots in the optimal time slot set are traversed. Then, the optimal scheduling success rate and its corresponding time slot size and injection time slot offset are output. Otherwise, the time slot size will be reselected from the optimal time slot set for iteration.

[0087] It should be noted that if Figure 3 As shown, compared with the scheduling method using fixed time slots, the deterministic network delay control method described in the present invention effectively improves the scheduling success rate, and the effect is more obvious when the queue capacity is limited.

[0088] like Figure 4 As shown, compared with the scheduling method using fixed time slots, the deterministic network delay control method described in the present invention can effectively improve the scheduling success rate under different network topologies.

[0089] See also Figure 5 , which shows a structural block diagram of a deterministic network delay control system of the present application.

[0090] like Figure 5As shown, the deterministic network delay control system 200 includes an acquisition module 210, an allocation module 220, a solution module 230, a selection module 240, a calculation module 250, a judgment module 260, a first output module 270 and a second output module 280.

[0091] Among them, the acquisition module 210 is configured to obtain the time-sensitive flow and network topology in the deterministic network; the allocation module 220 is configured to allocate routing paths to each time-sensitive flow in a pre-routing manner; the solution module 230 is configured to construct an optimization model based on the time-sensitive flow and the network topology, with minimizing the deterministic jitter of all time-sensitive flows as the optimization goal, and solve the optimization model to obtain an optimal time slot size set, wherein the optimal time slot size set contains the optimal time slot size of each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized; the selection module 240 is configured to select any optimal time slot size in the optimal time slot size set, and calculate the corresponding optimal time slot size through the optimal time slot size. a calculation module 250 configured to schedule the deterministic network using a greedy algorithm according to the mapping score and the queue resource balance value, and calculate the scheduling success rate of scheduling the deterministic network; a judgment module 260 configured to judge whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed; a first output module 270 configured to output the optimal time slot size and injection time slot offset corresponding to the current number of iterations if the scheduling success rate is greater than the preset threshold; a second output module 280 configured to output the maximum scheduling success rate in the iteration process, as well as the optimal time slot size and injection time slot offset corresponding to the iteration number where the maximum scheduling success rate is located, if the current iteration is completed.

[0092] It should be understood that Figure 5 Modules and references documented in Figure 1 Therefore, the operations and features described above for the method and the corresponding technical effects also apply to Figure 5 The modules in it will not be described in detail here.

[0093] In other embodiments, embodiments of the present invention further provide a computer-readable storage medium having a computer program stored thereon, wherein when the program instructions are executed by a processor, the processor is caused to execute the deterministic network delay control method in any of the above method embodiments;

[0094] As an embodiment, the computer-readable storage medium of the present invention stores computer-executable instructions, and the computer-executable instructions are configured as follows:

[0095] Obtaining time-sensitive flows and network topology in deterministic networks;

[0096] Use pre-routing to assign routing paths to each time-sensitive flow;

[0097] An optimization model is constructed based on the time-sensitive flows and the network topology with minimizing the deterministic jitter of all time-sensitive flows as an optimization goal, and the optimization model is solved to obtain an optimal time slot size set, wherein the optimal time slot size set includes the optimal time slot size of each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized;

[0098] Selecting any optimal time slot size from the optimal time slot size set, and calculating a corresponding injection time slot offset range based on the optimal time slot size;

[0099] Scheduling the deterministic network using a greedy algorithm according to the mapping score and the queue resource balance value, and calculating a scheduling success rate of scheduling the deterministic network;

[0100] Determine whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed;

[0101] If the scheduling success rate is greater than a preset threshold, the optimal time slot size and injection time slot offset corresponding to the current number of iterations are output;

[0102] If the current iteration is completed, the maximum scheduling success rate in the iteration process, as well as the optimal time slot size and injection time slot offset corresponding to the iteration number of the maximum scheduling success rate are output.

[0103] The computer-readable storage medium may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the deterministic network delay control system, etc. In addition, the computer-readable storage medium may include a high-speed random access memory, and may also include a memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state memory device. In some embodiments, the computer-readable storage medium may optionally include a memory remotely located relative to the processor, and these remote memories may be connected to the deterministic network delay control system via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0104] Figure 6 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 6 As shown, the device includes: a processor 310 and a memory 320. The electronic device may also include: an input device 330 and an output device 340. The processor 310, the memory 320, the input device 330 and the output device 340 may be connected via a bus or other means. Figure 6 The example of a bus connection is shown. Memory 320 is the aforementioned computer-readable storage medium. Processor 310 executes various server functional applications and data processing by running the non-volatile software programs, instructions, and modules stored in memory 320, thereby implementing the deterministic network delay control method of the aforementioned method embodiment. Input device 330 can receive input digital or character information and generate key signal input related to user settings and function control of the deterministic network delay control system. Output device 340 can include a display device such as a display screen.

[0105] The electronic device can execute the method provided by the embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the method provided by the embodiment of the present invention.

[0106] As an embodiment, the electronic device is applied to a deterministic network delay control system and is used for a client, and includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to:

[0107] Obtaining time-sensitive flows and network topology in deterministic networks;

[0108] Use pre-routing to assign routing paths to each time-sensitive flow;

[0109] An optimization model is constructed based on the time-sensitive flows and the network topology with minimizing the deterministic jitter of all time-sensitive flows as an optimization goal, and the optimization model is solved to obtain an optimal time slot size set, wherein the optimal time slot size set includes the optimal time slot size of each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized;

[0110] Selecting any optimal time slot size from the optimal time slot size set, and calculating a corresponding injection time slot offset range based on the optimal time slot size;

[0111] Scheduling the deterministic network using a greedy algorithm according to the mapping score and the queue resource balance value, and calculating a scheduling success rate of scheduling the deterministic network;

[0112] Determine whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed;

[0113] If the scheduling success rate is greater than a preset threshold, the optimal time slot size and injection time slot offset corresponding to the current number of iterations are output;

[0114] If the current iteration is completed, the maximum scheduling success rate in the iteration process, as well as the optimal time slot size and injection time slot offset corresponding to the iteration number of the maximum scheduling success rate are output.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A deterministic network delay control method, characterized in that: include: Obtaining time-sensitive flows and network topology in deterministic networks; Use pre-routing to assign routing paths to each time-sensitive flow; An optimization model is constructed based on the time-sensitive flows and the network topology with minimizing the deterministic jitter of all time-sensitive flows as an optimization goal, and the optimization model is solved to obtain an optimal time slot size set, wherein the optimal time slot size set includes the optimal time slot size of each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized; Selecting any optimal time slot size from the optimal time slot size set, and calculating a corresponding injection time slot offset range based on the optimal time slot size; Scheduling the deterministic network using a greedy algorithm according to the mapping score and the queue resource balance value, and calculating a scheduling success rate of scheduling the deterministic network; Determine whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed; If the scheduling success rate is greater than a preset threshold, the optimal time slot size and injection time slot offset corresponding to the current number of iterations are output; If the current iteration is completed, the maximum scheduling success rate in the iteration process, as well as the optimal time slot size and injection time slot offset corresponding to the iteration number of the maximum scheduling success rate are output.

2. A deterministic network delay control method according to claim 1, characterized in that: in, Each time-sensitive flow is defined as a nine-tuple ; Where, For the The source node of a time-sensitive flow, For the The end nodes of a time-sensitive flow, For the The generation cycle of a time-sensitive flow, For the The packet length of a time-sensitive flow, For the The routing path of a time-sensitive flow in the network, For the The injection slot offset of the time-sensitive stream, For the The maximum deterministic end-to-end delay that a time-sensitive flow can tolerate, For the The minimum deterministic end-to-end latency required for a time-sensitive flow, For the The maximum jitter that a time-sensitive flow can tolerate.

3. A deterministic network delay control method according to claim 2, characterized in that: in, The optimization objective of the optimization model is expressed as: ， Where, For the The injection slot offset of the time-sensitive stream, is the time slot length, is the number of time-sensitive flows; The constraints of the optimization model include deterministic delay constraint, injection slot constraint and slot size constraint; the deterministic delay constraint is expressed as: ， ， Where, For the The maximum deterministic end-to-end delay that a time-sensitive flow can tolerate, For the The minimum deterministic end-to-end latency required for a time-sensitive flow, For the The total number of hops in the time-sensitive flow routing path, For the The maximum end-to-end delay of a time-sensitive flow after allocating routes and injecting time slots, For the The minimum end-to-end delay of a time-sensitive flow after being assigned a route and injected into a time slot; The expression of the injection time slot constraint is: ， Where, For the The generation cycle of a time-sensitive flow; The expression of the time slot size constraint is: ， Where, To handle delay, is the propagation delay, The delay caused by time synchronization, is the link bandwidth, is the queue length, Generates the greatest common divisor of periods for all time-sensitive flows.

4. A deterministic network delay control method according to claim 3, characterized in that: Solving the optimization model to obtain the optimal time slot size set includes: The optimization model is solved to obtain the optimal time slot size of each time-sensitive flow, wherein the expression for calculating the optimal time slot size is: ， ， Where, is the minimum optimal time slot size, For the The optimal slot size for a time-sensitive flow; The optimal time slot size set is obtained based on the optimal time slot size of each time-sensitive flow .

5. A deterministic network delay control method according to claim 4, characterized in that: The expression for allocating the injection time slot offset range corresponding to any one of the optimal time slot sizes is: ， Where, For the The injection slot offset corresponding to the optimal slot size of each time-sensitive flow, is greater than The smallest integer, Not greater than The largest integer, Not greater than The maximum integer.

6. A deterministic network delay control method according to claim 1, characterized in that: The expression for calculating the scheduling success rate of scheduling the deterministic network is: ， Where, is the number of successfully scheduled flows, The total number of scheduling failure flows and scheduling success flows.

7. A deterministic network delay control system, characterized in that: include: an acquisition module configured to acquire time-sensitive flows and network topology in a deterministic network; an allocation module configured to allocate routing paths to each time-sensitive flow in a pre-routing manner; a solving module configured to construct an optimization model based on the time-sensitive flows and the network topology, with minimizing the deterministic jitter of all time-sensitive flows as an optimization goal, and solve the optimization model to obtain an optimal time slot size set, wherein the optimal time slot size set includes an optimal time slot size for each time-sensitive flow when the deterministic jitter of all time-sensitive flows is minimized; a selection module configured to select any optimal time slot size from the optimal time slot size set, and calculate a corresponding injection time slot offset range based on the optimal time slot size; a calculation module configured to schedule the deterministic network using a greedy algorithm according to a mapping score and a queue resource balance value, and calculate a scheduling success rate of scheduling the deterministic network; A judgment module is configured to judge whether the scheduling success rate is greater than a preset threshold or whether the current iteration is completed; A first output module is configured to output the optimal time slot size and injection time slot offset corresponding to the current number of iterations if the scheduling success rate is greater than a preset threshold; The second output module is configured to output the maximum scheduling success rate in the iteration process, and the optimal time slot size and injection time slot offset corresponding to the iteration number of the maximum scheduling success rate if the current iteration is completed.

8. An electronic device, characterized in that: include: At least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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