SRIO serial port video stream analysis method based on FPGA

Abstract

The application provides an SRIO serial port video stream analysis method based on FPGA, which comprises the following steps: confirming the flag bit of the video stream image data obtained through the SRIO serial port; performing padding processing on each row of image data in the video image data; buffering the current image data and synchronously performing clock domain conversion; reading the buffered image data according to a preset format, generating an image data valid enabling signal, and transmitting the image data in alignment with the image data of which the analysis is completed, so as to form a data flow. The application realizes the SRIO serial port image video stream analysis based on FPGA, can be used for efficiently and quickly recovering the image in the video stream, reduces the pressure of subsequent FPGA image processing, and can make the data flow, thereby improving the real-time performance of the overall FPGA system operation.

Description

Technical Field

[0001] This invention relates to the field of image data processing technology, and in particular to an FPGA-based SRIO serial port video stream parsing method. Background Technology

[0002] Currently, computer software technology provides an excellent platform for the development of video image processing technology, and the powerful processing capabilities of computer processors have been well applied in various video image processing algorithms. Highly integrated, high-performance, and low-power Field Programmable Gate Array (FPGA) devices offer broad development prospects for video image system designers, and the unique performance advantages of FPGAs occupy a very important position in embedded video image processing systems.

[0003] In practical applications, to meet the real-time requirements of data processing, data pipelined architecture is necessary when designing FPGA programs. By designing a data pipeline, the powerful parallel computing capabilities of the FPGA are utilized to achieve real-time processing of large amounts of data. If the data cannot be pipelined, the overall real-time performance of the FPGA design will be significantly compromised. Summary of the Invention

[0004] The technical problem to be solved by this invention is how to efficiently and quickly recover images from a video stream, making the data flow smoothly and improving the real-time performance of the overall FPGA system. In view of this, this invention provides an FPGA-based SRIO serial port video stream parsing method.

[0005] The technical solution adopted in this invention is an FPGA-based SRIO serial port video stream parsing method, comprising:

[0006] Step S1: The video stream image data obtained via the SRIO serial port is flagged and confirmed.

[0007] Step S2: Perform padding processing on each row of image data in the video image data;

[0008] Step S3: Cache the current image data and synchronously perform clock domain transformation;

[0009] Step S4: Read the cached image data according to the preset format, generate an enable signal for valid image data, and align it with the parsed image data for transmission to form a data pipeline.

[0010] In one implementation, the step of verifying the flag bits of the video stream image data acquired via the SRIO serial port includes:

[0011] The start of each frame of image data in the video stream and the start of each line of data in a frame of image data are confirmed by a flag bit.

[0012] In one embodiment, the step of reading the cached image data according to a preset format includes:

[0013] Simultaneously perform secondary flag confirmation processing on the current image data.

[0014] In one implementation, caching the current image data includes: caching the current image data in a FIFO and counting it.

[0015] In one implementation, the preset format includes: pre-configuring the number of frames, the size of each frame of image data, and the number of rows of the current image data.

[0016] In one embodiment, step S4 involves using a state machine to read cached image data according to a preset format and generate an enable signal for valid image data.

[0017] In one implementation, the states of the state machine include: start, read, line judgment, line delay, frame judgment, frame delay. If the current image data meets the state transition conditions, the operation corresponding to the next state is performed.

[0018] By adopting the above technical solution, the present invention realizes FPGA-based SRIO serial port image and video stream parsing, which can be used to efficiently and quickly recover images in video streams, reducing the pressure of subsequent FPGA image processing; and it can also make data flow smoothly, improving the real-time performance of the overall FPGA system operation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the FPGA-based SRIO serial video stream parsing method according to an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the overall system architecture for an implementation according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram illustrating the logic of state transition and image delay reading functions completed by internal counting of a state machine according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the image and video stream parsing process according to an embodiment of the present invention. Detailed Implementation

[0023] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0024] In the accompanying drawings, the thickness, size, and shape of the objects have been slightly exaggerated for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0025] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed feature, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0026] As used herein, the terms “basically,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to describe inherent biases in measured or calculated values ​​that will be recognized by those skilled in the art.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] The first embodiment of the present invention provides a method for parsing SRIO serial port video streams based on FPGA, such as... Figure 1 As shown, it includes the following steps:

[0030] Step S1: The video stream image data obtained via the SRIO serial port is flagged and confirmed.

[0031] Step S2: Perform padding processing on each row of image data in the video image data;

[0032] Step S3: Cache the current image data and synchronously perform clock domain transformation;

[0033] Step S4: Read the cached image data according to the preset format, generate an enable signal for valid image data, and align it with the parsed image data for transmission to form a data pipeline.

[0034] In one implementation, the step of verifying the flag bits of the video stream image data acquired via the SRIO serial port includes:

[0035] The start of each frame of image data in the video stream and the start of each line of data in a frame of image data are confirmed by a flag bit.

[0036] In one implementation, the step of reading cached image data according to a preset format may specifically include: synchronously performing secondary flag bit confirmation processing on the current image data.

[0037] In one implementation, caching the current image data includes: caching the current image data in a FIFO (FirstInputFirstOutput) and counting it.

[0038] In one implementation, the preset format includes: pre-configuring the number of frames, the size of each frame of image data, and the number of rows of the current image data.

[0039] In one implementation, step S4 involves using a state machine to read cached image data according to a preset format and generate an enable signal for valid image data.

[0040] In one implementation, the states of the state machine include: start, read, line judgment, line delay, frame judgment, frame delay. If the current image data meets the state transition conditions, the operation corresponding to the next state is performed.

[0041] The second embodiment of the present invention, corresponding to the first embodiment, is an application example based on the first embodiment.

[0042] In this embodiment, the overall hardware platform includes two FPGAs: a front-end interface board and a signal processing board. The overall system architecture is as follows: Figure 2 As shown.

[0043] Specifically, the front-end interface board is mainly used to receive infrared images acquired by infrared imaging devices (which can be understood as any possible image data generated in any other field) and package them into data packets according to a fixed format. Based on the requirements of this experiment, the image format is set to 1024x1280, with each column containing 1280 pixel values, for a total of 1024 columns. When packaging the data on the front-end interface board, a flag bit is added at the beginning of each column, meaning there is a start flag every 1280 data points, and each frame also has a start flag. In this way, the front-end interface board does not need to consider whether the data packets conform to the image's row and column structure when transmitting data; it only needs to ensure the flag bit generation is compliant. Finally, the packaged image data is transmitted to the signal processing board via a serial communication protocol. Using two boards, a real-world camera video transmission scenario is simulated. Since the data exists as a data stream during transmission, high-speed communication between the two boards is required to ensure the system's real-time performance; therefore, the SRIO serial communication protocol is used for data transmission.

[0044] The image data received by the signal processing board is transmitted in the form of data packets. To facilitate subsequent image processing, these image data packets need to be parsed to restore them to a data stream. Image data packets are received through the SRIO interface, and image parsing is performed using the frame header flags as keywords.

[0045] For example, an image can be 1280x1024 in size. When constructing the image parsing module, a finite state machine method is used to build the data packet parsing logic, set the packet header and frame header parsing conditions, and use the state transition of the finite state machine to complete the switching of the working mode and parse the image data.

[0046] Meanwhile, due to the inconsistent data intervals between each line of data transmitted from the front end, a first-level FIFO method is used in the logic construction to ensure the normal operation of subsequent algorithm data processing logic on image data and the stability of the overall system frame rate. This method sets a fixed time interval for the data, thereby restoring the original image data packets into a stable image data stream. In the programming of the relevant FIFOs, a finite state machine is used to control FIFO read / write operations. The state transition and image delay reading functions are completed through internal counting within the state machine. The specific implementation method is as follows: Figure 3The FIFO read / write operation is structured as follows: Idle is the initial state; vs_num is the frame counting state, used to count one frame of image data; hs_num is the row and column counting state; hs_delay is the row and column delay state; and vs_delay is the frame delay state. When entering a FIFO read / write operation, the state starts from Idle. When the jump flag is valid, the state changes to the frame counting state, indicating that an image frame header has been detected and the data writing operation to the FIFO has begun. When the image row and column flag is detected, the system jumps to the row and column counting state. After writing one column of data completely to the FIFO, it enters the row and column delay state. After a fixed delay, it checks whether one frame of image data is complete. If not, the row and column counting and delay states are repeated. After writing one frame of image data, it enters the frame delay state to perform a fixed-time delay operation between two frames.

[0047] The specific implementation steps are as follows, for reference only. Figure 4 :

[0048] 1. Check the flag bits of the video stream received by SRIO and apply a delay;

[0049] 2. After the judgment is completed, the data that meets the conditions is stored in the FIFO through the state machine and counted;

[0050] 3. The state machine is run in parallel. If the transition condition from a state is met, the operation corresponding to the next state is performed.

[0051] Fourth, based on the operation of the state machine, a valid enable signal for the data is generated. Specifically, at the start of the frame counting state, the frame valid signal is pulled high, and upon entering the frame delay state, the frame valid signal is pulled low. A high frame valid signal indicates that this frame of the image is valid. At the start of the row and column counting state, the column valid signal is pulled high, and upon entering the row and column delay state, the column valid signal is pulled low. A high column valid signal indicates that this column of image data is valid. The valid signal for image data is transmitted along with the image data, providing image data and a flag for judging data validity for subsequent image processing and other operations.

[0052] The above description is only a specific implementation method and typical application scenario of the present invention, but the protection scope of the present invention is not limited thereto. Any transformations or substitutions that can be conceived by those skilled in the art within the technical scope disclosed in the present invention are included within the scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

[0053] Compared with the prior art, this embodiment has at least the following advantages:

[0054] 1) This embodiment implements FPGA-based SRIO serial port image and video stream parsing, which can be used to efficiently and quickly recover images in the video stream, reducing the pressure on subsequent FPGA image processing;

[0055] 2) This embodiment can streamline data flow and improve the real-time performance of the overall FPGA system operation.

[0056] Through the description of specific embodiments, a more in-depth and specific understanding should be gained of the technical means and effects adopted by the present invention to achieve the intended purpose. However, the accompanying drawings are only provided for reference and illustration and are not intended to limit the present invention.

Claims

1. An FPGA-based SRIO serial port video stream parsing method, characterized in that, include: Step S1: The video stream image data obtained via the SRIO serial port is flagged and confirmed. Step S2: Perform padding processing on each line of image data in the video stream image data; Step S3: Cache the current image data and synchronously perform clock domain transformation; Step S4: Read the cached image data according to the preset format, generate an enable signal for valid image data, and align it with the parsed image data for transmission to form a data pipeline; The preset format includes: pre-configuring the number of frames, the size of each frame of image data, and the number of rows of the current image data; In step S4, a state machine is used to read the cached image data according to a preset format and generate an enable signal for valid image data. The states of the state machine include: start, read, line judgment, line delay, frame judgment, frame delay. If the current image data meets the state transition conditions, the operation corresponding to the next state is performed. When the frame counting state begins, the frame valid signal is pulled high. When the frame delay state is entered, the frame valid signal is pulled low. When the frame valid signal is pulled high, it indicates that this frame of image is valid. At the start of the row and column counting state, the column valid signal is pulled high, and when entering the row and column delay state, the column valid signal is pulled low. When the column valid signal is pulled high, it indicates that the image data of this column is valid. The valid signal of the image data is transmitted together with the image data.

2. The FPGA-based SRIO serial port video stream parsing method according to claim 1, characterized in that, The step of confirming the flag bits of the video stream image data acquired via the SRIO serial port includes: The start of each frame of image data in the video stream and the start of each line of data in a frame of image data are confirmed by a flag bit.

3. The FPGA-based SRIO serial port video stream parsing method according to claim 1, characterized in that, The step of reading the cached image data according to a preset format includes: Simultaneously perform secondary flag confirmation processing on the current image data.

4. The FPGA-based SRIO serial port video stream parsing method according to claim 1, characterized in that, The process of caching the current image data includes: caching the current image data in a FIFO and counting the data.

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