A three-dimensional chip, chip unit, reliability test method and related device

Abstract

The application discloses a three-dimensional chip, a chip unit, a reliability test method and related equipment, and relates to the technical field of chips, and can evaluate the reliability of a bonding structure between two adjacent chips. The three-dimensional chip comprises at least two chip units, the chip unit comprises a medium layer and a bonding structure penetrating through the medium layer; the bonding structures of the at least two chip units are bonded and connected to form a three-dimensional bonding structure, so that the at least two chip units form a three-dimensional chip; wherein one side of the chip unit away from the three-dimensional bonding structure is provided with a test structure, the test structure is connected to the medium layer, the test structure is used for conducting electric charges, and the test structure is also used for connecting an electric signal tester, so that the test structures on any two chip units form a leakage current test loop through the electric signal tester.

Claims

1. A three-dimensional chip, characterized in that, include: At least two chip units, each chip unit including a dielectric layer and a bonding structure passing through the dielectric layer; The bonding structures of the at least two chip units are bonded together to form a three-dimensional bonding structure, so that the at least two chip units form a three-dimensional chip. A test structure is provided on the side of the chip unit away from the three-dimensional bonding structure. The test structure is connected to the dielectric layer and is used to conduct charge. The test structure is also used to connect to an electrical signal tester so that the test structures on any two chip units can form a leakage current test loop through the electrical signal tester.

2. The three-dimensional chip according to claim 1, characterized in that, The chip unit is also provided with an electrical signal receiving terminal connected to the bonding structure on the side away from the three-dimensional bonding structure. The electrical signal receiving terminal is used to receive detection signals, and the test structure is used to conduct the charge generated by the dielectric layer when the electrical signal receiving terminal receives the detection signal.

3. The three-dimensional chip according to claim 2, characterized in that, The chip unit also includes: A first electrode, wherein at least one of the bonding structures in the chip unit is electrically connected to the first electrode, and the first electrode is used to access a high-level potential; The second electrode is electrically connected to at least one of the bonding structures in the chip unit, and the second electrode is used to access a low-level potential.

4. The three-dimensional chip according to claim 3, characterized in that, In the same chip unit, one of two adjacent bonding structures is electrically connected to the first electrode, and the other is electrically connected to the second electrode.

5. The three-dimensional chip according to claim 3, characterized in that, In the same three-dimensional bonding structure, two corresponding bonding structures are electrically connected to the first electrode; or, The two corresponding bonding structures are electrically connected to the second electrode.

6. The three-dimensional chip according to claim 3, characterized in that, The chip unit also includes: The top metal layer contains the test structure, the first electrode, and the second electrode.

7. A reliability testing method for a three-dimensional chip, characterized in that, include: A chip under test (DUT) is provided, and a test structure of the DUT is connected to an electrical signal tester. The DUT includes at least two chip units, each chip unit including a dielectric layer and a bonding structure penetrating the dielectric layer. The bonding structures of the at least two chip units are bonded together to form a three-dimensional bonding structure, thereby forming a three-dimensional chip. The test structure is disposed on the side of the chip unit away from the three-dimensional bonding structure and is connected to the dielectric layer. The test structure is used to conduct charge and is also used to connect to the electrical signal tester, so that the test structures on any two chip units form a leakage current test loop through the electrical signal tester. The leakage current state of the dielectric layer is detected using the electrical signal tester, and the reliability of the three-dimensional bonding structure is determined based on the leakage current state.

8. The reliability testing method according to claim 7, characterized in that, The step of detecting the leakage current state of the dielectric layer using the electrical signal tester includes: A detection signal is applied to the electrical signal receiving terminal of the chip under test, wherein the electrical signal receiving terminal is located on the side of the chip unit away from the three-dimensional bonding structure and is connected to the bonding structure; The leakage current state of the dielectric layer is detected using the electrical signal tester.

9. The reliability testing method according to claim 8, characterized in that, Determining the reliability of the three-dimensional bonding structure based on the leakage current state includes: The failure time of the three-dimensional chip is determined based on the detection signal and the leakage current state. The reliability of the three-dimensional bonding structure is evaluated based on the failure time.

10. The reliability testing method according to claim 8, characterized in that, Determining the reliability of the three-dimensional bonding structure based on the leakage current state includes: The leakage current of multiple three-dimensional chips was tested under different test conditions to obtain test sample data. The test conditions included test voltage and test ambient temperature. A three-dimensional chip lifetime assessment model is established based on the leakage current in the test sample data and the test conditions. The evaluation lifetime of the chip under test is determined based on the three-dimensional chip evaluation model and the operating condition data of the chip under test, wherein the operating condition data of the chip under test includes the operating ambient temperature and operating voltage.

11. The reliability testing method according to claim 10, characterized in that, The leakage current of multiple three-dimensional chips was tested under different test conditions to obtain test sample data, including: Based on a fixed test voltage and the corresponding leakage current, the failure time of the three-dimensional chip under different test ambient temperatures is determined. The failure time of the three-dimensional chip under different test voltages is determined based on the fixed test environment temperature and the corresponding leakage current.

12. The reliability testing method according to claim 11, characterized in that, The establishment of a three-dimensional chip lifetime assessment model based on the leakage current in the test sample data and the test conditions includes: Determine the fitting relationship curve between the failure time and different test environment temperatures under the fixed test voltage, and obtain a first slope, wherein the first slope is used to characterize the slope of the fitting relationship curve between the failure time and different test environment temperatures; A second slope is obtained by determining the fitting relationship curve between the failure time and different test voltages under the fixed test environment temperature, wherein the second slope is used to characterize the slope of the fitting relationship curve between the failure time and different test voltages. The three-dimensional chip lifetime assessment model is established based on the first slope and the second slope.

13. The reliability testing method according to claim 12, characterized in that, The determination of the evaluation lifetime of the chip under test based on the three-dimensional chip evaluation model and the operating condition data of the chip under test includes: The operating current is obtained based on the operating voltage; The operating ambient temperature and operating current of the chip under test are input into the three-dimensional chip evaluation model to output the evaluated lifetime.

14. An electronic device, characterized in that, include: The three-dimensional chip as described in any one of claims 1-6.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the reliability testing method as described in any one of claims 7-13.

16. A testing device, characterized in that, include: A memory, wherein a computer program is stored; A processor, which executes the computer program to implement the reliability testing method as described in any one of claims 7-13.

Images